Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and the semiconductor device comprises a plurality of storage units which are distributed in different layers and are stacked in a direction perpendicular to a substrate; the bit lines penetrate through the storage units of different layers and extend in the direction perpendicular to the substrate; each memory unit comprises a transistor, the transistor comprises a semiconductor layer and a gate electrode, the semiconductor layer forms a first cylindrical structure extending along a first direction parallel to the substrate, and the bit line surrounds the side surface of the first cylindrical structure formed by the semiconductor layers of the plurality of memory units and is connected with the side surface of the first cylindrical structure; the gate electrode fills the first cylindrical structure and extends out of the first cylindrical structure. According to the scheme provided by the embodiment, the bit line surrounds the transistor, the channel width is increased, and the on-state current of the transistor is improved.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device, which improves transistor performance.

[0006] This application provides a semiconductor device, including:

[0007] Multiple memory cells are stacked along the vertical substrate direction, distributed across different layers;

[0008] Bit lines extend through the memory cells in different layers along a direction perpendicular to the substrate;

[0009] The memory cell includes a transistor, the transistor including a semiconductor layer and a gate electrode, the semiconductor layer forming a first cylindrical structure extending in a first direction parallel to the substrate, the bit line surrounding and connecting to the side surface of the first cylindrical structure formed by the semiconductor layer of the plurality of memory cells; the gate electrode filling the first cylindrical structure and extending beyond the first cylindrical structure.

[0010] In some embodiments, the semiconductor device further includes multiple word lines distributed on different layers, the word lines extending along a second direction parallel to the substrate, the word lines connecting the gate electrodes of transistors in the same column distributed along the second direction on the same layer, the first direction and the second direction intersecting.

[0011] In some embodiments, the two side surfaces of the first cylindrical structure disposed opposite each other along the second direction have recessed regions, and the contact surface between the bit line and the two side surfaces disposed opposite each other along the second direction is located in the recessed regions.

[0012] In some embodiments, a gate insulating layer is disposed between the gate electrode and the semiconductor layer, the gate insulating layer extending from inside the first cylindrical structure to outside the first cylindrical structure and covering the side of the gate electrode facing the semiconductor layer; the semiconductor device further includes: an isolation layer surrounding the gate insulating layer disposed between the word line and the semiconductor layer and connected to the end face of the semiconductor layer.

[0013] In some embodiments, the semiconductor device further includes: a plurality of insulating layers and conductive layers that are alternately distributed from top to bottom along a direction perpendicular to the substrate, wherein the conductive layers include the gate electrode, the semiconductor layer, and the word line;

[0014] A first transverse trench extending in a second direction between adjacent insulating layers, and a first transverse groove extending in a first direction between adjacent insulating layers in communication with the first transverse trench.

[0015] The word lines are distributed in the first lateral trench, and the isolation layer, the semiconductor layer, the gate insulating layer, and the gate electrode are distributed sequentially from the outside to the inside in the first lateral groove, with the gate electrode filling the first lateral groove.

[0016] In some embodiments, the memory cell further includes a capacitor, the capacitor including a first capacitor electrode disposed on the side of the bit line away from the word line, the first capacitor electrode forming a second cylindrical structure extending in a first direction with an opening away from the semiconductor layer, the bottom wall of the second cylindrical structure being connected to the bottom wall of the first cylindrical structure.

[0017] In some embodiments, the capacitor further includes a first dielectric layer and a first sub-electrode, the first dielectric layer being distributed on the inner wall of the second cylindrical structure, and the first sub-electrode filling the second cylindrical structure.

[0018] In some embodiments, the semiconductor device further includes:

[0019] An isolation trench extending along a second direction and perpendicular to the substrate direction; and a second transverse trench extending along the second direction and communicating with the isolation trench and distributed between adjacent insulating layers; and a plurality of second transverse grooves extending along a first direction and spaced apart along the second direction and communicating with the second transverse trench and distributed between adjacent insulating layers.

[0020] Wherein, the second lateral groove exposes the bottom wall of the semiconductor layer; the first capacitor electrode is distributed on the inner wall of the second lateral groove; the first dielectric layer of the plurality of capacitors is connected to form an integral structure distributed on the inner wall of the second lateral groove where the first capacitor electrode is formed, as well as the inner wall of the second lateral trench and the isolation trench; the first sub-electrodes of the plurality of capacitors are connected to form an integral structure filling the second lateral groove, the second lateral trench and the isolation trench.

[0021] In some embodiments, the capacitor further includes a second dielectric layer and a second sub-electrode, the second sub-electrode surrounding the side surface of the second cylindrical structure via the second dielectric layer.

[0022] In some embodiments, the semiconductor device further includes: a fourth trench extending along a second direction and perpendicular to a substrate direction, the fourth trench exposing the side surface of a second cylindrical structure of a plurality of vertical columns of capacitors distributed along the second direction, the second sub-electrodes of the plurality of capacitors being connected to form an integral structure filling the trench, wherein a vertical column of capacitors includes a plurality of capacitors distributed along a direction perpendicular to the substrate.

[0023] This disclosure provides a method for manufacturing a semiconductor device, including:

[0024] A stacked structure comprising multiple alternating first insulating layers and sacrificial layers is formed on a substrate;

[0025] A plurality of first trenches extending in a first direction are formed and spaced apart along a second direction through the stacked structure perpendicular to the substrate direction, thereby forming a first dummy layer that fills the first trenches;

[0026] A plurality of first holes are formed penetrating the first dummy layer in a direction perpendicular to the substrate, and penetrating the first dummy layer in a second direction; the plurality of first holes are spaced apart in the second direction;

[0027] Etching removes the first insulating layer located between adjacent first holes and between adjacent sacrificial layers along the second direction;

[0028] A bit line is formed surrounding a plurality of sacrificial layers located between adjacent first holes along the second direction and extending along a direction perpendicular to the substrate;

[0029] A fifth trench extending in a second direction through the stacked structure perpendicular to the substrate is formed; the sacrificial layer is etched in a direction parallel to the substrate based on the fifth trench; a first lateral trench extending in a second direction between adjacent first insulating layers is formed; and a first lateral groove extending in a first direction between adjacent first insulating layers and adjacent first trenches is formed, communicating with the first lateral trench, the first lateral groove exposing the bit line; a semiconductor layer is formed distributed on the inner wall of the first lateral groove; and a gate electrode is formed filling the first lateral groove, the bit line surrounding the side surface of the semiconductor side and connected to the semiconductor layer.

[0030] In some embodiments, before forming bit lines that surround a plurality of sacrificial layers located between adjacent first vias along a second direction and extending along a direction perpendicular to the substrate, and before etching the sacrificial layers to form first lateral trenches extending along the second direction between adjacent first insulating layers, the method further includes:

[0031] The stacked structure is etched to form an isolation trench that penetrates the stacked structure in a direction perpendicular to the substrate and extends in a second direction. Based on the isolation trench, the sacrificial layer is etched to form a second lateral trench that communicates with the isolation trench and extends in a second direction between adjacent first insulating layers. A plurality of second lateral grooves that communicate with the second lateral trench, are located between adjacent first insulating layers, and are located between adjacent first trenches and extend in a first direction.

[0032] A first capacitor electrode is formed on the inner wall of the second transverse groove, and a first dielectric layer is formed on the inner wall of the second transverse groove, the inner wall of the second transverse trench, and the inner wall of the isolation trench. A first sub-electrode is formed to fill the second transverse groove, the second transverse trench, and the isolation trench. The first capacitor electrode is connected to the bottom wall of the semiconductor layer.

[0033] In some embodiments, the method further includes,

[0034] A fourth trench extending in the second direction is formed between the bit line and the isolation trench, exposing the side surface of the first capacitor electrodes in the same row of multiple layers.

[0035] A second dielectric layer is formed on the inner wall of the fourth trench and on the exposed side surface of the first capacitor electrode, and a second sub-electrode is formed to fill the fourth trench, the second sub-electrode surrounding the side surface of the first capacitor electrode.

[0036] In some embodiments, the formation of bit lines surrounding a plurality of sacrificial layers located between adjacent first vias along a second direction and extending along a direction perpendicular to the substrate includes:

[0037] A bitline structure layer is formed that covers the inner wall of the first hole but does not completely fill the first hole;

[0038] Etching removes the bit line structure layer on the bottom wall of the first hole;

[0039] A second insulating layer is formed to fill the first hole;

[0040] The first dummy layer is etched away to expose the first trench;

[0041] Based on the first trench etching of the bit line structure layer, the bit line structure layer is broken into multiple bit lines spaced apart by the second insulating layer along the second direction.

[0042] In some embodiments, forming the semiconductor layer distributed on the inner wall of the first transverse groove, and forming the gate electrode filling the first transverse groove, includes:

[0043] A semiconductor thin film, a gate insulating film, and a fifth conductive film are sequentially deposited in the first lateral trench and the first lateral groove, wherein the fifth conductive film fills the first lateral trench and the first lateral groove; the semiconductor thin film in the first lateral trench is etched away, while the gate insulating film and the fifth conductive film in the first lateral trench and the first lateral groove are retained, and the semiconductor thin film in the first lateral groove is retained, thereby forming a semiconductor layer, a gate insulating layer, and the gate electrode.

[0044] A sixth insulating film is deposited to fill the first lateral trench and the first lateral groove. The sixth insulating film in the first lateral trench is etched away. The insulating film in the first lateral groove is etched until the gate electrode is exposed, forming an isolation layer connected to the end face of the semiconductor layer.

[0045] A sixth conductive thin film is deposited to fill the first lateral trench, forming a word line, which is connected to the gate electrode.

[0046] This disclosure provides an electronic device, including any of the semiconductor devices described above, or a semiconductor device formed according to the manufacturing method of any of the semiconductor devices described above.

[0047] This application includes a semiconductor device and a method for manufacturing the same, as well as an electronic device. The semiconductor device includes: a plurality of memory cells stacked in different layers along a direction perpendicular to a substrate; bit lines extending through the memory cells in the different layers along a direction perpendicular to the substrate; each memory cell includes a transistor, the transistor including a semiconductor layer and a gate electrode, the semiconductor layer forming a first cylindrical structure extending in a first direction parallel to the substrate, the bit lines surrounding the side surface of the first cylindrical structure formed by the semiconductor layers of the plurality of memory cells and connected to the side surface of the first cylindrical structure; the gate electrode filling the first cylindrical structure and extending beyond the first cylindrical structure. The solution provided by the embodiments of this disclosure, where the bit lines surround the semiconductor layer, increases the contact area between the semiconductor layer and the bit lines, increases the channel width, and improves the transistor's on-state current.

[0048] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0049] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0050] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0051] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F Cross-sectional views of a semiconductor device along the AA', BB', CC', DD', EE', and FF' directions provided in some embodiments;

[0052] Figure 2A , Figure 2B , Figure 2C and Figure 2D Cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the first trench T are provided in some embodiments;

[0053] Figure 3A , Figure 3B , Figure 3C and Figure 3D Cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the first hole are provided in some embodiments;

[0054] Figure 4A , Figure 4B , Figure 4C and Figure 4D Cross-sectional views along the AA', BB', CC', and DD' directions after the exposed sacrificial layer is provided in some embodiments;

[0055] Figure 5A , Figure 5B , Figure 5C and Figure 5D Cross-sectional views along the AA', BB', CC', and DD' directions after the bitline structure layer is formed, as provided in some embodiments;

[0056] Figure 6A , Figure 6B , Figure 6C and Figure 6D Cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the second insulating layer are provided in some embodiments;

[0057] Figure 7A , Figure 7B , Figure 7C and Figure 7D Cross-sectional views along the AA', BB', CC', and DD' directions after bit lines are formed, provided in some embodiments;

[0058] Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E and Figure 8F Cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the second dummy layer are provided in some embodiments;

[0059] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E and Figure 9F Cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions respectively, provided in some embodiments after forming the isolation groove, the second transverse groove, and the second transverse recess;

[0060] Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E and Figure 10FCross-sectional views along the AA', BB', CC', DD', EE', and FF' directions respectively, provided in some embodiments after forming the first capacitor electrode, the first dielectric layer, and the first sub-electrode;

[0061] Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E and Figure 11F Cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after etching the second dummy layer, as provided in some embodiments;

[0062] Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E and Figure 12F Cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after the formation of the third trench are provided in some embodiments;

[0063] Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 13E and Figure 13F Cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after the formation of the second dielectric layer and the second sub-electrode, respectively, are provided in some embodiments.

[0064] Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E and Figure 14F Cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions respectively, provided in some embodiments after the formation of the fifth groove, the first transverse groove, and the first transverse recess;

[0065] Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 15E and Figure 15F Cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after the formation of the semiconductor layer, gate insulating layer, and gate electrode are provided in some embodiments.

[0066] Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 16E and Figure 16F The following are cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after the isolation layer has been formed, provided in some embodiments. Detailed Implementation

[0067] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0068] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0069] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0070] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0071] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0072] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0073] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0074] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0075] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0076] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0077] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.

[0078] In this embodiment of the disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0079] Figure 1A A cross-sectional view of a semiconductor device provided for some embodiments along the AA' direction parallel to the substrate. Figure 1B A cross-sectional view of a semiconductor device provided for some embodiments along the BB' direction parallel to the substrate. Figure 1C For along Figure 1A Cross-sectional view in the CC' direction. Figure 1D For along Figure 1A Cross-sectional view in the DD' direction. Figure 1E For along Figure 1A Cross-sectional view in the EE' direction. Figure 1F For along Figure 1A Cross-sectional views along the FF' direction, where AA' is a cross-sectional view parallel to the substrate through the semiconductor layer, BB' is a cross-sectional view parallel to the substrate but not through the semiconductor layer, and CC', DD', EE', and FF' are cross-sectional views perpendicular to the substrate at different locations on the semiconductor device. Figures 1A to 1F As shown, this disclosure provides a semiconductor device including a multilayer memory cell array and multiple bit lines 30 vertically stacked on a substrate 1. Each layer of the memory cell array may include a plurality of memory cells arranged in an array along a first direction X parallel to the substrate 1 and a second direction Y parallel to the substrate 1. The first direction X and the second direction Y may intersect. In some embodiments, the first direction X and the second direction Y may be perpendicular. The bit lines 30 may extend through the memory cells of different layers in a direction perpendicular to the substrate 1. Multiple memory cells stacked at the same position in different layers in a direction perpendicular to the substrate 1 are connected to the same bit line 30. Multiple memory cells in the same column of the same layer are respectively connected to multiple bit lines 30 spaced apart along the second direction Y.

[0080] In some embodiments, two adjacent memory cells along the first direction X are connected to different bit lines 30.

[0081] The word line 40 can extend along the second direction Y.

[0082] The storage unit can be a 1T1C storage unit or a storage unit with other structures.

[0083] Taking a 1T1C memory cell as an example, the memory cell may include a transistor and a capacitor connected to the transistor. The transistor and capacitor in the same memory cell may be distributed along a first direction X. The word line 40, the bit line 30, and the capacitor are distributed along the first direction X.

[0084] The transistor may include a semiconductor layer 23, which forms a first cylindrical structure extending along a first direction. The first cylindrical structure includes a bottom wall and a side surface, and the opening of the first cylindrical structure faces the word line 40. The bit line 30 surrounds and connects to the side surface of the first cylindrical structure of the semiconductor layer 23 of the vertically stacked memory cells. In the solution provided in this embodiment, the bit line 30 surrounds the semiconductor layer 23, and the large contact area between the bit line 30 and the channel increases the channel width, which can improve the on-state current of the transistor.

[0085] In some embodiments, the bit line 30 may completely or partially surround the semiconductor layer 23, i.e., along a direction parallel to the second direction Y and perpendicular to the substrate 1, the contact surface between the bit line 30 and the semiconductor layer 23 forms a closed structure, or an opening may exist. For example, for the topmost transistor, the bit line 30 partially surrounds the semiconductor layer 23, while for non-topmost transistors, the bit line 30 completely surrounds the semiconductor layer 23.

[0086] In some embodiments, the first cylindrical structure may include two side surfaces parallel to the substrate 1 and two side surfaces perpendicular to the substrate 1 and arranged opposite each other along the second direction Y. The two side surfaces arranged opposite each other along the second direction Y may have recessed regions, and the contact surface between the bit line 30 and the two side surfaces arranged opposite each other along the second direction Y is located in the recessed regions. However, the embodiments of this disclosure are not limited to this; the two side surfaces arranged opposite each other along the second direction Y may not have recessed regions. The solution provided in this embodiment increases the distance between adjacent BLs, reducing the coupling capacitance between adjacent BLs.

[0087] The word line 40 is connected to the gate electrode 26 of the transistors in the same column distributed along the second direction Y.

[0088] In some embodiments, the word line 40 and the gate electrode 26 are not integral structures; that is, the word line 40 and the gate electrode 26 are manufactured separately through different manufacturing steps. However, the embodiments disclosed herein are not limited to this, and the word line 40 and the gate electrode 26 may be integral structures.

[0089] In some embodiments, a gate insulating layer 24 is disposed between the gate electrode 26 and the semiconductor layer 23. The gate insulating layer 24 surrounds the gate electrode 26 and extends outside the first cylindrical structure to cover the side of the gate electrode 26 facing the semiconductor layer 23 on the side of the word line 40 facing the bit line 30. The gate insulating layer 24 may extend along a first direction X.

[0090] In some embodiments, the semiconductor device may further include an isolation layer 16 disposed between the word line 40 and the semiconductor layer 23, and connected to an end face of the semiconductor layer 23, surrounding the gate insulating layer 24. The isolation layer 16 isolates the word line 40 and the semiconductor layer 23.

[0091] In some embodiments, the semiconductor device includes a plurality of insulating and conductive layers alternately distributed from top to bottom along a direction perpendicular to the substrate; a first lateral trench extending along a second direction Y between adjacent insulating layers; and a plurality of first lateral grooves extending along a first direction and spaced apart along the second direction Y between adjacent insulating layers, communicating with the first lateral trenches; wherein the word line 40 is distributed in the first lateral trenches, the semiconductor layer 23, the isolation layer 16, the gate insulating layer 24, and the gate electrode 26 are sequentially distributed from the outside to the inside in the first lateral grooves, and the gate electrode 26 fills the first lateral grooves. The conductive layer may include the gate electrode 26, the semiconductor layer 23, and the word line 40, and the insulating layer may be an insulating film layer that spaced transistors of different layers between transistors distributed in different layers.

[0092] In some embodiments, such as Figure 1B As shown, the bit line 30 may include a first protrusion facing the word line 40 and a second protrusion away from the word line 40 disposed between adjacent semiconductor layers 23 along a direction perpendicular to the substrate 1.

[0093] In some embodiments, the capacitor includes a first capacitor electrode 41 disposed on the side of the bit line 30 opposite to the word line 40. The first capacitor electrode 41 may form a second cylindrical structure extending in a first direction X with an opening opposite to the semiconductor layer 23. The bottom wall of the second cylindrical structure is connected to the bottom wall of the first cylindrical structure. The first capacitor electrode 41 is multiplexed as one electrode of a transistor (either a source electrode or a drain electrode).

[0094] In some embodiments, the capacitor further includes a first dielectric layer 431 and a first sub-electrode 421, wherein the first dielectric layer 431 is distributed on the inner wall of the second cylindrical structure and the first sub-electrode 421 fills the second cylindrical structure.

[0095] In some embodiments, the semiconductor device may further include:

[0096] An isolation groove extending along a second direction Y through multiple insulating layers and multiple conductive layers; and a second transverse groove extending along a second direction Y and distributed between adjacent insulating layers in communication with the isolation groove; and a plurality of second transverse grooves extending along a first direction X and spaced apart along a second direction Y and distributed between adjacent insulating layers in communication with the second transverse groove.

[0097] In this embodiment, the second lateral groove exposes the bottom wall of the semiconductor layer 23; the first capacitor electrode 41 is distributed on the inner wall of the second lateral groove; the first dielectric layer 431 of the multiple capacitors are connected to form an integral structure distributed on the inner wall of the second lateral groove where the first capacitor electrode 41 is formed, as well as the inner wall of the second lateral trench and the isolation trench; the first sub-electrodes 421 of the multiple capacitors are connected to form an integral structure filling the second lateral groove, the second lateral trench and the isolation trench. Here, the multiple capacitors include multilayer capacitors in the same column. The solution provided in this embodiment can form the first capacitor electrode 41 of multiple capacitors at once, simplifying the process and reducing costs.

[0098] In some embodiments, the distance between the upper surface (the surface facing away from the substrate 1) and the lower surface (the surface facing the substrate 1) of the semiconductor layer 23 is the same as the distance between the upper surface and the lower surface of the first capacitor electrode 41.

[0099] In some embodiments, the capacitor may further include a second dielectric layer 432 and a second sub-electrode 422, the second sub-electrode 422 surrounding the side surface of the second cylindrical structure via the second dielectric layer 432. The solution provided in this embodiment, by providing electrodes both inside and outside the first capacitor electrode 41, can increase the facing area of ​​the capacitor, and by providing the second sub-electrode on the side surface of the first capacitor electrode, the capacitance of the capacitor is increased without increasing the occupied area.

[0100] In some embodiments, the semiconductor device may further include: a fourth trench extending along a second direction through a plurality of insulating layers, the fourth trench exposing the side surface of a second cylindrical structure of first capacitor electrodes of a plurality of vertically arranged capacitors distributed along the second direction, the second sub-electrodes of the plurality of capacitors being connected to form an integral structure filling the fourth trench, wherein a vertically arranged capacitor includes a plurality of capacitors distributed along a direction perpendicular to the substrate. The solution provided in this embodiment can form the second sub-electrodes of multiple capacitors in a single process, simplifying the process and reducing costs.

[0101] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. The "patterning process" mentioned in this embodiment includes deposition of a film layer, coating with photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of a film layer, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0102] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0103] 1) Formation of the first trench T1;

[0104] A first insulating film and a sacrificial layer film are sequentially deposited on a substrate 1 to form a stacked structure comprising a plurality of alternating first insulating layers 11 and sacrificial layers 10;

[0105] The stacked structure is etched from the top layer to the bottom layer along a direction perpendicular to the substrate 1 (the bottom first insulating layer 11 can be etched to a certain depth to expose the first insulating layer 11; or etched to expose the substrate 1) to form a plurality of first trenches T1, the first trenches T1 extending along the first direction X; the plurality of first trenches T1 are distributed at intervals along the second direction Y.

[0106] A first dummy layer film is deposited and smoothed to form a first dummy layer 91 filling the first trench T1; the first dummy layer 91 is flush with the topmost first insulating layer 11, such as... Figure 2A , Figure 2B , Figure 2C and Figure 2D As shown, where, Figure 2A , Figure 2B , Figure 2C and Figure 2D These are cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the first trench T1, provided in some embodiments.

[0107] In some embodiments, substrate 1 may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0108] In some embodiments, the first insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc. The materials of the subsequent second to seventh insulating films are similar and will not be described in detail.

[0109] In some embodiments, the sacrificial layer film may be a film layer that has an etching selectivity ratio with the first insulating film, such as silicon nitride (SiN).

[0110] In some embodiments, the first dummy layer film may be a film layer with an etching selectivity ratio to the first insulating film and the sacrificial layer film, such as polysilicon. The materials of the subsequent second and third dummy layer films are similar and will not be described in detail.

[0111] 2) Form the first hole K1;

[0112] The first dummy layer 91 is etched to form a first hole K1 that penetrates the first dummy layer 91 along a direction perpendicular to the substrate 1; a first hole K1 is formed in each first trench T1; and multiple first holes K1 in multiple first trenches T1 are distributed at intervals along the second direction Y.

[0113] In some embodiments, the first insulating layer 11 and the sacrificial layer 10 can be slightly etched along the second direction Y based on the first hole K1 to remove any remaining first dummy layer 91 on the two sidewalls of the first hole K1 that are opposite each other along the second direction Y. In this case, the size of the first hole K1 along the second direction Y is slightly enlarged, such as... Figure 3A , Figure 3B , Figure 3C and Figure 3D As shown, where, Figure 3A , Figure 3B , Figure 3C and Figure 3D These are cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the first hole K1, provided in some embodiments.

[0114] 3) Expose sacrificial layer 10;

[0115] Based on the lateral etching of the first hole K1 (along the direction parallel to the substrate 1), the first insulating layer 11 located between adjacent first holes K1 along the second direction Y is removed, so that the sacrificial layer 10 located between adjacent first holes K1 is in a suspended state. That is, the side of the sacrificial layer 10 located between adjacent first holes K1 facing the substrate 1, the side away from the substrate 1, and the two sides facing the adjacent first holes K1 are all exposed. The bottom of the first hole K1 exposes the substrate 1. At this time, the multiple first holes K1 are connected through the channels between the sacrificial layers 10 of adjacent layers (i.e., the channels located in the first insulating layer 11), such as... Figure 4A , Figure 4B, Figure 4C and Figure 4D As shown, where, Figure 4A , Figure 4B , Figure 4C and Figure 4D The images show cross-sectional views along the AA', BB', CC', and DD' directions after the exposed sacrificial layer 10 is provided in some embodiments. At this time, a portion of the first insulating layer 11 adjacent to the first hole K1 between adjacent first dummy layers 91 is also etched away.

[0116] 4) Form a bitline structure layer 30';

[0117] A first conductive film is deposited, which fills the gaps between adjacent sacrificial layers 10 along the second direction Y, but does not completely fill the first hole K1; that is, the first hole K1 is hollow.

[0118] The first conductive film on the bottom wall of the first hole K1 is etched away to form a bit line structure layer 30'; as follows: Figure 5A , Figure 5B , Figure 5C and Figure 5D As shown, where, Figure 5A , Figure 5B , Figure 5C and Figure 5D The images shown are cross-sectional views along the AA', BB', CC', and DD' directions after the bit line structure layer 30' has been formed, as provided in some embodiments. Subsequently, the bit line structure layer 30' can be etched to form multiple bit lines 30. Here, etching away the first conductive film on the bottom wall of the first hole K1 avoids the subsequent formation of multiple bit lines 30 connecting on the bottom wall of the first hole K1.

[0119] In some embodiments, the first conductive film may be one or more of the following different types of materials:

[0120] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal alloy containing these metals.

[0121] Alternatively, it can be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and aluminum-doped zinc oxide (AZO); or metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0122] Alternatively, it could be polycrystalline silicon, conductive doped semiconductor materials, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; or other materials that exhibit conductivity.

[0123] The materials of the second to sixth conductive films are similar to those of the first conductive film, and will not be described in detail here.

[0124] 5) Form a second insulating layer 12;

[0125] A second insulating film is deposited and smoothed to form a second insulating layer 12 filling the first hole K1; the second insulating layer 12 is flush with the first dummy layer 91; as shown... Figure 6A , Figure 6B , Figure 6C and Figure 6D As shown, where, Figure 6A , Figure 6B , Figure 6C and Figure 6D These are cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the second insulating layer 12, as provided in some embodiments.

[0126] 6) Form bit line 30;

[0127] Wet etching removes the first dummy layer 91 in the first trench T1;

[0128] Based on the first trench T1, the bit line structure layer 30' is wet-etched to form multiple bit lines 30 spaced apart along the second direction Y; the bit lines 30 extend in a direction perpendicular to the substrate 1, surround the sacrificial layer 10, adjacent bit lines 30 are separated by the second insulating layer 12, and along the first direction X, the bit lines 30 are disconnected from the first insulating layer 11, as shown below. Figure 7A , Figure 7B , Figure 7C and Figure 7D As shown, where, Figure 7A , Figure 7B , Figure 7C and Figure 7D These are cross-sectional views along the AA', BB', CC', and DD' directions after the bit line 30 is formed, provided in some embodiments. The dimension of the contact surface between the bit line 30 and the second insulating layer 12 along the first direction X is smaller than the dimension of the second insulating layer 12 along the first direction X.

[0129] 7) Form a second virtual layer 92;

[0130] A third insulating film is deposited to form a third insulating layer 13, which covers the inner wall of the first trench T1, the surface of the second insulating layer 12, and the surface of the bit line 30.

[0131] A second dummy layer film is deposited and smoothed to form a second dummy layer 92 filling the first trench T1 and the first hole K1; the surface of the second dummy layer 92 facing away from the substrate 1 is flush with the surface of the second insulating layer 12 facing away from the substrate 1; as shown Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E and Figure 8F As shown, where, Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E and Figure 8F These are cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after the formation of the second dummy layer 92, as provided in some embodiments.

[0132] 8) Forming an isolation groove T2, a second transverse groove T21, and a second transverse recess A2;

[0133] A fourth insulating film is deposited to form a fourth insulating layer 14 covering the structure formed above; the fourth insulating layer 14 serves as a hard mask layer for subsequent dry etching.

[0134] The stacked structure is etched from top to bottom along a direction perpendicular to the substrate 1 (etched to the bottommost first insulating layer 11 without penetrating the bottommost first insulating layer 11; or etched to the bottom where the substrate 1 is exposed), forming an isolation trench T2 extending along the second direction Y; the isolation trench T2 penetrates the stacked structure along a direction perpendicular to the substrate; the isolation trench T2 is located at the end outside the first trench T1 away from the first hole K1;

[0135] Based on the isolation trench T2, the sacrificial layer 10 is etched laterally to form a second lateral trench T21 and a second lateral groove A2; the second lateral trench T21 extends along the second direction Y, and the bottom wall exposes the third insulating layer 13; the bottom wall of the second lateral groove A2 exposes the sacrificial layer 10, and the sidewalls of the second lateral groove A2, which are arranged opposite each other along the second direction Y, expose the third insulating layer 13. A preset distance is maintained between the second lateral groove A2 and the first hole K1 to reserve space for subsequent transistor formation, such as... Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E and Figure 9F As shown, where, Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E and Figure 9FThe images show cross-sectional views along the directions AA', BB', CC', DD', EE', and FF' after the formation of the isolation groove T2, the second transverse groove T21, and the second transverse recess A2, respectively, according to some embodiments. A plurality of the second transverse recesses A2, distributed along the second direction Y, are spaced apart by a second dummy layer 92.

[0136] 9) Form the first capacitor electrode 41, the first dielectric layer 431, and the first sub-electrode 421;

[0137] A second conductive film is deposited, which covers the inner walls of the isolation trench T2, the second transverse trench T21, and the second transverse groove A2.

[0138] A third dummy layer film is deposited to form a third dummy layer that fills the isolation groove T2, the second transverse trench T21, and the second transverse recess A2;

[0139] Etching removes the third dummy layer in the isolation trench T2 and the second transverse trench T21;

[0140] The second conductive film not covered by the third dummy layer in the isolation trench T2 and the second lateral trench T21 is removed by etching, while the second conductive film in the second lateral groove A2 is retained, so that the second conductive films in different layers are disconnected, and the second conductive films in different second lateral grooves A2 in the same layer are disconnected, forming a plurality of first capacitor electrodes 41; the first capacitor electrodes 41 are reused as the first electrodes of the transistor.

[0141] The third dummy layer in the second transverse groove A2 is removed by etching; at this point, the third dummy layer has been completely removed.

[0142] A first dielectric film and a third conductive film are sequentially deposited and smoothed to form a first dielectric layer 431 and a first sub-electrode 421 of a capacitor. The first dielectric layer 431 covers the inner wall of the second lateral groove A2, the second lateral trench T21, and the inner wall of the isolation trench T2 where the first capacitor electrode 41 is formed. The first sub-electrode 421 fills the second lateral groove A2, the second lateral trench T21, and the isolation trench T2. The surface of the first sub-electrode 421 facing away from the substrate 1 is flush with the surface of the second dummy layer 92 facing away from the substrate 1. Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E and Figure 10F As shown, where, Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E and Figure 10FThe following are cross-sectional views along the AA', BB', CC', DD', EE' and FF' directions after the formation of the first capacitor electrode 41, the first dielectric layer 431 and the first sub-electrode 421 provided in some embodiments.

[0143] In some embodiments, the first sub-electrode 421 may include a first sub-layer 31 and a second sub-layer 32; the first sub-layer 31 may be a conductive material with good adhesion to other film layers, such as TiN, and the second sub-layer 32 may be a conductive material with low resistivity, such as tungsten. The first sub-layer 31 may cover the inner walls of the isolation trench T2, the second lateral trench T21, and the second lateral groove A2, and the second sub-layer 32 may fill the isolation trench T2, the second lateral trench T21, and the second lateral groove A2. In some embodiments, the first sub-layer 31 may fill the second lateral groove A2, cover the inner wall of the second lateral trench T21, and cover the inner wall of the isolation trench T2; the second sub-layer 32 may fill the second lateral trench T21 and fill the isolation trench T2.

[0144] In some embodiments, the first dielectric film may comprise one or more high-K dielectric materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include, but is not limited to, at least one of the following high-K materials: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.

[0145] The materials of the second dielectric film are similar to those of the first dielectric film, and will not be described in detail here.

[0146] 10) Etch the second dummy layer 92;

[0147] The second dummy layer 92 is etched, leaving the second dummy layer 92 in contact with the middle of the first capacitor electrode 41. This left-hand second dummy layer 92 is called the dummy sublayer 921. The dummy sublayer 921 has a first preset distance from the isolation trench T2 along the first direction X, and a second preset distance from the bottom wall of the first capacitor electrode 41 along the first direction X. Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E and Figure 11F As shown, where, Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E and Figure 11FCross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after etching the second dummy layer 92, as provided in some embodiments. This defines the region where the second sub-electrode 422 of the subsequent capacitor is formed. A certain distance is reserved between the second sub-electrode 422 and the bit line 30 to reduce coupling between the bit line 30 and the second sub-electrode 422.

[0148] 11) Formation of the third trench T3;

[0149] A fifth insulating film is deposited to form a fifth insulating layer 15, which fills the voids formed after the second dummy layer 92 is etched, i.e., fills the first trench T1.

[0150] A first hard mask film is deposited to form a first hard mask layer 61; in some embodiments, the first hard mask layer 61 may be a film layer with an etching selectivity ratio to the fifth insulating film, such as SiN;

[0151] The first hard mask layer 61 is etched to form a third trench T3. The third trench T3 extends along the second direction Y and completely exposes the surface of the dummy sublayer 921 facing away from the substrate 1. The dimension of the third trench T3 along the first direction X is larger than the dimension of the dummy sublayer 921 along the first direction X. That is, the third trench T3 also exposes the fifth insulating layer 15 adjacent to both ends of the dummy sublayer 921. The dimension of the third trench T3 along the first direction X is smaller than the dimension of the first capacitor electrode 41 along the first direction X. Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E and Figure 12F As shown, where, Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E and Figure 12F The images show cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after the formation of the third trench T3, as provided in some embodiments. The third trench T3 defines the region where the subsequent second sub-electrode 422 is located.

[0152] 12) Forming a second dielectric layer 432 and a second sub-electrode 422;

[0153] Wet etching removes the dummy sublayer 921;

[0154] The fifth insulating layer 15, the third insulating layer 13, and the first insulating layer 11 in the area defined by the third trench T3 are wet etched to form the fourth trench T4; the fourth trench T4 exposes part of the side surface of the first capacitor electrode 41 in the same column of multiple layers.

[0155] A second dielectric film and a fourth conductive film are sequentially deposited and smoothed to form a second dielectric layer 432 and a second sub-electrode 422 of the capacitor. The second dielectric layer 432 surrounds the first capacitor electrode 41 on the side surface of the fourth trench T4, and the second sub-electrode 422 surrounds the first capacitor electrode 41 on the side surface of the fourth trench T4 through the second dielectric layer 432, and fills the third trench T3 and the fourth trench T4. Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 13E and Figure 13F As shown, where, Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 13E and Figure 13F The images are cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after the formation of the second dielectric layer 432 and the second sub-electrode 422, respectively, provided in some embodiments.

[0156] In some embodiments, the second sub-electrode 422 may include a third sub-layer 33 and a fourth sub-layer 34; the third sub-layer 33 may be a conductive material with good adhesion to other film layers, such as TiN, and the fourth sub-layer 34 may be a conductive material with low resistivity, such as tungsten. That is, the deposition of the fourth conductive film may be achieved by sequentially depositing a first sub-conductive film and a second sub-conductive film to form the third sub-layer 33 and the fourth sub-layer 34. The third sub-layer 33 may fill the region between adjacent first capacitor electrodes 41 along the vertical direction. That is, the fourth sub-layer 34 may be distributed only between adjacent first capacitor electrodes 41 along the second direction Y.

[0157] 13) Form the fifth groove T5, the first transverse groove T51, and the first transverse recess A1;

[0158] The stacked structure is etched from the top layer to the bottom layer along a direction perpendicular to the substrate 1 (the etching stops on the substrate 1, and the bottom layer may or may not expose the substrate 1) to form a fifth trench T5 extending along the second direction Y; the fifth trench T5 penetrates the stacked structure along the second direction Y; the fifth trench T5 is located on the side of the bit line 30 away from the first capacitor electrode 41.

[0159] Based on the fifth trench T5 etching, the sacrificial layer 10 is removed to form a first lateral trench T51 and a first lateral groove A1; the first lateral trench T51 extends along the second direction Y, and the bottom wall exposes the third insulating layer 13; the bottom wall of the first lateral groove A1 exposes the first capacitor electrode 41, and the side wall of the first lateral groove A1 exposes the bit line 30; as Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E and Figure 14F As shown, where, Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E and Figure 14F These are cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after the formation of the fifth trench T5, the first lateral trench T51, and the first lateral recess A1, respectively, according to some embodiments. A transistor can subsequently be formed in the first lateral recess A1.

[0160] 14) Forming a semiconductor layer 23, a gate insulating layer 24, and a gate electrode 26;

[0161] A semiconductor thin film, a gate insulating film, and a fifth conductive film are sequentially deposited. The fifth conductive film, the gate insulating film, and the semiconductor thin film are then etched to form a semiconductor layer 23, a gate insulating layer 24, and a gate electrode 26. Specifically, the semiconductor thin film, the gate insulating film, and the fifth conductive film in the fifth trench T5 are etched away; the fifth conductive film, the gate insulating film, and the semiconductor thin film in the first lateral trench T51 are etched away; and a portion of the semiconductor thin film in the first lateral groove A1 is etched away. That is, the semiconductor layer 23 forms a first cylindrical structure. The bit line 30 surrounds the side surface of this first cylindrical structure. The gate insulating layer 24 and the gate electrode 26 extend from inside the first cylindrical structure to outside the first cylindrical structure formed by the semiconductor layer 23. This structure facilitates the spacing between the subsequently formed word line 40 and the semiconductor layer 23. Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 15E and Figure 15F As shown, where, Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 15E and Figure 15FThe figures are cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions respectively, provided in some embodiments after the formation of the semiconductor layer 23, the gate insulating layer 24, and the gate electrode 26. At this time, the semiconductor layer 23 is located in the first transverse groove A1, and the semiconductor layers 23 of different layers are disconnected, and the semiconductor layers 23 of different rows of the same layer are disconnected.

[0162] In some embodiments, the material of the semiconductor thin film may be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it may be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.

[0163] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0164] In some embodiments, the material of the metal oxide semiconductor layer or channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InWO4). Materials such as IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. As long as the leakage current of the transistor meets the requirements, it is acceptable. The specific requirements can be adjusted according to the actual situation.

[0165] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0166] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0167] In some embodiments, the material of the gate insulating layer 24 may comprise one or more high-K dielectric materials. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0168] 15) Form an isolation layer 16;

[0169] A sixth insulating film is deposited to fill the fifth trench T5, the first lateral trench T51, and the first lateral groove A1. The sixth insulating film in the fifth trench T5 and the first lateral trench T51 is etched away, while the sixth insulating film in the first lateral groove A1 is retained, forming an isolation layer 16. The isolation layer 16 covers the end face of the cylindrical structure formed by the semiconductor layer 23. Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 16E and Figure 16F As shown, where, Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 16E and Figure 16F The figures shown are cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after the isolation layer 16 is formed, according to some embodiments. The semiconductor layer 23 includes an end face and a bottom wall, as well as a side surface located between the end face and the bottom wall.

[0170] 16) Forming a character line 40;

[0171] A sixth conductive film is deposited to fill the fifth trench T5 and the first lateral trench T51. The sixth conductive film in the fifth trench T5 is etched away, while the sixth conductive film in the first lateral trench T51 is retained to form a word line 40.

[0172] A seventh insulating film is deposited to form a seventh insulating layer 17 that fills the fifth trench T5, as shown below. Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E and Figure 1F As shown.

[0173] The above manufacturing process is merely an example, and the embodiments disclosed herein are not limited thereto; manufacturing can be carried out in other ways.

[0174] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0175] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a plurality of memory cells distributed along a vertical substrate direction; a plurality of bit lines extending along a vertical substrate direction through the memory cells distributed along a vertical substrate direction; the memory cell comprises a transistor, the transistor comprises a semiconductor layer and a gate electrode, the semiconductor layer forms a first cylindrical structure extending along a first direction parallel to the substrate, the bit line surrounds a side surface of the first cylindrical structure formed by the semiconductor layer of the memory cell and is connected to the side surface of the first cylindrical structure; the gate electrode fills the first cylindrical structure and extends out of the first cylindrical structure.

2. The semiconductor device according to claim 1, wherein The semiconductor device further comprises a plurality of word lines distributed along a second direction parallel to the substrate, the word lines are connected to the gate electrodes of the transistors of the same column distributed along the second direction in the same layer, and the first direction and the second direction intersect.

3. The semiconductor device of claim 1, wherein The two side surfaces of the first cylindrical structure arranged opposite along the second direction have a recessed area, and the contact surface of the bit line with the two side surfaces arranged opposite along the second direction is located in the recessed area.

4. The semiconductor device according to claim 2, wherein A gate insulating layer is arranged between the gate electrode and the semiconductor layer, the gate insulating layer extends from inside the first cylindrical structure to outside the first cylindrical structure to cover the side of the gate electrode facing the semiconductor layer; The semiconductor device further comprises: an isolation layer arranged between the word line and the semiconductor layer and connected to the end surface of the semiconductor layer, which surrounds the gate insulating layer.

5. The semiconductor device of claim 4, wherein, The semiconductor device further comprises: a plurality of insulating layers and conductive layers alternately distributed from top to bottom along a direction perpendicular to the substrate, The conductive layer comprises the gate electrode, the semiconductor layer and the word line; a first lateral trench extending along the second direction is distributed between adjacent insulating layers, and a first lateral groove extending along the first direction is distributed between adjacent insulating layers and communicates with the first lateral trench; The word line is distributed in the first lateral trench, and the isolation layer, the semiconductor layer, the gate insulating layer and the gate electrode are sequentially distributed in the first lateral groove from outside to inside, and the gate electrode fills the first lateral groove.

6. The semiconductor device of claim 5, wherein, The memory cell further comprises a capacitor, the capacitor comprises a first capacitor electrode, the first capacitor electrode is arranged on the side of the bit line away from the word line, the first capacitor electrode forms a second cylindrical structure extending along the first direction with an opening away from the semiconductor layer, and the bottom wall of the second cylindrical structure is connected to the bottom wall of the first cylindrical structure.

7. The semiconductor device of claim 6, wherein, The capacitor further comprises a first dielectric layer and a first sub-electrode, the first dielectric layer is distributed on the inner wall of the second cylindrical structure, and the first sub-electrode fills the second cylindrical structure.

8. The semiconductor device of claim 7, wherein, The semiconductor device further comprises: an isolation groove extending along the second direction and perpendicular to the substrate direction; and a second lateral trench extending along the second direction is distributed between adjacent insulating layers and communicates with the isolation groove, and a plurality of second lateral grooves extending along the first direction and spaced apart along the second direction are distributed between adjacent insulating layers and communicate with the second lateral trench; The second lateral groove exposes the bottom wall of the semiconductor layer; the first capacitor electrode is distributed on the inner wall of the second lateral groove; the first dielectric layer of the plurality of capacitors is connected to form a unitary structure distributed on the inner wall of the second lateral groove where the first capacitor electrode is formed, and the inner wall of the second lateral groove and the isolation groove; the first sub-electrode of the plurality of capacitors is connected to form a unitary structure filling the second lateral groove, the second lateral groove and the isolation groove.

9. The semiconductor device of claim 8, wherein, The capacitor further comprises a second dielectric layer and a second sub-electrode, and the second sub-electrode surrounds the side surface of the second cylindrical structure through the second dielectric layer.

10. The semiconductor device of claim 9, wherein, The semiconductor device further comprises: a fourth groove extending along a second direction and perpendicular to the substrate direction, the fourth groove exposing the side surface of the second cylindrical structure of the first capacitor electrode of a plurality of vertically arranged capacitors distributed along the second direction, and the second sub-electrode of the plurality of capacitors is connected to form a unitary structure filling the fourth groove, wherein one vertical column of capacitors comprises a plurality of capacitors distributed along a direction perpendicular to the substrate direction.

11. A method of manufacturing a semiconductor device, characterized by Comprise: forming a stack structure comprising a plurality of first insulating layers and sacrificial layers arranged alternately on a substrate; forming a plurality of first trenches extending along a first direction and spaced along a second direction through the stack structure perpendicular to the substrate direction, and forming a first dummy layer filling the first trenches; forming a plurality of first holes through the first dummy layer along a direction perpendicular to the substrate direction and through the first dummy layer along the second direction; The plurality of first holes are spaced along the second direction; etching to remove the first insulating layer between the first holes adjacent along the second direction and between the adjacent sacrificial layers; forming a bit line surrounding the region between the first holes adjacent along the second direction and extending along a direction perpendicular to the substrate direction; forming a fifth trench extending along the second direction through the stack structure perpendicular to the substrate direction, based on the fifth trench, etching the sacrificial layer along a direction parallel to the substrate direction, forming a first lateral trench extending along the second direction between adjacent first insulating layers, and a first lateral groove extending along the first direction between adjacent first insulating layers and communicating with the first lateral trench, the first lateral groove exposing the bit line; forming a semiconductor layer distributed on the inner wall of the first lateral groove, and forming a gate electrode filling the first lateral groove, the bit line surrounding the side surface of the semiconductor side and connected with the semiconductor layer.

12. The method of manufacturing a semiconductor device according to Claim 11, wherein After forming a bit line surrounding the region between the first holes adjacent along the second direction and extending along a direction perpendicular to the substrate direction, etching the sacrificial layer to form a first lateral trench extending along the second direction between adjacent first insulating layers, further comprising: etching the stack structure to form an isolation groove extending through the stack structure along a direction perpendicular to the substrate and extending along a second direction, etching the sacrificial layer based on the isolation groove to form a second lateral trench extending along the second direction between adjacent first insulating layers and communicating with the isolation groove, and a plurality of second lateral recesses extending along the first direction between adjacent first trenches and between adjacent first insulating layers and communicating with the second lateral trench; forming a first capacitor electrode distributed on inner walls of the second lateral recesses, a first dielectric layer distributed on inner walls of the second lateral recesses, inner walls of the second lateral trench, and inner walls of the isolation groove, and a first sub-electrode filling the second lateral recesses, the second lateral trench, and the isolation groove, the first capacitor electrode being connected to bottom walls of the semiconductor layers.

13. The method of manufacturing a semiconductor device according to Claim 12, wherein The method further comprises, forming a fourth trench extending along the second direction and arranged between the bit line and the isolation groove to expose side surfaces of the first capacitor electrodes of the plurality of layers in the same column; forming a second dielectric layer distributed on inner walls of the fourth trench and exposed side surfaces of the first capacitor electrodes, and a second sub-electrode filling the fourth trench, the second sub-electrode surrounding the side surfaces of the first capacitor electrodes.

14. The method of manufacturing a semiconductor device according to any one of claims 11 to 13, wherein The forming the bit line surrounding the plurality of sacrificial layers in the region between the first holes adjacent along the second direction and extending along a direction perpendicular to the substrate comprises: forming a bit line structure layer covering inner walls of the first holes and not completely filling the first holes; etching and removing the bit line structure layer from bottom walls of the first holes; forming a second insulating layer filling the first holes; etching and removing the first dummy layer to expose the first trenches; etching the bit line structure layer based on the first trenches so that the bit line structure layer is broken into a plurality of bit lines spaced by the second insulating layer along the second direction.

15. The method of manufacturing a semiconductor device according to Claim 14, wherein The forming the semiconductor layer distributed on inner walls of the first lateral recesses and forming the gate electrode filling the first lateral recesses comprises: depositing, in the first lateral trench and the first lateral recess in sequence, a semiconductor thin film, a gate insulating thin film, and a fifth conductive thin film, the fifth conductive thin film filling the first lateral trench and the first lateral recess; etching and removing the semiconductor thin film in the first lateral trench, retaining the gate insulating thin film and the fifth conductive thin film in the first lateral trench and the first lateral recess, and retaining the semiconductor thin film in the first lateral recess, to form the semiconductor layer, the gate insulating layer, and the gate electrode; depositing a sixth insulating thin film filling the first lateral trench and the first lateral recess, etching and removing the sixth insulating thin film in the first lateral trench, and etching the insulating thin film in the first lateral recess to expose the gate electrode, to form an isolation layer connected to an end surface of the semiconductor layer; depositing a sixth conductive thin film to fill the first lateral trench, to form a word line connected to the gate electrode.

16. An electronic device, comprising: The semiconductor device comprises any one of the semiconductor devices as claimed in claims 1 to 10, or is formed by the manufacturing method of any one of the semiconductor devices as claimed in claims 11 to 15.

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