Semiconductor device, manufacturing method thereof, and memory system

Abstract

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and a memory system. The semiconductor device includes a metal layer and a first connection structure. The metal layer comprises a side part, an end part and a first extension part which are connected with one another, the side part extends along a first direction, the end part and the first extension part extend along a second direction intersecting with the first direction, and the end part and the first extension part are positioned at two ends of the side part in the first direction. The first connecting structure is located on the side, away from the end, of the first extending part and extends in the first direction, and the first connecting structure is connected with the first extending part.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and more particularly, to a semiconductor device, a manufacturing method of the semiconductor device, and a memory system. BACKGROUND

[0002] With the increasing demand for semiconductor device functions, the back-end structure and process of the semiconductor device are complex, the area overhead is large, which is not conducive to the improvement of integration, and the manufacturing cost is high. SUMMARY

[0003] In a first aspect, some embodiments of the present application provide a semiconductor device. The semiconductor device includes a metal layer and a first connection structure, the metal layer includes a side portion, an end portion and a first extension portion connected to each other, wherein the side portion extends along a first direction, the end portion and the first extension portion extend along a second direction intersecting the first direction, and the end portion and the first extension portion are located at both ends of the side portion in the first direction. The first connection structure is located on a side of the first extension portion away from the end portion and extends along the first direction, wherein the first connection structure is connected to the first extension portion.

[0004] In an example embodiment, the first extension portion surrounds a part of the side portion.

[0005] In an example embodiment, the semiconductor device further includes a second connection structure extending along the first direction, wherein a size of the second connection structure in the first direction is greater than a size of the first connection structure in the first direction.

[0006] In an example embodiment, a size of the first extension portion in the first direction is equal to a size of the first connection structure in the first direction, and a first end surface of the second connection structure away from the end portion is located on a side of the first extension portion away from the end portion.

[0007] In an example embodiment, the first connection structure and the second connection structure are made of the same material.

[0008] In an example embodiment, the semiconductor device further includes a pad structure, the pad structure is located on a side of the second connection structure close to the end portion and connected to the second connection structure.

[0009] In an example embodiment, the semiconductor device further includes a plurality of conductive pillars and an insulating layer. The plurality of conductive pillars are located in a space surrounded by the side portion and the end portion, wherein the conductive pillars extend along the first direction, and the insulating layer is located between the conductive pillars and the metal layer.

[0010] In an example embodiment, the semiconductor device further includes a plurality of transistors and a bit line structure. The plurality of transistors are located on a side of the plurality of conductive pillars away from the end portion, wherein a first active end of the transistor is connected to the conductive pillar. The bit line structure is located on a side of the plurality of transistors away from the plurality of conductive pillars, wherein a second active end of the transistor is connected to the bit line structure.

[0011] In an example embodiment, the transistor includes a semiconductor body extending along a first direction, a first end portion of the semiconductor body as the first active end connected to the conductive pillar, and a second end portion of the semiconductor body as the second active end connected to the bit line structure.

[0012] In an example embodiment, the semiconductor device further includes a peripheral circuit structure located on a side of the plurality of transistors away from the plurality of conductive pillars, wherein the first connection structure is connected to the peripheral circuit structure.

[0013] In a second aspect, some embodiments of the present application provide a memory system. The memory system includes a memory and a controller. The memory includes the semiconductor device as mentioned in any of the embodiments above. The controller is coupled to the memory and configured to control the memory to store data.

[0014] In a third aspect, some embodiments of the present application provide a method for manufacturing a semiconductor device. The method includes: forming a metal layer, wherein the metal layer includes a side portion, an end portion, and a first extension portion. The side portion extends along a first direction. The end portion and the first extension portion extend along a second direction intersecting the first direction. The end portion and the first extension portion are located at two ends of the side portion in the first direction. Forming a first connection structure on a side of the first extension portion away from the end portion, wherein the first connection structure extends along the first direction and is connected to the first extension portion.

[0015] In an example embodiment, forming the metal layer includes: forming an initial metal layer, wherein the initial metal layer includes a side portion, an end portion, and an initial extension portion. The initial extension portion extends along the second direction. The initial extension portion is located at one end of the side portion away from the end portion. Removing a portion of the initial extension portion, and the remaining initial extension portion is the first extension portion.

[0016] In an example embodiment, the method further includes: forming a second connection structure extending along the first direction on a side of the first extension portion away from the end portion, wherein a size of the second connection structure in the first direction is greater than a size of the first connection structure in the first direction.

[0017] In an example embodiment, the first connection structure and the second connection structure are formed in the same process.

[0018] In an example embodiment, the first connection structure and the second connection structure are formed in the same process, including: forming the first connection hole and the second connection hole on the side of the first extension part away from the end part through the same etching process; and filling the first connection hole and the second connection hole with the conductive material through the same thin film deposition process.

[0019] In an example embodiment, the manufacturing method further includes: forming a pad structure on the side of the second connection structure close to the end part, wherein the pad structure is connected with the second connection structure.

[0020] In an example embodiment, the manufacturing method further includes: forming a plurality of conductive pillars, wherein the plurality of conductive pillars are located in the space surrounded by the side part and the end part, and the conductive pillars extend along the first direction; and forming an insulating layer between the conductive pillars and the metal layer.

[0021] In an example embodiment, the manufacturing method further includes: forming a plurality of transistors, wherein the plurality of transistors are located on the side of the plurality of conductive pillars away from the end part, and a first active end of the transistor is connected with the conductive pillar; and forming a bit line structure on the side of the plurality of transistors away from the plurality of conductive pillars, wherein a second active end of the transistor is connected with the bit line structure.

[0022] In an example embodiment, forming the plurality of transistors includes: forming a plurality of semiconductor bodies, wherein the semiconductor bodies extend along the first direction, and a first end part of the semiconductor body serves as the first active end and is connected with the conductive pillar, and a second end part of the semiconductor body serves as the second active end and is connected with the bit line structure.

[0023] In an example embodiment, the manufacturing method further includes: connecting a peripheral circuit structure on the side of the plurality of transistors away from the plurality of conductive pillars.

[0024] In an example embodiment, the manufacturing method further includes: forming a semiconductor layer on the side of the plurality of semiconductor bodies in the second direction; and forming a first insulating structure penetrating through the semiconductor layer in the first direction; wherein forming the first connection structure on the side of the first extension part away from the end part includes: forming the first connection structure through the first insulating structure. BRIEF DESCRIPTION OF DRAWINGS

[0025] Other features, objects, and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments, read in conjunction with the accompanying drawings. In the drawings:

[0026] Figure 1 is a cross-sectional schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0027] Figure 2 is a flowchart schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0028] Figures 3A to 31 This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application during the manufacturing process;

[0029] Figures 4A to 4F This is a cross-sectional schematic diagram of a semiconductor device during the manufacturing process according to another embodiment of this application;

[0030] Figure 5 This is a schematic block diagram of a system with a memory system provided in the embodiments of this application; and

[0031] Figure 6A and Figure 6B This is a schematic block diagram of a memory system provided in an embodiment of this application. Detailed Implementation

[0032] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first connection structure discussed herein may also be referred to as the second connection structure, and vice versa.

[0034] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0035] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0036] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0037] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0038] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or can be inferred from the context.

[0039] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0040] Some embodiments of this application provide a semiconductor device. Figure 1 This is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this application. It should be noted that the D1 direction (corresponding to the first direction), D2 direction (corresponding to the second direction), and D3 direction (corresponding to the third direction) in each figure illustrate the spatial relationship of the components in the semiconductor device. For example, the D1 direction may be the extension direction of a side portion, and the D2 and D3 directions may be two directions that intersect (e.g., are perpendicular) to each other on a plane that intersects (e.g., is perpendicular) to the D1 direction. For example, the D2 direction may be the extension direction of an end portion and a first extension. Throughout this application, the same concepts will be used to describe the spatial relationship of the components in the semiconductor device.

[0041] like Figure 1 As shown, the semiconductor device 100 may include a metal layer 111 and a first connection structure 112. The metal layer 111 may include interconnected sides 1111, ends 1112, and a first extension 1113. The sides 1111 extend along a direction D1. The ends 1112 and the first extension 1113 extend along a direction D2, intersecting the direction D1. The ends 1112 and the first extension 1113 may be located at opposite ends of the sides 1111 in the direction D1. The first connection structure 112 may be located on the side of the first extension 1113 opposite to the ends 1112 and extends along the direction D1. The first connection structure 112 may be connected to the first extension 1113.

[0042] In some exemplary embodiments, the metal layer does not have a first extension and needs to be led out using an end portion. Compared to this exemplary embodiment, the semiconductor device 100 provided in this application embodiment, by adding a first extension 1113 to the metal layer 111, and having the first connection structure 112 lead out the metal layer 111 from the side of the first extension 1113 away from the end portion 1112, can reduce the difficulty of winding, optimize the downstream structural layout, and save area consumption.

[0043] In some embodiments, the side portion 1111, the end portion 1112, and the first extension layer 1113 may be an integral structure. For example, when the semiconductor device 100 is in Figure 1 In the illustrated placement position, the side portion 1111 and the end portion 1112 can generally form a cup-shaped structure with an opening facing downwards, and the first extension 1113 extends outwards at the opening edge of the cup-shaped structure. For example, the first extension 1113 can surround a portion of the side portion 1111. The outward extension distance of the first extension 1113 can be determined according to the dimensions of the first connecting structure 112. This application does not impose specific limitations on the extension dimensions of the first extension 1113 and / or the shape of the first extension 1113 in the direction perpendicular to D1.

[0044] In some embodiments, the metal layer 111 may further include a second extension 1114. The second extension 1114 may be located at one end of the side portion 1111 that is away from the end portion 1112 in the D1 direction. For example, the second extension 1114 may also extend outward at the opening edge of the cup-shaped structure formed by the side portion 1111 and the end portion 1112. The second extension 1114 may surround another portion of the side portion 1111 that is not surrounded by the first extension 1113. The extension dimension of the second extension 1114 may be smaller than the extension dimension of the first extension 1113. The side portion 1111, the end portion 1112, the first extension layer 1113, and the second extension 1114 may be an integral structure.

[0045] In some embodiments, the material of the metal layer 111 may include one or more of tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable metallic material. For example, the metal layer 111 may be made of a single material, such as tungsten.

[0046] In some embodiments, the first connection structure 112 may be generally columnar and contact the first extension 1113. The material of the first connection structure 112 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material.

[0047] In some embodiments, the semiconductor device 100 may further include a plurality of conductive pillars 113 and an insulating layer 114. The plurality of conductive pillars 113 may be located in the space enclosed by the side portion 1111 and the end portion 1112. A single conductive pillar 113 may extend along the D1 direction. For example, the plurality of conductive pillars 113 may be arranged in an array along the D2 and D3 directions. A single conductive pillar 113 may be a solid structure or a hollow structure. In the case of a hollow conductive pillar 113, the middle portion of the conductive pillar 113 may serve as a support structure. The end face of each conductive pillar 113 facing away from the end portion 1112 may be flush with the surface of the first extension 1113 facing away from the end portion 1112. Each conductive pillar 113 may have a spacing distance from the end portion 1112 in the D1 direction. The insulating layer 114 may be located between the metal layer 111 and the conductive pillars 113. For example, the insulating layer 114 may cover the conductive pillars 113. Optionally, the semiconductor device 100 may further include a conductive layer 115. The conductive layer 115 may cover the insulating layer 114 and fill the space between the metal layer 111 and the insulating layer 114. Alternatively, the semiconductor device 100 may not have the conductive layer 115, and the metal layer 111 may cover the insulating layer 114 and fill the space between the conductive pillars 113 covered by the insulating layer 114.

[0048] In some embodiments, the material of the conductive pillar 113 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, silicon, germanium silicon, or any other suitable conductive material. The material of the insulating layer 114 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials, or any other suitable insulating material. High dielectric materials may include, but are not limited to, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, and zirconium oxide. The material of the conductive layer 115 may be different from that of the metal layer 111. The material of the conductive layer 115 may include titanium, titanium nitride, tantalum, tantalum nitride, silicon, germanium, germanium silicon, or any other suitable one or more non-metallic conductive materials.

[0049] In some embodiments, conductive post 113, insulating layer 114, and conductive layer 115 (or conductive layer 115 and metal layer 111) may constitute a capacitor C. Conductive post 113 may be the first electrode of capacitor C. Conductive layer 115 (or conductive layer 115 and metal layer 111) may be the second electrode of capacitor C. Multiple capacitors C may be located in the space enclosed by side portion 1111 and end portion 1112, and the second electrodes of multiple capacitors C may be connected to each other. For example, in the operating state, the second electrodes of multiple capacitors C may be subjected to the same voltage.

[0050] In some embodiments, the semiconductor device 100 may further include a plurality of transistors T and a bit line structure 116. The plurality of transistors T may be located on the side of the plurality of conductive pillars 113 opposite to the end 1112. A first active terminal of the transistor T is connected to the conductive pillar 113. The bit line structure 116 may be located on the side of the plurality of transistors T opposite to the plurality of conductive pillars 113. A second active terminal of the transistor T may be connected to the bit line structure 116. For example, the transistor T may be a field-effect transistor. The first active terminal may be one of the source and drain, and the second active terminal may be the other of the source and drain. For example, the first active terminal may be the source, and the second active terminal may be the drain. The plurality of transistors T may correspond one-to-one with a plurality of capacitors C. The capacitors C and the transistors T may constitute a DRAM memory cell. The bit line structure 116 may extend along the D2 direction. The plurality of bit line structures 116 may be spaced apart along the D3 direction. The material of bit line structure 116 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, metal silicide, or any other suitable conductive material. Each of a number of transistors T arranged in the D2 direction is connected to one bit line structure 116.

[0051] In some embodiments, transistor T may include a semiconductor body 117. For example, semiconductor body 117 may be a columnar structure. Semiconductor body 117 may extend along the D1 direction and have a first end and a second end in the D1 direction. The first end may be close to the conductive post 113 and may be connected to the conductive post 113 as a first active end. The second end may be close to the bit line structure 116 and may be connected to the bit line structure 116 as a second active end. The material of semiconductor body 117 may include silicon, germanium, germanium-silicon, or any other suitable semiconductor material. For example, semiconductor body 117 is silicon. The bit line structure 116 and capacitor C are disposed on both sides of the extending direction of semiconductor body 117 (i.e., the D1 direction), which can further save area overhead and improve the planar integration of memory cells.

[0052] In some embodiments, the semiconductor device 100 may further include a capacitor connection structure 120. The capacitor connection structure 120 may be located between the conductive pillar 113 and the semiconductor body 117. For example, the capacitor connection structure 120 may be generally pillar-shaped, with its two end faces in the D1 direction contacting the conductive pillar 113 and the semiconductor body 117, respectively. The material of the capacitor connection structure 120 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, metal silicide, or any other suitable conductive material.

[0053] In some embodiments, the semiconductor device 100 may further include a gate structure 118 and a gate dielectric layer 119. The gate structure 118 may be located on at least one side of the semiconductor body 117 in the D2 and D3 directions, and extend along the D3 direction. For example, the gate structure 118 may be located on one or both sides of the semiconductor body 117 in the D2 direction, and furthermore, the gate structure 118 may be located on one or both sides of the semiconductor body 117 in the D3 direction. The gate dielectric layer 119 may be located between the gate structure 118 and the semiconductor body 117. For example, each of a number of semiconductor bodies 117 arranged in the D3 direction is connected to one gate structure 118. The material of the gate structure 118 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material. The material of the gate dielectric layer 119 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials, or any other suitable insulating materials.

[0054] In some embodiments, the semiconductor device 100 may further include a peripheral circuit structure 121. The peripheral circuit structure 121 may be located on the side of the plurality of transistors T opposite to the plurality of conductive pillars 113. For example, the peripheral circuit structure 121 may include a plurality of peripheral devices. The plurality of peripheral devices may be arranged in a plane perpendicular to the D1 direction. The types of peripheral devices may include, but are not limited to, field-effect transistors (e.g., planar field-effect transistors or fin field-effect transistors), diodes, resistors, capacitors, other active devices, or other passive devices. Some of the plurality of peripheral devices may be used to form any suitable digital, analog, and / or mixed-signal functional circuitry supporting an array of memory cells, such as row decoders (or word line drivers), column decoders (or bit line drivers), page buffers (or sense amplifiers), voltage generators, logic control circuits, input / output (I / O) circuits, and data buses, etc. In the semiconductor device 100, a first connection structure 112 is connected to the peripheral circuit structure 121. For example, the first connection structure 112 can be connected to the peripheral circuit structure 121 via interconnect lines 122 extending along the D2 direction and / or the D3 direction, and interconnect channels 123 extending along the D3 direction. The first connection structure 112 can be used to transmit signals with the peripheral circuit structure 121. For example, the peripheral circuit structure 121 transmits signals for controlling the metal layer 111 through the first connection structure 112. It should be noted that... Figure 1 The number of interconnects 122 and interconnect channels 123 shown is merely an example; in other examples, there may be multiple interconnects 122 and interconnect channels 123, which may be alternately arranged in the D1 direction.

[0055] In some embodiments, the semiconductor device 100 may further include a second connection structure 124. The second connection structure 124 may extend along the D1 direction. The dimension of the second connection structure 124 in the D1 direction is larger than the dimension of the first connection structure 112 in the D1 direction. For example, the second connection structure 124 may be generally columnar. The second connection portion 124 may have a first end face 1241 located on the side of the first extension 1113 facing away from the end portion 1112, and a second end face 1242 located on the side of the end face 1112 facing away from the first extension 1113. The dimension l1 of the first end face 1241 of the second connection structure 124 and the first extension 1113 in the D1 direction is equal to the dimension l2 of the first connection structure 112 in the D1 direction. In other words, the first end face 1241 of the second connection structure 124 may be substantially flush with the end face of the first connection structure 112 that does not contact the first extension 1113 (e.g., with an error of less than ±10%). Therefore, during the manufacturing process of the first connecting structure 112 and the second connecting structure 124, they can be formed from the side of the first extension 1113 away from the end 1112 through the same process, thereby optimizing the process and saving manufacturing costs.

[0056] In some embodiments, the first end face 1241 of the second connection structure 124 may also be connected to the peripheral circuit structure 121 via one or more interconnect lines 122 and one or more interconnect channels 123. The second connection structure 124 can be used to transmit signals with the peripheral circuit structure 121.

[0057] In some embodiments, the material of the first connection structure 112 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material. For example, the first connection structure 112 and the second connection structure 124 may be made of the same material and may be manufactured in the same process.

[0058] In some embodiments, a portion of the first connection structure 112 and a portion of the second connection structure 124 may pass through the semiconductor layer 125. When the semiconductor device 100 is in... Figure 1 In the shown placement, the semiconductor layer 125 can be at approximately the same height as the plurality of semiconductor bodies 117 relative to the peripheral circuit structure 121. The semiconductor layer 125 and the semiconductor bodies 117 can be separated from each other. The semiconductor layer 125 and the plurality of semiconductor bodies 117 can be formed by etching the same substrate. Thus, the semiconductor bodies 117 and the semiconductor layer 125 can be made of the same material.

[0059] In some embodiments, the semiconductor device 100 may further include a pad structure 126. The pad structure 126 may be located on the side of the second connection structure 124 near the end 1112 and connected to the second connection structure 124. For example, the second end face 1242 of the second connection structure 124 may contact the pad structure 126. The material of the pad structure 126 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material. The pad structure 126 can be used to connect to external devices and transmit signals. It should be noted that the number of pad structures 126 may be one or more; this application does not impose a specific limitation on this, and the number can be set according to actual needs.

[0060] Some embodiments of this application also provide a method for manufacturing a semiconductor device. Figure 2 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 2 As shown, a semiconductor device manufacturing method 200 (hereinafter referred to as manufacturing method 200) may include the following steps.

[0061] S210, forming a metal layer, wherein the metal layer includes interconnected sides, ends and a first extension, the sides extending along a first direction, the ends and the first extension extending along a second direction intersecting the first direction, the ends and the first extension being located at both ends of the sides in the first direction.

[0062] S220, a first connecting structure is formed on the side of the first extension away from the end, wherein the first connecting structure extends along a first direction and is connected to the first extension.

[0063] According to the manufacturing method provided in the embodiments of this application, a metal layer with a first extension is formed, which enables a first connecting structure extending along a first direction to connect with the first extension on the side opposite to the end, thereby leading out the metal layer, reducing the difficulty of winding, optimizing the subsequent process and structural layout, and saving area consumption.

[0064] Figures 3A to 31 This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application during the manufacturing process. The following is in conjunction with... Figures 3A to 31 A manufacturing method 200 including steps S210 and S220 will be described by way of example.

[0065] S210

[0066] Figure 3A The intermediate structure 300a is shown after the formation of the initial metal layer 311'. Figure 3B The intermediate structure 300b is shown after the metal layer 311 is formed. Figure 3C The intermediate structure 300c is shown after the formation of the insulating cover layer 329.Figure 3D The intermediate structure 300d is shown after the connecting load-bearing structure 330.

[0067] In some implementations, such as Figure 3A and Figure 3B As shown, prior to forming the metal layer 311, the manufacturing method 200 may further include forming a plurality of transistors T. For example, forming a plurality of transistors T may include forming a plurality of semiconductor bodies 317. Each semiconductor body 317 may extend along the D1 direction and has a first end and a second end in the D1 direction. The first end may be away from the unetched semiconductor layer 325, and the second end may be close to the unetched semiconductor layer 325. The first end may serve as a first active terminal (e.g., one of a source and a drain), and the second end may serve as a second active terminal (e.g., the other of a source and a drain). For example, the first active terminal may be a source, and the second active terminal may be a drain. The plurality of semiconductor bodies 317 may be formed by etching (e.g., dry etching and / or wet etching) an initial semiconductor layer (not shown). For example, the initial semiconductor layer may extend continuously along the D2 and D3 directions. The initial semiconductor layer may be a substrate, such as a silicon substrate. The initial semiconductor layer may have dimensions in the D1 direction. Multiple semiconductor bodies 317 are formed by etching an initial semiconductor layer to form multiple trenches extending along the D2 direction and multiple trenches extending along the D3 direction, thereby forming multiple semiconductor bodies 317 arranged in an array along the D2 direction.

[0068] When the intermediate structure 300a is in Figure 3A In the illustrated placement, the second ends of each of the semiconductor bodies 317 arranged along the D2 direction can be connected to each other by an unetched semiconductor layer 325. Furthermore, during the formation of the plurality of semiconductor bodies 317, a portion of the initial semiconductor layer is not etched, thus remaining on one side of the plurality of semiconductor bodies 317 in the D2 direction, and may be referred to as semiconductor layer 325. During the etching process, the semiconductor layer 325 can be separated from the plurality of semiconductor bodies 317 through patterning design.

[0069] Optionally, a first insulating structure 327 and a second insulating structure 328 penetrating the semiconductor layer 325 in the D1 direction can also be formed by etching and thin film deposition processes. The first insulating structure 327 can be connected to the first interconnect structure 312 to be formed (see reference). Figure 3G The second insulating structure 328 can be penetrated by the second connecting structure 324 to be formed (see reference). Figure 3G (passed through)

[0070] In some embodiments, after forming a plurality of semiconductor bodies 317, a gate structure 318 and a gate dielectric layer 319 may be formed. The gate structure 318 may be formed on at least one side of the semiconductor body 317 in the D2 and D3 directions and extends along the D3 direction. The gate dielectric layer 319 may be formed between the gate structure 318 and the semiconductor body 317.

[0071] In some embodiments, after forming the plurality of transistors T and before forming the metal layer 311, the manufacturing method 200 may further include forming a plurality of conductive pillars 313. Each conductive pillar 313 may extend along the D1 direction. For example, each conductive pillar 313 may be connected to a first end of each semiconductor body 317. Optionally, after forming the plurality of semiconductor bodies 317, a plurality of capacitor connection structures 320 may also be formed. Each capacitor connection structure 320 may be connected (e.g., contacted) to a first end of each semiconductor body 317. The plurality of conductive pillars 313 may be connected (e.g., contacted) to each capacitor connection structure 320.

[0072] In some embodiments, an insulating layer 314 covering each conductive post 313 can be formed by a thin-film deposition process. Alternatively, a conductive layer 315 covering the insulating layer 314 can be formed by a thin-film deposition process. For example, the conductive layer 315 can fill between the individual conductive posts 313 covered by the insulating layer 314 and can be used to provide a relatively flat surface that is generally perpendicular to the D1 direction.

[0073] The process of forming the metal layer 311 in step S210 is illustrated below with an example.

[0074] In some implementations, such as Figure 3A As shown, the initial metal layer 311' can be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The initial metal layer 311' may include interconnected sides 3111, ends 3112, and initial extensions 3113'. A plurality of conductive pillars 313 are located within the space enclosed by the sides 3111 and ends 3112. For example, the initial extension 3113' may surround the sides 3111 outside the space enclosed by the sides 3111 and ends 3112. When the intermediate structure 300a is in... Figure 3AIn the shown placement position, the initial extension 3113' can be located above the first insulating structure 327 and the second insulating structure 328. Optionally, if the manufacturing method 200 does not include the step of forming the conductive layer 315, the initial metal layer 311' can also fill between the individual conductive pillars 313 covered by the insulating layer 314. Thus, as described above, the insulating layer 314 can be formed between the metal layer 311 and the conductive pillars 313.

[0075] Next, as Figure 3A and Figure 3B As shown, an etching process (e.g., dry etching and / or wet etching) can be used to remove a portion of the initial extension 311', and the remaining initial extension 311' can be the first extension 3113. For example, when the intermediate structures 300a and 300b are in Figure 3A and Figure 3B In the illustrated placement position, the portion of the initial extension 3113' located above the first insulating structure 327 can be removed by patterning, allowing the first extension 3113 to surround a portion of the side portion 3111. Optionally, during the formation of the first extension 3113, another portion of the initial extension 3113' surrounding the side portion 3111 (this portion is not surrounded by the first extension 3113) can also be retained, thereby forming a second extension 3114. The extension dimension of the second extension 3114 can be smaller than the extension dimension of the first extension 3113. For example, the first extension 3113 and the second extension 3114 can be formed using the same mask.

[0076] In some implementations, such as Figure 3C As shown, when the intermediate structure 300c is in Figure 3C In the illustrated placement position, after forming the metal layer 311, an insulating capping layer 329 can be formed over the metal layer 311 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The insulating capping layer 329 can be used to provide a relatively flat surface that is generally perpendicular to the D1 direction. The material of the insulating capping layer 329 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. For example, the material of the insulating capping layer 329 may be silicon oxide.

[0077] In some implementations, such as Figure 3D As shown, the manufacturing method 200 may further include connecting a support structure 330 to the side of the end 3112 opposite to the first extension 3113. For example, the support structure 330 may contact a relatively flat surface of the insulating cover layer 329. The support structure 330 and the insulating cover layer 329 may be connected in an easily removable manner. The support structure 330 may be used to provide mechanical support during the manufacturing process.

[0078] S220

[0079] Figure 3E The intermediate structure 300e is shown after the bit line structure 316 is formed. Figure 3F An intermediate structure 300f is shown after the formation of the first connecting hole 331 and the second connecting hole 332. Figure 3G The intermediate structure 300g is shown after the formation of the first connecting structure 312 and the second connecting structure 324. Figure 3H The intermediate structure 300h is shown after the peripheral circuit structure 321 is connected. Figure 3I The semiconductor device 300 is shown after the pad structure 326 is formed.

[0080] In some embodiments, when forming the first connection structure 312 (see reference) Figure 3G Prior to this, manufacturing method 200 may also include the step of forming bit line structure 316. For example... Figure 3D and Figure 3E As shown, it can be Figure 3D The intermediate structure 300d shown is flipped 180° so that the support structure 330 is below. Further, chemical mechanical polishing (CMP) and / or etching processes can be used to remove the semiconductor layer 325 connected to the second ends of the plurality of semiconductor bodies 317, and a bit line structure 316 is formed on the side of the plurality of semiconductor bodies 317 opposite to the plurality of conductive pillars 313, such that the second ends of some semiconductor bodies 317 arranged in the D2 direction are connected to the same bit line structure 316.

[0081] In some implementations, such as Figure 3E and Figure 3F As shown, an etching process (dry etching and / or wet etching) can be used to form a first connecting hole 331 and a second connecting hole 332 on the side of the first extension 3113 opposite to the end 3112. Both the first connecting hole 331 and the second connecting hole 332 can extend along the D1 direction. For example, the first connecting hole 331 can pass through the first insulating structure 327 to the first extension 3113. The second connecting hole 332 can pass through the second insulating structure 328 and the insulating cover layer 329 to the support structure 330. By pre-forming the first insulating structure 327 and the second insulating structure 328, and when the materials of the first insulating structure 327, the second insulating structure 328, and the insulating cover layer 329 are the same, the first connecting hole 331 and the second connecting hole 332 can be formed by etching the same material, thereby helping to reduce the etching difficulty.

[0082] In some embodiments, the first connection hole 331 and the second connection hole 332 can be formed in the same etching process. For example, the first connection hole 331 and the second connection hole 332 can be formed using the same photomask for photolithography and etching, thereby saving process costs.

[0083] Furthermore, such as Figure 3F and Figure 3G As shown, conductive material can be filled into the first connection hole 331 and the second connection hole 332 using CVD, PVD, ALD, or any combination thereof to form the first connection structure 312 and the second connection structure 324. For example, filling the first connection hole 331 and the second connection hole 332 with conductive material can be done in the same thin film deposition process, thereby improving manufacturing efficiency and saving process costs.

[0084] After the above-mentioned process, the first connecting structure 312 and the second connecting structure 324 can be formed in the same process on the side of the first extension 3113 away from the end 3112, and the dimension of the second connecting structure 324 in the D1 direction can be larger than the dimension of the first connecting structure 312 in the D1 direction.

[0085] In some implementations, such as Figure 3G and Figure 3H As shown, after forming the first connection structure 312 and the second connection structure 324, interconnect lines 322 and interconnect channels 323, respectively connected to the first connection structure 312 and the second connection structure 324, may be formed. For example, at least one interconnect line 322 and at least one interconnect channel 323 may be formed alternately along the D1 direction. The interconnect line 322 may extend along the D2 direction and / or the D3 direction. The interconnect channel 323 may extend along the D3 direction.

[0086] In some implementations, such as Figure 3H As shown, the manufacturing method 200 also includes connecting a peripheral circuit structure 321 to the side of the plurality of semiconductor bodies 317 opposite to the plurality of conductive pillars 313. The internal structure of the peripheral circuit structure 321 has been described above and will not be repeated here. For example, the peripheral circuit structure 321 may be connected to... Figure 3G The intermediate structure 300g shown is manufactured in parallel, thereby improving manufacturing efficiency and reducing the mutual influence of thermal effects during manufacturing. For example, the peripheral circuit structure 321 can be connected to... (The sentence is incomplete and requires more context to translate accurately.) Figure 3G The intermediate structure 300g shown is connected to form the intermediate structure 300h. The "bonding technology" referred to in this application may include, but is not limited to, hybrid bonding, anodic bonding, melt bonding, eutectic bonding, etc.

[0087] In some implementations, such as Figure 3H and Figure 3IAs shown, the manufacturing method 200 may further include the step of flipping the intermediate structure 300h another 180° and removing the carrier structure 330. This exposes the second connection structure 324 on the surface of the insulating cover layer 329 facing away from the peripheral circuit structure 321. Further, a pad structure 326 may be formed on the side of the second connection structure 324 near the end 3112. The pad structure 326 is connected (e.g., in contact) to the second connection structure 324.

[0088] Figures 4A to 4F This is a cross-sectional schematic diagram of the semiconductor device provided in another embodiment of this application during the manufacturing process. For example... Figure 4A As shown, the formed metal layer 411 includes a side portion 4111 and an end portion 4112, but does not include, for example, the side portion 4111 and the end portion 4112. Figure 3B The first extension 3113 is shown. (See example...) Figure 4B As shown, when the intermediate structure 400b is in Figure 4B In the shown placement position, a third connection hole 433 extending along the D1 direction can be formed from above the metal layer 411. Further, as... Figure 4B and Figure 4C As shown, conductive material can be filled into the third connection hole 433 to form the third connection structure 434. Next, as... Figure 4C and Figure 4D As shown, the peripheral circuit structure 421 can be connected above the third connection structure 434. Subsequently, as... Figure 4D and Figure 4E As shown, the intermediate structure 400d can be flipped 180° so that the end 4112 is on top, forming an opening 435 that exposes the end 4112. Finally, as... Figure 4E and Figure 4F As shown, conductive material can be deposited on the inner wall of the opening 435 to form a fourth connection structure 436. The fourth connection structure 436 can be used to bring out the metal layer 411. Optionally, the fourth connection structure 436 can be connected to the peripheral circuit structure 421 (not shown) via a third connection structure 434.

[0089] Compared to Figures 4A to 4F The semiconductor device manufacturing process shown is in Figures 3A to 31 In the manufacturing process of the provided semiconductor device, by forming a first extension 3113 (reference) Figure 3B The metal layer 311 enables the first connection structure 312 (reference) extending along the D1 direction to... Figure 3G The first extension 3113 is connected to the side opposite to the end 3112, thereby leading out the metal layer 311, which can reduce the difficulty of winding, optimize the subsequent process and structural layout, and save area.

[0090] This application also provides a memory system. Figure 5This is a schematic block diagram of a system with a memory system provided in the embodiments of this application. Figure 6A and Figure 6B This is a schematic block diagram of a memory system provided in an embodiment of this application.

[0091] like Figure 5 As shown, system 50 can be a mobile phone, desktop computer, laptop computer, tablet computer, onboard computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 51 located therein). Figure 5 As shown, system 50 may include a host 54 and a memory system 51, the memory system 51 having one or more memories 52 and a controller 53. The host 54 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 54 may be configured to send or receive data to and from the memory 52.

[0092] Memory 52 may include the semiconductor devices described in any embodiment of this application. According to some embodiments, controller 53 is coupled to memory 52 and host 54 and is configured to control memory 52. ​​Controller 53 may manage data stored in memory 52 and communicate with host 54. In some embodiments, controller 53 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 53 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in a mobile device such as a smartphone, tablet, laptop, etc. Controller 53 may be configured to control the operation of memory 52, such as read, erase, and program operations. Controller 53 may also be configured to manage various functions related to data stored in or to be stored in memory 52, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 53 is further configured to process error correction codes (ECCs) related to data read from or written to memory 52. ​​Controller 53 may also perform any other appropriate functions, such as formatting memory 52. ​​Controller 53 may communicate with external devices (e.g., host 54) according to a specific communication protocol. For example, controller 53 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0093] The controller 53 and one or more memories 52 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 51 can be implemented and packaged into different types of end electronic products. Figure 6AIn one example shown, controller 53 and a single memory 52 may be integrated into memory card 55. Memory card 55 may include PC card (PCMCIA, Personal Computer Memory Card International Association), CF card, Smart Media (SM) card, memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. Memory card 55 may further include a connection between memory card 55 and a host (e.g., Figure 5 The host 54) is coupled to the memory card connector 56. In such a way... Figure 6B In another example shown, the controller 53 and multiple memories 52 may be integrated into the SSD 57. The SSD 57 may further include a connection between the SSD 57 and the host (e.g., ...). Figure 5 The host 54 is coupled to the SSD connector 58. In some implementations, the storage capacity and / or operating speed of the SSD 57 is higher than that of the memory card 55.

[0094] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor device, comprising: a metal layer including a side portion, an end portion, and a first extension portion connected to each other, wherein the side portion extends in a first direction, the end portion and the first extension portion extend in a second direction intersecting the first direction, and the end portion and the first extension portion are located at both ends of the side portion in the first direction; and a first connection structure located on a side of the first extension portion away from the end portion and extending in the first direction, wherein the first connection structure is connected to the first extension portion.

2. The semiconductor device of claim 1, wherein, The first extension portion surrounds a portion of the side portion.

3. The semiconductor device of claim 1, wherein, The semiconductor device further comprises a second connection structure extending in the first direction, wherein a size of the second connection structure in the first direction is greater than a size of the first connection structure in the first direction.

4. The semiconductor device of claim 3, wherein, A first end surface of the second connection structure away from the end portion has a size in the first direction equal to a size of the first extension portion in the first direction, and the first end surface is located on a side of the first extension portion away from the end portion.

5. The semiconductor device of claim 3, wherein, The first connection structure and the second connection structure are made of the same material.

6. The semiconductor device of claim 4, wherein, The semiconductor device further comprises: a pad structure located on a side of the second connection structure close to the end portion and connected to the second connection structure.

7. The semiconductor device according to any one of Claims 1 to 6, wherein The semiconductor device further comprises: a plurality of conductive pillars located in a space surrounded by the side portion and the end portion, wherein the conductive pillars extend in the first direction; and an insulating layer located between the conductive pillars and the metal layer.

8. The semiconductor device of claim 7, wherein, The semiconductor device further comprises: a plurality of transistors located on a side of the plurality of conductive pillars away from the end portion, wherein a first active end of the transistor is connected to the conductive pillar; and a bit line structure located on a side of the plurality of transistors away from the plurality of conductive pillars, wherein a second active end of the transistor is connected to the bit line structure.

9. The semiconductor device of claim 8, wherein, The transistor includes a semiconductor body extending in the first direction, a first end portion of the semiconductor body serving as the first active end and being connected to the conductive pillar, and a second end portion of the semiconductor body serving as the second active end and being connected to the bit line structure.

10. The semiconductor device of claim 8, wherein, The semiconductor device further comprises: a peripheral circuit structure located on a side of the plurality of transistors away from the plurality of conductive pillars, wherein the first connection structure is connected to the peripheral circuit structure. 11.A memory system, comprising: a memory including the semiconductor device according to any one of claims 1 to 10; and a controller coupled to the memory and configured to control the memory to store data. 12.A method for manufacturing a semiconductor device, comprising: forming a metal layer, wherein the metal layer includes a side portion, an end portion, and a first extension portion connected to each other, the side portion extends in a first direction, the end portion and the first extension portion extend in a second direction intersecting the first direction, and the end portion and the first extension portion are located at both ends of the side portion in the first direction; and A first connecting structure is formed on a side of the first extending portion away from the end portion, wherein the first connecting structure extends in the first direction and is connected with the first extending portion.

13. The manufacturing method of claim 12, wherein, Forming the metal layer includes: forming an initial metal layer, wherein the initial metal layer includes the side portion, the end portion, and an initial extending portion, the initial extending portion extends in the second direction, and the initial extending portion is located at an end of the side portion away from the end portion; and removing a portion of the initial extending portion, and the remaining initial extending portion is the first extending portion.

14. The manufacturing method according to claim 12, wherein, The manufacturing method further includes: forming a second connecting structure extending in the first direction on a side of the first extending portion away from the end portion, wherein a size of the second connecting structure in the first direction is greater than a size of the first connecting structure in the first direction.

15. The manufacturing method of claim 14, wherein, The first connecting structure and the second connecting structure are formed in a same process.

16. The manufacturing method of claim 15, wherein, The first connecting structure and the second connecting structure are formed in a same process includes: forming a first connecting hole and a second connecting hole on a side of the first extending portion away from the end portion through a same etching process; and filling a conductive material in the first connecting hole and the second connecting hole through a same thin film deposition process.

17. The manufacturing method of claim 14, wherein, The manufacturing method further includes: forming a pad structure on a side of the second connecting structure close to the end portion, wherein the pad structure is connected with the second connecting structure.

18. The manufacturing method according to any one of claims 12 to 17, wherein, The manufacturing method further includes: forming a plurality of conductive pillars, wherein the plurality of conductive pillars are located in a space surrounded by the side portion and the end portion, the conductive pillars extend in the first direction; and forming an insulating layer between the conductive pillars and the metal layer.

19. The manufacturing method of claim 18, wherein, The manufacturing method further includes: forming a plurality of transistors, wherein the plurality of transistors are located on a side of the plurality of conductive pillars away from the end portion, and a first active end of the transistor is connected with the conductive pillar; and forming a bit line structure on a side of the plurality of transistors away from the plurality of conductive pillars, wherein a second active end of the transistor is connected with the bit line structure.

20. The manufacturing method of claim 19, wherein, Forming the plurality of transistors includes: forming a plurality of semiconductor bodies, wherein the semiconductor bodies extend in the first direction, and a first end portion of the semiconductor body as the first active end is connected with the conductive pillar, and a second end portion of the semiconductor body as the second active end is connected with the bit line structure.

21. The manufacturing method of claim 20, wherein, The manufacturing method further includes: connecting a peripheral circuit structure on a side of the plurality of transistors away from the plurality of conductive pillars.

22. The manufacturing method of claim 20, wherein, The manufacturing method further includes: forming a semiconductor layer on a side of the plurality of semiconductor bodies in the second direction; and forming a first insulating structure penetrating through the semiconductor layer in the first direction; wherein forming a first connecting structure on a side of the first extending portion away from the end portion includes: forming the first connecting structure through the first insulating structure.

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