Semiconductor device, manufacturing method thereof and electronic equipment
By setting a protective layer on the substrate during the semiconductor device manufacturing process to cover the sidewalls and bottom wall of the recess, the problem of uneven corrosion of silicon substrates during etching is solved, thereby improving the integrity and reliability of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-02
- Publication Date
- 2026-03-10
AI Technical Summary
During the semiconductor device manufacturing process, different crystal planes of the silicon substrate have different etching rates during the etching process, resulting in the formation of pits or bumps, which affect device performance and reliability, and increase the risk of device stripping.
A protective layer is formed on the substrate to cover the sidewalls and bottom wall of the recess. The protective layer extends to a preset height to prevent substrate corrosion and to avoid blocking the conductive parts when removing the parasitic semiconductor layer.
By setting a protective layer, damage to the substrate during the etching process is avoided, improving the integrity and reliability of the device and preventing peeling.
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Figure CN121645840A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology
[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.
[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention
[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.
[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device, which improves device integrity.
[0006] This application provides a semiconductor device, including:
[0007] Multiple memory cells are stacked along the vertical substrate direction, distributed across different layers;
[0008] Word lines, which penetrate the memory cells of different layers, extend along a direction perpendicular to the substrate;
[0009] The memory cell includes a transistor, the transistor includes a semiconductor layer, the semiconductor layer surrounds the word line, and the semiconductor layers of the plurality of transistors are spaced apart on the sidewalls of the word line in a direction perpendicular to the substrate.
[0010] The recessed portion of the memory cell extends through different layers. The sidewall of the recessed portion is provided with a plurality of conductive portions spaced apart along a direction perpendicular to the substrate. The plurality of conductive portions are respectively connected to a plurality of semiconductor layers. The bottom wall of the recessed portion exposes the substrate, and the surface of the substrate exposed in the recessed portion is covered with a protective layer. The protective layer extends to a predetermined height on the sidewall of the recessed portion.
[0011] In some embodiments, the protective layer extends continuously from the bottom wall of the recess to the side wall of the recess, and extends on the side wall of the recess to a position no higher than the location of the conductive portion closest to the substrate.
[0012] In some embodiments, the recess includes a capacitor hole, the conductive portion includes a first capacitor electrode, the capacitor hole includes a first hole extending in a direction perpendicular to the substrate and a plurality of first lateral grooves surrounding the first hole communicating with the first hole, the plurality of first lateral grooves being spaced apart in a direction perpendicular to the substrate, the plurality of first lateral grooves corresponding one-to-one with a plurality of semiconductor layers, the first lateral grooves exposing the corresponding semiconductor layer, and the first capacitor electrode being distributed on the inner wall of the first lateral groove.
[0013] In some embodiments, the recess includes a bit line groove, the conductive portion includes a bit line, the bit line and the word line are distributed along a first direction parallel to the substrate, the bit line groove includes a first trench penetrating the memory cell in different layers along a direction perpendicular to the substrate and a plurality of first lateral trenches extending along a second direction parallel to the substrate and communicating with the first trenches, the plurality of first lateral trenches being spaced apart along a direction perpendicular to the substrate; the first lateral trenches expose the semiconductor layer of a row of transistors distributed along the second direction, the bit line fills the first lateral trenches; the first direction and the second direction intersect.
[0014] This disclosure provides a method for manufacturing a semiconductor device, including:
[0015] A stacked structure comprising multiple alternating first insulating layers and first sacrificial layers is formed on a substrate;
[0016] An initial recess is formed that penetrates the stacked structure. Based on the initial recess, the first sacrificial layer is etched along a direction parallel to the substrate to form a lateral recess. A conductive portion is formed in the lateral recess.
[0017] An initial protective layer is formed covering the bottom and sidewalls of the initial depression, and an initial barrier layer is formed filling the initial depression;
[0018] The initial barrier layer is etched, and the initial barrier layer at a predetermined height at the bottom of the initial depression is retained as a barrier layer. The initial protective layer not covered by the barrier layer is etched away, and the retained initial protective layer is retained as a protective layer; thus forming a filling layer that fills the initial depression.
[0019] A second hole is formed penetrating the stacked structure along a direction perpendicular to the substrate. Based on the second hole, the first insulating layer is etched along a direction parallel to the substrate to form a second lateral groove. A second sacrificial layer is formed in the second lateral groove. A semiconductor structure layer, a gate insulating structure layer, and a word line are formed sequentially from the outside to the inside in the second lateral groove and the second hole. The second sacrificial layer surrounds the semiconductor structure layer. The semiconductor structure layer and the gate insulating structure layer are distributed on the bottom wall and sidewall of the second lateral groove and the second hole. The word line fills the second lateral groove and the second hole. The semiconductor structure layer connects to the conductive portion.
[0020] The filler layer is etched away to expose the second sacrificial layer and the barrier layer;
[0021] The second sacrificial layer and the barrier layer are etched away to expose the semiconductor structure layer and the protective layer; the exposed semiconductor structure layer is etched to form a plurality of semiconductor layers spaced apart along a direction perpendicular to the substrate.
[0022] In some embodiments, forming the filling layer that fills the initial depression includes: sequentially forming an isolation layer that covers the bottom wall and side wall of the initial depression on which the protective layer and the barrier layer are disposed, and a dummy layer that fills the initial depression.
[0023] In some embodiments, forming an initial recess through the stacked structure, etching the first sacrificial layer along a direction parallel to the substrate based on the initial recess to form a lateral recess, and forming a conductive portion in the lateral recess includes:
[0024] A first trench is formed that penetrates the stacked structure along a direction perpendicular to the substrate;
[0025] Based on the first trench, the first sacrificial layer is etched along a direction parallel to the substrate to form a first lateral trench;
[0026] A bit line is formed to fill the first transverse trench.
[0027] In some embodiments, forming an initial recess through the stacked structure, etching the first sacrificial layer along a direction parallel to the substrate based on the initial recess to form a lateral recess, and forming a conductive portion in the lateral recess further includes:
[0028] A first hole is formed that penetrates the stacked structure along a direction perpendicular to the substrate;
[0029] Based on the first hole, the first sacrificial layer is etched along a direction parallel to the substrate to form a first lateral groove;
[0030] A first capacitor electrode is formed distributed on the inner wall of the first transverse groove; a fifth insulating layer is formed to fill the first transverse groove.
[0031] In some embodiments, the etching to remove the filler layer includes: simultaneously etching to remove the filler layer in the first hole and the first trench.
[0032] This disclosure provides an electronic device, including any of the semiconductor devices described above, or a semiconductor device formed by a manufacturing method of any of the semiconductor devices described above.
[0033] This application includes a semiconductor device comprising: a plurality of memory cells stacked in different layers along a direction perpendicular to a substrate; word lines extending through the memory cells in the different layers along a direction perpendicular to the substrate; each memory cell including a transistor, each transistor including a semiconductor layer surrounding the word line, the semiconductor layers of the plurality of transistors being spaced apart on the sidewalls of the word line along a direction perpendicular to the substrate; and recesses extending through the memory cells in the different layers, the sidewalls of the recesses having a plurality of conductive portions spaced apart along a direction perpendicular to the substrate, the plurality of conductive portions being respectively connected to the plurality of semiconductor layers, the bottom wall of the recess exposing the substrate, and the surface of the substrate exposed in the recess being covered with a protective layer, the protective layer extending to a predetermined height on the sidewalls of the recess. The solution provided by this disclosure, by providing a protective layer on the substrate surface, can protect the substrate during device manufacturing and prevent peeling.
[0034] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.
[0035] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description
[0036] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.
[0037] Figure 1 This is a schematic cross-sectional view of a substrate formed in a technical solution;
[0038] Figure 2 A schematic cross-sectional view of a semiconductor device provided for an exemplary embodiment;
[0039] Figure 3A schematic cross-sectional view along the direction parallel to the substrate after forming a stacked structure, provided for some embodiments;
[0040] Figure 4 A cross-sectional view along the direction perpendicular to the substrate after the formation of the first trench, provided for some embodiments;
[0041] Figure 5 A cross-sectional view along a direction perpendicular to the substrate after forming the first lateral trench, provided for some embodiments;
[0042] Figure 6 A cross-sectional view along a direction perpendicular to the substrate after the bit line is formed, provided for some embodiments;
[0043] Figure 7 A cross-sectional view along the direction perpendicular to the substrate after the formation of the first initial protective layer and the first initial barrier layer, provided for some embodiments;
[0044] Figure 8 A cross-sectional view along the direction perpendicular to the substrate after the formation of the first barrier layer, provided for some embodiments;
[0045] Figure 9 A cross-sectional view along the direction perpendicular to the substrate after the formation of the first protective layer, provided for some embodiments;
[0046] Figure 10 A cross-sectional view along the direction perpendicular to the substrate after forming the first isolation layer and the first dummy layer, provided for some embodiments;
[0047] Figure 11 A cross-sectional view along the direction perpendicular to the substrate after forming a stacked structure including a first hole and a second hole, as provided for some embodiments;
[0048] Figure 12 A cross-sectional view along the direction perpendicular to the substrate after forming the first lateral groove, provided for some embodiments;
[0049] Figure 13 A cross-sectional view along the direction perpendicular to the substrate after the formation of the first capacitor electrode and the fifth insulating layer, provided for some embodiments;
[0050] Figure 14 A cross-sectional view along the direction perpendicular to the substrate after forming the second initial protective layer and the second initial barrier layer, provided for some embodiments;
[0051] Figure 15 A cross-sectional view along the direction perpendicular to the substrate after the formation of the second barrier layer, provided for some embodiments;
[0052] Figure 16 A cross-sectional view along the direction perpendicular to the substrate after the formation of the second protective layer, provided for some embodiments;
[0053] Figure 17 A cross-sectional view along the direction perpendicular to the substrate after forming the second isolation layer and the second dummy layer, provided for some embodiments;
[0054] Figure 18 A cross-sectional view along the direction perpendicular to the substrate after the formation of the semiconductor structure layer, the gate insulating structure layer, and the word line is provided for some embodiments;
[0055] Figure 19 A cross-sectional view along the direction perpendicular to the substrate after etching away the first and second dummy layers, as provided in some embodiments;
[0056] Figure 20 A cross-sectional view along the direction perpendicular to the substrate after exposing the second sacrificial layer, provided for some embodiments;
[0057] Figure 21 A cross-sectional view along the direction perpendicular to the substrate after etching to remove the second sacrificial layer, provided for some embodiments. Detailed Implementation
[0058] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.
[0059] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.
[0060] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values shown in the drawings.
[0061] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.
[0062] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.
[0063] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.
[0064] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.
[0065] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.
[0066] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.
[0067] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.
[0068] In some technical solutions, when manufacturing multi-layered stacked memory cell arrays, parasitic semiconductor layers are removed by etching the semiconductor layers from the outside of the transistor holes. This etching process can damage the silicon substrate. The silicon substrate has different crystal planes, and these different crystal planes have different etching rates in chemical solutions. This difference can lead to some crystal planes being over-etched, forming pits or bumps, such as... Figure 1As shown, this affects the performance and reliability of the device. Moreover, when the Si substrate is severely corroded or pitted, it increases the risk of device peeling, which may lead to electrical performance and long-term reliability issues, and in severe cases, may cause device failure.
[0069] In this embodiment of the disclosure, by providing a protective layer on the substrate, the substrate can be protected during the etching process to remove parasitic semiconductor layers, thereby preventing substrate corrosion and improving device reliability.
[0070] Figure 2 This is a cross-sectional view of a semiconductor device perpendicular to the substrate, provided as an embodiment of this disclosure. Figure 2 As shown, this disclosure provides a semiconductor device that may include:
[0071] Multiple memory cells are stacked along the direction perpendicular to substrate 1, distributed across different layers;
[0072] Word line 40 extends through the memory cells in different layers along a direction perpendicular to the substrate 1;
[0073] The memory cell includes a transistor, the transistor includes a semiconductor layer 23, the semiconductor layer 23 surrounds the word line 40, and the semiconductor layers 23 of the plurality of transistors are spaced apart on the sidewall of the word line 40 in a direction perpendicular to the substrate 1.
[0074] The recessed portion A0 penetrates through different layers of the memory cell. The sidewall of the recessed portion A0 is provided with a plurality of conductive portions E0 distributed at intervals along a direction perpendicular to the substrate 1. The plurality of conductive portions E0 are respectively connected to a plurality of semiconductor layers 23. The bottom wall of the recessed portion A0 exposes the substrate 1, and the surface of the substrate 1 exposed in the recessed portion is covered with a protective layer 60. The protective layer 60 extends to a predetermined height on the sidewall of the recessed portion A0.
[0075] The solution provided in this disclosure can protect the substrate with a protective layer to prevent damage to the substrate during the manufacturing process of semiconductor devices, ensure the integrity of the devices, and prevent peeling.
[0076] In some embodiments, the protective layer 60 extends continuously from the bottom wall of the recess A0 to the side wall of the recess A0, and extends to a position no higher than the location of the conductive portion E0 closest to the substrate 1. That is, the protective layer 60 extends below the bottom conductive portion E0, so that it does not obstruct the parasitic semiconductor layer when it is removed. In some embodiments, the protective layer 60 may extend to the conductive portion E0 closest to the substrate 1. The height of the protective layer 60 is variable, which reduces process requirements and makes it easy to implement.
[0077] In some implementations, the protective layer 60 may only cover the surface of the substrate 1 exposed in the recess A0, that is, the height of the protective layer 60 extending on the sidewall of the recess A0 may be less than [the required height]. Figure 1 The height shown in the figure is sufficient to cover substrate 1.
[0078] Figure 2 The shape of the protective layer 60 shown is merely an example. The embodiments disclosed herein are not limited to this and may have other shapes. When the shape of the bottom wall of the recessed portion A0 changes, the shape of the protective layer 60 may change accordingly.
[0079] In some embodiments, such as Figure 4 , Figure 5 As shown, the recessed portion A0 can be a bit line groove. The recessed portion A0 can include a first trench T1 penetrating different layers of the memory cell along a direction perpendicular to the substrate 1, and a plurality of first lateral trenches V1 extending along a second direction parallel to the substrate 1 and communicating with the first trench T1. The plurality of first lateral trenches V1 are spaced apart along a direction perpendicular to the substrate 1. The conductive portion E0 can include a bit line 30. The first lateral trenches V1 expose the semiconductor layer 23 of a row of transistors distributed along the second direction, and the bit line 30 fills the first lateral trenches V1. The protective layer 60 disposed in the bit line groove is a first protective layer 61.
[0080] In some embodiments, such as Figure 12 , Figure 13 As shown, the recessed portion A0 can be a capacitor hole, and the conductive portion E0 can include a first capacitor electrode 41. The capacitor hole includes a first hole K1 extending perpendicular to the substrate direction and a plurality of first lateral grooves A1 surrounding the first hole K1 and communicating with the first hole K1. The plurality of first lateral grooves A1 are spaced apart perpendicular to the substrate 1, and each of the plurality of first lateral grooves A1 corresponds one-to-one with a plurality of semiconductor layers 23. The first lateral groove A1 exposes the corresponding semiconductor layer 23, and the first capacitor electrode 41 is distributed on the inner wall of the first lateral groove A1. The protective layer 60 disposed in the capacitor hole is a second protective layer 62.
[0081] In some embodiments, the recessed portion A0 may include bit line grooves and capacitor holes, that is, a protective layer 60 is provided in both the bit line grooves and the capacitor holes. The solution provided in this embodiment, by providing a protective layer 60 in both the bit line grooves and the capacitor holes, is beneficial for protecting the substrate. However, this disclosure is not limited to this; the protective layer 60 may be provided only in the bit line grooves, or only in the capacitor holes.
[0082] The semiconductor device may include a multilayer memory cell array stacked along a direction perpendicular to the substrate. The memory cell array may include a plurality of memory cells distributed along a first direction parallel to the substrate 1 and a second direction parallel to the substrate 1. Each memory cell may include transistors and capacitors distributed along the first direction, and bit lines 30 may extend along the second direction. A first capacitor electrode 41, word lines 40, and bit lines 30 are distributed along the first direction. The first and second directions may intersect. In some embodiments, the first and second directions may be perpendicular.
[0083] Figure 2 The structure shown is merely an example, and the embodiments disclosed herein are not limited thereto. Various modifications are possible, and this application can be applied to any structure that requires etching to remove the parasitic semiconductor layer.
[0084] This disclosure provides a method for manufacturing a semiconductor device, including:
[0085] A stacked structure comprising multiple alternating first insulating layers and first sacrificial layers is formed on a substrate;
[0086] An initial recess is formed that penetrates the stacked structure in a direction perpendicular to the substrate. Based on the initial recess, the first sacrificial layer is etched in a direction parallel to the substrate to form a lateral recess. A conductive portion is formed in the lateral recess.
[0087] An initial protective layer is formed covering the bottom and sidewalls of the initial depression, and an initial barrier layer is formed filling the initial depression;
[0088] The initial barrier layer is etched, and the initial barrier layer at a predetermined height at the bottom of the initial depression is retained as a barrier layer. The initial protective layer not covered by the barrier layer is etched away, and the retained initial protective layer is retained as a protective layer; thus forming a filling layer that fills the initial depression.
[0089] A second hole is formed through the stacked structure. Based on the second hole, the first insulating layer is etched along a direction parallel to the substrate to form a second lateral groove. A second sacrificial layer is formed in the second lateral groove. A semiconductor structure layer, a gate insulating structure layer, and a word line are formed sequentially from the outside to the inside in the second lateral groove and the second hole. The second sacrificial layer surrounds the semiconductor structure layer. The semiconductor structure layer and the gate insulating structure layer are distributed on the bottom wall and side wall of the second lateral groove and the second hole. The word line fills the second lateral groove and the second hole. The semiconductor structure layer connects to the conductive portion.
[0090] The filler layer is etched away to expose the second sacrificial layer and the barrier layer;
[0091] The second sacrificial layer and the barrier layer are etched away to expose the semiconductor structure layer and the protective layer; the exposed semiconductor structure layer is etched to form a plurality of semiconductor layers spaced apart along a direction perpendicular to the substrate.
[0092] In some embodiments, the filling layer may be a two-layer structure, and forming the filling layer that fills the initial depression includes: sequentially forming an isolation layer covering the bottom wall and sidewalls of the initial depression on which the protective layer and the barrier layer are disposed, and a dummy layer filling the initial depression. The isolation layer film and the dummy layer film may be sequentially deposited in the initial depression to form the isolation layer and the dummy layer.
[0093] In some embodiments, the initial recess can be a trench, and the conductive portion can be a bit line. Forming the initial recess through the stacked structure, etching the first sacrificial layer along a direction parallel to the substrate based on the initial recess to form a lateral recess, and forming the conductive portion in the lateral recess may include:
[0094] A first trench is formed that penetrates the stacked structure along a direction perpendicular to the substrate;
[0095] Based on the first trench, the first sacrificial layer is etched along a direction parallel to the substrate to form a first lateral trench;
[0096] A bit line is formed to fill the first transverse trench.
[0097] In some embodiments, the initial recess may be a hole, and the conductive portion may be a first capacitor electrode. The process of forming an initial recess penetrating the stacked structure, etching the first sacrificial layer along a direction parallel to the substrate based on the initial recess to form a lateral recess, and forming a conductive portion in the lateral recess may include:
[0098] A first hole is formed that penetrates the stacked structure along a direction perpendicular to the substrate;
[0099] Based on the first hole, the first sacrificial layer is etched along a direction parallel to the substrate to form a first lateral groove;
[0100] A first capacitor electrode is formed distributed on the inner wall of the first transverse groove; a fifth insulating layer is formed to fill the first transverse groove.
[0101] In some embodiments, the initial recess may include a groove and a hole, i.e., forming a first groove and a first lateral groove, and forming a first hole and a first lateral groove, with a first protective layer formed in the first groove and a second protective layer formed in the first hole.
[0102] In some embodiments, the etching to remove the filler layer includes: simultaneously etching to remove the filler layer in the first hole and the first trench.
[0103] The technical solution of this embodiment is further illustrated below through the manufacturing process of the protective layer in this embodiment. The "patterning process" mentioned in this embodiment includes deposition of a film layer, coating with photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of a film layer, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film manufactured on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."
[0104] In one exemplary embodiment, the protective layer may be disposed in the bit groove, and the manufacturing process of the protective layer may include:
[0105] 101) Forming a stacked structure;
[0106] A first insulating film and a first sacrificial layer film are sequentially and alternately deposited on substrate 1 to form a stacked structure comprising multiple alternately arranged first insulating layers 11 and first sacrificial layers 10; as shown Figure 3 As shown, Figure 3 A schematic cross-sectional view along a direction parallel to substrate 1 after forming a stacked structure, as provided in some embodiments.
[0107] As used herein, the term "substrate" means and includes a base material or structure on which a material such as a vertical field-effect transistor is formed. A substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. A substrate can be a conventional silicon substrate or other bulk substrate that includes layers of semiconductor material.
[0108] In some embodiments, the first insulating film may be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K < 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2). The materials of the subsequent fourth and fifth insulating films are similar to those of the first insulating film and will not be described further.
[0109] In some embodiments, the first sacrificial layer film may be a film layer that has an etching selectivity ratio with the first insulating film, such as SiN.
[0110] 102) Form the first trench T1;
[0111] The stacked structure is etched from the top layer to the bottom layer along a direction perpendicular to the substrate 1 (etching until the substrate 1 is exposed) to form a plurality of first trenches T1 penetrating the stacked structure along a direction perpendicular to the substrate 1, such as... Figure 4 As shown, Figure 4 A cross-sectional view along a direction perpendicular to the substrate 1 after the formation of the first trench T1 is provided for some embodiments. The first trench T1 may penetrate the stacked structure along a second direction Y.
[0112] 103) Form the first transverse groove V1;
[0113] Based on the lateral etching (i.e., etching parallel to the substrate 1) of the first sacrificial layer 10 of the first trench T1, a plurality of first lateral trenches V1 are formed, and after etching the first sacrificial layer 10, the different first trenches T1 remain unconnected, such as... Figure 5 As shown, Figure 5 A cross-sectional view along a direction perpendicular to the substrate 1 after the formation of the first lateral trench V1, provided for some embodiments.
[0114] 104) Formation of bit line 30;
[0115] A first conductive film is deposited, covering the bottom and sidewalls of the first trench T1, filling multiple first transverse trenches V1; the first conductive film in the first trench T1 is etched away (i.e., the first conductive film covering the bottom and sidewalls of the first trench T1 is etched away), while retaining the first conductive film in the first transverse trenches V1 (due to process reasons, a small amount of the first conductive film in the first transverse trenches V1 may be etched away during the etching process), forming bit lines 30, which fill the first transverse trenches V1; as Figure 6 As shown, Figure 6 A cross-sectional view of the bit line 30 after it has been formed, in a direction perpendicular to the substrate 1, provided for some embodiments.
[0116] In some embodiments, the first conductive film may be one or more of the following different types of materials:
[0117] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal alloy containing these metals.
[0118] Alternatively, it can be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and aluminum-doped zinc oxide (AZO); or metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).
[0119] Alternatively, it could be polycrystalline silicon, conductive doped semiconductor materials, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; or other materials that exhibit conductivity.
[0120] The materials for the second and third conductive films are similar and will not be described in detail here.
[0121] 105) Form a first initial protective layer 61' and a first initial barrier layer 91';
[0122] After sequentially depositing a first protective layer film and a first barrier layer film, the layers are smoothed to form a first initial protective layer 61' and a first initial barrier layer 91'. The first initial protective layer 61' covers the side of the topmost first insulating layer 11 facing away from the substrate 1, as well as the bottom and sidewalls of the first trench T1. The first initial barrier layer 91' fills the first trench T1. Figure 7 As shown, Figure 7 A cross-sectional view along a direction perpendicular to the substrate 1 after the formation of the first initial protective layer 61' and the first initial barrier layer 91', provided for some embodiments.
[0123] In some embodiments, the first protective layer film and the subsequent second protective layer film may be film layers with an etching selectivity ratio to the first insulating film, such as SiN.
[0124] In some embodiments, the first barrier layer film may be a film layer with an etching selectivity ratio to the first protective layer film and the first insulating film, such as polysilicon. The subsequent second barrier layer film material is similar and will not be described in detail.
[0125] 106) Form the first barrier layer 91;
[0126] The first initial barrier layer 91' is etched, leaving the first initial barrier layer 91' located at the bottom of the first trench T1, referred to as the first barrier layer 91; as shown Figure 8 As shown, Figure 8 A cross-sectional view along a direction perpendicular to the substrate 1 after the formation of the first barrier layer 91, provided for some embodiments.
[0127] The first barrier layer 91 is used to define the first protective layer 61. In some embodiments, the first barrier layer 91 may be distributed on the sidewall of the bottommost first insulating layer 11 exposed in the first trench T1, and also distributed on the substrate 1 exposed in the first trench T1. In this case, the first barrier layer 91 covers the first initial protective layer 61' distributed on the substrate 1 exposed in the first trench T1 and the bottommost first insulating layer 11 exposed on the sidewall of the first trench T1.
[0128] 107) Form the first protective layer 61;
[0129] The first initial protective layer 61' not covered by the first barrier layer 91 is etched away, leaving the first initial protective layer 61' covered by the first barrier layer 91, referred to as the first protective layer 61; as shown. Figure 9 As shown, Figure 9 This is a cross-sectional view along a direction perpendicular to the substrate 1 after the formation of the first protective layer 61, provided for some embodiments. The first protective layer 61 can protect the substrate 1 during the subsequent removal of the parasitic semiconductor layer through the first trench T1.
[0130] Figure 9 The shape of the first protective layer 61 shown is merely an example, and the embodiments disclosed herein are not limited to this. It can be other shapes. For example, when the shape of the first groove T1 changes, the shape of the first protective layer 61 disposed on the bottom wall and side wall of the first groove T1 changes accordingly.
[0131] 108) Form the first filling layer;
[0132] After depositing the first filler layer film, it is ground flat to form the first filler layer that fills the first trench T1;
[0133] The first filling layer may include a first isolation layer 71 and a first dummy layer 81; that is, a first isolation layer film and a first dummy layer film may be deposited sequentially and then polished to form a first isolation layer 71 covering the bottom wall and sidewalls of the first trench T1, and a first dummy layer 81 filling the first trench T1, such as... Figure 10 As shown, Figure 10 This is a cross-sectional view along a direction perpendicular to the substrate 1 after the formation of the first isolation layer 71 and the first dummy layer 81, as provided in some embodiments. Here, the first trench T1 is the first trench T1 with the first protective layer 61 and the first barrier layer 91 already formed. The first isolation layer 71 also covers the topmost first insulating layer 11 on the side facing away from the substrate 1. The side of the first dummy layer 81 facing away from the substrate 1 is flush with the side of the first isolation layer 71 facing away from the substrate 1.
[0134] In some embodiments, the first isolation layer film may be a film layer with an etching selectivity ratio to the first insulating film, such as SiN. The materials for the subsequent second isolation layer film are similar and will not be described further.
[0135] In some embodiments, the first dummy layer film may be a film layer with an etching selectivity ratio to the first isolation layer film, such as polysilicon. The materials for the second dummy layer film are similar and will not be described further.
[0136] When the first initial protective layer 61' and the first isolation layer 71 use the same material, such as SiN, etching the first initial protective layer 61' and then depositing the first isolation layer 71 can make the thickness of the SiN covering the surface of the first barrier layer 91 and the sidewall of the first trench T1 consistent, which facilitates the subsequent synchronous etching to remove the SiN covering the surface of the first barrier layer 91 and the sidewall of the first trench T1.
[0137] In some embodiments, a protective layer may be disposed in a capacitor hole, and the manufacturing process of the protective layer may include:
[0138] 201) Forming a stacked structure including a first hole K1 and a second hole K2;
[0139] A first insulating film and a first sacrificial layer film are sequentially and alternately deposited on substrate 1 to form a stacked structure comprising a plurality of alternately arranged first insulating layers 11 and first sacrificial layers 10;
[0140] The stacked structure is etched from the top layer to the bottom layer along a direction perpendicular to the substrate 1 (etched until the substrate 1 is exposed) to form a plurality of first holes K1 and a plurality of second holes K2 that penetrate the stacked structure along a direction perpendicular to the substrate 1. Subsequently, capacitors can be formed in the first holes K1, and a plurality of semiconductor layers of a plurality of transistors can be formed in the second holes K2, as well as word lines can be formed.
[0141] A third insulating film and a fourth dummy layer film are deposited to form a third insulating layer 13 covering the bottom and sidewalls of the first hole K1 and the second hole K2, and a fourth dummy layer 84 filling the first hole K1 and the second hole K2. In some embodiments, the third insulating film may be a film layer with an etching selectivity ratio to the first insulating film and the first sacrificial layer film, such as silicon oxynitride (SiON), and the fourth dummy layer 84 may be a film layer with an etching selectivity ratio to the third insulating film, such as polysilicon.
[0142] A fourth insulating film is deposited to form a fourth insulating layer 14, which covers the stacked structure and can subsequently protect the second hole K2. Figure 11 As shown, Figure 11 A cross-sectional view along a direction perpendicular to substrate 1 after forming a stacked structure including a first hole K1 and a second hole K2, as provided in some embodiments.
[0143] The manufacturing process described above is merely an example, and the embodiments disclosed herein are not limited thereto.
[0144] 202) Form the first transverse groove A1;
[0145] The fourth insulating layer 14 is etched to expose the first hole K1;
[0146] The third insulating layer 13 and the fourth dummy layer 84 in the first hole K1 are removed by etching;
[0147] Based on the first hole K1, the first sacrificial layer 10 is etched laterally until the third insulating layer 13 of the second hole K2 is exposed, forming a first lateral groove A1; as Figure 12 As shown, Figure 12 A cross-sectional view along a direction perpendicular to the substrate 1 after forming the first lateral groove A1, provided for some embodiments. The first lateral groove A1 is an annular groove surrounding the first hole K1.
[0148] 203) Form the first capacitor electrode 41 and the fifth insulating layer 15;
[0149] A second conductive film and a fifth insulating film are sequentially deposited. The second conductive film and the fifth insulating film in the first hole K1 are then etched away, while the second conductive film and the fifth insulating film in the first transverse groove A1 are retained, forming a first capacitor electrode 41 and a fifth insulating layer 15. The fifth insulating layer 15 fills the first transverse groove A1. Figure 13 As shown, Figure 13 A cross-sectional view along the direction perpendicular to the substrate 1 after the formation of the first capacitor electrode 41 and the fifth insulating layer 15, provided for some embodiments.
[0150] 204) Forming a second initial protective layer 62' and a second initial barrier layer 92';
[0151] After sequentially depositing the second protective layer film and the second barrier layer film, the layers are smoothed to form the second initial protective layer 62' and the second initial barrier layer 92'. The second initial protective layer 62' covers the side of the fourth insulating layer 14 facing away from the substrate 1, as well as the bottom wall and sidewalls of the first hole K1, and the second initial barrier layer 92' fills the first hole K1. Figure 14 As shown, Figure 14 A cross-sectional view along a direction perpendicular to the substrate 1 after the formation of the second initial protective layer 62' and the second initial barrier layer 92', provided for some embodiments.
[0152] In some embodiments, the second protective layer film may be a film layer with an etching selectivity ratio to the first insulating film, such as SiN.
[0153] In some embodiments, the second barrier layer film may be a film layer having an etching selectivity ratio with the second protective layer film and the first insulating film, such as polysilicon.
[0154] 205) Forming a second barrier layer 92;
[0155] The second initial barrier layer 92' is etched, leaving the second initial barrier layer 92' located at the bottom of the first hole K1, referred to as the second barrier layer 92. The second barrier layer 92 is distributed on the sidewall of the bottommost first insulating layer 11 exposed in the first hole K1, and also distributed on the substrate 1 exposed in the first hole K1, as shown below. Figure 15 As shown, Figure 15 A cross-sectional view along a direction perpendicular to the substrate 1 after the formation of the second barrier layer 92 is provided for some embodiments. At this time, the second barrier layer 92 covers the second initial protective layer 62' distributed on the substrate 1 exposed in the first hole K1 and on the sidewall of the bottom first insulating layer 11 exposed in the first hole K1.
[0156] 107) Formation of a second protective layer 62;
[0157] The second initial protective layer 62' not covered by the second barrier layer 92 is etched away, leaving the second initial protective layer 62' covered by the second barrier layer 92, referred to as the second protective layer 62; as shown. Figure 16 As shown, Figure 16 This is a cross-sectional view along a direction perpendicular to the substrate 1 after the formation of the second protective layer 62, as provided in some embodiments. The second protective layer 62 can protect the substrate 1 during the subsequent removal of the parasitic semiconductor layer through the first hole K1.
[0158] 108) Forming a second filling layer;
[0159] After depositing the second filling layer film, it is smoothed to form the second filling layer that fills the first hole K1;
[0160] The second filling layer may include a second isolation layer 72 and a second dummy layer 82; that is, a second isolation layer film and a second dummy layer film may be deposited sequentially and then ground smooth to form a second isolation layer 72 covering the bottom wall and sidewalls of the first hole K1, and a second dummy layer 82 filling the first hole K1, such as... Figure 17 As shown, Figure 17 This is a cross-sectional view along a direction perpendicular to the substrate 1 after the formation of the second isolation layer 72 and the second dummy layer 82, as provided in some embodiments. Here, the first hole K1 is the first hole K1 where the second protective layer 62 and the second barrier layer 92 have been formed. The second isolation layer 72 also covers the side of the fourth insulating layer 14 facing away from the substrate 1. The side of the second dummy layer 82 facing away from the substrate 1 is flush with the side of the second isolation layer 72 facing away from the substrate 1.
[0161] Subsequently, the second hole K2 can be exposed. Based on the second hole K2, the first insulating layer 11 is laterally etched to form multiple second lateral grooves A2. A second sacrificial layer 83 is formed in the second lateral grooves A2, and the second sacrificial layer 83 does not completely fill the second lateral grooves A2. Subsequently, a semiconductor thin film, a gate insulating thin film, and a third conductive thin film are deposited sequentially to form a semiconductor structure layer 23', a gate insulating structure layer 24', and a word line 40. The semiconductor structure layer 23' includes multiple semiconductor layers 23, which are connected to form an integral semiconductor structure layer 23'. The gate insulating structure layer 24' includes multiple gate insulating layers 24 of multiple transistors. At this time, the semiconductor structure layer 23' and the gate insulating structure layer 24' are distributed from the outside to the inside of the inner walls of the second hole K2 and the second lateral groove A2. The word line 40 fills the second hole K2 and the second lateral groove A2. The second sacrificial layer 83 surrounds the semiconductor structure layer 23' and is connected to the first isolation layer 71 and the second isolation layer 72. Figure 18 As shown, Figure 18 This is a cross-sectional view along a direction perpendicular to the substrate 1 after the formation of the semiconductor structure layer 23', the gate insulating structure layer 24', and the word line 40 in some embodiments. At this time, a parasitic semiconductor layer exists between the plurality of semiconductor layers 23. In some embodiments, the second sacrificial layer 83 may be a film layer having an etch selectivity ratio with the first insulating film and the first sacrificial layer film, such as polysilicon.
[0162] In some embodiments, the parasitic semiconductor layer can be removed by the following steps:
[0163] 301) Etch away the first dummy layer 81 and the second dummy layer 82, such as... Figure 19 As shown, Figure 19 A cross-sectional view along a direction perpendicular to the substrate 1 after etching away the first dummy layer 81 and the second dummy layer 82, as provided in some embodiments.
[0164] 302) Etch away the first isolation layer 71 and the second isolation layer 72 to expose the first barrier layer 91 and the second barrier layer 92, and expose the second sacrificial layer 83; as Figure 20 As shown, Figure 20 A cross-sectional view along a direction perpendicular to the substrate 1 after exposing the second sacrificial layer 83, provided for some embodiments.
[0165] 303) Etching removes the second sacrificial layer 83, exposing the parasitic semiconductor layer between the semiconductor layers 23. During the etching process of removing the second sacrificial layer 83, the first barrier layer 91 and the second barrier layer 92 are also removed. Due to the protection of the first barrier layer 91 and the second barrier layer 92, the first protective layer 61 and the second protective layer 62 are prevented from being etched. The first protective layer 61 and the second protective layer 62 can protect the substrate 1, thereby achieving protection of the substrate 1. Figure 21 As shown, Figure 21 A cross-sectional view along the direction perpendicular to the substrate 1 after etching away the second sacrificial layer 83, as provided in some embodiments.
[0166] 304) The exposed semiconductor structure layer 23' is etched to remove the parasitic semiconductor layer, so that the semiconductor structure layer 23' forms multiple semiconductor layers 23 that are spaced apart from each other along a direction perpendicular to the substrate, such as... Figure 2 As shown. Subsequently, the fifth insulating layer 15 can be removed, and a dielectric layer and a second capacitor electrode can be formed in the first hole K1 and the first transverse groove A1.
[0167] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.
[0168] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.
Claims
1. A semiconductor device, characterized by, The application relates to a memory device and a manufacturing method thereof. The memory device comprises a plurality of memory cells stacked along a vertical substrate direction, a plurality of word lines extending along the vertical substrate direction through the memory cells in different layers, and a plurality of transistors comprising a plurality of semiconductor layers surrounding the word lines, wherein the semiconductor layers of the plurality of transistors are spaced apart along a vertical substrate direction on sidewalls of the word lines. The memory device further comprises a plurality of recesses through the memory cells in different layers, wherein sidewalls of the recesses are provided with a plurality of conductive portions spaced apart along a vertical substrate direction, the conductive portions are connected to the semiconductor layers respectively, a bottom wall of the recesses exposes the substrate, and a surface of the substrate exposed in the recesses is covered with a protective layer extending to a preset height on the sidewalls of the recesses. The protective layer continuously extends from the bottom wall of the recesses to the sidewalls of the recesses and extends to a position not higher than the conductive portion closest to the substrate on the sidewalls of the recesses. The recesses comprise capacitor holes, and the conductive portions comprise first capacitor electrodes, wherein the capacitor holes comprise a first hole extending along a vertical substrate direction and a plurality of first lateral recesses surrounding the first hole and communicating with the first hole, the first lateral recesses are spaced apart along a vertical substrate direction, the first lateral recesses correspond to the semiconductor layers respectively, the first lateral recesses expose the semiconductor layers respectively, and the first capacitor electrodes are distributed on inner walls of the first lateral recesses.
2. The semiconductor device according to claim 1, wherein The recesses comprise bit line grooves, and the conductive portions comprise bit lines, wherein the bit lines and the word lines are distributed along a first direction parallel to the substrate, the bit line grooves comprise a first groove extending through the memory cells in different layers along a vertical substrate direction and a plurality of first lateral grooves extending along a second direction parallel to the substrate and communicating with the first groove, the first lateral grooves are spaced apart along a vertical substrate direction, the first lateral grooves expose the semiconductor layers of a column of transistors distributed along the second direction, and the bit lines fill the first lateral grooves.
3. The semiconductor device of claim 1, wherein The first direction and the second direction intersect.
4. The semiconductor device according to any one of claims 1 to 3, wherein The application relates to a manufacturing method of a memory device. The method comprises the following steps: forming a stack structure comprising a plurality of first insulating layers and a plurality of first sacrificial layers alternately arranged on a substrate; forming an initial recess through the stack structure, etching the first sacrificial layers along a direction parallel to the substrate based on the initial recess to form a lateral recess, and forming a conductive portion in the lateral recess; forming an initial protective layer covering a bottom wall and sidewalls of the initial recess and an initial barrier layer filling the initial recess; etching the initial barrier layer to retain the initial barrier layer at a preset height of the bottom of the initial recess as a barrier layer, etching and removing the initial protective layer not covered by the barrier layer to retain the initial protective layer as a protective layer; and forming a filling layer filling the initial recess.
5. A method of manufacturing a semiconductor device, characterized by The application further relates to a memory device and a manufacturing method thereof. forming a second hole penetrating through the stack structure along a direction perpendicular to the substrate, etching the first insulating layer along a direction parallel to the substrate based on the second hole to form a second lateral recess, and forming a second sacrificial layer in the second lateral recess; the second sacrificial layer surrounds the semiconductor structure layer, the semiconductor structure layer and the gate insulating structure layer are distributed on a bottom wall and side walls of the second lateral recess and the second hole, the word line fills the second lateral recess and the second hole, and the semiconductor structure layer is connected to the conductive part; etching to remove the filling layer to expose the second sacrificial layer and the barrier layer; etching to remove the second sacrificial layer and the barrier layer to expose the semiconductor structure layer and the protection layer; etching the exposed semiconductor structure layer so that the semiconductor structure layer forms a plurality of semiconductor layers spaced apart along a direction perpendicular to the substrate.
6. The method of manufacturing a semiconductor device according to claim 5, wherein The forming of the filling layer filling the initial recess includes sequentially forming an isolation layer covering the bottom wall and the side wall of the initial recess provided with the protection layer and the barrier layer and a dummy layer filling the initial recess.
7. The method of manufacturing a semiconductor device according to claim 5, wherein The forming of the initial recess penetrating through the stack structure, the etching of the first sacrificial layer along a direction parallel to the substrate based on the initial recess, the forming of a lateral recess, and the forming of a conductive part in the lateral recess include: forming a first trench penetrating through the stack structure along a direction perpendicular to the substrate; etching the first sacrificial layer along a direction parallel to the substrate based on the first trench to form a first lateral trench; forming a bit line filling the first lateral trench.
8. The method of manufacturing a semiconductor device according to claim 7, wherein The forming of the initial recess penetrating through the stack structure, the etching of the first sacrificial layer along a direction parallel to the substrate based on the initial recess, and the forming of a lateral recess and a conductive part in the lateral recess further include: forming a first hole penetrating through the stack structure along a direction perpendicular to the substrate; etching the first sacrificial layer along a direction parallel to the substrate based on the first hole to form a first lateral recess; forming a first capacitor electrode distributed on an inner wall of the first lateral recess and forming a fifth insulating layer filling the first lateral recess.
9. The method of manufacturing a semiconductor device according to claim 8, wherein The etching to remove the filling layer includes etching to simultaneously remove the filling layer in the first hole and the first trench.
10. An electronic device, comprising: The semiconductor device includes the semiconductor device as claimed in any one of claims 1 to 4 or formed by the manufacturing method of the semiconductor device as claimed in any one of claims 5 to 9.