Semiconductor structure and preparation method thereof
By forming an isolation layer within the transistor containment trench and using a sacrificial material layer to protect the semiconductor layer and gate insulating layer, the problem of word line etching damage is solved, thus improving the performance of the three-dimensional dynamic random access memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-09
- Publication Date
- 2026-03-10
AI Technical Summary
Existing three-dimensional dynamic random access memory is prone to damage to the transistor containment trenches during word line etching, and existing processes cannot meet the high selectivity requirements of indium gallium zinc oxide and indium zinc oxide materials, thus affecting device performance.
By forming an isolation layer in the transistor containment trench and using a sacrificial material layer as a support for the isolation layer, the word lines are prevented from directly contacting wet etching, protecting the semiconductor layer and gate insulating layer in the transistor containment trench from damage, and the sacrificial material layer is removed after the word lines are formed.
This effectively avoids etching damage to the word lines, improves the electrical performance of the device, meets subsequent electrical requirements, and enhances the overall performance of the device.
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Figure CN121645845A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology
[0002] With the development of communication and digital technologies, people are constantly pursuing products with lower power consumption, lighter weight, and better performance. Three-dimensional dynamic random access memory (DRAM) can achieve higher integration density and larger storage capacity, and has gradually become one of the important research directions in memory. Currently, the performance of DRAM is still being continuously improved. Summary of the Invention
[0003] Based on this, the present disclosure provides a semiconductor structure and its fabrication method, which can effectively avoid etching damage to word lines, thereby improving device performance.
[0004] According to some embodiments, this disclosure provides a method for fabricating a semiconductor structure, including:
[0005] A stacked structure is formed, the stacked structure comprising multiple layers of first dielectric layers and multiple layers of second dielectric layers alternately stacked along a first direction;
[0006] The etched stacked structure forms multiple word line holes that penetrate the stacked structure and are spaced apart;
[0007] Based on the word line holes, each first dielectric layer is etched laterally to form a transistor accommodating trench within the first dielectric layer;
[0008] A first semiconductor material layer, a first insulating material layer, and a sacrificial material layer are sequentially formed on the inner wall of the transistor receiving groove and word line hole;
[0009] The sacrificial material layer, the first insulating material layer, and the first semiconductor material layer located on the inner wall of the word line hole are removed in sequence, so that the first semiconductor material layer retained in the transistor receiving trench forms a semiconductor layer, and the first insulating material layer retained in the transistor receiving trench forms a gate insulating layer.
[0010] An isolation layer is formed on the exposed sidewall of the semiconductor layer and gate insulating layer near the word line hole within the transistor accommodating trench;
[0011] Remove the sacrificial material layer from the transistor containment trench;
[0012] Word lines are formed in transistor accommodating slots and word line holes, and the word lines at least cover the exposed surfaces of the gate insulating layer and the isolation layer.
[0013] According to some embodiments, before etching the stacked structure to form a plurality of word line vias that penetrate the stacked structure and are spaced apart, the fabrication method further includes:
[0014] The etched stacked structure forms a plurality of isolation trenches spaced apart in the second direction; the isolation trenches penetrate the stacked structure along the first direction and extend along the third direction; the first direction, the second direction and the third direction intersect each other;
[0015] An etch barrier layer and an isolation structure are sequentially formed on the inner wall of the isolation trench;
[0016] The etching of the stacked structure to form multiple word line holes that penetrate the stacked structure and are spaced apart includes: etching the stacked structure between adjacent isolation trenches to form word line holes;
[0017] The method of laterally etching each first dielectric layer based on word line holes to form transistor receiving trenches within the first dielectric layers includes: laterally etching each first dielectric layer based on word line holes until an etch barrier layer is exposed to obtain transistor receiving trenches.
[0018] According to some embodiments, a first semiconductor material layer, a first insulating material layer, and a sacrificial material layer are sequentially formed on the inner walls of the transistor accommodating trench and the word line via, including:
[0019] A first semiconductor material layer is formed conformally on the inner wall of the word line hole and the inner wall of each transistor receiving groove;
[0020] A first insulating material layer is formed conformally on the surface of the first semiconductor material layer away from the word line holes and the inner wall of each transistor receiving groove;
[0021] A sacrificial material layer is formed on the surface of the first insulating material layer opposite to the first semiconductor material layer to fill the transistor accommodating trench and word line hole.
[0022] According to some embodiments, the sacrificial material layer, the first insulating material layer, and the first semiconductor material layer located on the inner wall of the word line hole are removed sequentially, so that the first semiconductor material layer retained in the transistor receiving trench forms a semiconductor layer, and the first insulating material layer retained in the transistor receiving trench forms a gate insulating layer, including:
[0023] Remove the sacrificial material layer located inside the letter hole;
[0024] A wet etching process is used to remove the first insulating material layer and the first semiconductor material layer located in the word line hole, and the first insulating material layer and the first semiconductor material layer located in the first region of the transistor accommodating trench are further removed to form a gate insulating layer and a semiconductor layer accordingly.
[0025] The first region is the area within the transistor accommodating slot that is close to the word line hole and where the distance between the accommodating region and the inner wall of the word line hole is greater than the target value.
[0026] According to some embodiments, an isolation layer is formed on the exposed sidewall of the semiconductor layer and gate insulating layer near the word line hole in the transistor receiving trench, including: forming an isolation layer that fills a first region and covers the exposed sidewall of the semiconductor layer and gate insulating layer near the word line hole in the inner wall of the transistor receiving trench.
[0027] According to some embodiments, word lines are formed within transistor accommodating slots and word line vias, including:
[0028] A word line material layer is formed to fill word line vias and transistor accommodating slots, so that the word line material layer constitutes a word line.
[0029] According to some embodiments, the material of the sacrificial material layer includes polycrystalline silicon; the material of the first semiconductor material layer includes indium gallium zinc oxide; and the material of the word line material layer includes indium zinc oxide.
[0030] According to some embodiments, after removing the sacrificial material layer in the transistor accommodating trench, the fabrication method further includes: heat treatment of the semiconductor layer; wherein the process temperature of the heat treatment is not higher than 400°C.
[0031] According to some embodiments, this disclosure also provides a semiconductor structure, including: a stacked structure, a semiconductor layer, a gate insulating layer, an isolation layer, and word lines.
[0032] The stacked structure includes multiple layers of first dielectric layers and multiple layers of second dielectric layers alternately stacked along a first direction; the stacked structure has a plurality of word line vias arranged at intervals throughout the stacked structure, and a transistor receiving trench located within the first dielectric layers and surrounding the word line vias. A semiconductor layer conformally covers the inner wall of the transistor receiving trench outside a first region; the first region is a region within the transistor receiving trench near one end of the word line via and where the distance between the semiconductor layer and the inner wall of the word line via is greater than a target value. A gate insulating layer conformally covers the surface of the semiconductor layer facing away from the inner wall of the transistor receiving trench. An isolation layer is located in the first region of the transistor receiving trench and covers the exposed sidewalls of the semiconductor layer and the gate insulating layer near the word line vias. Word lines are located within the transistor receiving trench and word line vias and at least cover the exposed surfaces of the gate insulating layer and the isolation layer.
[0033] According to some embodiments, this disclosure provides another aspect of an electronic device, including a semiconductor structure fabricated by the method for fabricating a semiconductor structure according to the above embodiments, or a semiconductor structure as described in the foregoing embodiments.
[0034] The embodiments disclosed herein may have, or at least have, the following advantages:
[0035] In this embodiment, a sacrificial material layer within the transistor receptacle is used to form an isolation layer on the exposed sidewalls of the semiconductor layer and gate insulating layer near the word line vias. This isolation layer provides etching protection for the semiconductor layer and gate insulating layer within the transistor receptacle. The sacrificial material layer is then removed, and word lines filling the word line vias and the transistor receptacle are formed. In other words, this disclosure uses a sacrificial material layer instead of word lines to provide support for the isolation layer, allowing the word lines to be formed after the isolation layer. Thus, during word line formation, the isolation layer protects the semiconductor layer and gate insulating layer within the transistor receptacle from etching damage, and avoids the need for multiple wet etching processes in existing processes, thereby preventing damage caused by repeated wet etching and improving the electrical performance of the word lines. Therefore, this embodiment can quantitatively control the loss of word line material within the transistor receptacle, effectively avoiding etching damage to the word lines, making it easier to meet subsequent electrical requirements, and thus improving device performance. Attached Figure Description
[0036] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.
[0037] Figure 1 This is a top view schematic diagram of a semiconductor structure provided in some embodiments;
[0038] Figure 2(a) shows Figure 1 The cross-sectional schematic diagram of the structure shown is along the aa' direction; Figure 2(b) is... Figure 1 The cross-sectional schematic diagram of the structure shown is along the bb' direction; Figure 2(c) is... Figure 1 A schematic diagram of the cross-section of the structure shown along the cc' direction;
[0039] Figure 3 This is a top view schematic diagram of an electronic device provided in some embodiments;
[0040] Figure 4 This is a schematic flowchart of a method for fabricating a semiconductor structure provided in some embodiments;
[0041] Figure 5 This is a schematic diagram of the process of forming an isolation trench, etching a barrier layer and an isolation structure in a method for fabricating a semiconductor structure provided in some embodiments;
[0042] Figure 6 This is a schematic flowchart of step S400 in a method for fabricating a semiconductor structure provided in some embodiments;
[0043] Figure 7 This is a schematic flowchart of step S500 in a method for fabricating a semiconductor structure provided in some embodiments;
[0044] Figure 8(a) is a cross-sectional schematic diagram of the structure obtained in step S100 of a semiconductor structure fabrication method provided in some embodiments along the aa' direction; Figure 8(b) is a cross-sectional schematic diagram of the structure obtained in step S100 of a semiconductor structure fabrication method provided in some embodiments along the bb' direction; Figure 8(c) is a cross-sectional schematic diagram of the structure obtained in step S100 of a semiconductor structure fabrication method provided in some embodiments along the cc' direction.
[0045] Figure 9(a) is a cross-sectional schematic diagram along the aa' direction of the structure obtained after etching the stacked structure based on the mask pattern in the first mask layer in a semiconductor structure fabrication method provided in some embodiments; Figure 9(b) is a cross-sectional schematic diagram along the bb' direction of the structure obtained after etching the stacked structure based on the mask pattern in the first mask layer in a semiconductor structure fabrication method provided in some embodiments; Figure 9(c) is a cross-sectional schematic diagram along the cc' direction of the structure obtained after etching the stacked structure based on the mask pattern in the first mask layer in a semiconductor structure fabrication method provided in some embodiments.
[0046] Figure 10(a) is a cross-sectional schematic diagram of the structure obtained in step S152 of a semiconductor structure fabrication method provided in some embodiments, along the bb' direction; Figure 10(b) is a cross-sectional schematic diagram of the structure obtained in step S152 of a semiconductor structure fabrication method provided in some embodiments, along the cc' direction;
[0047] Figure 11(a) is a cross-sectional schematic diagram along the aa' direction of the structure obtained after forming the second etch protection layer and the second mask layer in a semiconductor structure fabrication method provided in some embodiments;
[0048] Figure 12(a) is a cross-sectional schematic diagram of the structure obtained in step S200 along the aa' direction in a method for fabricating a semiconductor structure provided in some embodiments;
[0049] Figure 13(a) is a cross-sectional schematic diagram of the structure obtained in step S300 along the aa' direction in a method for fabricating a semiconductor structure provided in some embodiments;
[0050] Figure 14(a) is a cross-sectional schematic diagram of the structure obtained in step S400 of a semiconductor structure fabrication method provided in some embodiments, along the aa' direction; Figure 14(b) is a cross-sectional schematic diagram of the structure obtained in step S400 of a semiconductor structure fabrication method provided in some embodiments, along the bb' direction; Figure 14(c) is a cross-sectional schematic diagram of the structure obtained in step S400 of a semiconductor structure fabrication method provided in some embodiments, along the cc' direction.
[0051] Figure 15(a) is a cross-sectional schematic diagram of the structure obtained in step S500 along the aa' direction in a method for fabricating a semiconductor structure provided in some embodiments;
[0052] Figure 16(a) is a cross-sectional schematic diagram of the structure obtained in step S600 along the aa' direction in a method for fabricating a semiconductor structure provided in some embodiments;
[0053] Figure 17(a) is a schematic cross-sectional view of the structure obtained in step S700 along the aa' direction in a method for fabricating a semiconductor structure provided in some embodiments;
[0054] Figure 18(a) is a cross-sectional schematic diagram of the structure obtained in step S801 along the aa' direction in a semiconductor structure fabrication method provided in some embodiments.
[0055] Explanation of reference numerals in the attached figures:
[0056] 1-Substrate; 11-Semiconductor layer; 110-First semiconductor material layer; 12-Gate insulating layer; 120-First insulating material layer; 13-Isolation layer; 14-Word line; 150-Sacrificial material layer;
[0057] 2-Contact hole; 21-First etch protection layer; 211-First sub-etch protection layer; 212-Second sub-etch protection layer; 22-Second etch protection layer; 221-First and second etch protection layers; 222-Second and second etch protection layers; 3-Isolation structure;
[0058] D - Stacked structure; D11 - First dielectric layer; D12 - Second dielectric layer; D121 - First conductive unit; D122 - Second conductive unit; D120 - Etching barrier layer; G1 - Word line hole; G2 - Transistor accommodating trench; G3 - Isolation trench; Y1 - First mask layer; Y2 - Second mask layer. Detailed Implementation
[0059] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, which illustrate embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.
[0061] It should be understood that when a component or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.
[0062] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.
[0063] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0064] When used here, "deposition" processes include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).
[0065] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the present disclosure.
[0066] With the development of communication and digital technologies, people are constantly pursuing products with lower power consumption, lighter weight, and better performance. Three-dimensional dynamic random access memory (DRAM) can achieve higher integration density and larger storage capacity, and has gradually become one of the important research directions in memory. Currently, the performance of DRAM is still being continuously improved.
[0067] Three-dimensional dynamic random access memory (DRAM) is constructed by laterally etching silicon oxide (SiO2) layers and silicon nitride (SiN) layers, followed by the sequential formation of semiconductor layers, gate insulating layers, and word lines. However, during the lateral wet etching of word lines within the word holes, word lines within the transistor containment trenches inevitably suffer damage. Furthermore, the subsequent removal of semiconductor layer material from the word holes also results in damage to the word lines within the transistor containment trenches. Moreover, indium gallium zinc oxide (IGZO) and indium zinc oxide (IZO) materials have similar properties. Therefore, when both the semiconductor layer and word lines are made of IZO, no suitable solution can achieve a high selectivity ratio between IZO and IZO, and current processes cannot meet subsequent electrical requirements.
[0068] Based on this, the present disclosure provides a semiconductor structure and its fabrication method, which can effectively avoid etching damage to word lines, thereby improving device performance.
[0069] Please see Figures 1-2(c) This disclosure provides a semiconductor structure in some embodiments, including: a stacked structure D, a semiconductor layer 11, a gate insulating layer 12, an isolation layer 13, and a word line 14. Figure 2(a) shows... Figure 1 The schematic diagram of the cross-section of the semiconductor structure shown in Figure 2(b) along the aa' direction is shown in Figure 2(b). Figure 1 The schematic diagram of the cross-section of the semiconductor structure shown in Figure 2(c) along the bb' direction is shown. Figure 1 The diagram shows a cross-sectional view of the semiconductor structure along the cc' direction. Figure 1 This is a schematic cross-sectional view of the semiconductor structure shown in Figure 2(a) along the dd' direction.
[0070] Referring to Figure 2(a), the stacked structure D includes multiple layers of first dielectric layers D11 and multiple layers of second dielectric layers D12 alternately stacked along a first direction (e.g., the X direction). The stacked structure D has a plurality of word line vias G1 arranged at intervals throughout the stacked structure D, and a transistor receiving trench G2 located within the first dielectric layers D11 and surrounding the word line vias G1. A semiconductor layer 11 conformally covers a portion of the inner wall of the transistor receiving trench outside a first region; the first region is the area within the transistor receiving trench G2 near one end of the word line via G1 and at a distance greater than a target value from the inner wall of the word line via G1. A gate insulating layer 12 conformally covers the surface of the semiconductor layer 11 facing away from the inner wall of the transistor receiving trench G2. An isolation layer 13 is located in the first region of the transistor receiving trench G2 and covers the exposed sidewalls of the semiconductor layer 11 and the gate insulating layer 12 near the word line via G1. Word lines 14 are located within the transistor receiving trench G2 and the word line vias G1, and at least cover the exposed surfaces of the gate insulating layer 12 and the isolation layer 13. Referring to Figures 2(b) and 2(c), the semiconductor structure also includes an etch stop layer D120 and an isolation structure 3. The etch stop layer D120 conformally covers the stacked structure D. The isolation structure 3 is disposed within the gap between adjacent etch stop layers D120.
[0071] In this embodiment, the isolation layer 13 is located within the transistor receiving trench G2 and covers the exposed sidewalls of the semiconductor layer 11 and the gate insulating layer 12 near the word line via G1. The isolation layer 13 provides etching protection for the semiconductor layer 11 and the gate insulating layer 12 within the transistor receiving trench G2. That is, the isolation layer protects the semiconductor layer and the gate insulating layer within the transistor receiving trench from etching damage. This allows for quantitative control of material loss within the transistor receiving trench G2, effectively avoiding etching damage to the channel structure, making it easier to meet subsequent electrical requirements, and thus improving device performance.
[0072] In some examples, the stacked structure D is disposed on the substrate 1.
[0073] For example, substrate 1 can be made of semiconductor material, insulating material, conductive material, or any combination thereof. Substrate 1 can be a single-layer structure or a multilayer structure. For example, substrate 1 can be a silicon (Si) substrate, silicon germanium (SiGe) substrate, silicon germanium carbon (SiGeC) substrate, silicon carbide (SiC) substrate, gallium arsenide (GaAs) substrate, indium arsenide (InAs) substrate, indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 1 can be a layered substrate including, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.
[0074] For example, the material of the first dielectric layer D11 includes, but is not limited to, silicon oxide.
[0075] For example, the material of the second dielectric layer D12 includes, but is not limited to, silicon nitride. Thus, by depositing a stack of silicon oxide and silicon nitride layers, the process challenges posed by etching a metal / silicon oxide stack are avoided.
[0076] In some examples, each second dielectric layer D12 includes: a first conductive unit D121 extending in a third direction (e.g., the Z direction), and a plurality of second conductive units D122 spaced apart in the third direction (e.g., the Z direction). One end of the first conductive unit D121 has a contact hole 2.
[0077] Here, the first dielectric layer D11 can be located between adjacent second dielectric layers D12 or on one side of the first and last second dielectric layers D12, and the number of the first dielectric layer D11 can match the stacking number of the second dielectric layers D12.
[0078] In some embodiments, the semiconductor layer 11 is made of indium gallium zinc oxide. The word line 14 is made of indium zinc oxide.
[0079] For example, semiconductor layer 11 may include a channel layer. Word line 14 may include the gates of a plurality of transistors distributed along a first direction.
[0080] In some examples, the gate insulating layer 12 includes, but is not limited to, an HK (high-K) dielectric layer. An HK dielectric layer is a dielectric layer having a high dielectric constant K, for example, greater than 3.9.
[0081] For example, the gate insulating layer 12 may be disposed between the semiconductor layer 11 and the gate.
[0082] In some examples, the material of the isolation layer 13 includes, but is not limited to, silicon oxide.
[0083] For example, the material of the etch barrier layer D120 includes, but is not limited to, silicon nitride.
[0084] For example, the material of the isolation structure 3 includes, but is not limited to, silicon oxide.
[0085] Please see Figure 4 This disclosure provides a method for fabricating a semiconductor structure, including steps S100 to S800, through some embodiments.
[0086] S100, forming a stacked structure, the stacked structure including multiple layers of first dielectric layers and multiple layers of second dielectric layers alternately stacked along a first direction.
[0087] S200, etching the stacked structure to form multiple word line holes that run through the stacked structure and are spaced apart.
[0088] S300, based on word line holes, laterally etch each first dielectric layer to form transistor accommodating trenches within the first dielectric layer.
[0089] S400, a first semiconductor material layer, a first insulating material layer, and a sacrificial material layer are sequentially formed on the inner wall of the transistor receiving groove and the word line hole.
[0090] S500, the sacrificial material layer, the first insulating material layer and the first semiconductor material layer located on the inner wall of the word line hole are removed in sequence, so that the first semiconductor material layer retained in the transistor receiving trench forms a semiconductor layer and the first insulating material layer retained in the transistor receiving trench forms a gate insulating layer.
[0091] S600 forms an isolation layer on the exposed sidewall of the semiconductor layer and gate insulating layer near the word line hole within the transistor accommodating trench.
[0092] S700, removes the sacrificial material layer in the transistor containment trench.
[0093] S800 forms word lines in transistor accommodating slots and word line holes, and the word lines at least cover the exposed surfaces of the gate insulating layer and the isolation layer.
[0094] In this embodiment, a sacrificial material layer within the transistor accommodating trench is used to form an isolation layer on the exposed sidewalls of the semiconductor layer and gate insulating layer near the word line vias. This isolation layer provides etching protection for the semiconductor layer and gate insulating layer within the transistor accommodating trench. The sacrificial material layer is then removed, and word lines filling the word line vias and the transistor accommodating trench are formed. In other words, this disclosure uses a sacrificial material layer instead of word lines to provide support for the formation of the isolation layer, allowing the word lines to be formed after the isolation layer. Thus, during word line formation, the isolation layer protects the semiconductor layer and gate insulating layer within the transistor accommodating trench from etching damage. Furthermore, it avoids the need for word lines in the transistor accommodating trench to undergo multiple wet etching processes, thus preventing damage caused by repeated wet etching and improving the electrical performance of the word lines. Therefore, this embodiment can quantitatively control the loss of material within the transistor accommodating trench, effectively avoiding etching damage to the channel structure, making it easier to meet subsequent electrical requirements, thereby improving device performance.
[0095] In some embodiments, please refer to Figure 5 Before step S200, which involves etching the stacked structure to form multiple word line holes that penetrate the stacked structure and are spaced apart, the fabrication method further includes steps S151 to S152.
[0096] S151, an etched stacked structure is formed to create a plurality of isolation trenches spaced apart in the second direction; the isolation trenches penetrate the stacked structure along the first direction and extend along the third direction. The first direction, the second direction, and the third direction intersect each other.
[0097] S152, an etching barrier layer and an isolation structure are sequentially formed on the inner wall of the isolation groove.
[0098] In step S200, etching the stacked structure to form multiple word line holes that penetrate the stacked structure and are spaced apart includes etching the stacked structure between adjacent isolation trenches to form word line holes.
[0099] Step S300 involves laterally etching each of the first dielectric layers based on the word line holes to form transistor receiving trenches within the first dielectric layers, including: laterally etching each of the first dielectric layers based on the word line holes until the etching barrier layer is exposed to obtain transistor receiving trenches.
[0100] In some embodiments, please refer to Figure 6 Step S400 involves sequentially forming a first semiconductor material layer, a first insulating material layer, and a sacrificial material layer on the inner wall of the transistor receiving groove and word line hole, including steps S401 to S403.
[0101] S401, a first semiconductor material layer is formed conformally on the inner wall of the word line hole and the inner wall of each transistor receiving groove.
[0102] S402, a first insulating material layer is formed on the surface of the first semiconductor material layer away from the inner wall of the word line hole and the inner wall of each transistor receiving groove.
[0103] S403, a sacrificial material layer is formed on the surface of the first insulating material layer away from the first semiconductor material layer to fill the transistor accommodating trench and word line hole.
[0104] In some embodiments, please refer to Figure 7 Step S500 sequentially removes the sacrificial material layer, the first insulating material layer, and the first semiconductor material layer located on the inner wall of the word line hole, so that the first semiconductor material layer retained in the transistor receiving trench forms a semiconductor layer, and the first insulating material layer retained in the transistor receiving trench forms a gate insulating layer, including steps S501 to S502.
[0105] S501, Remove the sacrificial material layer located inside the word line hole.
[0106] S502, a wet etching process is used to remove the first insulating material layer and the first semiconductor material layer located in the word line hole, and the first insulating material layer and the first semiconductor material layer located in the first region of the transistor accommodating trench are further removed to form a gate insulating layer and a semiconductor layer accordingly.
[0107] The first region is the area within the transistor accommodating slot that is close to the word line hole and where the distance between the accommodating region and the inner wall of the word line hole is greater than the target value.
[0108] In some embodiments, step S600 forms an isolation layer on the exposed sidewall of the semiconductor layer and gate insulating layer near the word line hole in the transistor receiving trench, including: forming an isolation layer that fills the first region and covers the exposed sidewall of the semiconductor layer and gate insulating layer near the word line hole on the inner wall of the transistor receiving trench.
[0109] In some embodiments, after removing the sacrificial material layer in the transistor accommodating trench in step S700, the preparation method further includes: heat treatment of the semiconductor layer; wherein the process temperature of the heat treatment is not higher than 400°C.
[0110] In some embodiments, step S800, forming word lines in the transistor accommodating slot and word line via, includes forming a word line material layer that fills the word line via and the transistor accommodating slot, so that the word line material layer constitutes a word line.
[0111] In some embodiments, the sacrificial material layer is made of polycrystalline silicon. The first semiconductor material layer is made of indium gallium zinc oxide. The word line material layer is made of indium zinc oxide.
[0112] It should be noted that in the above embodiments, the execution order of the steps in the method is not strictly limited. These steps may not necessarily be executed in the described order, and may be executed in other ways. Moreover, at least a portion of any step may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps. The method is limited to enabling the fabrication of the corresponding memory.
[0113] To more clearly illustrate the manufacturing method provided in the above embodiments, the following is combined with... Figures 8(a) to 18(a) The preparation method is described in detail.
[0114] In step S100, referring to Figures 8(a), 8(b) and 8(c), a stacked structure D is formed, which includes multiple layers of first dielectric layer D11 and multiple layers of second dielectric layer D12 that are alternately stacked along a first direction (e.g., the X direction).
[0115] In some examples, the stacked structure D is disposed on the substrate 1.
[0116] For example, substrate 1 can be made of semiconductor material, insulating material, conductive material, or any combination thereof. Substrate 1 can be a single-layer structure or a multilayer structure. For example, substrate 1 can be a silicon (Si) substrate, silicon germanium (SiGe) substrate, silicon germanium carbon (SiGeC) substrate, silicon carbide (SiC) substrate, gallium arsenide (GaAs) substrate, indium arsenide (InAs) substrate, indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 1 can be a layered substrate including, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.
[0117] For example, the material of the first dielectric layer D11 includes, but is not limited to, silicon oxide.
[0118] For example, the material of the second dielectric layer D12 includes, but is not limited to, silicon nitride. Thus, by depositing a stack of silicon oxide and silicon nitride layers, the process challenges posed by etching a metal / silicon oxide stack are avoided.
[0119] Here, the first dielectric layer D11 can be located between adjacent second dielectric layers D12 or on one side of the first and last second dielectric layers D12. The number of first dielectric layers D11 can be matched with the number of stacked second dielectric layers D12. Each first dielectric layer D11 and each second dielectric layer D12 can be formed using a deposition process.
[0120] For example, the deposition processes mentioned above and below include, but are not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular layer deposition (MLD), and plasma enhanced chemical vapor deposition (PECVD).
[0121] Furthermore, after forming the stacked structure D, a first etch protection layer 21 and a first mask layer Y1 can be formed on the upper surface of the top second dielectric layer D12.
[0122] For example, the first mask layer Y1 includes a photoresist layer and / or a hard mask layer, thereby facilitating subsequent etching of the stacked structure D based on the mask pattern in the first mask layer Y1.
[0123] In some examples, the first etch protection layer 21 includes a first sub-etch protection layer 211 and a second sub-etch protection layer 212 stacked along a first direction (e.g., the X direction).
[0124] For example, the first sub-etching protective layer 211 is made of carbon. The second sub-etching protective layer 212 is made of silicon oxynitride. In this way, the stacked structure D can be protected when it is subsequently etched based on the mask pattern in the first mask layer Y1.
[0125] In step S151, referring to Figures 9(a), 9(b), and 9(c), the etched stacked structure D forms a plurality of isolation trenches G3 spaced apart in a second direction (e.g., the Z direction). The isolation trenches G3 penetrate the stacked structure D along a first direction (e.g., the X direction) and extend along a third direction (e.g., the Y direction). The first direction (e.g., the X direction), the second direction (e.g., the Z direction), and the third direction (e.g., the Y direction) intersect each other.
[0126] For example, the stacked structure D is etched based on the mask pattern in the first mask layer Y1.
[0127] In step S152, please refer to Figures 10(a) and 10(b), an etching barrier layer D120 and an isolation structure 3 are sequentially formed on the inner wall of the isolation trench G3.
[0128] Here, after removing the area filling isolation structure 3, the process further includes: sequentially performing an annealing process, a chemical mechanical polishing process, and a cleaning process on the aforementioned structure.
[0129] In step S200, please refer to Figures 11(a) to 12(a) The process of etching the stacked structure D to form multiple word line holes G1 that penetrate the stacked structure D and are spaced apart includes etching the stacked structure D between adjacent isolation trenches G3 to form word line holes G1.
[0130] In some embodiments, referring to FIG11(a), after forming the etch barrier layer D120 and the isolation structure 3, a second etch protection layer 22 and a second mask layer Y2 can be formed on the upper surface of the top second dielectric layer D12.
[0131] For example, the second mask layer Y2 includes a photoresist layer and / or a hard mask layer, thereby facilitating subsequent etching of the stacked structure D based on the mask pattern in the second mask layer Y2.
[0132] In some examples, the second etch protection layer 22 includes a third sub-etch protection layer 221 and a fourth sub-etch protection layer 222 stacked along a first direction (e.g., the X direction).
[0133] For example, the material of the third sub-etching protective layer 221 includes carbon. The material of the fourth sub-etching protective layer 222 includes silicon oxynitride. In this way, the stacked structure D can be protected when it is subsequently etched based on the mask pattern in the second mask layer Y2.
[0134] In some embodiments, referring to FIG12(a), the stacked structure D is etched based on the mask pattern in the second mask layer Y2 to form word line holes G1.
[0135] In step S300, referring to FIG13(a), each first dielectric layer D11 is laterally etched based on word line hole G1 to form transistor receiving trench G2 in the first dielectric layer D11, including: laterally etching each first dielectric layer D11 based on word line hole G1 until the etching barrier layer D120 is exposed to obtain transistor receiving trench G2.
[0136] In some embodiments, a wet etching process is used to etch the sidewalls of the first dielectric layer D11 to form a transistor accommodating trench G2.
[0137] In step S401, referring to Figures 14(a), 14(b) and 14(c), a first semiconductor material layer 110 is formed conformally on the inner wall of the word line hole G1 and the inner wall of each transistor receiving groove G2.
[0138] In some examples, the material of the first semiconductor material layer 110 includes indium gallium zinc oxide.
[0139] In some examples, the first semiconductor material layer 110 can be formed using an ALD process.
[0140] In step S402, referring to Figures 14(a), 14(b) and 14(c), a first insulating material layer 120 is formed conformally on the surface of the first semiconductor material layer 110 away from the inner wall of the word line hole G1 and the inner wall of each transistor receiving groove G2.
[0141] In some examples, the first insulating layer 120 includes, but is not limited to, an HK (high-K) dielectric layer. An HK dielectric layer refers to a dielectric layer having a high dielectric constant K, for example, greater than 3.9.
[0142] In some examples, the first insulating layer 120 can be formed using the ALD process.
[0143] In step S403, referring to Figures 14(a), 14(b) and 14(c), a sacrificial material layer 150 is formed on the surface of the first insulating material layer 120 opposite to the first semiconductor material layer 110 to fill the transistor accommodating trench G2 and the word line hole G1.
[0144] In some examples, during wet etching, the sacrificial material layer 150 has a high selectivity to the first insulating material layer 120. The sacrificial material layer 150 also has a high selectivity to the first semiconductor material layer 110. Thus, during wet etching of the first insulating material layer 120 or the first semiconductor material layer 110, etching damage to the sacrificial material layer 150 can be minimized. For example, the material of the sacrificial material layer 150 may include, but is not limited to, polysilicon or doped silicon.
[0145] In some examples, the sacrificial material layer 150 can be formed using a PECVD process. The temperature of the PECVD process needs to be below 400°C.
[0146] In some examples, the sacrificial material layer 150 may not completely fill the word line via G1. The sacrificial material layer 150 covers the surface of the first insulating material layer 120 within the word line via G1 that faces away from the first semiconductor material layer 110.
[0147] In step S501, referring to FIG15(a), the sacrificial material layer 150 located in the word line hole G1 is removed.
[0148] In some examples, wet etching or gas etching processes can be used to remove the sacrificial material layer 150 located within the word line hole G1.
[0149] In step S502, please refer to FIG15(a), a wet etching process is used to remove the first insulating material layer 120 and the first semiconductor material layer 110 located in the word line hole G1, and the first insulating material layer 120 and the first semiconductor material layer 110 located in the first region of the transistor receiving trench G2 are further removed to form the gate insulating layer 12 and the semiconductor layer 11.
[0150] The first region is the area within the transistor accommodating slot G2 near the word line hole G1, where the distance between the accommodating slot G2 and the inner wall of the word line hole G1 is greater than the target value. This ensures that the subsequent isolation layer has sufficient space to accommodate it.
[0151] In step S600, referring to FIG16(a), an isolation layer 13 is formed on the exposed sidewall of the semiconductor layer 11 and the gate insulating layer 12 near the word line hole G1 in the transistor receiving groove G2, including: forming an isolation layer 13 that fills the first region and covers the exposed sidewall of the semiconductor layer 11 and the gate insulating layer 12 near the word line hole G1 on the inner wall of the transistor receiving groove G2.
[0152] In some examples, the isolation layer 13 formed on the inner wall of the transistor accommodating trench G2 to fill the first region includes: forming an isolation material layer (not shown) on the inner wall of the word line hole G1 to fill the first region of the transistor accommodating trench G2 using an ALD process; removing the isolation material layer on the inner wall of the word line hole G1 using a wet etching process or a gas etching process, and retaining the isolation material layer located in the first region to form the isolation layer 13.
[0153] In step S700, referring to FIG17(a), the sacrificial material layer 150 in the transistor receiving trench G2 is removed.
[0154] In some examples, a wet etching process is used to remove the sacrificial material layer 150 within the transistor containment trench G2.
[0155] In some embodiments, after removing the sacrificial material layer 150 in the transistor accommodating trench G2 in step S700, the process further includes: performing heat treatment on the semiconductor layer 11. The heat treatment process temperature is not higher than 400°C. For example, the heat treatment process temperature can be 400°C, 350°C, 300°C, 250°C, 200°C, 150°C, 100°C, or 50°C, etc.
[0156] In step S800, referring to FIG18(a), word lines 14 are formed in transistor accommodating groove G2 and word line hole G1, including: forming a word line material layer (not shown) that fills word line hole G1 and transistor accommodating groove G2, so that the word line material layer constitutes word line 14.
[0157] In some examples, the word line 14, which fills the word line via G1 and the transistor accommodating slot G2, is formed using an ALD process.
[0158] In some examples, the material of word line 14 may include, but is not limited to, indium zinc oxide.
[0159] Some embodiments of this disclosure also provide an electronic device, including the semiconductor structure described in any of the foregoing embodiments, or a semiconductor structure formed according to the fabrication method of the semiconductor structure described in any of the foregoing embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.
[0160] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0161] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.
Claims
1. A method of fabricating a semiconductor structure, characterized by, The method comprises the following steps: forming a stack structure comprising a plurality of first dielectric layers and a plurality of second dielectric layers alternately stacked along a first direction; etching the stack structure to form a plurality of word line holes penetrating through the stack structure and arranged at intervals; based on the word line holes, etching each of the first dielectric layers laterally to form a transistor accommodating groove in the first dielectric layer; forming, in sequence, a first semiconductor material layer, a first insulating material layer and a sacrificial material layer on the inner walls of the transistor accommodating groove and the word line hole; sequentially removing the sacrificial material layer, the first insulating material layer and the first semiconductor material layer on the inner wall of the word line hole, so that the first semiconductor material layer remaining in the transistor accommodating groove forms a semiconductor layer, and the first insulating material layer remaining in the transistor accommodating groove forms a gate insulating layer; forming an isolation layer on the exposed sidewalls of the semiconductor layer and the gate insulating layer in the transistor accommodating groove close to the word line hole; removing the sacrificial material layer in the transistor accommodating groove; forming a word line in the transistor accommodating groove and the word line hole, the word line covering at least the exposed surfaces of the gate insulating layer and the isolation layer.
2. The method of producing a semiconductor structure according to claim 1, wherein Before the step of etching the stack structure to form a plurality of word line holes penetrating through the stack structure and arranged at intervals, the method further comprises: etching the stack structure to form a plurality of isolation grooves arranged at intervals in a second direction; the isolation grooves penetrate through the stack structure along the first direction and extend along a third direction; the first direction, the second direction and the third direction intersect with each other; forming, in sequence, an etching stop layer and an isolation structure on the inner walls of the isolation grooves; wherein the step of etching the stack structure to form a plurality of word line holes penetrating through the stack structure and arranged at intervals comprises: etching the stack structure between adjacent isolation grooves to form the word line holes; the step of based on the word line holes, etching each of the first dielectric layers laterally to form a transistor accommodating groove in the first dielectric layer comprises: based on the word line holes, etching each of the first dielectric layers laterally until the etching stop layer is exposed to obtain the transistor accommodating groove.
3. The method of producing a semiconductor structure according to claim 1 or 2, wherein The step of forming, in sequence, a first semiconductor material layer, a first insulating material layer and a sacrificial material layer on the inner walls of the transistor accommodating groove and the word line hole comprises: forming the first semiconductor material layer conformally on the inner walls of the word line hole and the inner walls of each of the transistor accommodating grooves; forming the first insulating material layer conformally on the surfaces of the first semiconductor material layer away from the inner walls of the word line hole and each of the transistor accommodating grooves; forming the sacrificial material layer filling the transistor accommodating groove and the word line hole on the surface of the first insulating material layer away from the first semiconductor material layer.
4. The method of producing a semiconductor structure according to claim 3, wherein The step of sequentially removing the sacrificial material layer, the first insulating material layer and the first semiconductor material layer on the inner wall of the word line hole, so that the first semiconductor material layer remaining in the transistor accommodating groove forms a semiconductor layer, and the first insulating material layer remaining in the transistor accommodating groove forms a gate insulating layer comprises: removing the sacrificial material layer in the word line hole; adopting a wet etching process to remove the first insulating material layer and the first semiconductor material layer located in the word line hole, and continuously remove the first insulating material layer and the first semiconductor material layer located in the first region of the transistor accommodating groove, to correspondingly form the gate insulating layer and the semiconductor layer; wherein the first region is a region in the transistor accommodating groove close to one end of the word line hole and having a distance greater than a target value from the inner wall of the word line hole.
5. The method of producing a semiconductor structure according to claim 4, wherein forming an isolation layer on the exposed sidewall of the semiconductor layer and the gate insulating layer close to the word line hole in the transistor accommodating groove, comprising: forming an isolation layer on the inner wall of the transistor accommodating groove in a conformal manner to fill the first region and cover the exposed sidewall of the semiconductor layer and the gate insulating layer close to the word line hole.
6. The method of producing a semiconductor structure according to claim 1, wherein forming a word line in the transistor accommodating groove and the word line hole, comprising: forming a word line material layer to fill the word line hole and the transistor accommodating groove, so that the word line material layer constitutes the word line.
7. The method of producing a semiconductor structure according to claim 6, wherein the material of the sacrificial material layer comprises polysilicon; the material of the first semiconductor material layer comprises indium gallium zinc oxide; and the material of the word line material layer comprises indium zinc oxide.
8. The method of producing a semiconductor structure according to claim 1, wherein after removing the sacrificial material layer in the transistor accommodating groove, the preparation method further comprises: performing heat treatment on the semiconductor layer; wherein the process temperature of the heat treatment is not higher than 400°C.
9. A semiconductor structure, characterized by comprising: a stack structure comprising a plurality of first dielectric layers and a plurality of second dielectric layers alternately stacked along a first direction; the stack structure has a plurality of word line holes spacedly arranged through the stack structure, and a transistor accommodating groove located in the first dielectric layer and surrounding the word line hole; a semiconductor layer conformally covering the inner wall of the transistor accommodating groove except for a first region; the first region is a region in the transistor accommodating groove close to one end of the word line hole and having a distance greater than a target value from the inner wall of the word line hole; a gate insulating layer conformally covering the surface of the semiconductor layer away from the inner wall of the transistor accommodating groove; an isolation layer located in the first region of the transistor accommodating groove and covering the exposed sidewall of the semiconductor layer and the gate insulating layer close to the word line hole; a word line located in the transistor accommodating groove and the word line hole and covering at least the exposed surface of the gate insulating layer and the isolation layer.
10. An electronic device, comprising: comprising: a semiconductor structure prepared by the preparation method of the semiconductor structure according to any one of claims 1-8, or the semiconductor structure according to claim 9.