Dynamic random access memory device and manufacturing method thereof

Abstract

The invention provides a dynamic random access memory device and a manufacturing method thereof. The dynamic random access memory device comprises a substrate, a bit line, a dummy bit line, a dummy insulation structure and a cover layer. The substrate includes an array region, a peripheral region, and a dummy region between the array region and the peripheral region. A bit line is over the substrate in the array region. A dummy bit line is over the substrate in the dummy region. The dummy insulating structures are located between the dummy bit lines, and the top surfaces of the dummy insulating structures are lower than the top surfaces of the dummy bit lines. The cap layer is located in the dummy region to cover the top of the dummy bit line and the top of the dummy insulating structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor memory device and a manufacturing method thereof, and more particularly to a dynamic random access memory device and a manufacturing method thereof that can reduce the number of dummy bit lines. BACKGROUND

[0002] As the size of dynamic random access memory (DRAM) is scaled down, the manufacturing of DRAM becomes more difficult, and the structure has to be changed to improve the yield. For example, in the process of removing the sacrificial oxide layer between the plurality of bit line structures in the array region, a photoresist pattern is provided to expose the array region and shield the area outside the array region. However, the etchant can penetrate from the edge of the photoresist pattern to the bottom of the photoresist pattern, and the sacrificial oxide layer under the photoresist pattern that should be left can be removed, so that the range of the array region expands to an unexpected position, and the yield is reduced. To solve this problem, the existing DRAM device proposes to reduce the opening of the photoresist pattern to be smaller than the range of the predetermined array region, that is, to increase the number of dummy bit line structures to ensure that the range of the array region does not expand to an unexpected position. However, in this way, the number of active bit lines is sacrificed. Moreover, as product specifications vary, the coverage position of the photoresist pattern needs to be adjusted according to the penetration of the etchant, and this adjustment requirement will increase the process difficulty and development time. In addition, as the size of the DRAM device is scaled down, the accuracy of the range of the array region will be more difficult to control, and thus the yield of the DRAM device is reduced. SUMMARY

[0003] The DRAM device and the manufacturing method thereof provided by the present disclosure can solve the problem of etchant penetration, thereby reducing the use of dummy bit lines and improving the yield of the device.

[0004] Some embodiments of the present disclosure provide a DRAM device, including a substrate, a bit line, a dummy bit line, a dummy insulating structure, and a cap layer. The substrate includes an array region, a peripheral region, and a dummy region between the array region and the peripheral region. The bit line is located above the substrate in the array region, and the dummy bit line is located above the substrate in the dummy region. The dummy insulating structure is located between the dummy bit lines, and the top surface of the dummy insulating structure is lower than the top surface of the dummy bit line. The cap layer is located in the dummy region to cover the top of the dummy bit line and the top of the dummy insulating structure.

[0005] Some embodiments disclosed herein provide a method for manufacturing a DRAM device, including forming bit line structures above a substrate; forming recessed insulating material layers between the bit line structures, the top surfaces of the recessed insulating material layers being lower than the top surfaces of the bit line structures; forming a capping layer in a dummy region and exposing an array region, the dummy region being located at the edge of the array region, the portion of the bit line structures covered by the capping layer being a plurality of dummy bit lines, the portion of the bit line structures exposed by the capping layer being a plurality of bit lines, and the portion of the recessed insulating material layers covered by the capping layer being a dummy insulating structure; and removing the portion of the recessed insulating material layers located in the array region.

[0006] According to the DRAM device and manufacturing method disclosed herein, by forming a dummy insulating structure in the dummy region and forming a capping layer to seal the top of the dummy bit lines and the dummy insulating structure, the effect of preventing etchant from penetrating into the dummy region can be achieved. Therefore, the embodiments can precisely define the range of the array region, thereby increasing the number of active bits that can be formed, reducing the number of dummy bits, and facilitating process miniaturization. Attached Figure Description

[0007] Figure 1 This is a partial top view of the array region and peripheral region of a DRAM device according to some embodiments of the present disclosure during one step.

[0008] Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8 , Figure 9 This is a schematic diagram of a DRAM device at various intermediate manufacturing stages according to some embodiments of this disclosure. Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 6A , Figure 7A A partial 3D view of the DRAM device; Figure 5B , Figure 6B , Figure 7B , Figure 8 , Figure 9 Is along, for example Figure 1 A partial cross-sectional view of the DRAM device is shown in the section line AA direction.

[0009] Figure 10 This is a cross-sectional schematic diagram of an intermediate manufacturing stage of a DRAM device according to some embodiments of the present disclosure.

[0010] Figure 11 A partial top view of the array region and peripheral region of a DRAM device according to some embodiments of the present disclosure is shown.

[0011] Legend

[0012] 10: DRAM devices

[0013] 100: Base

[0014] 13a, 23a, 24a, 25a, 26a, 262a, 273a, 421a, 611a: Top surface

[0015] 421b: Bottom surface

[0016] 101: Active Region

[0017] 102: Isolation Structure

[0018] 104: Word Line

[0019] 13: Dummy bit line

[0020] 13T, 23T: Top

[0021] 241: Semiconductor material layer

[0022] 243: Conductive material layer

[0023] 21: Position line contact element

[0024] 23: Bit Line

[0025] 230: Bitline stacking structure

[0026] 231: Bitline Structure

[0027] 24: Bitline layer

[0028] 25: Mask layer

[0029] 26, 262: Insulating material layer

[0030] 262h: Node contact hole

[0031] 264: Concave

[0032] 27: Spacing structure

[0033] 271: First spacer material layer

[0034] 272: Second spacer material layer

[0035] 273: Third spacer material layer

[0036] 32: Component Structure

[0037] 320: Gate oxide layer

[0038] 321: Semiconductor layer

[0039] 322: First gate conductive layer

[0040] 323: Second gate conductive layer

[0041] 325: Hard mask layer

[0042] 326: Spacer

[0043] 40: Patterned Mask

[0044] 401: Striped pattern

[0045] 403: Gap

[0046] 410: First dielectric layer

[0047] 41: The remaining portion of the first dielectric layer

[0048] 420: Second dielectric layer

[0049] 42: Cap layer

[0050] 421: Main body

[0051] 422: Protrusion

[0052] 51: Photoresist pattern

[0053] 42E, 51E, AD-E: Edge

[0054] 610: Capacitor contact structure

[0055] 611: Node contact plug

[0056] 615: Landing mat

[0057] A1: Array area

[0058] A2: Surrounding Area

[0059] AD: Virtual Area

[0060] D1: First Direction

[0061] D2: Second Direction

[0062] D3: Third direction

[0063] AA: Section Detailed Implementation

[0064] The following provides many different embodiments for implementing different components of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the invention. Furthermore, when the description refers to a first element being formed above or on a second element, unless specifically excluded, it can mean that the first and second elements are in direct contact or not. Additionally, for the purpose of simplicity and clarity, the embodiments of the present invention may use the same or similar element symbols for the same or similar elements in many examples, and may only show a portion of the DRAM device relating to the present invention.

[0065] The following is Figures 1 to 10 This disclosure describes an embodiment of a DRAM device and a method for manufacturing the same. Please refer to... Figure 1 and Figure 10 The DRAM device 10 includes a substrate 100, multiple word lines 104, bit line contacts 21, dummy bit lines 13, bit lines 23, and capacitor contact structures 610. The substrate 100 includes an array region A1, a peripheral region A2, and a dummy region AD located between the array region A1 and the peripheral region A2. Furthermore, the substrate 100 may include multiple doped regions as active regions 101. An isolation structure 102 surrounding the active regions 101 and multiple word lines 104 may be formed in the substrate 100.

[0066] In some embodiments, each bit line 23 and each dummy bit line 13 may extend along a first direction D1, and these bit lines 23 and dummy bit lines 13 may be arranged along a third direction D3. The first direction D1 is, for example (but not limited to), perpendicular to a second direction D2. Furthermore, each word line 104 may extend along a third direction D3, that is, the word lines 104 may intersect with the bit lines 23, and these word lines 104 may be arranged along the first direction D1. In one embodiment, the extension direction of each active region 101 may form an angle (e.g., approximately 10° to 40°) with the third direction D3 to improve aggregation. In some embodiments, each active region 101 may intersect with two word lines 104 and one bit line 23, and may be electrically connected to the upper bit line 23 via bit line contacts 21. Viewed from top, these bit line contacts 21 may be staggered and may be spaced apart from the word lines 104 in the extension direction of the bit lines 23 (e.g., along the first direction D1).

[0067] In some embodiments, word lines 104 may be formed in the substrate 100 such that their top surface is lower than the top surface of the substrate 100, and are therefore also referred to as buried word lines. Each word line 104 may include a gate dielectric layer, a barrier layer, and a conductive layer formed sequentially in a trench. The word lines 104 may be formed using known structures and methods. After the word lines 104 are formed in the trench, an insulating layer may be formed over each word line 104 to fill any remaining gaps in the trench, such that the top surface of the insulating layer is substantially coplanar with the top surface of the substrate 100.

[0068] This disclosure proposes a novel DRAM device and its manufacturing method to address the problem in existing processes where etching solution improperly penetrates beyond the predetermined area of ​​the array region during the removal of the sacrificial oxide layer. Therefore, compared to conventional processes, the manufacturing method proposed in this disclosure can accurately define the range of the array region and reduce the number of dummy components (or the area of ​​the dummy region AD). The following is an illustration of the manufacturing method of some embodiments of the DRAM device disclosed herein.

[0069] Reference Figure 2 The substrate 100 may be made of semiconductor materials, such as silicon, gallium arsenide, gallium nitride, germanium silicide, or combinations thereof. In another embodiment, the substrate 100 may be a substrate with a semiconductor overlaid on an insulating layer. In this document, when the film layer is formed in a blanket manner, it means that the formed film layer simultaneously covers both the array region A1 and the peripheral region A2. The isolation structure 102 may be a shallow trench isolation structure, for example, comprising an isolation liner and an isolation filler formed sequentially. The isolation liner and the isolation filler may comprise nitrides or oxides, such as silicon oxide, silicon nitride, silicon oxynitride, and / or combinations thereof. It should be understood that this disclosure may employ any known isolation structure 102 and its manufacturing method.

[0070] According to some embodiments, a plurality of bit line stack structures 230 are formed over a substrate 100. In some embodiments, the bit line stack structure 230 includes a bit line layer 24 on the substrate 100 and a mask layer 25 on the bit line layer 24. The bit line layer 24 includes, for example, a semiconductor material layer 241 and a conductive material layer 243 in sequence.

[0071] In some embodiments, the semiconductor material layer 241 may be an undoped semiconductor layer, a doped semiconductor layer, or a polysilicon layer. Bit line contacts 21 may extend into the substrate 100 and may comprise polysilicon, a metal, or a metal nitride. The conductive material layer 243 may comprise a first conductive material layer on the semiconductor material layer 241 and a second conductive material layer on the first conductive material layer. The first and second conductive material layers may comprise undoped or doped polysilicon, a metal, or a metal nitride, such as tungsten (W), titanium (Ti), or titanium nitride (TiN). The resistance of the second conductive material layer above it is, for example, lower than the resistance of the semiconductor material layer 241. In some examples, the semiconductor material layer 241 is, for example, polysilicon, and the first and second conductive material layers of the conductive material layer 243 are, respectively, a titanium nitride layer and a tungsten metal layer. The mask layer 25 may comprise nitrides, oxides, or combinations thereof.

[0072] Additionally, multiple device structures 32 may be formed in the peripheral region A2. The device structure 32 may be, for example, a gate stack of a transistor device. In one embodiment, the device structure 32 includes, sequentially formed on the substrate 100, a gate oxide layer 320, a semiconductor layer 321 (e.g., a polysilicon layer), a first gate conductive layer 322 (e.g., a titanium nitride layer), a second gate conductive layer 323 (e.g., a tungsten metal layer), and a hard mask layer 325 (e.g., a silicon nitride layer). Spacers 326 are formed on the sidewalls of the device structure 32. It should be understood that this disclosure may employ any known device structure 32 and its manufacturing method, and is not limited thereto.

[0073] Additionally, in some embodiments, during the formation of the bit line stack structure 230, the corresponding bit line contact 21 and its surrounding substrate 100 are partially removed to form recesses surrounding each bit line contact 21. These recesses expose portions of the active region 101 and portions of the isolation structure 102.

[0074] Subsequently, spacer structures 27 can be formed on the sidewalls of these bit line stack structures 230 and the aforementioned recesses to form a bit line structure 231 comprising the bit line stack structure 230 and the spacer structures 27. The spacer structures 27 may include combinations of different dielectric materials, such as a first spacer material layer 271, a second spacer material layer 272, and a third spacer material layer 273. In some embodiments, the first spacer material layer 271 may fill the recesses, and the second spacer material layer 272 may be formed on the sidewalls of the bit line stack structure 230. The second spacer material layer 272 may also be formed on the first spacer material layer 271. The third spacer material layer 273 may be conformally formed on the second spacer material layer 272. The first spacer material layer 271, the second spacer material layer 272, and the third spacer material layer 273 may each comprise, for example, silicon oxide, silicon nitride, other suitable dielectric materials, air gaps, or combinations thereof. In some embodiments, the third spacer material layer 273 and the second spacer material layer 272 may comprise different materials. For example, the third spacer material layer 273 may be a silicon nitride layer. An insulating material layer 26 may be formed on the third spacer layer 273 to fill the gaps. The top surface 273a of the third spacer layer 273 may be coplanar with the top surface 26a of the insulating material layer 26.

[0075] Then, refer to Figure 3According to some embodiments, a patterned mask 40 is formed over the bit line structure 231 and the insulating material layer 26. The patterned mask 40 includes a plurality of strip patterns 401, with gaps 403 between the strip patterns 401. The extension direction of the strip patterns 401 is different from (e.g., but not limited to, perpendicular to) the extension direction of the bit line structure 231. For example, if each bit line structure 231 extends in a first direction D1, then each strip pattern 401 may extend in a third direction D3. The gaps 403 expose a portion of the bit line structure 231 and the insulating material layer 26, and the ends may expose a portion of the insulating material layer 26 closest to the peripheral region A2. The strip patterns 401 and the bit line structure 231 are used to define the node contact plugs 611 (marked in...) of the DRAM device. Figure 10 The position of (in the middle). In this embodiment, the patterned mask 40 can cover the peripheral area A2, and the gap 403 does not expose the element structure 32.

[0076] Then, refer to Figure 4 According to some embodiments, a first dielectric layer 410 is formed over a patterned mask 40 to fill the gaps 403 between the stripe patterns 401. The first dielectric layer 410 and the stripe patterns 401 comprise different materials. For example, the first dielectric layer 410 comprises a nitride, and the stripe patterns 401 comprise an oxide.

[0077] Then, refer to Figure 5A , Figure 5B The first dielectric layer 410 is etched back to expose the stripe pattern 401, and the remaining portion 41 of the first dielectric layer 410 still fills the gaps 403 between the stripe patterns 401. Then, the stripe pattern 401 is removed to expose the underlying insulating material layer 26. Next, according to some embodiments of this disclosure, the insulating material layer 26 is further recessed, for example by an etch-back process, to expose the top 23T of the bit line structure 231, forming a recessed insulating material layer 262 between the bit line structures 231. Figure 5B As shown, in some embodiments, the top surface 262a of the recessed insulating material layer 262 is lower than the top surface 23a of the bit line structure 231, for example, lower than the top surface 25a of the mask layer 25, and higher than the top surface 24a of the bit line layer 24.

[0078] In detail, after the recessed insulating material layer 26, the tops 23T of two adjacent bit line structures 231 together with the top surface 262a of the recessed insulating material layer 262 between them define a recess 264. According to this disclosure, the degree of recess in the recessed insulating material layer 262 is such that a gap is created between the tops 23T of the bit line structures 231 closest to the peripheral region A2, so that the subsequently formed capping layer can at least fill the recess 264 closest to the peripheral region A2 and act as a capping layer for the recessed insulating material layer 262.

[0079] Then, refer to Figure 6A , Figure 6B A second dielectric layer 420 is formed by blanketing the remaining portion 41 of the first dielectric layer and the recessed insulating material layer 262. The second dielectric layer 420 also fills the recess 264 above the recessed insulating material layer 262. In this way, the second dielectric layer 420 can cover the top 23T of the bit line structure 231.

[0080] In some embodiments, the second dielectric layer 420 and the insulating material layer 26 comprise different materials. The second dielectric layer 420 may comprise a denser material than the insulating material layer 26 and a dielectric material with a relatively high selectivity for etchants that remove the insulating material layer 26, to form a protective effect like a sealing cap over the recessed insulating material layer 262. For example, the insulating material layer 26 may comprise silicon oxide, and the second dielectric layer 420 may comprise silicon nitride.

[0081] According to the embodiments disclosed herein, after a second dielectric layer 420 is formed over the bit line structure 231 and the recessed insulating material layer 262 and the recess 264 is filled, the range of active bits in the array region A1 is then defined.

[0082] Reference Figure 7A , Figure 7B According to some embodiments, a photoresist pattern 51 is formed on the second dielectric layer 420. The opening of the photoresist pattern 51 corresponds to the array region A1 and covers the dummy region AD. In detail, the photoresist pattern 51 is separated from the underlying bit line structure 231 and the recessed insulating material layer 262 by the second dielectric layer 420.

[0083] Then, refer to Figure 8 According to some embodiments, a second dielectric layer 420 is patterned using a photoresist pattern 51 as an etching mask to remove a portion of the second dielectric layer 420, leaving a capping layer 42. For example, dry etching is used to remove the portion of the second dielectric layer 420 exposed by the openings in the photoresist pattern 51, exposing the top 23T of the bit line structure 231 in the array region A1 and the recessed insulating material layer 262. The formed capping layer 42 covers the bit line structure 231 in the dummy region AD and fills the recess 264 above the recessed insulating material layer 262 in the dummy region AD. In some embodiments, the edge 42E of the capping layer 42 is substantially aligned with the edge 51E of the photoresist pattern 51 and also substantially aligned with the edge AD-E of the dummy region AD.

[0084] Then, refer to Figure 9Using the capping layer 42 as a mask, the recessed insulating material layer 262 located in the array region A1 is removed to form a node contact hole 262h. In one embodiment, the exposed substrate 100 may be further etched so that the node contact hole 262h extends into the substrate 100. The recessed insulating material layer 262 can be removed by a wet etching process using blister etching. In some embodiments, the etchant of the aforementioned wet etching process has a high selectivity for the capping layer 42 and the insulating material layer 26, selectively removing the insulating material layer 26, but not substantially affecting the capping layer 42. In this disclosure, the capping layer 42 can prevent the etchant from penetrating into the dummy region AD during the formation of the node contact hole 262h, preventing the recessed insulating material layer 262 located in the dummy region AD from being etched. After the node contact hole 262h is formed, the dummy region AD still retains the recessed insulating material layer 262 (or dummy insulating structure). The photoresist pattern 51 can then be removed by, for example, an ashing process, leaving a capping layer 42.

[0085] According to one embodiment of this disclosure, such as Figure 9 As shown, the capping layer 42 is located in the dummy region AD, and the bit line structure 231 covered by the capping layer 42 can be referred to as the dummy bit line 13. In contrast, the bit line structure 231 located in the array region A1 and not covered by the capping layer 42 can be referred to as the bit line 23. The capping layer 42 includes a main body portion 421 and a protrusion portion 422. The main body portion 421 is located on the dummy bit line 13 and covers its top surface 13a (i.e., the top surface of the mask layer 25 or the third spacer material layer 273). The protrusion portion 422 protrudes from the bottom surface 421b of the main body portion 421 and fills the gap between the top 13T of the dummy bit lines 13 (i.e., the recess 264 above the insulating material layer 262) to act as a seal on the recessed insulating material layer 262. In addition to being located in the dummy region AD, the main body portion 421 of the capping layer 42 can also extend to the peripheral region A2. The top surface of the capping layer 42 (e.g., the top surface 421a of the main body 421) is higher than the top surface of the spacer structure 27 (e.g., the top surface 273a of the third spacer material layer 273). Furthermore, the top surface 421a of the main body 421 is a generally flat surface and can have good adhesion to the photoresist pattern 51 subsequently formed on it.

[0086] After that, as Figure 10As shown, a node contact plug 611 can be formed in the node contact hole 262h, located on one side of the bit line 23 and contacting the active region 101. The height of the top surface of the node contact plug 611 may be between the top and bottom surfaces of the mask layer 25, but the invention is not limited thereto. In some embodiments, the conductive material forming the node contact plug 611 includes, for example, doped polysilicon, metal, or metal nitride, metal silicide, or a combination thereof. In this embodiment, the node contact plug 611 includes a doped polysilicon layer 611' and a metal silicide layer 612 (e.g., cobalt silicide (CoSi)) formed sequentially to reduce subsequent contact resistance.

[0087] Subsequently, according to some embodiments, a landing pad 615 comprising a barrier layer 613 and a conductive layer 614 may be formed on the node contact plug 611. The barrier layer 613 may comprise a metal nitride, such as titanium nitride (TiN). The conductive layer 614 may comprise doped polysilicon, a metal, or a metal nitride, such as tungsten (W). The landing pad 615 serves to electrically connect the node contact plug 611 to a subsequently formed capacitor. Hereinafter, the landing pad 615 and the node contact plug 611 are collectively referred to as the capacitor contact structure 610. The capacitor contact structure 610 is electrically connected to the active region 101. Subsequently, an insulator 620 is formed between two adjacent landing pads 615. Furthermore, according to some embodiments, the top surface 262a of the dummy insulating structure 262 may be higher than the top surface 611a of the node contact plug 611.

[0088] After forming the capacitor contact structure 610, any known components such as capacitors, metal layers, etc., can be formed to complete the fabrication of the DRAM device 10. It is worth noting that in the above embodiments or variations thereof, the steps may include other known applicable processes. For the sake of simplicity and clarity of the embodiments, the drawing and detailed description of these known processes are omitted.

[0089] like Figure 10 As shown, in some embodiments of the DRAM device 10 disclosed herein, the capping layer 42 has multiple protrusions 422 extending downward between the dummy bit lines 13 and filling the recesses 264, thus forming a protective function like a sealing cap above the dummy insulating structure 262. In this way, when removing the recessed insulating material layer 262 of the array region A1, the capping layer 42 can prevent etchant from penetrating to areas other than the active bits, i.e., the etchant cannot penetrate into the dummy region AD, thereby protecting the dummy bit lines 13 and the dummy insulating structure 262 located in the dummy region AD. Therefore, as Figure 7A The photoresist pattern 51 shown can accurately define the range of active bits to be formed, thereby reducing the number of dummy bits. An example is provided below with accompanying diagrams.

[0090] Reference Figure 11The diagram illustrates a partial top view of the array region A1 and the peripheral region A2 of a DRAM device according to some embodiments of the present disclosure. Figure 11 An embodiment is shown in which a capping layer 42 and a photoresist pattern 51 surround an array region A1, and the edge 42E of the capping layer 42 is substantially aligned with the edge 51E of the photoresist pattern 51.

[0091] In traditional manufacturing processes, during the formation of node contact holes, the etchant penetrates from the bottom edge of the photoresist pattern, rather than removing the insulating material layer beneath it as intended. The closer the insulating material layer is to the edge of the photoresist pattern, the deeper the resulting hole depth. Since traditional methods cannot control this penetration problem, the only solution is to increase the coverage area of ​​the photoresist pattern (e.g., the area from the edge E0 to the dashed line E2 of a traditional photoresist pattern is the traditional dummy area). However, this sacrifices the area of ​​the array region A1, reducing the number of active bits and thus increasing costs. Furthermore, the holes created after forming the node contact holes are filled with conductive material in subsequent processes. The deeper the holes, the closer the bottom of the filled conductive material is to the substrate, making it easier to form leakage paths.

[0092] By using the capping layer 42 in this embodiment to block the penetration of the etchant, its cooperation with the photoresist pattern 51 can precisely define the range of the active bit region (in the array region A1), without considering the penetration effect of the etchant, making the process simple and time-saving. Therefore, compared with the edge E0 of the traditional photoresist pattern, the edge 51E of the photoresist pattern 51 can be closer to the peripheral region A2 (the range from edge 51E to the dashed line E2 is the range of the dummy region AD in this embodiment). That is, the range for forming active bits can be further expanded outward, thereby increasing the number of active bits that can be formed and reducing the number of dummy bits. Furthermore, the capping layer 42 can protect the recessed insulating material layer 262 in the dummy region AD from being etched away, so that it will not be filled with conductive material in subsequent processes, thus preventing leakage paths and improving product yield. In addition, the expanded region obtained by this embodiment (i.e., the range from edge E0 to edge 51E) can be used to set other components, such as setting repair bits to repair defects in the DRAM device 10, thereby improving yield. Furthermore, this embodiment can accurately define the range of the array region A1 and reduce the range of the dummy region AD, which is beneficial to the miniaturization of the DRAM device 10.

[0093] Compared to traditional processes, this embodiment can increase the number of active bits, allowing for a higher number of memory bits per wafer, thus achieving production targets with fewer wafers. Therefore, this invention reduces manufacturing costs and energy consumption, thereby decreasing carbon emissions, water resources, and chemical usage per unit of DRAM device production. Furthermore, the improved yield of the DRAM device and its manufacturing method reduces waste during manufacturing. Therefore, this invention provides a green semiconductor technology.

Claims

1. A dynamic random access memory (DRAM) device, comprising: Comprising: a substrate comprising an array region, a peripheral region, and a dummy region between the array region and the peripheral region; a plurality of bit lines over the substrate in the array region; a plurality of dummy bit lines over the substrate in the dummy region; a dummy insulating structure between the dummy bit lines, and a top surface of the dummy insulating structure is lower than a top surface of the dummy bit lines; and a cap layer over the dummy region covering a top of the dummy bit lines and a top of the dummy insulating structure. The cap layer comprises:

2. The DRAM device of claim 1, wherein, a main portion covering the top surfaces of the dummy bit lines; and a plurality of protruding portions protruding from a bottom surface of the main portion to fill recesses on the dummy insulating structure. Further comprising:

3. The DRAM device of claim 1, wherein, a capacitance contact structure between the bit lines and electrically connected to an active region in the substrate, wherein each of the dummy bit lines comprises a spacer structure on sidewalls of each of the dummy bit lines, and a top surface of the cap layer is higher than a top surface of the spacer structure. Each of the bit lines and each of the dummy bit lines each comprises:

4. The DRAM device of claim 3, wherein, a bit line layer over the substrate; and a mask layer over the bit line layer, wherein the top surface of the dummy insulating structure is lower than a top surface of the mask layer. The top surface of the dummy insulating structure is higher than a top surface of the bit lines.

5. The DRAM device of claim 4, wherein, The cap layer and the dummy insulating structure comprise different materials.

6. The DRAM device of claim 3, wherein, The capacitance contact structure comprises:

7. The DRAM device of claim 3, wherein, a node contact plug contacting the substrate; and a landing pad over the node contact plug, wherein the top surface of the dummy insulating structure is higher than a top surface of the node contact plug. The cap layer comprises nitride.

8. The DRAM device of claim 1, wherein, The cap layer further extends to the peripheral region to cover a plurality of element structures of the peripheral region.

9. The DRAM device of claim 1, wherein, Comprising:

10. A method of manufacturing a DRAM device, characterized by, forming a plurality of bit line structures over a substrate; forming a plurality of recessed insulating material layers between the bit line structures, a top surface of the recessed insulating material layers being lower than a top surface of the bit line structures; forming a cap layer over a dummy region and exposing an array region, the dummy region being located at an edge of the array region, portions of the bit line structures covered by the cap layer being a plurality of dummy bit lines, portions of the bit line structures exposed by the cap layer being a plurality of bit lines, and portions of the recessed insulating material layers covered by the cap layer being a dummy insulating structure; and removing portions of the recessed insulating material layers located in the array region. The cap layer comprises:

11. The method of manufacturing a DRAM device according to claim 10, wherein, a main portion covering top surfaces of the dummy bit lines; and a plurality of protruding portions protruding from a bottom surface of the main portion to fill recesses on the dummy insulating structure. Further comprising:

12. The method for manufacturing a DRAM device according to claim 10, wherein, forming a capacitance contact structure between the bit lines and electrically connected to an active region in the substrate, wherein each of the dummy bit lines comprises a spacer structure on sidewalls of each of the dummy bit lines, and a top surface of the cap layer is higher than a top surface of the spacer structure. Forming the recessed insulating material layers comprises:

13. The method for manufacturing a DRAM device according to claim 10, wherein filling an insulating material layer between the bit line structures, a top surface of the insulating material layer being coplanar with top surfaces of the bit line structures; ​ forming a patterned mask over the bit line structures and the insulating material layer, the patterned mask comprising a plurality of strip patterns, each of the strip patterns extending in a direction different from that of each of the bit line structures; blanket forming a first dielectric layer over the patterned mask, the first dielectric layer filling gaps between the strip patterns; removing portions of the first dielectric layer to expose the strip patterns; removing the strip patterns to expose the insulating material layer; and recessing the insulating material layer to expose top portions of the bit line structures and to form the recessed insulating material layer between the bit line structures.

14. The method of fabricating a DRAM device of claim 10, wherein, each of the bit lines and the dummy bit lines comprises: a bit line layer over the substrate; and a mask layer over the bit line layer, wherein a top surface of the dummy insulating structure is lower than a top surface of the mask layer.

15. The method of manufacturing a DRAM device according to Claim 14, wherein, the top surface of the dummy insulating structure is higher than a top surface of the bit line layer.

16. The method of fabricating a DRAM device of claim 13, wherein, the cap layer and the insulating material layer comprise different materials.

17. The method of fabricating a DRAM device of claim 10, wherein, removing portions of the recessed insulating material layer in the array region by a wet etch, the wet etch having a high selectivity ratio for the cap layer and the recessed insulating material layer.

18. The method for manufacturing a DRAM device according to Claim 10, wherein, further comprising forming a capacitor contact structure between the bit lines, wherein the capacitor contact structure comprises: a node contact plug contacting the substrate; and a landing pad over the node contact plug, wherein a top surface of the dummy insulating structure is higher than a top surface of the node contact plug.

19. The method of fabricating a DRAM device of claim 10, wherein, the cap layer comprises nitride.

20. The method of fabricating a DRAM device of claim 10, wherein, the cap layer further extends to a peripheral region to cover element structures in the peripheral region, the dummy region being between the array region and the peripheral region.

Images