Dynamic random access memory structure and manufacturing method thereof
By employing a storage node contact window structure that is narrow at the top and wide at the bottom in dynamic random access memory, the problem of increased resistance caused by reduced contact area is solved, thereby improving component current and manufacturing process stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-24
- Publication Date
- 2026-03-10
AI Technical Summary
As component linewidths shrink, the contact area between the memory node contact window and the active region of the component in dynamic random access memory becomes smaller, leading to increased resistance. Furthermore, the manufacturing process for contact windows with high aspect ratios becomes more complex and difficult.
The memory node contact window structure is narrower at the top and wider at the bottom. By forming the memory node contact window on both sides of the bit line, the contact area is increased, and the interface is formed through a multi-step etching process to ensure good contact.
The reduced resistance and increased component current enhance the fabrication margin of the structure, ensuring that overall performance is not affected even with a reduced linewidth.
Smart Images
Figure CN121645849A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor structure and its manufacturing method, and particularly to a dynamic random access memory (DRAM) structure and its manufacturing method. Background Technology
[0002] A dynamic random access memory (DRAM) has been developed, comprising transistors and capacitors coupled to each other. In this DRAM, capacitors are used as storage nodes. However, as component linewidths shrink, the contact area between the storage node contact (SNC) and the active region of the component decreases, leading to increased resistance. Furthermore, the fabrication process for high aspect ratio contact windows becomes increasingly complex and difficult. Summary of the Invention
[0003] This invention provides a dynamic random access memory structure with an improved storage node contact window (SNC) contact area, thereby reducing resistance and increasing component current, and ensuring that the overall performance of the structure is not affected even if the linewidth is reduced.
[0004] The present invention also provides a method for manufacturing a dynamic random access memory structure, which can increase the manufacturing process margin and create a contact window that is narrow at the top and wide at the bottom to increase the SNC contact area.
[0005] A dynamic random access memory (DRAM) structure according to the present invention includes a substrate, a component isolation structure, embedded word lines, bit lines, and multiple memory node contact windows. The component isolation structure is located in the substrate and defines multiple active regions within the substrate. The embedded word lines are located in the substrate and intersect with the active regions and the component isolation structure, wherein the embedded word lines extend along a first direction. The bit lines are located on the substrate and extend along a second direction, wherein the second direction is perpendicular to the first direction. Memory node contact windows are located on both sides of the bit lines and extend from above the substrate into each active region. Each memory node contact window has a top-narrow, bottom-wide structure and has an interface within the top-narrow, bottom-wide structure.
[0006] In one embodiment of the present invention, the top surface of each active area below the contact window of the storage node is concave and complementary to the bottom surface of the above-mentioned narrow-at-the-top and wide-at-the-bottom structure.
[0007] In one embodiment of the present invention, in a top view, the upper area of the above-mentioned narrow-at-the-top and wide-at-the-bottom structure is smaller than its lower area.
[0008] In one embodiment of the present invention, the interface within the above-described narrow-at-the-top and wide-at-the-bottom structure is located below the top of the substrate.
[0009] In one embodiment of the present invention, the interface within the above-mentioned narrow-at-the-top and wide-at-the-bottom structure is a concave surface.
[0010] In one embodiment of the present invention, the above-described dynamic random access memory structure may further include a plurality of bit line spacers located on the sidewalls of the bit lines.
[0011] In one embodiment of the present invention, the upper part of the narrow-upper-wide-lower structure is located on the side wall of the bit line gap wall, and the lower part of the narrow-upper-wide-lower structure is located below the bit line gap wall.
[0012] In one embodiment of the present invention, the above-described dynamic random access memory structure may further include a bit line contact window located between the bit line and the active region below it.
[0013] In one embodiment of the present invention, the bottom surface of the bit line contact window is lower than the bottom surface of the storage node contact window.
[0014] In one embodiment of the present invention, the above-described dynamic random access memory structure may further include a barrier layer located between the bit line contact window and the memory node contact window.
[0015] Another method for manufacturing a dynamic random access memory (DRAM) structure according to the present invention includes the following steps: Forming a component isolation structure within a substrate to define a plurality of active regions. Forming embedded word lines in the substrate that intersect the plurality of active regions and the component isolation structure, wherein the embedded word lines extend along a first direction. Forming bit lines on the substrate extending along a second direction, exposing the active regions and the component isolation structure, wherein the second direction is perpendicular to the first direction. Performing a first etching process on the substrate to form first recesses in the active regions on both sides of the bit lines. Forming a first conductor layer within the first recesses. Forming bit line spacers on the sidewalls of the bit lines. Performing a second etching process to form second recesses in the first conductor layer. Forming a second conductor layer within the second recesses, such that the first conductor layer and the second conductor layer constitute a memory node contact window.
[0016] In another embodiment of the present invention, before forming the bit line on the substrate, the invention may further include forming a bit line contact window opening on an active region overlapping with the bit line, and then forming a bit line contact window in the bit line contact window opening, wherein the width of the bit line contact window opening is greater than the width of the bit line contact window.
[0017] In another embodiment of the invention, after forming the bit line, a barrier layer may be formed within the bit line contact window opening.
[0018] In another embodiment of the present invention, the first etching process includes using a first patterned mask layer to cover the structure other than the first recess.
[0019] In another embodiment of the present invention, the second etching process includes using a second patterned mask layer to cover the structure other than the second recess.
[0020] In another embodiment of the invention, the first recess extends into the element isolation structure adjacent to the active region.
[0021] In another embodiment of the invention, the bit line gap wall partially overlaps with the first conductor layer.
[0022] To make the above features of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description
[0023] Figure 1 This is a cross-sectional view of an intermediate fabrication process of a dynamic random access memory structure according to an embodiment of the present invention.
[0024] Figure 2 yes Figure 1 A top view of the dynamic random access memory architecture;
[0025] Figure 3 Therefore Figure 1 A cross-sectional view of the structure for subsequent manufacturing processes;
[0026] Figure 4 Therefore Figure 3 A cross-sectional view of the structure for subsequent manufacturing processes;
[0027] Figure 5 Therefore Figure 4 A cross-sectional view of the structure for subsequent manufacturing processes;
[0028] Figure 6 Therefore Figure 5 A cross-sectional view of the structure for subsequent manufacturing processes;
[0029] Figure 7 yes Figure 6 A top view of the dynamic random access memory architecture;
[0030] Figure 8 Therefore Figure 6 A cross-sectional view of the structure for subsequent manufacturing processes;
[0031] Figure 9 Therefore Figure 8 A cross-sectional view of the structure for subsequent manufacturing processes;
[0032] Figure 10 Therefore Figure 9 A cross-sectional view of the structure for subsequent manufacturing processes;
[0033] Figure 11 yes Figure 10 A top view of the dynamic random access memory architecture;
[0034] Figure 12 Therefore Figure 10 A cross-sectional view of the structure for subsequent manufacturing processes.
[0035] Symbol Explanation
[0036] 100: Base
[0037] 100t: Top
[0038] 102: Component isolation structure
[0039] 104: First dielectric layer
[0040] 106: Second dielectric layer
[0041] 108: Third dielectric layer
[0042] 110, 110': Bit line contact window
[0043] 110b: Bottom surface
[0044] 112: Top Cover Layer
[0045] 114: Lining
[0046] 116: Barrier Layer
[0047] 116t, AAT: Top surface
[0048] 118, 120: Spare wall of the position line
[0049] 122: Interface
[0050] 124: Barrier layer
[0051] 126: Conductive layer
[0052] AA: Active Zone
[0053] BL: Bitline
[0054] C1: First conductor layer
[0055] C2: Second conductor layer
[0056] O1: Bit line contact window opening
[0057] PM1: First patterned mask layer
[0058] PM2: Second Patterned Mask Layer
[0059] R1: First recessed portion
[0060] R2: Second recess
[0061] SNC: Storage Node Contact Window
[0062] w1, w2: Width
[0063] WL: Embedded letter line Detailed Implementation
[0064] The invention can be understood by referring to the following detailed description and the accompanying drawings. Furthermore, the dimensions of the various regions in the drawings are for illustrative purposes only and are not intended to limit the scope of the invention.
[0065] Figures 1 to 12 This is a manufacturing flowchart of a dynamic random access memory structure according to an embodiment of the present invention, wherein... Figure 2 , Figure 7 and Figure 11 This is a top view, and for clarity, some components have been omitted. Figure 1 , Figures 3-6 , Figures 8-10 as well as Figure 12 This is a cross-sectional view of the manufacturing process shown by line I-I' in the aforementioned top view, and the scale of the cross-sectional view does not completely match that of the aforementioned top view.
[0066] Please refer to the following: Figure 1 and Figure 2 A device isolation structure 102 is formed within a substrate 100 to define an active region AA, wherein the substrate 100 is, for example, a silicon substrate, and the device isolation structure 102 is, for example, a shallow trench isolation structure (STI), but is not limited thereto. (In top view...) Figure 2The diagram shows that embedded word lines WL are formed in the substrate 100, intersecting with a plurality of active regions AA and a component isolation structure 102. The embedded word lines WL extend along a first direction (e.g., the Y direction), and the method for forming the embedded word lines WL can utilize existing technology. Then, a stacked structure comprising a first dielectric layer 104, a second dielectric layer 106, and a third dielectric layer 108 can be formed on the surface of the substrate 100, wherein there is an etch selectivity between the first dielectric layer 104 and the second dielectric layer 106, and an etch selectivity between the second dielectric layer 106 and the third dielectric layer 108. In one embodiment, the first dielectric layer 104 and the third dielectric layer 108 are silicon oxide layers, and the second dielectric layer 106 is a silicon nitride layer, but the invention is not limited thereto. In other embodiments, the first dielectric layer 104, the second dielectric layer 106, and the third dielectric layer 108 can be made of other suitable materials. Furthermore, one or more layers of the above-described stacked structure can be omitted, or one or more layers can be added therebetween. Next, a bit line BL extending along a second direction (such as the X direction) is formed on the substrate 100, exposing the active region AA and the device isolation structure 102, wherein the second direction is perpendicular to the first direction. Before forming the bit line BL, a bit line contact window opening O1 may be formed on the active region AA that overlaps with the bit line BL, and then a bit line contact window 110 may be formed in the bit line contact window opening O1. The method for forming the bit line contact window opening O1 may include, but is not limited to, forming a patterned photoresist (not shown) on the third dielectric layer 108 to expose the area where the bit line contact window opening O1 is to be formed, and then using an etching process to remove the stacked structure in the exposed area and the substrate 100 below it. The method for forming the bit line contact window 110 includes, but is not limited to, forming a polysilicon layer, a metal layer, and a silicon nitride layer sequentially on the entire substrate 100, and then using photolithography and etching processes to define the bit line contact window 110, bit line BL, and capping layer 112 within the bit line contact window opening O1, and defining the bit line contact window 110', bit line BL, and capping layer 112 on a third dielectric layer 108 outside the bit line contact window opening O1, with a second dielectric layer 106 serving as an etching stop layer. However, the invention is not limited to this. In other embodiments, the bit line contact window 110' outside the bit line contact window opening O1 can be replaced with a nitride or oxide. The materials of the bit line contact window 110, bit line BL, and capping layer 112 can also be other suitable materials. In this embodiment, the width w1 of the bit line contact window opening O1 is greater than the width w2 of the bit line contact window 110, so that a barrier layer can be subsequently formed within the bit line contact window opening O1. When there is a bit line contact window opening O1, the position of the embedded word line WL (in the Z direction) will be lower than the bit line contact window opening O1.
[0067] Then, please refer to Figure 3After the bit line BL is formed, a barrier layer 116 can be formed within the bit line contact window opening O1. Before forming the barrier layer 116, a liner 114 is formed on the surface of the bit line contact window opening O1, which facilitates the adhesion of the barrier layer 116 to the device isolation structure 102 and the active region AA. In one embodiment, the liner 114 is, for example, a silicon oxide layer, and the barrier layer 116 is, for example, a silicon nitride layer, but the invention is not limited thereto. In other embodiments, the liner 114 and the barrier layer 116 can be made of other suitable materials. Then, a bit line spacer 118 is conformally deposited on the surface of the second dielectric layer 106 and on the bit line BL and the capping layer 112. The material of the bit line spacer 118 is, for example, silicon carbide (SiCO) or silicon oxide, but the invention is not limited thereto.
[0068] Next, please refer to Figure 4 The bit line spacer 118 is etched back until the second dielectric layer 106 is exposed. Then, using the bit line spacer 118 as a mask, the exposed second dielectric layer 106 and the first dielectric layer 104 are etched until the active region AA and the device isolation structure 102 are exposed. During this etching process, the exposed substrate 114 and barrier layer 116 are also etched, causing the top surface 116t of the barrier layer 116 to be concave.
[0069] Next, please refer to Figure 5 A first etching process is performed to form a first recess R1 in the active regions AA on both sides of the bit line BL. The first recess R1 extends into the device isolation structure 102 adjacent to the active regions AA. In one embodiment, the first etching process includes using a first patterned mask layer PM1 to cover the structure other than the first recess R1, and Figure 5 The first patterned mask layer PM1 only represents its masking position; in reality, the height of the first patterned mask layer PM1 may be higher. The first etching process is silicon etching, so the etching rate of the active region AA is higher than the etching rate of the device isolation structure 102, which can form a deeper recess in the active region AA.
[0070] Then, please refer to Figure 6 and Figure 7 In removing Figure 5 After the first patterned mask layer PM1, a first conductor layer C1 is formed in the first recess R1. The method for forming the first conductor layer C1 is, for example, but not limited to, depositing polysilicon and then performing an etch-back process (dry or wet fabrication process) until the device isolation structure 102 is exposed. Figure 7 The larger the area of overlap between the first conductor layer C1 and the active region AA, the lower the resistance of the memory structure.
[0071] Next, please refer to Figure 8Another bit line spacer 120 is conformally deposited on the surface of substrate 100, the surface of first conductor layer C1, the surface of barrier layer 116, the surface of bit line spacer 118, and capping layer 112. The material of bit line spacer 120 is, for example, silicon nitride, but the invention is not limited thereto. If there is an etch selectivity ratio between bit line spacer 118 and bit line spacer 120, it is beneficial to control and adjust the subsequent etching process.
[0072] Then, please refer to Figure 9 To form the second recess R2 in the first conductor layer C1, a spin-coated dielectric (SOD) can be formed all over the substrate 100, followed by a planarization process (such as CMP). Subsequently, a second patterned mask layer PM2 is formed on the planarized spin-coated dielectric (not shown) to cover the structure except for the second recess R2. Figure 9 The second patterned mask layer PM2 only represents its masking position; in reality, the second patterned mask layer PM2 is formed on top of the SOD. Then, using the second patterned mask layer PM2 as an etching mask, a second etching process is performed on the SOD, the underlying bit line gap wall 120, and the first conductor layer C1 to form an opening in the SOD and a second recess R2 in the first conductor layer C1, with the remaining first conductor layer C1 partially overlapping the bit line gap wall 120. The second etching process is, for example, a punch etch process. Moreover, since the first conductor layer C1 is formed first, the second recess R2 does not need to be etched too deeply, and the barrier layer 116 is less likely to be damaged as a result.
[0073] Next, please refer to Figure 10 and Figure 11 A second conductor layer C2 is formed within the second recess R2, such that the first conductor layer C1 and the second conductor layer C2 constitute the storage node contact window SNC. The method for forming the second conductor layer C2 includes, but is not limited to, depositing polysilicon to fill the opening of the SOD (i.e., corresponding to...). Figure 11 The area marked by the second conductor layer C2 is then etched back (dry or wet fabrication process) until the bit line gap wall 120 is exposed. In the top view, the first conductor layer C1 and the corresponding second conductor layer C2 partially overlap, and the area of the first conductor layer C1, which is the lower part of the memory node contact window SNC, overlapping with the active region AA is larger than the area of the second conductor layer C2, which is the upper part of the memory node contact window SNC, overlapping with the active region AA. In another embodiment, by adjusting the design of the active region AA, the embedded word line WL, and the bit line BL, the first conductor layer C1 and the corresponding second conductor layer C2 can also be made to completely overlap, that is, the second conductor layer C2, which is the upper part of the memory node contact window SNC, is located within the range of the first conductor layer C1 in the top view.
[0074] Afterwards, you can refer to Figure 12 A barrier layer 124 can be first formed on the inner surface of the opening formed by the gap wall 120 and the second conductor layer C2, and then a conductive layer 126 can be formed therein as a landing pad. The barrier layer 124 is, for example, titanium nitride (TiN) or cobalt silicide (CoSi), and the conductive layer 126 is, for example, tungsten (W), but is not limited thereto. The barrier layer 124 and the conductive layer 126 can be formed in a... Figure 10 On a higher horizontal surface of the top cap layer 112, a portion of the barrier layer 124 and conductive layer 126 can subsequently be removed using a planarization process (such as CMP), exposing the bit line spacer wall 120 and the top cap layer 112. A capacitor (not shown) coupled to the conductive layer 126 can then be formed.
[0075] An embodiment of the dynamic random access memory structure of the present invention is as follows: Figure 10 and Figure 11 As shown, the system includes at least a substrate 100, a component isolation structure 102, an embedded word line WL, a bit line BL, and multiple memory node contact windows SNCs. The component isolation structure 102 is located within the substrate 100 and defines multiple active regions AA within the substrate 100. The embedded word line WL is located within the substrate 100 and intersects with the active regions AA and the component isolation structure 102, wherein the embedded word line WL extends along the Y direction. The bit line BL is located on the substrate 100 and extends along the X direction, wherein the X direction is perpendicular to the Y direction. The memory node contact windows SNCs are located on both sides of the bit line BL and extend from above the substrate 100 into each active region AA. Each memory node contact window SNC has a narrow-at-the-top, wide-at-the-bottom structure, namely a narrower second conductor layer C2 and a wider first conductor layer C1, and has an interface 122 therein. This interface 122 extends from one side to the other, running through the entire narrow-at-the-top, wide-at-the-bottom structure. Figure 10 In this invention, interface 122 is located below the top 100t of the substrate 100 and is concave, but the invention is not limited thereto.
[0076] In one embodiment, the top surface AAt of each active region AA below the storage node contact window SNC is concave and complementary to the bottom surface of the aforementioned narrow-at-the-top, wide-at-the-bottom structure (i.e., the bottom surface of the first conductor layer C1). The sidewalls of the bit line BL have multiple bit line gap walls 118 and 120. In one embodiment, the upper part of the narrow-at-the-top, wide-at-the-bottom structure (i.e., the second conductor layer C2) is located on the sidewall of the bit line gap wall 120, and the lower part of the narrow-at-the-top, wide-at-the-bottom structure (i.e., the first conductor layer C1) is located below the bit line gap wall 120. In one embodiment, the bit line contact window 110 is located between the bit line BL and the active regions AA below it, and the bottom surface 110b of the bit line contact window 110 is lower than the bottom surface of the storage node contact window SNC.
[0077] exist Figure 11In this structure, the upper area of the narrow-at-the-top, wide-at-the-bottom configuration is smaller than the lower area. That is, the area of the second conductor layer C2, which forms the upper part of the storage node contact window SNC, is smaller than the area of the first conductor layer C1, which forms the lower part of the storage node contact window SNC. Because the area of the first conductor layer C1 is larger, its contact area with the active region AA is larger, which reduces the resistance and thus increases the component current. Even with a reduction in semiconductor component linewidth, the overall performance of the dynamic random access memory structure remains unaffected.
[0078] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the appended claims.
Claims
1. A dynamic random access memory structure, comprising: a substrate; device isolation structures in the substrate and defining a plurality of active regions within the substrate; buried word lines in the substrate and crossing the plurality of active regions and the device isolation structures, wherein the buried word lines extend in a first direction; bit lines on the substrate and extending in a second direction, wherein the second direction is perpendicular to the first direction; and a plurality of storage node contact windows on the substrate and extending from above the substrate into each of the active regions, wherein each of the storage node contact windows has a top narrow bottom wide structure and an interface within the top narrow bottom wide structure.
2. The dynamic random access memory structure of claim 1, wherein a top surface of each of the active regions under the plurality of storage node contact windows is concave and complementary to a bottom surface of the top narrow bottom wide structure.
3. The dynamic random access memory structure of claim 1, wherein in a top view, an upper portion of the top narrow bottom wide structure has a smaller area than a lower portion of the top narrow bottom wide structure.
4. The dynamic random access memory structure of claim 1, wherein the interface within the top narrow bottom wide structure is below a top portion of the substrate.
5. The dynamic random access memory structure of claim 1, wherein the interface within the top narrow bottom wide structure is concave.
6. The dynamic random access memory structure of claim 1, further comprising bit line spacers on sidewalls of the bit lines.
7. The dynamic random access memory structure of claim 6, wherein an upper portion of the top narrow bottom wide structure is on sidewalls of the bit line spacers and a lower portion of the top narrow bottom wide structure is below the bit line spacers.
8. The dynamic random access memory structure of claim 1, further comprising a bit line contact window between the bit line and the active region below the bit line.
9. The dynamic random access memory structure of claim 8, wherein a bottom surface of the bit line contact window is lower than a bottom surface of the storage node contact window.
10. The dynamic random access memory structure of claim 8, further comprising a barrier layer between the bit line contact window and the storage node contact window.
11. A method of fabricating a dynamic random access memory structure, comprising: forming device isolation structures in a substrate to define a plurality of active regions; forming buried word lines in the substrate and crossing the plurality of active regions and the device isolation structures, wherein the buried word lines extend in a first direction; forming bit lines on the substrate and extending in a second direction and exposing the plurality of active regions and the device isolation structures, wherein the second direction is perpendicular to the first direction; performing a first etching fabrication process on the substrate to form first recesses in the plurality of active regions on both sides of the bit lines; forming a first conductor layer in the first recesses; forming bit line spacers on sidewalls of the bit lines; performing a second etching fabrication process to form second recesses in the first conductor layer; and forming a second conductor layer in the second recesses such that the first conductor layer and the second conductor layer form a storage node contact window. 12. The method of claim 11, wherein forming the bit line on the substrate further comprises: forming a bit line contact opening on the plurality of active regions overlapping the bit line; and forming a bit line contact in the bit line contact opening, wherein a width of the bit line contact opening is greater than a width of the bit line contact.
13. The method of claim 12, wherein forming the bit line further comprises forming a barrier layer within the bit line contact opening after forming the bit line.
14. The method of claim 11, wherein the first etching process comprises using a first patterned mask layer to cover structures other than the first recess.
15. The method of claim 11, wherein the second etching process comprises using a second patterned mask layer to cover structures other than the second recess.
16. The method of claim 11, wherein the first recess extends into the element isolation structure adjacent to the active region.
17. The method of claim 11, wherein the bit line spacer partially overlaps the first conductor layer.