Semiconductor device including leakage prevention layer and method of manufacturing same

Abstract

A semiconductor device including a leakage prevention layer and a method of manufacturing the same are provided. The semiconductor device comprises a substrate, a bit line and a word line. The substrate includes an active region. The word line is embedded in the substrate and extends along a first direction. The bit line is disposed on the substrate and extends along a second direction different from the first direction. The active region includes a first semiconductor layer having a first dopant concentration and a second semiconductor layer having a second dopant concentration that is less than the first dopant concentration.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Patent Application No. 18 / 829,688, filed September 10, 2024, the contents of which are incorporated herein in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates to a semiconductor device and a method of manufacturing the same. In particular, the present disclosure relates to a semiconductor device including a leakage prevention layer and a method of manufacturing the same. BACKGROUND

[0004] With the rapid growth of the electronics industry, the development of integrated circuits (ICs) has enabled high performance and miniaturization. With advances in IC materials and design technology, generations of ICs have been produced, with each generation of circuitry being smaller and more complex than the last.

[0005] Dynamic random access memory (DRAM) devices are a type of random access memory that stores each data bit in a separate capacitor within an integrated circuit. Generally, DRAMs are arranged in a square array of cells having one capacitor and one transistor per cell. DRAM cells have been developed to be 4F 2 DRAM cells with vertical transistors, where F represents the minimum feature width or critical dimension (CD) of photolithography. However, recently, DRAM manufacturers have faced a significant challenge in scaling down the memory cell area while continuing to scale down the word line pitch. For example, leakage between landing pads and bit lines has become a critical issue, which degrades the performance of semiconductor devices.

[0006] The above background description is provided for the purpose of background information only and is not admitted to be prior art to the present disclosure. Any acknowledgement of the above background description is not to be construed as an admission that the above background description discloses subject matter of the present disclosure, nor does it constitute any part of the prior art of the present disclosure. SUMMARY

[0007] One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a bit line, and a word line. The substrate includes an active region. The word line is embedded in the substrate and extends along a first direction. The bit line is disposed on the substrate and extends along a second direction different from the first direction. The active region includes a first semiconductor layer having a first dopant concentration and a second semiconductor layer having a second dopant concentration, the second dopant concentration being less than the first dopant concentration.

[0008] Another aspect of this disclosure provides a semiconductor device. The semiconductor device includes a substrate, a bit line, and a word line. The word line is embedded within the substrate and extends along a first direction. The bit line is disposed on the substrate and extends along a second direction different from the first direction. The word line includes a first conductive layer and a surface modification structure disposed on the first conductive layer and in contact with an active region.

[0009] Another aspect of this disclosure provides a method for manufacturing a semiconductor device. The method includes: providing a substrate having an active region; forming a word line within the substrate, wherein the word line extends along a first direction; and forming a bit line on the substrate, wherein the bit line extends along a second direction different from the first direction, wherein forming the active region includes: forming a first semiconductor layer having a first dopant concentration; and forming a second semiconductor layer having a second dopant concentration less than the first dopant concentration.

[0010] Embodiments of this disclosure illustrate a semiconductor device. In some embodiments, the active region of the semiconductor device may include a first semiconductor layer and a second semiconductor layer on the first semiconductor layer. The dopant concentration of the second semiconductor layer is lower than that of the first semiconductor layer. The second semiconductor layer may include epitaxial silicon. Compared to the first semiconductor layer, the second semiconductor layer can generate a relatively smaller electric field. Therefore, the gate-induced drain current (GIDL) can be reduced. In some embodiments, the word line of the semiconductor device may include a junction modification structure sandwiched between the first and second conductive layers. The work function of the junction modification structure is lower than that of the first conductive layer and lower than that of the second conductive layer. Therefore, the GIDL can be reduced. The resistance of the word line can be reduced. Read / write performance can be improved.

[0011] The technical features and advantages of this disclosure have been broadly summarized above, thus enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0012] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0013] According to some embodiments of this disclosure Figure 1A This is a top view of a semiconductor device.

[0014] According to some embodiments of this disclosure Figure 1B For semiconductor devices along Figure 1A A partial cross-sectional schematic diagram of line A-A' shown.

[0015] According to some embodiments of this disclosure Figure 1C for Figure 1A The diagram shows a cross-sectional view of the capacitor assembly.

[0016] According to some embodiments of this disclosure Figure 2 This is a flowchart of a method for manufacturing a semiconductor device.

[0017] According to some embodiments of this disclosure Figure 3A This demonstrates one or more stages of a demonstrative manufacturing method for semiconductor devices.

[0018] According to some embodiments of this disclosure Figure 3B This demonstrates one or more stages of a demonstrative manufacturing method for semiconductor devices.

[0019] According to some embodiments of this disclosure Figure 3C This demonstrates one or more stages of a demonstrative manufacturing method for semiconductor devices.

[0020] According to some embodiments of this disclosure Figure 3D This demonstrates one or more stages of a demonstrative manufacturing method for semiconductor devices.

[0021] According to some embodiments of this disclosure Figure 3E This demonstrates one or more stages of a demonstrative manufacturing method for semiconductor devices.

[0022] According to some embodiments of this disclosure Figure 3F This demonstrates one or more stages of a demonstrative manufacturing method for semiconductor devices.

[0023] According to some embodiments of this disclosure Figure 3G This demonstrates one or more stages of a demonstrative manufacturing method for semiconductor devices.

[0024] The reference numerals in the attached figures are explained as follows:

[0025] 100: Semiconductor devices

[0026] 110: Base

[0027] 110s1: Surface

[0028] 112: Isolation Structure

[0029] 120: Active Zone

[0030] 121: Semiconductor layer

[0031] 122: Semiconductor layer

[0032] 122s1: Surface

[0033] 122s2: Surface

[0034] 130: Character Line

[0035] 131: Insulating film

[0036] 132: Conductive layer

[0037] 133: Interface Modification Structure

[0038] 134: Conductive layer

[0039] 135: Cap layer

[0040] 135s1: Surface

[0041] 140: Bit line

[0042] 142: Bit line contact

[0043] 144: Cap layer

[0044] 150: Capacitor Contact

[0045] 152: Dielectric Structure

[0046] 160: Capacitor Structure

[0047] 162: Lower electrode

[0048] 164: Capacitor dielectric

[0049] 166: Upper electrode

[0050] 172: Support layer

[0051] 174: Support layer

[0052] 176: Support layer

[0053] 180: Grounding electrode

[0054] 200: Method

[0055] 201: Operation

[0056] 202: Operation

[0057] 203: Operation

[0058] 204: Operation

[0059] 205: Operation

[0060] 206: Operation

[0061] 207: Operation

[0062] A-A': line

[0063] D: Direction

[0064] L1: Length

[0065] L2: Length

[0066] O1: Opening

[0067] O2: Opening

[0068] O3: Opening

[0069] P1: Planting Techniques

[0070] P2: Etching technology

[0071] P3: Etching Technology

[0072] X: Direction

[0073] Y: direction

[0074] Z: Direction Detailed Implementation

[0075] The embodiments or examples of this disclosure illustrated in the accompanying drawings are now described using specific language. It should be understood that this is not intended to limit the scope of this disclosure. Any substitutions or modifications to the embodiments described herein, and any further application of the principles described herein, should be considered as commonly occurring to those skilled in the art to which this disclosure pertains. Reference numerals may be repeated in the embodiments, but even if they share the same reference numerals, it does not necessarily mean that one or more features of one embodiment are applicable to another embodiment.

[0076] It should be understood that although terms such as first, second, third, etc., are used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, the first element, component, region, layer, or section discussed below may also be referred to as the second element, component, region, layer, or section without departing from the teachings of the present invention.

[0077] The terminology used herein is for describing specific exemplary embodiments only and is not intended to limit the concept of the invention. Unless expressly indicated herein, the singular forms “a” and “the” as used herein may also include the plural forms. It should be further understood that when the word “comprising” is used in this specification, it indicates the presence of the stated feature, integer, step, operation, element, or component, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

[0078] According to some embodiments of this disclosure Figure 1A This is a top view of semiconductor device 100. In some embodiments, semiconductor device 100 may include cell regions in which memory devices are formed. The memory devices may include, for example, dynamic random access memory (DRAM) devices, one-time programmable (OTP) memory devices, static random access memory (SRAM) devices, or other suitable memory devices. In some embodiments, DRAM may include, for example, transistors, capacitors, and other components. During a read operation, word lines may be active, turning on transistors. The enabled transistors allow the voltage across the capacitor to be read via a sense amplifier through the bit lines. During a write operation, when word lines are active, data to be written can be provided on the bit lines.

[0079] Semiconductor device 100 may include a substrate 110, an active region 120, word lines 130, bit lines 140, capacitor contacts 150, and capacitor structures 160.

[0080] Active regions 120 can be defined within the base 110. Active regions 120 can be separated from each other by isolation structures 112. Each active region 120 can contain an elliptical profile, an oval profile, a circular profile, or other suitable profile. The major axis of the active region 120 can extend along the D direction, which can be inclined relative to the X and Y directions.

[0081] In some embodiments, each character line 130 may extend along the X direction. The character line 130 may extend across the active region 120.

[0082] In some embodiments, each bit line 140 may extend along the Y direction. The bit line 140 may extend across the active region 120 and the word line 130.

[0083] In some embodiments, each bit line contact 142 may be connected to bit line 140. In some embodiments, bit line contacts 142 may overlap bit lines 140 along the Z direction. In some embodiments, bit line contacts 142 may overlap active regions 120 along the Z direction.

[0084] Each capacitor contact 150 may be surrounded by word lines 130 and bit lines 140. The capacitor contacts 150 may partially overlap the active region 120 along the Z direction.

[0085] A capacitor structure 160 may be provided on or above the capacitor contact 150. The capacitor structure 160 may overlap the capacitor contact 150 along the Z direction.

[0086] According to some embodiments of this disclosure Figure 1B For semiconductor device 100 along Figure 1A A partial cross-sectional schematic diagram of line A-A' shown.

[0087] The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate 110 may comprise elemental semiconductors, including silicon or germanium in single-crystal, polycrystalline, or amorphous form; compound semiconductor materials, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductor materials, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable materials; or combinations thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy with a gradient Ge characteristic, wherein the composition of Si and Ge varies from one ratio at one location of the gradient SiGe characteristic to another ratio at another location. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy is mechanically strained by another material in contact with it. In some embodiments, the substrate 110 may have a multilayer structure, or the substrate 110 may comprise a multilayer compound semiconductor structure. In some embodiments, the substrate 110 may have a first conductivity type (e.g., P-type).

[0088] In some embodiments, the isolation structure 112 may be embedded within the substrate 110. The isolation structure 112 may be recessed from the surface 110s1 (or upper surface) of the substrate 110. In some embodiments, the isolation structure 112 may comprise, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (N2OSi2), silicon oxynitride (N2OSi2), or other suitable materials.

[0089] In some embodiments, a portion of the substrate 110 may be removed to form a trench, and one or more dielectric materials may be filled into the trench to form an isolation structure 112. In some embodiments, the isolation structure 112 may include shallow trench isolation (STI).

[0090] In some embodiments, the active region 120 may include a semiconductor layer 121 and a semiconductor layer 122. The semiconductor layer 121 may be disposed within the substrate 110. In some embodiments, the semiconductor layer 121 may be spaced apart from the surface 110s1 of the substrate 110. In some embodiments, the semiconductor layer 121 may have a second conductivity type (e.g., N-type). In some embodiments, the dopant concentration of the semiconductor layer 121 may be approximately 10. 14 cm -3 With about 10 15 cm -3 Within the range between.

[0091] Semiconductor layer 122 may be disposed on or above semiconductor layer 121. In some embodiments, semiconductor layer 122 is closer to surface 110s1 of substrate 110 than semiconductor layer 121. In some embodiments, the dopant concentration of semiconductor layer 122 may be lower than the dopant concentration of semiconductor layer 121. In some embodiments, the dopant concentration of semiconductor layer 122 may be less than 10. 14 cm -3 In some embodiments, the dopant concentration of semiconductor layer 122 may be approximately equal to 0.

[0092] In some embodiments, semiconductor layer 122 can be used to reduce GIDL current. In some embodiments, semiconductor layer 122 generates or induces a relatively smaller electric field for GIDL current compared to semiconductor layer 121.

[0093] In some embodiments, semiconductor layer 122 may comprise one or more Group 14 materials, such as silicon, germanium, combinations thereof, or other suitable materials. In some embodiments, semiconductor layer 122 may comprise an epitaxial structure. For example, semiconductor layer 122 may comprise epitaxial silicon, epitaxial germanium, epitaxial silicon-germanium, or other suitable materials.

[0094] Semiconductor layer 121 may have a length L1 (or a vertical length) along the Z direction. Semiconductor layer 122 may have a length L2 (or a vertical length) along the Z direction. In some embodiments, the length L2 of semiconductor layer 122 may be greater than the length L1 of semiconductor layer 121, thereby optimizing the electric field.

[0095] Word line 130 (or gate structure) may be embedded within substrate 110. Word line 130 may be embedded within isolation structure 112. In some embodiments, word line 130 may pass through substrate 110. In some embodiments, word line 130 may pass through semiconductor layer 121. In some embodiments, word line 130 may pass through semiconductor layer 122. In some embodiments, word line 130 may include insulating film 131, conductive layer 132, junction modification structure 133, and conductive layer 134.

[0096] An insulating film 131 (or gate dielectric) may be disposed within the substrate 110. The insulating film 131 may be embedded in the isolation structure 112. In some embodiments, the insulating film 131 may extend through the substrate 110. In some embodiments, the insulating film 131 may extend through the semiconductor layer 121. In some embodiments, the insulating film 131 may extend through the semiconductor layer 122. The insulating film 131 may separate the conductive layer 132 from the substrate 110. The insulating film 131 may separate the conductive layer 132 from the active region 120. The insulating film 131 may separate the junction modification structure 133 from the substrate 110. The insulating film 131 may separate the junction modification structure 133 from the active region 120. The insulating film 131 may separate the conductive layer 134 from the substrate 110. The insulating film 131 may separate the conductive layer 134 from the active region 120.

[0097] The insulating film 131 may comprise, for example, silicon dioxide (SiO2), a high-dielectric-constant material, or a combination thereof. Exemplary high-dielectric-constant materials include dielectric materials with a dielectric constant exceeding that of silicon dioxide (SiO2), or dielectric materials having a dielectric constant higher than about 3.9. In some embodiments, the high-dielectric-constant material may comprise hafnium oxide (HfO2), silicon-doped hafnium oxide (HSO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium silicate (ZrSiO4), aluminum oxide (Al2O3), or other suitable materials.

[0098] The conductive layer 132 may be embedded within the substrate 110. The conductive layer 132 may be embedded within the isolation structure 112. In some embodiments, the conductive layer 132 may penetrate the substrate 110. In some embodiments, the conductive layer 132 may penetrate the semiconductor layer 121. In some embodiments, the conductive layer 132 may penetrate the semiconductor layer 122. In some embodiments, the conductive layer 132 may comprise a metal, metal nitride, alloy, or other suitable material. The conductive layer 132 may comprise titanium (Ti), tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), silver (Ag), gold (Au), titanium nitride, tungsten nitride, or other suitable materials. In some embodiments, the conductive layer 132 may be laterally overlapped with the semiconductor layer 121, or overlapped along the D direction of the semiconductor layer 121.

[0099] The junction modification structure 133 may be disposed on or above the conductive layer 132. The junction modification structure 133 may be disposed between the conductive layer 132 and the conductive layer 134. The junction modification structure 133 may be embedded within the isolation structure 112. In some embodiments, the junction modification structure 133 may penetrate the substrate 110. In some embodiments, the junction modification structure 133 may penetrate the semiconductor layer 121. In some embodiments, the junction modification structure 133 may penetrate the semiconductor layer 122. The junction modification structure 133 may be disposed between the conductive layer 132 and the conductive layer 134. The junction modification structure 133 can be used to modify the work function of the word line 130. The junction modification structure 133 can be used to reduce the GIDL current. In some embodiments, the work function of the junction modification structure 133 may be less than the work function of the conductive layer 132. In some embodiments, the work function of the junction modification structure 133 may be less than the work function of the conductive layer 134.

[0100] In some embodiments, the junction modification structure 133 may comprise one or more Group 14 materials. In some embodiments, the junction modification structure 133 may comprise doped polysilicon or other suitable materials, such as doped germanium or other suitable materials. In some embodiments, the junction modification structure 133 may have a second conductivity type. In some embodiments, the dopant concentration of the junction modification structure 133 may be greater than the dopant concentration of the semiconductor layer 121. In some embodiments, the dopant concentration of the junction modification structure 133 may be greater than the dopant concentration of the semiconductor layer 122. In some embodiments, the dopant concentration of the junction modification structure 133 may be approximately 10. 19 cm -3 With approximately 5x10 20 cm -3 Within the range between.

[0101] In some embodiments, the interface modification structure 133 may laterally overlap the semiconductor layer 121 or overlap the semiconductor layer 121 along the D direction. In some embodiments, the interface modification structure 133 may laterally overlap the semiconductor layer 122 or overlap the semiconductor layer 122 along the D direction.

[0102] The conductive layer 134 may be disposed on or above the interface modification structure 133. The conductive layer 134 may be embedded within the substrate 110. The conductive layer 134 may be embedded within the isolation structure 112. In some embodiments, the conductive layer 134 may penetrate the substrate 110. In some embodiments, the conductive layer 134 may penetrate the semiconductor layer 121. In some embodiments, the conductive layer 134 may penetrate the semiconductor layer 122. In some embodiments, the conductive layer 134 may comprise a metal, metal nitride, alloy, or other suitable material. The conductive layer 134 may comprise titanium (Ti), tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), silver (Ag), gold (Au), titanium nitride, tungsten nitride, or other suitable materials. In some embodiments, the conductive layer 134 may be laterally overlapped with the semiconductor layer 122, or overlapped along the D direction of the semiconductor layer 122.

[0103] A capping layer 135 may be disposed on or above the conductive layer 134. The capping layer 135 may cover the character lines 130. The capping layer 135 may be formed of an insulating material, such as silicon nitride (Si3N4), silicon oxynitride (N2OSi2), silicon oxynitride (N2OSi2), or other suitable materials. In some embodiments, the surface 135s1 (e.g., the upper surface) of the capping layer 135 may be substantially aligned with or coplanar with the surface 122s1 (or the upper surface) of the semiconductor layer 122.

[0104] In some embodiments, bit line contact 142 may be disposed on or above substrate 110. In some embodiments, bit line contact 142 may be disposed on or above active region 120. In some embodiments, bit line contact 142 may be disposed on or above semiconductor layer 122. In some embodiments, bit line contact 142 may contact semiconductor layer 122. In some embodiments, bit line contact 142 may comprise a conductive film, such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), silver (Ag), gold (Au), alloys of the foregoing, or any metallic material with suitable resistance and gap-filling capability. In some embodiments, bit line contact 142 may comprise polysilicon. In some embodiments, bit line contact 142 may comprise one or more layers.

[0105] In some embodiments, bit line 140 may be disposed on or above active region 120. In some embodiments, bit line 140 may be disposed on or above semiconductor layer 122. In some embodiments, bit line 140 may be disposed on or above bit line contact 142. Bit line 140 may be electrically connected to bit line contact 142. Bit line 140 may comprise a metal, such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), silver (Ag), gold (Au), alloys thereof, or combinations thereof.

[0106] The semiconductor device 100 may further include a capping layer 144. The capping layer 144 may cover the bit line 140. The capping layer 144 may be disposed on or over the bit line 140. In some embodiments, the capping layer 144 may comprise, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (N2OSi2), silicon oxynitride (N2OSi2), or other suitable materials.

[0107] In some embodiments, the capacitive contact 150 may be disposed on or above the substrate 110. In some embodiments, the capacitive contact 150 may be disposed on or above the active region 120. In some embodiments, the capacitive contact 150 may contact the semiconductor layer 122. In some embodiments, a portion of the capacitive contact 150 may be embedded within the active region 120. In some embodiments, a portion of the capacitive contact 150 may be embedded within the semiconductor layer 122. In some embodiments, a portion of the capacitive contact 150 may contact the surface 122s2 (or lateral surface) of the semiconductor layer 122. The capacitive contact 150 may be electrically connected to the capacitor structure 160. The capacitive contact 150 may comprise a metal, such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), alloys thereof, combinations thereof, or any metallic material.

[0108] The semiconductor device 100 may further include a dielectric structure 152. The dielectric structure 152 may be disposed on or above a substrate 110. The dielectric structure 152 may be disposed on or above an active region 120. The dielectric structure 152 may be disposed on or above an isolation structure 112. Bit lines 140 may be embedded within the dielectric structure 152. Bit line contacts 142 may be embedded within the dielectric structure 152. A capping layer 144 may be embedded within the dielectric structure 152. Capacitor contacts 150 may be embedded within the dielectric structure 152. The dielectric structure 152 may comprise one or more layers. In some embodiments, the dielectric structure 152 may comprise, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (N2OSi2), silicon oxynitride (N2OSi2), or other suitable materials.

[0109] althoughFigure 1B Not shown, the semiconductor device 100 may further include other features as needed. For example, the semiconductor device 100 may also include bit line spacers disposed on the sidewalls of the bit line 140, the bit line contact 142, and the capping layer 144. In some embodiments, the bit line spacers may comprise one or more materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, high dielectric constant materials, air gaps, or combinations thereof.

[0110] In some embodiments, the semiconductor device 100 may further include a landing pad. In some embodiments, the landing pad may cover the top surface of the capacitive contact 150. The landing pad may electrically connect the capacitive contact 150 and the capacitive structure 160. The landing pad may pass through a portion of the dielectric structure 152 and the bit line spacer. In some embodiments, the landing pad may contain a metal, such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), silver (Ag), gold (Au), alloys thereof, or combinations thereof.

[0111] According to some embodiments of this disclosure Figure 1C This is a cross-sectional schematic diagram of a feature (e.g., a capacitor assembly) above capacitor contact 150.

[0112] The semiconductor device 100 may further include support layers 172, 174 and 176 located at different heights for supporting the capacitor structure 160.

[0113] In some embodiments, such as Figure 1B As shown, a support layer 172 (or lower support layer) may be disposed on or above the dielectric structure 152. In some embodiments, the support layer 172 may be used to support the capacitor structure 160. The support layer 172 may be used to define the pattern of the capacitor structure 160. In some embodiments, the support layer 172 may comprise silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, or other suitable materials.

[0114] In some embodiments, a support layer 174 (or an intermediate support layer) may be disposed on or above support layer 172. In some embodiments, support layer 174 may be spaced apart from support layer 172. In some embodiments, support layer 174 may be used to support capacitor structure 160. The support layer 174 may be used to define the pattern of capacitor structure 160. In some embodiments, support layer 174 may comprise silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, or other suitable materials.

[0115] In some embodiments, a support layer 176 (or upper support layer) may be disposed on or above support layer 174. In some embodiments, support layer 176 may be spaced apart from support layer 174. In some embodiments, support layer 176 may be used to support capacitor structure 160. The support layer 176 may be used to define the pattern of capacitor structure 160. In some embodiments, support layer 176 may comprise silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, or other suitable materials.

[0116] like Figure 1B As shown, capacitor structure 160 may be disposed on or above capacitor contact 150. In some embodiments, capacitor structure 160 may be supported by support layers 172, 174, and 176, and capacitor structure 160 may contact support layers 172, 174, and 176. In some embodiments, capacitor structure 160 may include a lower electrode 162, a capacitor dielectric 164, and an upper electrode 166.

[0117] In some embodiments, such as Figure 1B As shown, the lower electrode 162 (or the first electrode) may be electrically connected to the capacitive contact 150. In some embodiments, the lower electrode 162 may be disposed within an opening defined by support layers 172, 174, and 176. In some embodiments, the lower electrode 162 may be disposed on or in contact with a lateral surface of support layer 172. In some embodiments, the lower electrode 162 may be disposed on or in contact with a lateral surface of support layer 174. In some embodiments, the lower electrode 162 may be disposed on or in contact with a lateral surface of support layer 176. The lower electrode 162 may comprise a conductive material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, tungsten nitride, or the like), a metal (e.g., copper, tungsten, ruthenium, iridium, nickel, osmium, rhodium, aluminum, molybdenum, cobalt, or the like), and a conductive metal oxide (e.g., iridium oxide or the like).

[0118] A capacitor dielectric 164 may be compliantly disposed on the lower electrode 162. In some embodiments, the capacitor dielectric 164 may be disposed on or in contact with the upper surface of the support layer 172. In some embodiments, the capacitor dielectric 164 may be disposed on or in contact with the upper surfaces of the support layers 174 and 176. In some embodiments, the capacitor dielectric 164 may be disposed on or in contact with the lower surfaces of the support layers 174 and 176. In some embodiments, the capacitor dielectric 164 may be disposed on or in contact with the lateral surfaces of the support layers 174 and 176. The capacitor dielectric 164 may comprise silicon oxide, tungsten oxide, copper oxide, aluminum oxide, hafnium oxide, or the like.

[0119] In some embodiments, the upper electrode 166 (or the second electrode) may be disposed on the capacitor dielectric 164. The upper electrode 166 may be separated from the lower electrode 162 by the capacitor dielectric 164. The upper electrode 166 may comprise one or more conductive materials, conductive metal nitrides (e.g., titanium nitride, tantalum nitride, tungsten nitride, or the like), metals (e.g., copper, tungsten, ruthenium, iridium, nickel, osmium, rhodium, aluminum, molybdenum, cobalt, or the like), and conductive metal oxides (e.g., iridium oxide or the like). In some embodiments, from the top view, each of the support layer 172, support layer 174, and support layer 176 may be defined as an annular profile to accommodate the capacitor structure 160.

[0120] In some embodiments, the semiconductor device 100 may further include a ground electrode 180. In some embodiments, the ground electrode 180 may be electrically connected to ground potential. In some embodiments, the ground electrode 180 may be electrically connected to capacitor structure 160. In some embodiments, the ground electrode 180 may be electrically connected to and in contact with upper electrode 166. In some embodiments, the ground electrode 180 may comprise doped polysilicon or other suitable material.

[0121] According to some embodiments of this disclosure Figure 2 A flowchart of a semiconductor device manufacturing method 200.

[0122] Method 200 may begin with operation 201, in which a substrate is provided. An isolation structure (e.g., STI) may be formed within the substrate.

[0123] Method 200 can then proceed to operation 202, in which the implantation technique is implemented to form the first semiconductor layer.

[0124] Method 200 may then proceed to operation 203, in which an etching technique is performed to remove a portion of the first semiconductor layer.

[0125] Method 200 may then proceed to operation 204, in which a second semiconductor layer is formed on the first semiconductor layer. The second semiconductor layer may comprise an epitaxial structure, such as epitaxial silicon, epitaxial silicon-germanium, or other suitable materials. The doping concentration of the second semiconductor layer is lower than that of the first semiconductor layer. Polishing or grinding techniques may be performed to planarize the upper surfaces of the isolation structure and the second semiconductor layer.

[0126] Method 200 may then proceed to operation 205, in which a portion of the substrate, the first semiconductor layer, and the second semiconductor layer is removed to form an opening.

[0127] Method 200 may then proceed to operation 206, in which a character line is formed within the opening. Each character line may include a first conductive layer, a junction modification structure on the first conductive layer, and a second conductive layer on the junction modification structure. The work function of the junction modification structure may be less than the work function of the first conductive layer. The work function of the junction modification structure may be less than the work function of the second conductive layer. The junction modification structure may include a doped Group 14 material, such as doped polysilicon. The dopant concentration of the junction modification structure may be greater than the dopant concentration of the first semiconductor layer.

[0128] Method 200 can then proceed to operation 207, in which bit lines are formed on the substrate. Capacitive contacts and capacitor structures can be formed on the substrate, thereby producing a semiconductor device.

[0129] Method 200 is merely exemplary and is not intended to limit this disclosure beyond what is expressly stated in the invention claims. Additional operations may be provided before, during, or after each operation of method 200, and some described operations may be replaced, deleted, or rearranged for additional method embodiments. In some embodiments, method 200 may include... Figure 2 Further operations not shown in the figure. In some embodiments, method 200 may include Figure 2 One or more operations are shown in the diagram.

[0130] According to some embodiments of this disclosure Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F and Figure 3G This demonstrates the various stages of a demonstrative manufacturing method for semiconductor devices.

[0131] See Figure 3A A substrate 110 is provided. An isolation structure 112 may be formed within the substrate 110. In some embodiments, a portion of the substrate 110 may be removed to form an opening (not shown), and one or more dielectric materials may be deposited to fill the opening, thereby producing the isolation structure 112. The isolation structure 112 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), flow-through chemical vapor deposition (FCVD), or other suitable processes. In some embodiments, polishing or grinding techniques (e.g., chemical mechanical polishing (CMP)) may be performed to planarize the upper surface of the substrate 110 and the upper surface of the isolation structure 112. Figure 3A Display and operate the corresponding stage 201.

[0132] See Figure 3BThe implantation technique P1 can be implemented. Impurities can be doped into the surface 110s1 of the substrate 110, thereby producing the semiconductor layer 121. Figure 3B Display and operate the corresponding stage 202.

[0133] See Figure 3C Etching technology P2 can be implemented. Removable. Figure 3B A portion 110p1 of the substrate 110 is shown to form an opening O1 (or trench) in the recess of the self-isolating structure 112. In some embodiments, a portion of the semiconductor layer 121 may be removed. In some embodiments, an etching technique P2 may be performed after the semiconductor layer 121 has been produced. The etching technique P2 may include dry etching, wet etching, or other suitable techniques. Figure 3C Display and operate the corresponding stage 203.

[0134] See Figure 3D A semiconductor layer 122 can be formed. In some embodiments, a semiconductor layer 122 with an opening O1 filled can be formed on or above the semiconductor layer 121. The semiconductor layer 122 can be formed, for example, using metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), similar methods, or combinations thereof. In some embodiments, polishing or grinding techniques (e.g., CMP) can be implemented to planarize the surface 122s1 of the semiconductor layer 122 and the upper surface of the isolation structure 112. Figure 3D Display and operate the corresponding stage 204.

[0135] See Figure 3E Etching technique P3 can be implemented. In some embodiments, a portion of semiconductor layer 121 can be removed. In some embodiments, a portion of semiconductor layer 122 can be removed. A portion of isolation structure 112 can be removed. Openings O2 and O3 can be formed. Openings O2 and O3 can have different depths. Etching technique P3 can include dry etching, wet etching, or other suitable techniques. In some embodiments, etching technique P3 can be implemented after semiconductor layer 122 has been produced. Figure 3E Display and operate the corresponding stage 205.

[0136] See Figure 3F An insulating film 131, a conductive layer 132, a junction modification structure 133, a conductive layer 134, and a capping layer 135 can be formed within the opening. Each of the insulating film 131, conductive layer 132, junction modification structure 133, conductive layer 134, and capping layer 135 can be formed by CVD, PVD, ALD, PECVD, LPCVD, FCVD, or other suitable techniques. In some embodiments, polishing or grinding techniques (e.g., CMP) can be implemented to planarize the surface 122s1 of the semiconductor layer 122 and the surface 135s1 of the capping layer 135.Figure 3F Display and operate the corresponding stage 206.

[0137] See Figure 3G A semiconductor device 100 can be produced by forming bit lines 140, bit line contacts 142, capping layers 144, capacitor contacts 150, dielectric structures 152, and capacitor structures 160. Each of the bit lines 140, bit line contacts 142, capping layers 144, capacitor contacts 150, dielectric structures 152, and capacitor structures 160 can be formed by CVD, PVD, ALD, PECVD, LPCVD, FCVD, or other suitable techniques. Figure 3G Display and operate the corresponding stage 207.

[0138] One aspect of this disclosure provides a semiconductor device. The semiconductor device includes a substrate, a bit line, and a word line. The substrate includes an active region. The word line is embedded within the substrate and extends along a first direction. The bit line is disposed on the substrate and extends along a second direction different from the first direction. The active region includes a first semiconductor layer having a first dopant concentration and a second semiconductor layer having a second dopant concentration less than the first dopant concentration.

[0139] Another aspect of this disclosure provides a semiconductor device. The semiconductor device includes a substrate, a bit line, and a word line. The word line is embedded within the substrate and extends along a first direction. The bit line is disposed on the substrate and extends along a second direction different from the first direction. The word line includes a first conductive layer and a surface modification structure disposed on the first conductive layer and in contact with an active region.

[0140] Another aspect of this disclosure provides a method for manufacturing a semiconductor device. The method includes: providing a substrate having an active region; forming a word line within the substrate, wherein the word line extends along a first direction; and forming a bit line on the substrate, wherein the bit line extends along a second direction different from the first direction, wherein forming the active region includes: forming a first semiconductor layer having a first dopant concentration; and forming a second semiconductor layer having a second dopant concentration less than the first dopant concentration.

[0141] Embodiments of this disclosure illustrate a semiconductor device. In some embodiments, the active region of the semiconductor device may include a first semiconductor layer and a second semiconductor layer on the first semiconductor layer. The dopant concentration of the second semiconductor layer is lower than that of the first semiconductor layer. The second semiconductor layer may include epitaxial silicon. Compared to the first semiconductor layer, the second semiconductor layer can generate a relatively smaller electric field. Therefore, the gate-induced drain current (GIDL) can be reduced. In some embodiments, the word line of the semiconductor device may include a junction modification structure sandwiched between the first and second conductive layers. The work function of the junction modification structure is lower than that of the first conductive layer and lower than that of the second conductive layer. Therefore, the GIDL can be reduced. The resistance of the word line can be reduced. Read / write performance can be improved.

[0142] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0143] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this document that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor device, comprising: a substrate comprising an active region; a word line embedded within the substrate and extending along a first direction; and a bit line disposed on the substrate and extending along a second direction different from the first direction, wherein the active region comprises: a first semiconductor layer having a first dopant concentration; and a second semiconductor layer having a second dopant concentration, and the second dopant concentration is less than the first dopant concentration.

2. The semiconductor device of claim 1, wherein the second semiconductor layer is closer to an upper surface of the substrate than the first semiconductor layer.

3. The semiconductor device of claim 1, wherein the second dopant concentration of the second semiconductor layer is substantially equal to 0.

4. The semiconductor device of claim 1, wherein a vertical length of the second semiconductor layer is greater than a vertical length of the first semiconductor layer.

5. The semiconductor device of claim 1, wherein the word line comprises: a first conductive layer; and a junction modification structure disposed on the first conductive layer.

6. The semiconductor device of claim 5, wherein the junction modification structure comprises a doped semiconductor layer.

7. The semiconductor device of claim 6, wherein a third dopant concentration of the junction modification structure is greater than the first dopant concentration.

9. The semiconductor device of claim 5, wherein the word line further comprises: a second conductive layer disposed on the junction modification structure.

10. The semiconductor device of claim 9, wherein the second conductive layer laterally overlaps the second semiconductor layer.

8. The semiconductor device of claim 7, wherein the third dopant concentration of the junction modification structure is in a range between about 10 19 cm -3 and about 5 x 10 20 cm -3 .

11. The semiconductor device of claim 5, wherein the junction modification structure laterally overlaps the first semiconductor layer.

12. The semiconductor device of claim 5, wherein the junction modification structure laterally overlaps the second semiconductor layer. ​ ​ ​

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