Memory element with recessed conductive plug and recessed channel layer and method of making same

Abstract

The invention provides a memory element with a recessed conductive plug and a recessed channel layer and a method of fabricating the same. A memory element including a capacitor disposed on a semiconductor substrate; and a conductive plug located over the capacitor. The conductive plug has a first recessed upper surface. The memory element also includes a channel layer disposed over the conductive plug. The channel layer has a second recessed upper surface. The memory element also includes a bit line disposed over the channel layer; and a word line disposed between the conductive plug and the bit line.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Patent Application No. 18 / 825,216, filed September 5, 2024, the contents of which are incorporated herein in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates to a memory element and a method of fabricating the same. In particular, a memory element having a recessed conductive plug and a recessed channel layer and a method of fabricating the same. BACKGROUND

[0004] Dynamic random access memory (DRAM) can provide more memory cells per unit wafer area than other types of memory, such as static random access memory (SRAM), due to its simple structure. DRAM is constructed of a plurality of DRAM cells, each including a capacitor for storing information and a transistor coupled to the capacitor for regulating when the capacitor is charged or discharged. During a read operation, a word line (WL) is asserted and turns on the transistor. The enabled transistor allows a sense amplifier to read the voltage across the capacitor through a bit line (BL). During a write operation, write data is provided on the BL while the WL is asserted.

[0005] To meet the demand for larger memory storage, the size of DRAM memory cells is continually shrinking, resulting in a substantial increase in the packing density of these DRAMs. However, the fabrication and integration of memory elements involve many complex steps and operations. The integration in memory elements is becoming increasingly complex. The increasing complexity of the fabrication and integration of memory elements can result in defects. Therefore, there is a need to continually improve the structure and fabrication process of memory elements to address their defects and improve their performance.

[0006] The above background description is provided for the purpose of making known information behind the disclosure. The above background description does not constitute an admission of prior art nor does it in any way limit the scope of the patent disclosure. Any consideration of the above state of the art is not, and should not be, taken as an indication that it is considered prior art for any purpose. SUMMARY

[0007] In one embodiment of the disclosure, a memory element is provided. The memory element includes a capacitor disposed above a semiconductor substrate and a conductive plug disposed above the capacitor. The conductive plug has a first recessed upper surface. The memory element also includes a channel layer disposed above the conductive plug. The channel layer has a second recessed upper surface. The memory element further includes a bit line disposed above the channel layer and a word line disposed between the conductive plug and the bit line. The channel layer is surrounded by the word line.

[0008] In one embodiment, the second recessed upper surface of the channel layer partially overlaps the first recessed upper surface of the conductive plug in a top view. In one embodiment, the channel layer is in direct contact with the first recessed upper surface of the conductive plug. In one embodiment, the bit line is in direct contact with the second recessed upper surface of the channel layer. In one embodiment, the second recessed upper surface of the channel layer is higher than an upper surface of the word line.

[0009] In one embodiment, the bit line has a T-shaped profile. In one embodiment, the memory element further includes a gate dielectric layer surrounding the channel layer, wherein the word line is separated from the channel layer by the gate dielectric layer. In one embodiment, the gate dielectric layer is in direct contact with the first recessed upper surface of the conductive plug. In one embodiment, an upper surface of the gate dielectric layer is higher than the second recessed upper surface of the channel layer.

[0010] In one embodiment, a portion of the channel layer is sandwiched between the bit line and the gate dielectric layer. In one embodiment, the bit line has a lower portion extending into the channel layer and an upper portion above the lower portion, wherein the upper portion of the bit line laterally extends beyond opposite edges of the bit line lower portion. In one embodiment, an upper surface of the gate dielectric layer is covered by and in direct contact with the upper portion of the bit line. In one embodiment, the lower portion of the bit line is separated from the gate dielectric layer.

[0011] In another embodiment of the disclosure, a memory element is provided. The memory element includes a capacitor disposed above a semiconductor substrate and a conductive plug disposed above the capacitor. The memory element also includes a channel layer disposed above the conductive plug. An upper surface of the conductive plug is higher than a lower surface of the channel layer. The memory element further includes a bit line disposed above the channel layer. An upper surface of the channel layer is higher than a lower surface of the bit line. In addition, the memory element includes a gate dielectric layer and a word line between the conductive plug and the bit line. The gate dielectric layer is disposed between the word line and the channel layer.

[0012] In one embodiment, the channel layer is in direct contact with the conductive plug. In one embodiment, the bit line is in direct contact with the channel layer. In one embodiment, the lower surface of the bit line is higher than an upper surface of the word line. In one embodiment, the lower surface of the channel layer is higher than an upper surface of the capacitor.

[0013] In one embodiment, the channel layer is surrounded by the gate dielectric layer, and the gate dielectric layer is surrounded by the word line. In one embodiment, an upper surface of the gate dielectric layer is substantially coplanar with the upper surface of the channel layer. In one embodiment, the upper surface of the gate dielectric layer is higher than an upper surface of the word line. In one embodiment, the upper surface of the conductive plug is higher than a lower surface of the gate dielectric layer.

[0014] In one embodiment, the gate dielectric layer is in direct contact with the conductive plug. In one embodiment, the bit line has a lower portion extending into the channel layer and an upper portion disposed above the lower portion, wherein the upper surface of the channel layer is covered by the upper portion of the bit line. In one embodiment, an upper surface of the gate dielectric layer is covered by the upper portion of the bit line. In one embodiment, the upper portion of the bit line laterally extends beyond opposite edges of the lower portion of the bit line, wherein the edges of the lower portion of the bit line are separated from the gate dielectric layer by the channel layer.

[0015] Another embodiment of the disclosure provides a method of fabricating a memory element. The method includes forming a capacitor over a semiconductor substrate; and forming a conductive plug over the capacitor. The method also includes forming a word line over the conductive plug; and forming an opening to penetrate the word line to expose the conductive plug. The method further includes performing a first etching process to form a first recess in the conductive plug via the opening; and forming a channel layer in the opening. In addition, the method includes performing a second etching process to form a second recess in the channel layer; and forming a bit line over the channel layer.

[0016] In one embodiment, the channel layer extends into the first recess of the conductive plug. In one embodiment, the bit line extends into the second recess of the channel layer. In one embodiment, the second recess of the channel layer partially overlaps the first recess of the conductive plug in a top view. In one embodiment, prior to forming the channel layer, the method further includes forming a dielectric portion over the conductive plug; forming the word line over the dielectric portion; forming a dielectric layer over the word line; and partially etching the dielectric layer, the word line, and the dielectric portion to form the opening. In one embodiment, sidewalls of the word line are aligned with sidewalls of the dielectric portion.

[0017] In one embodiment, after the opening is formed, the sidewalls of the conductive plug are covered by the dielectric portion. In one embodiment, the method further comprises forming a gate dielectric layer lining the opening prior to forming the channel layer, wherein the gate dielectric layer is in direct contact with the word line. In one embodiment, the gate dielectric layer extends into the first recess to be in direct contact with the conductive plug. In one embodiment, after forming the channel layer, the method further comprises forming a photoresist layer and a plurality of dielectric spacers on the word line, wherein the sidewalls of the photoresist layer are covered by the dielectric spacers. Further, the method comprises performing a second etching process using the photoresist layer and the dielectric spacers as a mask to form the second recess in the channel layer.

[0018] In one embodiment, prior to performing the second etching process, an upper surface of the gate dielectric layer is covered by the dielectric spacers. In one embodiment, prior to performing the second etching process, an upper surface of the channel layer is partially covered by the dielectric spacers. In one embodiment, the bit line has a lower portion filling the second recess of the channel layer and an upper portion disposed above the lower portion, wherein the upper portion of the bit line laterally extends beyond opposite edges of the lower portion of the bit line. In one embodiment, an upper surface of the gate dielectric layer is covered by and in direct contact with the upper portion of the bit line.

[0019] The present disclosure provides embodiments of a memory element and a method of fabricating the same. In some embodiments, the memory element includes a conductive plug disposed above the capacitor, a channel layer disposed above the conductive plug, and a bit line disposed above the channel layer. In some embodiments, the conductive plug and the channel layer have recessed upper surfaces. As a result, the contact area between the channel layer and the conductive plug and between the bit line and the channel layer can be increased, thereby reducing contact resistance. In this way, drive current can be increased, and performance of the memory element can be improved. In addition, the increased contact area provides a larger process window for fabrication of memory elements such as bit line landing.

[0020] The foregoing has outlined rather broadly the technical features of the present disclosure in order that the detailed description of the present disclosure that follows can be better understood. Additional technical features and advantages of the present disclosure will be described in the detailed description of the present disclosure that follows. The foregoing summary of the technical features of the present disclosure should not be considered complete with respect to the disclosure. Its sole purpose is to excite interest in the present disclosure by more fully BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and together with the description, explain the principles of the present disclosure. Figure OneThe aspects of the disclosure are best understood from the following detailed description. It is to be noted that various features will be described which, alone or in various combinations, can be applied to various embodiments of the application. Each feature will be presented in the context of a particular aspect and it will be apparent by those skilled in the art that the features or combinations of features can be applied to other aspects. Features can be combined from different aspects. Various features can be omitted, substituted and / or augmented, in various embodiments, without departing from the scope of the present disclosure. The various features of the disclosure will be discussed in the context of exemplary embodiments.

[0022] Figure 1 is a top view schematic diagram illustrating a memory element of some embodiments of the present disclosure.

[0023] Figure 2 is a cross-sectional view schematic diagram illustrating a cross-section of a memory element of some alternative embodiments of the present disclosure along Figure 1 the cross-sectional line A-A' in FIG. 1.

[0024] Figure 3 is a flow schematic diagram illustrating a method of fabricating a memory element of some embodiments of the present disclosure.

[0025] Figure 4 is a top view schematic diagram illustrating an intermediate stage of forming a capacitor over a semiconductor substrate during fabrication of a memory element of some embodiments of the present disclosure.

[0026] Figure 5 is a cross-sectional view schematic diagram illustrating a cross-section of an intermediate stage of forming a memory element of some embodiments of the present disclosure along Figure 4 the cross-sectional line A-A' in FIG. 3.

[0027] Figure 6 is a top view schematic diagram illustrating an intermediate stage of forming a conductive layer over a capacitor during fabrication of a memory element of some embodiments of the present disclosure.

[0028] Figure 7 is a cross-sectional view schematic diagram illustrating a cross-section of an intermediate stage of forming a memory element of some embodiments of the present disclosure along Figure 6 the cross-sectional line A-A' in FIG. 6.

[0029] Figure 8 is a top view schematic diagram illustrating an intermediate stage of etching a conductive layer to form a conductive plug during fabrication of a memory element of some embodiments of the present disclosure.

[0030] Figure 9 is a cross-sectional view schematic diagram illustrating a cross-section of an intermediate stage of forming a memory element of some embodiments of the present disclosure along Figure 8 the cross-sectional line A-A' in FIG. 9.

[0031] Figure 10 is a top view schematic diagram illustrating an intermediate stage of sequentially forming a dielectric layer and a word line layer over a conductive plug during fabrication of a memory element of some embodiments of the present disclosure.

[0032] Figure 11 is a cross-sectional view schematic diagram illustrating a cross-section of an intermediate stage of forming a memory element of some embodiments of the present disclosure alongFigure 10 The section line A-A' in the diagram forms a cross-section of the intermediate stage of the memory element.

[0033] Figure 12 This is a top view schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure where dielectric layers and word line layers are etched during the formation of memory elements to form dielectric portions and word lines.

[0034] Figure 13 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 12 The section line A-A' in the diagram forms a cross-section of the intermediate stage of the memory element.

[0035] Figure 14 This is a top view schematic diagram illustrating an intermediate stage in the formation of a dielectric layer above the word line during the formation of memory elements according to some embodiments of the present disclosure.

[0036] Figure 15 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 14 The section line A-A' in the diagram forms a cross-section of the intermediate stage of the memory element.

[0037] Figure 16 This is a top view schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure where openings are formed during the formation of memory elements to expose conductive plugs.

[0038] Figure 17 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 16 The section line A-A' in the diagram forms a cross-section of the intermediate stage of the memory element.

[0039] Figure 18 This is a top view schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure during the formation of a memory element, in which conductive plugs are etched through openings to form a first groove.

[0040] Figure 19 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 18 The section line A-A' in the diagram forms a cross-section of the intermediate stage of the memory element.

[0041] Figure 20 This is a top view schematic diagram illustrating some embodiments of the present disclosure of the intermediate stages of forming a gate dielectric layer and a channel layer in an opening and a first recess during the formation of a memory element.

[0042] Figure 21 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 20 The section line A-A' in the diagram forms a cross-section of the intermediate stage of the memory element.

[0043] Figure 22is a top view schematic diagram illustrating an intermediate stage of forming a photoresist layer and a dielectric gap sub in a dielectric layer above a channel layer during formation of a memory element in accordance with some embodiments of the present disclosure.

[0044] Figure 23 is a cross-sectional view schematic diagram illustrating a cross-section of an intermediate stage of forming a memory element along a cross-sectional line A-A' in Figure 22

[0045] Figure 24 is a top view schematic diagram illustrating an intermediate stage of etching a channel layer to form a second recess during formation of a memory element in accordance with some embodiments of the present disclosure.

[0046] Figure 25 is a cross-sectional view schematic diagram illustrating a cross-section of an intermediate stage of forming a memory element along a cross-sectional line A-A' in Figure 24

[0047] Figure 26 is a top view schematic diagram illustrating an intermediate stage of forming a bit line layer above a channel layer and in a second recess during formation of a memory element in accordance with some embodiments of the present disclosure.

[0048] Figure 27 is a cross-sectional view schematic diagram illustrating a cross-section of an intermediate stage of forming a memory element along a cross-sectional line A-A' in Figure 26

[0049] wherein the reference signs are explained as follows:

[0050] 10: manufacturing method

[0051] 100: memory element

[0052] 101: semiconductor substrate

[0053] 103a: capacitor

[0054] 103b: capacitor

[0055] 105: conductive layer

[0056] 105a: conductive plug

[0057] 105b: conductive plug

[0058] 107a: pattern

[0059] 107b: pattern

[0060] 111: dielectric layer

[0061] 111a: dielectric portion

[0062] 111b: dielectric portion ​​​

[0063] 113: word line layer

[0064] 113a: word line

[0065] 113b: word line

[0066] 115a: pattern

[0067] 115b: pattern

[0068] 117: dielectric layer

[0069] 119: patterned mask

[0070] 122a: opening

[0071] 122b: opening

[0072] 124a: opening

[0073] 124b: opening

[0074] 126a: first recess

[0075] 126b: first recess

[0076] 131a: gate dielectric layer

[0077] 131b: gate dielectric layer

[0078] 133a: channel layer

[0079] 133b: channel layer

[0080] 135: photoresist layer

[0081] 137a: dielectric spacer

[0082] 137b: dielectric spacer

[0083] 140a: opening

[0084] 140b: opening

[0085] 142a: second recess

[0086] 142b: second recess

[0087] 145: bit line layer

[0088] 145a: bit line

[0089] 145b: bit line

[0090] 147a: lower portion

[0091] 147b: lower portion

[0092] 149a: upper portion

[0093] 149b: upper portion

[0094] 151: patterned mask

[0095] B1: lower surface

[0096] B2: lower surface

[0097] B3: lower surface

[0098] E1: edge

[0099] E2: edge

[0100] P: portion

[0101] S11-S29: steps

[0102] SW1: sidewall

[0103] SW2: sidewall

[0104] SW3: sidewall

[0105] SW4: sidewall

[0106] SW5: sidewall

[0107] T1: upper surface

[0108] T2: upper surface

[0109] T3: upper surface

[0110] T4: upper surface

[0111] T5: upper surface

[0112] T6: upper surface

[0113] T7: upper surface DETAILED DESCRIPTION

[0114] The following description describes specific examples of components and configurations to simplify the present disclosure. These specific examples are merely intended to provide examples for discussion and are not intended to limit the scope of the present disclosure. For example, when a first component is described as being formed on a second component, the example can include embodiments where the first and second components are in direct contact, and embodiments where additional components are formed between the first and second components such that the first and second components are not in direct contact. Additionally, embodiments of the present disclosure can repeatedly refer to reference numerals and / or letters in many examples. These repetitions are for the purpose of simplification and clarity, and do not inherently represent a particular relationship between the various embodiments and / or the configurations being discussed, unless specifically stated otherwise in the text.

[0115] Moreover, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0116] Figure 1 is a top view schematic diagram illustrating a memory element 100 in accordance with some embodiments of the present disclosure. Figure 2 is a cross-sectional view schematic diagram illustrating a memory element 100 along a cross-sectional line A-A' in Figure 1 of FIG. 1 in accordance with some alternative embodiments of the present disclosure.

[0117] As shown in FIGS. 1 and 2, in accordance with some embodiments, the memory element 100 includes a semiconductor substrate 101 and a plurality of capacitors 103a and 103b disposed above the semiconductor substrate 101. In some embodiments, a plurality of conductive plugs 105a and 105b are disposed above the capacitors 103a and 103b, respectively. In some embodiments, the memory element 100 includes a dielectric portion 111a disposed above the conductive plug 105a and a word line 113a disposed above the dielectric portion 111a. Figure 1 Figure 2 In some embodiments, sidewalls of the capacitor 103a and sidewalls of the conductive plug 105a are covered by the dielectric portion 111a. In some embodiments, sidewalls of the dielectric portion 111a are substantially aligned with sidewalls of the word line 113a. In the context of the present disclosure, the word "substantially" means preferably at least 90%, more preferably 95%, even more preferably 98%, and most preferably 99%.

[0118] In some embodiments, the memory element 100 includes a dielectric portion 111b disposed above the conductive plug 105b and a word line 113b disposed above the dielectric portion 111b. In some embodiments, sidewalls of the capacitor 103b and sidewalls of the conductive plug 105b are covered by the dielectric portion 111b. In some embodiments, sidewalls of the dielectric portion 111b are substantially aligned with sidewalls of the word line 113b. In some embodiments, the memory element 100 includes a dielectric layer 117 disposed above the word lines 113a and 113b.

[0119] In some embodiments, the memory element 100 includes a dielectric portion 111b disposed above the conductive plug 105b and a word line 113b disposed above the dielectric portion 111b. In some embodiments, sidewalls of the capacitor 103b and sidewalls of the conductive plug 105b are covered by the dielectric portion 111b. In some embodiments, sidewalls of the dielectric portion 111b are substantially aligned with sidewalls of the word line 113b. In some embodiments, the memory element 100 includes a dielectric layer 117 disposed above the word lines 113a and 113b.

[0120] ​In addition, according to some embodiments, the memory element 100 includes a gate dielectric layer 131a and a channel layer 133a that pass through the dielectric layer 117, the word line 113a, and the dielectric portion 111a. In some embodiments, the channel layer 133a is surrounded by the gate dielectric layer 131a, and the gate dielectric layer 131a is surrounded by the word line 113a. In some embodiments, the channel layer 133a is separated from the dielectric layer 117, the word line 113a, and the dielectric portion 111a by the gate dielectric layer 131a. In some embodiments, the gate dielectric layer 131a is in direct contact with the word line 113a and the channel layer 133a.

[0121] In some embodiments, the memory element 100 also includes a gate dielectric layer 131b and a channel layer 133b that pass through the dielectric layer 117, the word line 113b, and the dielectric portion 111b. In some embodiments, the channel layer 133b is surrounded by the gate dielectric layer 131b, and the gate dielectric layer 131b is surrounded by the word line 113b. In some embodiments, the channel layer 133b is separated from the dielectric layer 117, the word line 113b, and the dielectric portion 111b by the gate dielectric layer 131b. In some embodiments, the gate dielectric layer 131b is in direct contact with the word line 113b and the channel layer 133b.

[0122] In some embodiments, the gate dielectric layer 131a and the channel layer 133a extend into the conductive plug 105a such that an upper surface T2 of the conductive plug 105a is higher than a lower surface B1 of the channel layer 133a and a lower surface B2 of the gate dielectric layer 131a. In some embodiments, the conductive plug 105a has an upper surface T2 and an upper surface T3. The upper surface T3 is an upper surface of a recess of the conductive plug 105a. Thus, the upper surface T2 is higher than the upper surface T3, which is referred to as a recessed upper surface of the conductive plug 105a.

[0123] In some embodiments, the gate dielectric layer 131a and the channel layer 133a are in direct contact with the recessed upper surface T3 of the conductive plug 105a. In some embodiments, the gate dielectric layer 131a and the channel layer 133a are separated from the capacitor 103a by a portion of the conductive plug 105a. In some embodiments, the lower surface B1 of the channel layer 133a and the lower surface B2 of the gate dielectric layer 131a are higher than an upper surface T1 of the capacitor 103a.

[0124] It should be appreciated that the above features also exist in the capacitor 103b, the conductive plug 105b, the gate dielectric layer 131b, and the channel layer 133b, which are not repeated here.

[0125] Furthermore, according to some embodiments, the memory element 100 includes bit lines 145a and 145b disposed above the dielectric layer 117. In some embodiments, bit line 145a is disposed above the channel layer 133a and the gate dielectric layer 131a, and bit line 145b is disposed above the channel layer 133b and the gate dielectric layer 131b. In some embodiments, bit line 145a is electrically connected to capacitor 103a via channel layer 133a and conductive plug 105a, and bit line 145b is electrically connected to capacitor 103b via channel layer 133b and conductive plug 105b.

[0126] In some embodiments, bit line 145a includes a lower portion 147a extending into channel layer 133a and an upper portion 149a disposed above the lower portion 147a. In some embodiments, bit line 145b includes a lower portion 147b extending into channel layer 133b and an upper portion 149b disposed above the lower portion 147b. In some embodiments, the upper portion 149a of bit line 145a extends laterally beyond the opposite edge of the lower portion 147a of bit line 145a, and the upper portion 149b of bit line 145b extends laterally beyond the opposite edge of the lower portion 147b of bit line 145b (e.g., the opposite edges E1 and E2 of the lower portion 147b of bit line 145b). Therefore, bit lines 145a and 145b in Figure 2 The cross-sectional view has a T-shaped profile.

[0127] In some embodiments, the opposing edges (e.g., opposing edges E1 and E2) of the lower portions 147a and 147b of bit lines 145a and 145b are separated from the gate dielectric layers 131a and 131b by channel layers 133a and 133b. In some embodiments, channel layer 133a has a portion sandwiched between the lower portion 147a of bit line 145a and the gate dielectric layer 131a, and channel layer 133b has a portion sandwiched between the lower portion 147b of bit line 145b and the gate dielectric layer 131b. For example, a portion P of channel layer 133a is sandwiched between the lower portion 147a of bit line 145a and the gate dielectric layer 131a.

[0128] In some embodiments, bit line 145a extends into channel layer 133a such that an upper surface T6 of channel layer 133a is higher than a lower surface B3 of bit line 145a. In some embodiments, channel layer 133a has an upper surface T6 and an upper surface T7. Upper surface T7 is the upper surface of a recessed portion of channel layer 133a. Therefore, upper surface T6 is higher than upper surface T7, and upper surface T7 is referred to as the recessed upper surface of channel layer 133a.

[0129] In some embodiments, Figure 1In the top view, the recessed upper surface T3 of the conductive plug 105a partially overlaps with the recessed upper surface T7 of the channel layer 133a. In some embodiments, the bit line 145a is in direct contact with the recessed upper surface T7 of the channel layer 133a. In some embodiments, the recessed upper surface T7 of the channel layer 133a is higher than an upper surface T4 of the word line 113a.

[0130] In some embodiments, an upper surface T5 of the gate dielectric layer 131a is substantially coplanar with an upper surface T6 of the channel layer 133a. In some embodiments, the upper surface T5 of the gate dielectric layer 131a and the upper surface T6 of the channel layer 133a are higher than the recessed upper surface T7 of the channel layer 133a. In some embodiments, both the upper surface T5 of the gate dielectric layer 131a and the upper surface T6 of the channel layer 133a are higher than the upper surface T4 of the word line 113a.

[0131] It should be understood that the above features also exist in word line 113b, gate dielectric layer 131b, channel layer 133b and bit line 145b, which will not be described in detail here.

[0132] In some embodiments, the memory element 100 includes conductive plugs 105a and 105b disposed above capacitors 103a and 103b, channel layers 133a and 133b disposed above the conductive plugs 105a and 105b, and bit lines 145a and 145b disposed above the channel layers 133a and 133b. In some embodiments, the conductive plugs 105a and 105b and the channel layers 133a and 133b have recessed upper surfaces. Therefore, the contact area between the channel layers 133a and 133b and the conductive plugs 105a and 105b, and the contact area between the bit lines 145a and 145b and the channel layers 133a and 133b, is increased. Consequently, the contact resistance is reduced. This allows for increased drive current and improved performance of the memory element 100. Furthermore, the increased contact area provides a larger process window for manufacturing memory elements, such as bit line landings.

[0133] Figure 3 This is a flowchart illustrating a method 10 for fabricating a memory element 100 according to some embodiments of this disclosure, and the fabrication method 10 includes steps S11, S13, S15, S17, S19, S21, S23, S25, S27, and S29. (In conjunction with...) Figures 4 to 27 right Figure 3 Steps S11 to S29 will be explained in detail.

[0134] Figure 4 , Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 ,Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 and Figure 26 A top view of memory element 100 at an intermediate stage of its formation is shown, and Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 25 and Figure 27 This is an example of a cross-sectional view of memory element 100 at an intermediate stage of its formation. It should be understood that... Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 25 and Figure 27 They are respectively along Figure 4 , Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 and Figure 26 A sectional view along section line A-A'.

[0135] like Figure 4 and Figure 5 As shown, a semiconductor substrate 101 is provided. The semiconductor substrate 101 may be or may include a package substrate, an interposer, a printed circuit board (PCB), and / or other circuit carriers capable of carrying integrated circuits (ICs).

[0136] Semiconductor substrate 101 may include a variety of passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable integrated circuit (IC) components, or combinations thereof.

[0137] Furthermore, the semiconductor substrate 101 may include various material layers (e.g., dielectric layers, semiconductor layers, and / or conductive layers) configured to form IC features (e.g., doped regions, isolation features, gate features, source / drain features, interconnect features, other features, or combinations thereof). For clarity, the semiconductor substrate 101 has been simplified. It should be understood that additional features may be added to the semiconductor substrate 101, and some features described below may be replaced, modified, or eliminated in other embodiments.

[0138] Please refer to the following: Figure 4 and Figure 5 According to some embodiments, multiple capacitors 103a and 103b are formed on the semiconductor substrate 101. The corresponding steps are as follows: Figure 3 Step S11 of the fabrication method 10 is shown. In some alternative embodiments, capacitors 103a and 103b are formed in the semiconductor substrate 101. In some embodiments, capacitors 103a and 103b are spaced apart from each other.

[0139] Next, according to some embodiments, a conductive layer 105 is formed over a semiconductor substrate 101, and a patterned mask including patterns 107a and 107b is formed over the conductive layer 105, such as... Figure 6 and Figure 7 As shown. In some embodiments, the sidewalls and top surfaces of capacitors 103a and 103b are covered by a conductive layer 105. In some embodiments, in Figure 6 In the top view, the pattern 107a of the patterned mask overlaps with the capacitor 103a, and the pattern 107b of the patterned mask overlaps with the capacitor 103b.

[0140] In some embodiments, the conductive layer 105 comprises aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), combinations thereof, or other suitable conductive materials. In some embodiments, the fabrication technique of the conductive layer 105 includes a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or other suitable deposition processes. In some embodiments, the conductive layer 105 and the patterned mask having patterns 107a, 107b comprise different materials, allowing for different etching selectivity in subsequent etching processes.

[0141] Subsequently, as Figure 8 and Figure 9 As shown, according to some embodiments, a patterned mask with patterns 107a and 107b is used as a mask to etch the conductive layer 105, so that conductive plugs 105a and 105b are formed above capacitors 103a and 103b. The corresponding steps are as follows:Figure 3 As shown in step S13 of the preparation method 10. In some embodiments, a wet etching process, a dry etching process, or a combination thereof is used to etch the conductive layer 105.

[0142] In some embodiments, Figure 8 In the top view, conductive plugs 105a and 105b overlap with capacitors 103a and 103b. In some embodiments, the sidewalls of capacitors 103a and 103b are substantially aligned with the sidewalls of conductive plugs 105a and 105b. For example, the sidewalls SW1 of capacitor 103a are substantially aligned with the sidewalls SW2 of conductive plug 105a. After forming conductive plugs 105a and 105b, the patterned mask with patterns 107a and 107b can be removed (see...). Figure 6 and Figure 7 In some embodiments, the patterned mask is removed by a stripping process, an ashing process, an etching process, or other suitable process.

[0143] Then, according to some embodiments, such as Figure 10 and Figure 11 As shown, a dielectric layer 111 is formed over a semiconductor substrate 101, and a word line layer 113 is formed over the dielectric layer 111. In some embodiments, the sidewalls of conductive plugs 105a and 105b and the sidewalls of capacitors 103a and 103b are covered by the dielectric layer 111. For example, the sidewalls SW1 of capacitor 103a and the sidewalls SW2 of conductive plug 105a are covered by the dielectric layer 111.

[0144] In some embodiments, the dielectric layer 111 comprises silicon nitride, silicon oxide, silicon oxynitride, combinations thereof, or other suitable dielectric materials. In some embodiments, the dielectric layer 111 is fabricated using a deposition process, such as CVD, PVD, ALD, spin-coating, or other suitable deposition processes. In some embodiments, the character line layer 113 comprises polysilicon, aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), combinations thereof, or other suitable materials. In some embodiments, the character line layer 113 is fabricated using a CVD process, PVD process, sputtering process, electroplating process, or other suitable processes.

[0145] Please refer to the following: Figure 10 and Figure 11 According to some embodiments, a patterned mask including patterns 115a and 115b is formed over the character line layer 113. In some embodiments, the pattern 115a of the patterned mask is arranged parallel to the pattern 115b of the patterned mask. In some embodiments, in Figure 10In the top view, the conductive plug 105a overlaps with the pattern 115a of the patterned mask, and the conductive plug 105b overlaps with the pattern 115b of the patterned mask.

[0146] Next, according to some embodiments, such as Figure 12 and Figure 13 As shown, a patterned mask with patterns 115a and 115b is used as a mask to etch the character line layer 113 and the dielectric layer 111, so that the character lines 113a, 113b and the dielectric portions 111a, 111b are formed above the conductive plugs 105a, 105b. The corresponding steps are as follows: Figure 3 The preparation method 10 shown is illustrated in step S15. In some embodiments, the character line layer 113 and the dielectric layer 111 are etched by a wet etching process, a dry etching process, or a combination thereof.

[0147] In some embodiments, the sidewalls of character lines 113a and 113b are substantially aligned with the sidewalls of dielectric portions 111a and 111b. For example, the sidewalls SW4 of character line 113a are substantially aligned with the sidewalls SW3 of dielectric portion 111a. In some embodiments, the sidewalls of capacitors 103a and 103b and the sidewalls of conductive plugs 105a and 105b are covered by dielectric portions 111a and 111b. For example, the sidewalls SW1 of capacitor 103a and the sidewalls SW2 of conductive plug 105a are covered by dielectric portion 111a.

[0148] After forming the character lines 113a, 113b and the dielectric portions 111a, 111b, the patterned mask with patterns 115a and 115b can be removed (see reference). Figure 10 and Figure 11 In some embodiments, the patterned mask is removed by a stripping process, an ashing process, an etching process, or other suitable process.

[0149] Subsequently, according to some embodiments, such as Figure 14 and Figure 15 As shown, a dielectric layer 117 is formed over a semiconductor substrate 101, and a patterned mask 119 having openings 122a and 122b is formed over the dielectric layer 117. In some embodiments, word lines 113a and 113b are covered by the dielectric layer 117. In some embodiments, the sidewalls of word lines 113a and 113b, as well as the sidewalls of dielectric portions 111a and 111b, are covered by the dielectric layer 117. For example, the dielectric layer 117 covers the sidewalls SW3 of dielectric portion 111a and the sidewalls SW4 of word line 113a.

[0150] In some embodiments, the dielectric layer 117 is partially exposed via openings 122a and 122b of the patterned mask 119. Furthermore, according to some embodiments, inFigure 14 In the top view, the opening 122a of the patterned mask 119 overlaps with the capacitor 103a and the conductive plug 105a, and the opening 122b of the patterned mask 119 overlaps with the capacitor 103b and the conductive plug 105b. The corresponding steps are as follows: Figure 3 Step S17 of preparation method 10 is shown.

[0151] Then, according to some embodiments, such as Figure 16 and Figure 17 As shown, a patterned mask 119 is used as a mask to form multiple openings 124a and 124b to penetrate the dielectric layer 117, character lines 113a and 113b, and dielectric portions 111a and 111b, thereby exposing conductive plugs 105a and 105b. The corresponding steps are as follows: Figure 3 The preparation method 10 shown is illustrated in step S19. In some embodiments, the fabrication techniques for openings 124a and 124b include performing a wet etching process, a dry etching process, or a combination thereof.

[0152] In some embodiments, the upper surface of the conductive plug 105a is partially exposed through the opening 124a, and the upper surface of the conductive plug 105b is partially exposed through the opening 124b. In some embodiments, after forming the openings 124a and 124b, the upper surface of the conductive plug 105a is partially covered by the remaining portion of the dielectric portion 111a, and the upper surface of the conductive plug 105b is partially covered by the remaining portion of the dielectric portion 111b. Furthermore, in some embodiments, after forming the openings 124a and 124b, the sidewalls of the conductive plugs 105a and 105b, and the sidewalls of the capacitors 103a and 103b, are covered by the remaining portions of the dielectric portions 111a and 111b. For example, the sidewalls SW1 of the capacitor 103a and the sidewalls SW2 of the conductive plug 105a are covered by the remaining portion of the dielectric portion 111a.

[0153] Once the conductive plugs 105a and 105b are exposed through the openings 124a and 124b, the patterned mask 119 can be removed. In some embodiments, the patterned mask 119 is removed by a stripping process, an ashing process, an etching process, or other suitable process.

[0154] Next, according to some embodiments, such as Figure 18 and Figure 19 As shown, an etching process is performed via openings 124a and 124b to form first grooves 126a and 126b in conductive plugs 105a and 105b. The corresponding steps are as follows: Figure 3As shown in step S21 of the preparation method 10. In some embodiments, after the first grooves 126a and 126b are formed, the upper surfaces of the portions of the conductive plugs 105a and 105b covered by the dielectric portions 111a and 111b (e.g., the upper surfaces of the portions of the conductive plugs 105a and 105b not recessed by the etching process) are higher than the upper surfaces of the recessed portions of the conductive plugs 105a and 105b.

[0155] For example, the upper surface T2 of the portion of the conductive plug 105a covered by the dielectric portion 111a is higher than the upper surface T3 of the recessed portion of the conductive plug 105a. In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination thereof.

[0156] Subsequently, according to some embodiments, such as Figure 20 and Figure 21 As shown, gate dielectric layers 131a and 131b, and channel layers 133a and 133b are formed in openings 124a and 124b and first recesses 126a and 126b. In some embodiments, channel layer 133a is surrounded by gate dielectric layer 131a, and channel layer 133b is surrounded by gate dielectric layer 131b. The corresponding steps are as follows... Figure 3 Steps S23 and S25 of preparation method 10 are shown.

[0157] In some embodiments, the lower surfaces of the gate dielectric layers 131a and 131b and the lower surfaces of the channel layers 133a and 133b are lower than the upper surfaces of the portions of the conductive plugs 105a and 105b covered by the dielectric portions 111a and 111b (e.g., the upper surfaces of the portions of the conductive plugs 105a and 105b not recessed by the etching process). For example, the upper surface T2 of a portion of the conductive plug 105a is covered by the dielectric portion 111a, and the lower surface B1 of the channel layer 133a and the lower surface B2 of the gate dielectric layer 131a are lower than the upper surface T2.

[0158] In some embodiments, the lower surfaces of the gate dielectric layers 131a and 131b and the lower surfaces of the channel layers 133a and 133b are in direct contact with the recessed upper surfaces of the conductive plugs 105a and 105b. For example, the lower surface B1 of the channel layer 133a and the lower surface B2 of the gate dielectric layer 131a are in direct contact with the recessed upper surface T3 of the conductive plug 105a.

[0159] In some embodiments, gate dielectric layers 131a and 131b comprise silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or other suitable dielectric materials. In some embodiments, channel layers 133a and 133b comprise indium gallium zinc oxide (InGaZnO). However, any other suitable material may be used, such as indium zinc oxide (InZnO), indium tin oxide (InSnO), indium oxide (InOx), or gallium oxide (GaOx).

[0160] In some embodiments, the formation of gate dielectric layers 131a, 131b and channel layers 133a, 133b includes sequentially depositing gate dielectric material (not shown) and channel material (not shown) in openings 124a, 124b, in recesses 126a, 126b, and over dielectric layer 117, and performing a planarization process to remove excess gate dielectric material and channel material outside openings 124a, 124b and recesses 126a, 126b. The deposition process may include CVD, PVD, ALD, spin-coating, or other suitable deposition processes. The planarization process may include chemical mechanical polishing (CMP).

[0161] Then, according to some embodiments, such as Figure 22 and Figure 23 As shown, a photoresist layer 135 is formed above the dielectric layer 117, and a plurality of dielectric spacers 137a and 137b are formed to cover the sidewalls of the photoresist layer 135. For example, each sidewall SW5 of the photoresist layer 135 is covered by dielectric spacers 137a. According to some embodiments, after the photoresist layer 135 and dielectric spacers 137a and 137b are formed, the channel layer 133a is partially exposed through opening 140a, and the channel layer 133b is partially exposed through opening 140b.

[0162] In some embodiments, the upper surfaces of gate dielectric layers 131a and 131b are covered by dielectric spacers 137a and 137b. For example, the upper surface T5 of gate dielectric layer 131a is covered by dielectric spacer 137a. In some embodiments, the upper surfaces of channel layers 133a and 133b are partially covered by dielectric spacers 137a and 137b. For example, the upper surface T6 of channel layer 133a is partially covered by dielectric spacer 137a.

[0163] In some embodiments, dielectric spacers 137a and 137b are formed after the photoresist layer 135 is formed. The formation of dielectric spacers 137a and 137b may include depositing a dielectric layer (not shown) over the photoresist layer 135, performing an etching process to remove the horizontal portions of the dielectric layer, leaving the vertical portions of the dielectric layer. The remaining vertical portions of the dielectric layer are referred to as dielectric spacers 137a and 137b. In some embodiments, the etching process is an isotropic etching process.

[0164] Next, according to some embodiments, such as Figure 24 and Figure 25 As shown, an etching process is performed using photoresist layer 135 and dielectric spacers 137a and 137b as a mask to form second grooves 142a and 142b in channel layers 133a and 133b. The corresponding steps are as follows: Figure 3 As shown in step S27 of the fabrication method 10, after the second grooves 142a and 142b are formed, the photoresist layer 135 and the dielectric spacers 137a and 137b can be removed.

[0165] In some embodiments, after the second grooves 142a and 142b are formed, the upper surfaces of the portions of the channel layers 133a and 133b covered by the dielectric spacers 137a and 137b are higher than the upper surfaces of the recessed portions of the channel layers 133a and 133b. For example, the channel layer 133a is covered by the dielectric spacer 137a (see reference 137a). Figure 22 and Figure 23 The upper surface T6 of the portion covered by the gate dielectric layer 131a and 131b is higher than the upper surface T7 of the recessed portion of the channel layer 133a. In some embodiments, the upper surfaces of each of the gate dielectric layers 131a and 131b are higher than the upper surfaces of each of the recessed portions of the channel layers 133a and 133b. For example, the upper surface T5 of the gate dielectric layer 131a is higher than the upper surface T7 of the recessed portion of the channel layer 133a.

[0166] In some embodiments, Figure 24 In the top view, the second grooves 142a and 142b of the channel layers 133a and 133b partially overlap with the first grooves 126a and 126b of the conductive plugs 105a and 105b (see reference). Figure 18 and Figure 19 In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination thereof.

[0167] Subsequently, according to some embodiments, such as Figure 26 and Figure 27As shown, a bit line layer 145 is formed in the second recesses 142a and 142b and above the dielectric layer 117, and a patterned mask 151 is formed above the bit line layer 145. In some embodiments, the upper surfaces of the gate dielectric layers 131a and 131b and the upper surfaces of the channel layers 133a and 133b are covered by the bit line layer 145. For example, upper surfaces T5, T6, and T7 are covered by the bit line layer 145.

[0168] In some embodiments, bitline layer 145 includes aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), combinations thereof, or other suitable materials. In some embodiments, the fabrication technique of bitline layer 145 includes a deposition process, such as CVD, PVD, ALD, sputtering, electroplating, or other suitable deposition process.

[0169] Please refer back to this page. Figure 1 and Figure 2 According to some embodiments, a patterned mask 151 is used as a mask to etch the bit line layer 145 to form bit lines 145a and 145b. In some embodiments, bit line 145a is formed over channel layer 133a and in second recess 142a (see reference). Figure 24 and Figure 25 Furthermore, bit line 145b is formed above channel layer 133b and in second groove 142b (see reference). Figure 24 and Figure 25 The corresponding steps are as follows: Figure 3 Step S29 of preparation method 10 is shown.

[0170] In some embodiments, the bit line layer 145 is etched using a wet etching process, a dry etching process, or a combination thereof. After forming the bit lines 145a and 145b, the patterned mask 151 can be removed (see reference). Figure 26 and Figure 27 In some embodiments, the patterned mask 151 is removed by a stripping process, an ashing process, an etching process, or other suitable process. Once the patterned mask 151 is removed, the memory element 100 is complete. In some embodiments, the memory element 100 is part of DRAM.

[0171] This disclosure provides embodiments of a memory element 100 and a method for fabricating the same. In some embodiments, the memory element 100 includes conductive plugs 105a and 105b disposed above capacitors 103a and 103b, channel layers 133a and 133b disposed above the conductive plugs 105a and 105b, and bit lines 145a and 145b disposed above the channel layers 133a and 133b. In some embodiments, the conductive plugs 105a and 105b have recessed upper surfaces (e.g., upper surface T3), and the channel layers 133a and 133b have recessed upper surfaces (e.g., upper surface T7). Therefore, the contact area between the channel layers 133a and 133b and the conductive plugs 105a and 105b is increased, and the contact area between the bit lines 145a and 145b and the channel layers 133a and 133b is also increased. Therefore, the contact resistance is reduced. In this way, the drive current can be increased, and the performance of the memory element 100 can be improved. In addition, the increased contact area provides a larger process window for the fabrication of memory elements, such as those with bit-line landing.

[0172] In one embodiment of this disclosure, a memory element is provided. The memory element includes a capacitor disposed above a semiconductor substrate; and a conductive plug disposed above the capacitor. The conductive plug has a first recessed upper surface. The memory element also includes a channel layer disposed above the conductive plug. The channel layer has a second recessed upper surface. The memory element further includes a bit line disposed above the channel layer; and a word line disposed between the conductive plug and the bit line. The channel layer is surrounded by the word line.

[0173] In another embodiment of this disclosure, a memory element is provided. The memory element includes a capacitor disposed above a semiconductor substrate and a conductive plug disposed above the capacitor. The memory element also includes a channel layer disposed above the conductive plug. An upper surface of the conductive plug is higher than a lower surface of the channel layer. The memory element further includes a bit line disposed above the channel layer. An upper surface of the channel layer is higher than a lower surface of the bit line. Furthermore, the memory element includes a gate dielectric layer and a word line located between the conductive plug and the bit line. The gate dielectric layer is disposed between the word line and the channel layer.

[0174] Another embodiment of this disclosure provides a method for fabricating a memory element. The method includes forming a capacitor over a semiconductor substrate and forming a conductive plug over the capacitor. The method also includes forming a word line over the conductive plug and forming an opening to penetrate the word line and expose the conductive plug. The method further includes performing a first etching process through the opening to form a first groove in the conductive plug and forming a channel layer in the opening. Furthermore, the method includes performing a second etching process to form a second groove in the channel layer and forming a bit line over the channel layer.

[0175] The embodiments disclosed herein have several advantageous features. By forming recessed conductive plugs and recessed channel layers, the contact area can be increased, thereby reducing contact resistance and increasing the drive current of the memory element. As a result, the performance of the memory element can be improved.

[0176] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0177] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this document that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A memory element comprising: a capacitor disposed above a semiconductor substrate; a conductive plug disposed above the capacitor, wherein the conductive plug has a first recessed upper surface; a channel layer disposed above the conductive plug, wherein the channel layer has a second recessed upper surface; a bit line disposed above the channel layer; and a word line disposed between the conductive plug and the bit line, wherein the channel layer is surrounded by the word line.

2. The memory element of claim 1, wherein the second recessed upper surface of the channel layer partially overlaps the first recessed upper surface of the conductive plug as viewed from a top view.

3. The memory element of claim 1, wherein the channel layer is in direct contact with the first recessed upper surface of the conductive plug.

4. The memory element of claim 1, wherein the bit line is in direct contact with the second recessed upper surface of the channel layer.

5. The memory element of claim 1, wherein the second recessed upper surface of the channel layer is higher than an upper surface of the word line.

6. The memory element of claim 1, wherein the bit line has a T-shaped profile.

7. The memory element of claim 1, further comprising a gate dielectric layer surrounding the channel layer, wherein the word line is separated from the channel layer by the gate dielectric layer.

8. The memory element of claim 7, wherein the gate dielectric layer is in direct contact with the first recessed upper surface of the conductive plug.

9. The memory element of claim 7, wherein an upper surface of the gate dielectric layer is higher than the second recessed upper surface of the channel layer.

10. The memory element of claim 7, wherein a portion of the channel layer is sandwiched between the bit line and the gate dielectric layer.

11. The memory element of claim 7, wherein the bit line has a lower portion extending into the channel layer and an upper portion above the lower portion, and wherein the upper portion of the bit line laterally extends beyond opposite edges of the lower portion of the bit line.

12. The memory element of claim 11, wherein an upper surface of the gate dielectric layer is covered by and in direct contact with the upper portion of the bit line.

13. The memory element of claim 11, wherein the lower portion of the bit line is separated from the gate dielectric layer.

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