Contact structure, semiconductor device including contact structure, and method of manufacturing semiconductor device

Abstract

The invention provides a contact structure, a semiconductor device including the contact structure, and a manufacturing method of the semiconductor device. The contact structure comprises a body part and an extension part extending downwards from the body part, and the extension part comprises a groove. The groove is recessed into a bottom surface of the extension portion, and the groove is recessed toward the body portion and exposed out of the body portion.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Patent Application No. 18 / 825,237, filed September 5, 2024, the contents of which are incorporated herein in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates to a contact structure, a semiconductor device having the same, and a method of manufacturing the semiconductor device. In particular, a contact structure having an extension. BACKGROUND

[0004] Semiconductor devices are used in a variety of electronic applications, including personal computers, cell phones, digital cameras, and other electronic devices. To meet increasing demands for computing performance, semiconductor devices continue to be shrunk in size. However, such shrinking also presents increasingly frequent and impactful challenges. Thus, while reducing complexity, challenges to improve quality, yield, performance, and reliability remain.

[0005] The above description of the prior art is provided only as background information and does not constitute admission of prior art by the Applicant, does not constitute any part of the prior art for the present disclosure, and does not constitute admission of any part of the above description of the prior art as prior art to the present disclosure. Any acknowledgement of the above description of the prior art is solely for the purpose of the priority application of this patent application. SUMMARY

[0006] One aspect of the present disclosure provides a semiconductor device, including a substrate; a word line structure including a word line electrode; a dopant region including an upper portion adjacent to the word line structure and a lower portion below the upper portion; and a contact structure including a body portion on the dopant region and an extension portion below the body portion. A top surface of the word line electrode of the word line structure is lower than a top surface of the upper portion of the dopant region, and the upper portion of the dopant region has a tapered cross-sectional profile.

[0007] Another aspect of the present disclosure provides a semiconductor device, including a substrate having an isolation layer disposed therein; a plurality of dopant regions disposed within an active region defined by the isolation layer; and a plurality of first word line structures disposed within the isolation layer and a plurality of second word line structures disposed within the active region.

[0008] Another aspect of the present disclosure provides a semiconductor device including a substrate; a word line structure disposed in the substrate; a dopant region including an upper portion adjacent to the word line structure and a lower portion disposed under the upper portion; a bit line contact disposed in the substrate and protruding from the substrate; and a bit line disposed on the bit line contact. The word line structure includes a word line dielectric layer contacting the lower portion of the dopant region, a word line electrode disposed on the word line dielectric layer, and a word line cap layer disposed on the word line electrode. A top surface of the word line electrode of the word line structure is lower than a top surface of the upper portion of the dopant region. The upper portion of the dopant region has a tapered cross-sectional profile.

[0009] Due to the design of the semiconductor device of the present disclosure, the extension portion can increase the contact area of the contact structure. As a result, the performance of the semiconductor device can be improved.

[0010] The foregoing has outlined rather broadly the technical features of the present disclosure in order that the detailed description of the present disclosure that follows can be better understood. Additional technical features and advantages of the present disclosure will be described hereinafter. The present disclosure is to be considered as encompassing all possible combinations of the technical features explicitly included or inherent to the technology described herein. One skilled in the art will readily recognize from the disclosure herein, given the benefit of the present disclosure, that alternative embodiments of the present disclosure can be implemented and / or performed without deviating from the scope of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0011] The disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, in which like reference symbols refer to like elements throughout the several views.

[0012] According to an embodiment of the present disclosure, Figure 1 A method of manufacturing a semiconductor device is shown in the form of a flow chart.

[0013] According to an embodiment of the present disclosure, Figures 2 to 10 Cross-sectional schematic views of processes of manufacturing a semiconductor device are shown.

[0014] According to an embodiment of the present disclosure, Figure 11 A top view schematic diagram of an intermediate semiconductor device is shown.

[0015] Figure 12 is a cross-sectional schematic view along Figure 11 line A-A' of the semiconductor device.

[0016] According to an embodiment of the present disclosure, Figure 13 A top view schematic diagram of an intermediate semiconductor device is shown.

[0017] Figure 14 is a cross-sectional schematic view alongFigure 13 A schematic diagram of the cross section of line A-A'.

[0018] According to one embodiment of this disclosure, Figure 15 Showing a top view of the intermediate semiconductor device.

[0019] According to one embodiment of this disclosure, Figure 16 and Figure 17 For along Figure 15 A cross-sectional view of line A-A' shows the manufacturing process for a semiconductor device.

[0020] According to one embodiment of this disclosure, Figure 18 Showing a top view of the intermediate semiconductor device.

[0021] Figure 19 For along Figure 18 A schematic diagram of the cross section of line A-A'.

[0022] According to one embodiment of this disclosure, Figure 20 Showing a top view of the intermediate semiconductor device.

[0023] Figure 21 For along Figure 20 A schematic diagram of the cross section of line A-A'.

[0024] According to one embodiment of this disclosure, Figure 22 Showing a top view of the intermediate semiconductor device.

[0025] According to one embodiment of this disclosure, Figures 23 to 26 For along Figure 22 A cross-sectional view of line A-A' shows the manufacturing process for a semiconductor device.

[0026] Figure 27 For along Figure 26 A schematic diagram of the cross sections along lines B-B' and C-C'.

[0027] According to some embodiments of this disclosure Figure 28 and Figure 29 This diagram shows a cross-sectional view of the body and extension of the semiconductor device.

[0028] According to another embodiment of this disclosure, Figure 30 This is a cross-sectional schematic diagram of a semiconductor device.

[0029] According to various embodiments of this disclosure Figure 31 This is a cross-sectional schematic diagram of a semiconductor device.

[0030] According to various embodiments of this disclosure Figures 32 to 33 This is a cross-sectional schematic diagram showing the manufacturing process of semiconductor devices.

[0031] Wherein, the reference numerals are explained as follows:

[0032] 1A: semiconductor device

[0033] 1B: semiconductor device

[0034] 1C: semiconductor device

[0035] 1D: semiconductor device

[0036] 1E: semiconductor device

[0037] 10: method

[0038] 101: base

[0039] 101P: protrusion

[0040] 101PT: top surface

[0041] 101TS: top surface

[0042] 103: isolation layer

[0043] 105: impurity region

[0044] 107B: impurity region

[0045] 107B-1: upper portion

[0046] 107B-2: lower portion

[0047] 107BS: bottom surface

[0048] 107C: impurity region

[0049] 107C-1: upper portion

[0050] 107C-2: lower portion

[0051] 107TS: top surface

[0052] 107S1: sidewall

[0053] 107S2: sidewall

[0054] 111: bottom dielectric layer

[0055] 113: middle dielectric layer

[0056] 115: top dielectric layer

[0057] 200: word line structure

[0058] 200': word line structure

[0059] 201: word line dielectric layer

[0060] 201': Character line dielectric layer

[0061] 203: Conductive layer at the bottom of the character line

[0062] 203': Bottom conductive layer of character line

[0063] 205: Top conductive layer of character line

[0064] 205': Top conductive layer of character line

[0065] 205'TS: Top surface

[0066] 207: Character Line Cover Layer

[0067] 207': Character line capping

[0068] 301: Bit line contact

[0069] 301O: Bit line contact opening

[0070] 303: Bitline

[0071] 400: Contact Structure

[0072] 401: Ontology Department

[0073] 401O: Unit contact opening

[0074] 403: Extension

[0075] 403BS: bottom surface

[0076] 403E: Extended unit contact opening

[0077] 403R: Trench

[0078] 403TS: Top surface

[0079] 611: First insulating material

[0080] 711: First Sacrifice Layer

[0081] 711O: First middle opening

[0082] 713: Second Sacrificial Layer

[0083] 713O: Second middle opening

[0084] 811: First masking layer

[0085] 813: Second masking layer

[0086] 815: Third masking layer

[0087] 817: Barrier Layer

[0088] 901: Depression

[0089] 901BS: Bottom

[0090] 901P: Intersection

[0091] 901S1: Sidewall

[0092] 901S2: Sidewall

[0093] AA: Active Zone

[0094] CP1: Center point

[0095] CP2: Center point

[0096] D1: Diameter

[0097] D2: Diameter

[0098] H1: Height

[0099] H2: Height

[0100] S1: Sidewall

[0101] S2: Sidewall

[0102] S11: Steps

[0103] S13: Steps

[0104] S15: Steps

[0105] T1: Top surface

[0106] T2: Top surface

[0107] TR1: Trench

[0108] TR2: Trench

[0109] Z: Direction

[0110] α: Angle Detailed Implementation

[0111] The following disclosure provides numerous different embodiments or examples to achieve different features of the provided technical content. To simplify this disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this disclosure. For example, when the description refers to a first feature being formed on or above a second feature, it may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or designations may be repeated in various examples. This repetition is for simplification and clarity and is not intended to limit the relationship between the various embodiments and / or configurations discussed.

[0112] Furthermore, the use of spatially related terms such as "below," "under," "down," "above," "above," and similar terms is for the convenience of describing the relationship between one element or feature shown in the accompanying drawings and one or more other elements or features. These spatially related terms are used to cover different orientations of the device in use or operation, other than those depicted in the accompanying drawings. The instrument may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related terms used therein can be interpreted accordingly.

[0113] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it can be directly connected to or coupled to another component or layer, or there may be a component or layer in between.

[0114] It should be understood that although terms such as "first," "second," etc., are used herein to describe various elements, these elements are not limited by these terms. Unless otherwise stated, these terms are used only to distinguish one element from other elements. Thus, for example, a first element, first component, or first segment discussed below may be referred to as a second element, second component, or second segment without departing from the teachings of this disclosure.

[0115] Unless the context otherwise specifies, the terms used here, such as “same,” “equal to,” “plane,” or “coplanar,” when referring to orientation, layout, location, shape, size, quantity, or other measure, do not necessarily mean exactly the same orientation, layout, location, shape, size, quantity, or other measure. Rather, they mean that these orientations, layouts, locations, shapes, sizes, quantities, or other measures are substantially the same within acceptable variations, for example, variations that may arise from the manufacturing process. The term “probably” may be used here to express this meaning. For example, items described as “probably the same,” “probably equal,” or “probably plane” may be exactly the same, equal, or plane, or the same, equal, or plane within acceptable variations that may arise from the manufacturing process.

[0116] In this disclosure, a semiconductor device generally refers to a device that can operate using the characteristics of semiconductors, and optoelectronic devices, light-emitting display devices, semiconductor circuits and electronic devices all fall within the scope of semiconductor devices.

[0117] It should be noted that in the description of this disclosure, "above" corresponds to the direction of the Z-direction arrow, and "below" corresponds to the opposite direction of the Z-direction arrow.

[0118] According to one embodiment of this disclosure, Figure 1 A method for manufacturing a semiconductor device 10 is shown in flowchart form. According to an embodiment of this disclosure, Figures 2 to 10 This is a schematic cross-sectional view showing a process for manufacturing a semiconductor device. According to an embodiment of this disclosure, Figure 11 Showing a top view of the intermediate semiconductor device. Figure 12 For along Figure 11 A schematic diagram of the cross section of line A-A'.

[0119] See Figures 1 to 10 In step S11, a substrate 101 is provided, a plurality of word line structures 200 are formed in the substrate 101, a bottom dielectric layer 111 is formed on the substrate 101, a bit line contact 301 is formed on the substrate 101, an intermediate dielectric layer 113 and a top dielectric layer 115 are sequentially formed on the bottom dielectric layer 111, a bit line 303 is formed on the bit line contact 301, and a plurality of cell contact openings 401O are formed in the top dielectric layer 115, the intermediate dielectric layer 113 and the bottom dielectric layer 111 to expose the substrate 101.

[0120] See Figure 2 The substrate 101 may include a bulk semiconductor substrate. For example, the bulk semiconductor substrate may be formed of an elemental semiconductor such as silicon or germanium; it may be formed of a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, other group III-V compound semiconductors or group II-VI compound semiconductors, or combinations thereof.

[0121] See Figure 2An isolation layer 103 can be formed within the substrate 101. A series of deposition processes can be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 101. Photolithography processes and subsequent etching processes, such as anisotropic dry etching processes, can be performed to form trenches that penetrate the pad oxide and pad nitride layers and extend into the substrate 101. An insulating material can be deposited within the trenches, followed by a planarization process, such as chemical mechanical polishing, until the top surface 101TS of the substrate 101 is exposed to remove excess filler material, providing a generally flat surface for subsequent process steps, and simultaneously forming the isolation layer 103. For example, the insulating material can be silicon oxide or other suitable insulating materials. In some embodiments, the isolation layer 103 can define an active region AA within the substrate 101.

[0122] See Figure 2 An impurity region 105 can be formed within the active region AA. In some embodiments, the impurity region 105 can be formed by a planting process using P-type or N-type dopants. The impurity region 105 can serve as the source and / or drain of the semiconductor device 1A.

[0123] The term "P-type dopant" refers to impurities that, when added to an intrinsic semiconductor material, create valence electron vacancies. Examples of P-type dopants in silicon-containing semiconductors include, but are not limited to, boron, aluminum, gallium, and indium. The term "N-type dopant" refers to impurities that, when added to an intrinsic semiconductor material, contribute free electrons to the intrinsic semiconductor material. Examples of N-type dopants in silicon-containing materials include, but are not limited to, antimony, arsenic, and phosphorus.

[0124] See Figure 2 A first masking layer 811 may be formed on the substrate 101. In some embodiments, the first masking layer 811 may be a photoresist layer and may contain a pattern of multiple character line structures 200.

[0125] See Figure 3 The first masking layer 811 can be used as a mask to perform a trench etching process to remove a portion of the isolation layer 103 and a portion of the substrate 101, while simultaneously forming multiple trenches TR1 and TR2. In some embodiments, the multiple trenches TR2 formed in the substrate 101 are shallower than the multiple trenches TR1 formed in the isolation layer 103. After forming the multiple trenches TR1 and TR2, the first masking layer 811 can be removed.

[0126] See Figure 4A first insulating material 611 can be compliantly formed on the substrate 101, the insulating layer 103, and in the plurality of trenches TR1, TR2. The layer of the first insulating material 611 may have a U-shaped cross-sectional profile in the plurality of trenches TR1, TR2. In some embodiments, the layer of the first insulating material 611 may have a thickness in the range of about 1 nm to about 7 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, about 5 nm, about 6 nm, or about 7 nm.

[0127] In some embodiments, the layer of the first insulating material 611 may be formed by a thermal oxidation process. For example, the layer of the first insulating material 611 may be formed by oxidizing the surfaces of a plurality of trenches TR1, TR2. In some embodiments, the layer of the first insulating material 611 may be formed by a deposition process such as chemical vapor deposition or atomic layer deposition. The first insulating material 611 may comprise a dielectric material with a high dielectric constant, an oxide, a nitride, an oxide oxynitride, or a combination thereof. In some embodiments, after depositing an inner polysilicon liner layer (not shown), the layer of the first insulating material 611 may be formed by radical oxidation of the inner polysilicon liner layer. In some embodiments, after forming an inner silicon nitride liner layer (not shown), the layer of the first insulating material 611 may be formed by radical oxidation of the inner silicon nitride liner layer.

[0128] In some embodiments, the high dielectric constant dielectric material may comprise a hafnium-containing material. For example, the hafnium-containing material may be hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, or a combination thereof. For example, in some embodiments, the high dielectric constant dielectric material may be lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon nitride, aluminum oxide, or a combination thereof.

[0129] See Figure 4 Multiple character line bottom conductive layers 203 can be formed respectively and correspondingly in multiple trenches TR1, TR2. For example, conductive material (not shown) can be formed to fill the multiple trenches TR1, TR2. Subsequently, an etch-back process can be performed to partially remove the conductive material formed in the multiple trenches TR1, TR2, and simultaneously form multiple character line bottom conductive layers 203. In some embodiments, the conductive material can be a work function material, such as titanium, titanium nitride, silicon, silicon germanium, or a combination thereof. It should be noted that the term "work function" refers to the bulk chemical potential of a material (e.g., a metal) relative to a vacuum level. For example, in one embodiment, the conductive material is titanium nitride, and it can be formed by chemical vapor deposition.

[0130] See Figure 4Multiple word-line top conductive layers 205 can be formed within multiple trenches TR1 and TR2. For example, in some embodiments, the multiple word-line top conductive layers 205 can be formed from polysilicon, polysilicon, polysilicon-germanium, doped polysilicon, doped polysilicon-germanium, doped polysilicon-germanium, or a combination thereof. In some embodiments, the multiple word-line top conductive layers 205 can be doped with P-type or N-type dopants. In some embodiments, conductive materials, such as polysilicon, polysilicon, or polysilicon-germanium, can be deposited within multiple trenches TR1 and TR2. Subsequently, an etch-back process can be performed to remove portions of the conductive material to form the multiple word-line top conductive layers 205. In some embodiments, dopants can be added during the deposition process of the conductive material. In some embodiments, dopants can be implanted using a placement process after the etch-back process.

[0131] See Figure 4 A character line capping layer 207 can be formed to completely fill the plurality of trenches TR1, TR2. For example, in some embodiments, the character line capping layer 207 can be formed from silicon nitride, silicon oxynitride, silicon nitride oxide, or other suitable dielectric materials. For example, in some embodiments, the character line capping layer 207 can be formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0132] It should be noted that, in this disclosure, silicon oxynitride refers to a substance containing silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0133] See Figure 5 A planarization process, such as chemical mechanical polishing, can be performed until the top surface 101TS of the substrate 101 is exposed to remove excess material and provide a generally flat surface for subsequent process steps. After the planarization process, the layers of the first insulating material 611 can be converted into multiple word line dielectric layers 201 within multiple trenches TR1 and TR2, respectively and accordingly. The word line capping layer 207 can be converted into multiple segments and formed on multiple word line top conductive layers 205, respectively and accordingly. The multiple word line dielectric layers 201, multiple word line bottom conductive layers 203, multiple word line top conductive layers 205, and multiple word line capping layers 207 together constitute multiple word line structures 200. It should be noted that although the word line structures 200 within trench TR1 and the word line structures 200 within trench TR2 differ in size, their layer composition remains the same.

[0134] See Figure 6A bottom dielectric layer 111 can be formed on the substrate 101. For example, in some embodiments, the bottom dielectric layer 111 may be made of silicon oxide, undoped silicate glass, fluorosilicate glass, borosilicate glass, spin-coated low dielectric constant dielectric layer, chemical vapor deposition low dielectric constant dielectric layer, or a combination thereof. As used herein, the term "low dielectric constant" refers to a dielectric material with a dielectric constant less than that of silicon oxide. In some embodiments, the bottom dielectric layer 111 may comprise a self-planarizing material, such as spin-coated glass or spin-coated low dielectric constant dielectric material, such as SiLK. TM The use of self-planarizing dielectric materials eliminates the need for subsequent planarization steps. In some embodiments, the bottom dielectric layer 111 can be formed by deposition processes, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or spin coating.

[0135] See Figure 6 A second masking layer 813 may be formed on the bottom dielectric layer 111. In some embodiments, the second masking layer 813 may be a photoresist layer and may include a pattern of bit line contacts 301.

[0136] See Figure 7 A second masking layer 813 can be used as a mask to perform a bit line contact etching process to remove a portion of the bottom dielectric layer 111 and a portion of the impurity region 105, while simultaneously forming a bit line contact opening 301O. The bit line contact opening 301O can extend into the impurity region 105 and can be located between the word line structures 200 in the trench TR2. After forming the bit line contact opening 301O, the second masking layer 813 can be removed.

[0137] See Figure 8 The bit line contact 301 can be formed within the bit line contact opening 301O by depositing a conductive material and performing a planarization process such as chemical mechanical polishing. For example, in some embodiments, the conductive material may be tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, or magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. The bit line contact 301 may be electrically connected to the impurity region 105.

[0138] See Figure 9An intermediate dielectric layer 113 may be formed on the bottom dielectric layer 111. In some embodiments, the intermediate dielectric layer 113 may be formed of the same material as the bottom dielectric layer 111, but is not limited thereto. In some embodiments, bit lines 303 may be formed within the intermediate dielectric layer 113 and may be formed on bit line contacts 301. Bit lines 303 may be electrically coupled to impurity regions 105 via bit line contacts 301. For example, in some embodiments, bit lines 303 may be formed of tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, or magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0139] See Figure 9 A top dielectric layer 115 may be formed on the intermediate dielectric layer 113. In some embodiments, the top dielectric layer 115 may be formed of the same material as the bottom dielectric layer 111, but is not limited thereto. A third masking layer 815 may be formed on the top dielectric layer 115. In some embodiments, the third masking layer 815 may be a photoresist layer and may contain a pattern of multiple unit contact openings 401O.

[0140] See Figure 10 A third masking layer 815 can be used as a mask to perform a cell contact etching process to remove portions of the top dielectric layer 115, the intermediate dielectric layer 113, and the bottom dielectric layer 111. After performing the cell contact etching process, multiple cell contact openings 401O can be formed through the top dielectric layer 115, the intermediate dielectric layer 113, and the bottom dielectric layer 111.

[0141] For the sake of brevity, clarity, and ease of description, only one unit contact opening 401O will be described.

[0142] See Figure 11 and Figure 12 The third mask layer 815 is removed by an ashing process or other suitable semiconductor process. A portion of the impurity region 105 and a portion of the isolation layer 103 are exposed through the cell contact opening 401O. In some embodiments, the cell contact opening 401O may have a square cross-sectional profile in a top view. In some embodiments, the cell contact opening 401O may have a rectangular cross-sectional profile (not shown).

[0143] According to one embodiment of this disclosure, Figure 13 Showing a top view of the intermediate semiconductor device. Figure 14 For along Figure 13 A schematic cross-sectional view of line A-A'. According to an embodiment of this disclosure, Figure 15 This shows a top view schematic diagram of an intermediate semiconductor device. According to an embodiment of this disclosure... Figure 16 and Figure 17 For along Figure 15A schematic cross-sectional view along line A-A' shows the manufacturing process of a semiconductor device. According to an embodiment of this disclosure, Figure 18 Showing a top view of the intermediate semiconductor device. Figure 19 For along Figure 18 A schematic diagram of the cross section of line A-A'.

[0144] See Figure 1 and Figures 13 to 19 In step S13, a first sacrificial layer 711 and a second sacrificial layer 713 are sequentially formed to partially fill multiple unit contact openings 401O, and multiple first intermediate openings 711O and multiple second intermediate openings 713O that expose the impurity region 105 are sequentially formed.

[0145] An opening adjustment process can be implemented to adjust the exposed portion within the cell contact opening 401O. In some embodiments, the opening adjustment process may include a deposition operation followed by an etching operation. The deposition operation and the subsequent etching operation can be referred to as a cycle. Multiple cycles may be performed during the opening adjustment process. During the deposition operation, a sacrificial material may be deposited to completely fill the cell contact opening 401O. The subsequent etching operation may remove a portion of the sacrificial material, leaving an intermediate opening inside the cell contact opening 401O. This effectively reduces the size of the exposed portion of the cell contact opening 401O, such that the cell contact opening 401O is only partially filled. For a visual representation of this process, please refer to [link to relevant documentation]. Figures 13 to 19 The example shown is an opening adjustment process that includes two cycles.

[0146] See Figure 13 and Figure 14 During the deposition operation of the first cycle of the aperture adjustment process, a first sacrificial layer 711 may be deposited to completely fill the cell contact opening 401O. The first sacrificial layer 711 may be formed of a sacrificial material. For example, in some embodiments, the first sacrificial layer 711 may be formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. A planarization process may be performed until the top surface of the top dielectric layer 115 is exposed to provide a generally flat surface for subsequent semiconductor processes. In some embodiments, the planarization process is optional.

[0147] In some embodiments, the sacrificial material may be a material that exhibits etch selectivity towards the top dielectric layer 115 and the impurity region 105 (or the substrate 101). For example, in some embodiments, the sacrificial material may be formed from silicon nitride, boron nitride, silicon boron nitride, phosphorus boron nitride, boron carbide silicon nitride, or a combination thereof. For example, in some embodiments, the sacrificial material may be formed from boron nitride, silicon boron nitride, phosphorus boron nitride, boron carbide silicon nitride, or a combination thereof.

[0148] See Figure 15 andFigure 16 During the etching operation of the first cycle of the opening adjustment process, an etching process may be performed to remove a portion of the first sacrificial layer 711, forming the first intermediate opening 711O. The remaining first sacrificial layer 711 is primarily attached to the sidewalls of the cell contact opening 401O. At this stage, the exposed portion of the cell contact opening 401O may still contain the isolation layer 103 and the impurity region 105. In some embodiments, the first intermediate opening 711O may have a circular cross-sectional profile in a top view, but is not limited thereto. In some embodiments, the first intermediate opening 711O may have a diameter (or size) D1.

[0149] See Figure 17 During the deposition operation of the second cycle of the opening adjustment process, additional sacrificial material can be compliantly deposited on the top dielectric layer 115 to transform the first sacrificial layer 711 into the second sacrificial layer 713. At this stage, the substrate of the first intermediate opening 711O can be filled, and the sidewalls and bottom of the cell contact opening 401O can be completely covered.

[0150] See Figure 18 and Figure 19 During the etching operation of the second cycle of the opening adjustment process, an etching process may be performed to remove a portion of the second sacrificial layer 713, thereby forming the second intermediate opening 713O. The remaining second sacrificial layer 713 is primarily attached to the sidewalls of the cell contact opening 401O. The remaining second sacrificial layer 713 may be thicker than the remaining first sacrificial layer 711. At this stage, the exposed portion of the cell contact opening 401O may contain only the impurity region 105. In some embodiments, the second intermediate opening 713O may have a circular cross-sectional profile in a top view, but is not limited thereto. In some embodiments, the second intermediate opening 713O may have a diameter (or size) D2. The diameter D2 of the second intermediate opening 713O may be smaller than the diameter D1 of the first intermediate opening 711O.

[0151] Alternatively, in some embodiments, after the second intermediate opening 713O (not shown) is formed, the exposed portion of the cell contact opening 401O may include both the impurity region 105 and the isolation layer 103. However, after the second intermediate opening 713O is formed, the area of ​​the exposed portion within the cell contact opening 401O may be smaller than the area of ​​the exposed portion within the cell contact opening 401O after the first intermediate opening 711O is formed.

[0152] In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed until the top surface of the top dielectric layer 115 is exposed to remove excess material and provide a generally flat surface for subsequent process steps. In some embodiments, the planarization process is optional.

[0153] In some embodiments, additional cycles of the aperture adjustment process may be performed until the desired intermediate aperture diameter (or size) is achieved. In other embodiments, the aperture adjustment process achieves the desired intermediate aperture diameter in only one cycle.

[0154] According to one embodiment of this disclosure, Figure 20 Showing a top view of the intermediate semiconductor device. Figure 21 For along Figure 20 A schematic cross-sectional view of line A-A'. According to an embodiment of this disclosure, Figure 22 This shows a top view schematic diagram of an intermediate semiconductor device. According to an embodiment of this disclosure... Figures 23 to 26 For along Figure 22 A cross-sectional view of line A-A' shows the manufacturing process for a semiconductor device. Figure 27 For along Figure 26 A schematic diagram of the cross sections along lines B-B' and C-C'.

[0155] See Figure 1 and Figures 20 to 27 In step S15, a plurality of barrier layers 817 are formed within the plurality of second intermediate openings 713O, the second sacrificial layer 713 is removed, the plurality of unit contact openings 401O are deepened to form a plurality of extended unit contact openings 403E, the plurality of barrier layers 817 are removed, and a plurality of contact structures 400 are formed within the plurality of extended unit contact openings 403E.

[0156] For the sake of brevity, clarity, and ease of description, only one barrier layer 817 will be described.

[0157] See Figure 20 and Figure 21 The barrier layer 817 can completely fill the second intermediate opening 713O. In some embodiments, the top surfaces of the second sacrificial layer 713 and the barrier layer 817, as well as the top surface of the top dielectric layer 115, are substantially coplanar. In some embodiments, the barrier layer 817 can be formed of a material that is etch-selective to the second sacrificial layer 713 and the top dielectric layer 115. In some embodiments, the barrier layer 817 can be a photoresist layer.

[0158] Alternatively, in some embodiments, the top surface of the barrier layer 817 may be lower than the top surface of the second sacrificial layer 713 or the top surface of the top dielectric layer 115 (not shown).

[0159] See Figure 22 and Figure 23The second sacrificial layer 713 can be removed. In some embodiments, the removal of the second sacrificial layer 713 can be achieved by an etching process such as a wet etching process. In some embodiments, during the wet etching process, the ratio of the etching rate of the second sacrificial layer 713 to the etching rate of the barrier layer 817 can be between about 100:1 and about 2:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, during the wet etching process, the ratio of the etching rate of the second sacrificial layer 713 to the etching rate of the top dielectric layer 115 can be between about 100:1 and about 2:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1.

[0160] See Figure 24 An etching process, such as an anisotropic dry etching process, can be used to deepen the cell contact opening 401O toward the substrate 101. The anisotropic dry etching process can employ a barrier layer 817 as a mask. After performing the anisotropic dry etching process, the cell contact opening 401O can be extended to form an extended cell contact opening 403E. The lower section of the extended cell contact opening 403E can surround the protrusion 101P of the impurity region 105, which is shielded by the barrier layer 817.

[0161] See Figure 25 The barrier layer 817 can be removed, for example, using an ashing or etching process. In some embodiments, the top surface 101PT of the protrusion 101P and the top surface 101TS of the substrate 101 may be substantially coplanar. In some embodiments, since the protrusion 101P is consumed during the removal of the barrier layer 817, the top surface 101PT of the protrusion 101P may be slightly lower than the top surface 101TS (not shown) of the substrate 101.

[0162] See Figure 26 and Figure 27 Conductive material can be deposited to completely fill the extended cell contact opening 403E. A planarization process, such as chemical mechanical polishing, can be performed until the top surface of the top dielectric layer 115 is exposed to remove excess material, providing a generally flat surface for subsequent process steps and simultaneously forming multiple contact structures 400. For example, in some embodiments, the conductive material may be tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, or tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0163] For the sake of brevity, clarity, and ease of description, only one contact structure 400 will be described.

[0164] In some embodiments, the contact structure 400 may include a body portion 401 and an extension portion 403. The extension portion 403 may be disposed within the lower section of the extended unit contact opening 403E and surround the protrusion 101P of the impurity region 105. In some embodiments, the top surface 403TS of the extension portion 403, the top surface 101PT of the protrusion 101P, and the top surface 101TS of the base 101 may be substantially coplanar. In some embodiments, the bottom surface 403BS of the extension portion 403 may be substantially flat. In some embodiments, the extension portion 403 may have a square annular cross-sectional profile when viewed from above.

[0165] The body portion 401 may be formed on the extension portion 403 and the protrusion portion 101P. In some embodiments, the body portion 401 may have a square cross-sectional profile in a top view. In some embodiments, the body portion 401 may have a rectangular cross-sectional profile (not shown) in a top view. In some embodiments, the ratio of the height H1 of the extension portion 403 to the height H2 of the contact structure 400 may be between about 0.05 and about 0.30, between about 0.1 and about 0.30, or between about 0.15 and about 0.20.

[0166] The extension 403 may extend from the body portion 401 toward the base 101. The groove 403R may be recessed into the bottom surface 403BS of the extension 403 and recessed toward the body portion 401. The groove 403R may accommodate the protrusion 101P, and the protrusion 101P directly contacts the body portion 401. In some embodiments, in a top view, the center point CP1 of the body portion 401 (shown as a crosshair) may be aligned with the center point CP2 of the groove (shown as a crosshair). The center point CP2 of the groove may be referred to as the center point CP2 of the protrusion 101P.

[0167] In the description of this disclosure, an xyz coordinate system is used, where x and y represent directions in a plane parallel to the main surface of the structure, and z represents a direction perpendicular to that plane; when one feature is aligned with another feature, these features have substantially the same (x,y) coordinates.

[0168] The contact area of ​​the contact structure 400 can be increased by using the extension portion 403. This improves the performance of the semiconductor device 1A.

[0169] According to another embodiment of this disclosure, Figure 28 This is a cross-sectional schematic diagram showing the main body 401 and extension 403 of the semiconductor device 1B.

[0170] See Figure 28 Semiconductor device 1B may have the same characteristics as... Figure 27 The structures shown are similar. Figure 28 Zhongyu Figure 27Identical or similar elements are marked with similar reference symbols, and repeated descriptions are omitted.

[0171] In semiconductor device 1B, the main body 401 may have a circular cross-sectional profile when viewed from above. The extension 403 may have an annular cross-sectional profile when viewed from above.

[0172] According to another embodiment of this disclosure, Figure 29 This is a cross-sectional schematic diagram of the main body 401 and the extension 403 of the semiconductor device 1C.

[0173] See Figure 29 Semiconductor device 1C may have the same characteristics as... Figure 27 The structures shown are similar. Figure 29 Zhongyu Figure 27 Identical or similar elements are marked with similar reference symbols, and repeated descriptions are omitted.

[0174] In some embodiments, from a top view of the semiconductor device 1C, the center point CP1 of the body portion 401 is not aligned with the center point CP2 of the trench (or the center point CP2 of the protrusion 101P).

[0175] According to another embodiment of this disclosure, Figure 30 A cross-sectional schematic diagram of the semiconductor device 1D is shown.

[0176] See Figure 30 Semiconductor device 1D may have the same characteristics as Figure 27 The structures shown are similar. Figure 30 Zhongyu Figure 27 Identical or similar elements are marked with similar reference symbols, and repeated descriptions are omitted.

[0177] In the semiconductor device 1D, the bottom surface 403BS of the extension 403 is inclined relative to the top surface 101TS of the substrate 101. In some embodiments, the bottom surface 403BS near the word line structure 200 disposed in the trench TR2 may be higher than the bottom surface 403BS near the word line structure 200 disposed in the trench TR1.

[0178] According to various embodiments of this disclosure Figure 31 A cross-sectional schematic diagram of semiconductor device 1E is shown. Figure 31 The semiconductor device 1E in the middle may have the same characteristics as... Figure 26 The structures shown are similar. Figure 31 Zhongyu Figure 26 Identical or similar elements are marked with similar reference symbols, and repeated descriptions are omitted.

[0179] See Figure 31The semiconductor device 1E may include a plurality of first word line structures 200 and a plurality of second word line structures 200' within a substrate 101, wherein the plurality of first word line structures 200 are disposed within a plurality of first trenches TR1 in an isolation layer 103, and the plurality of second word line structures 200' are disposed within a plurality of second trenches TR2 in an impurity region 105 defined by the isolation layer 103. The first word line structure 200 includes a first word line dielectric layer 201, a first word line bottom conductive layer 203, a first word line top conductive layer 205, and a first word line capping layer 207, and... Figure 26 The character line structure 200 within the middle trench TR1 is identical. The second character line structure 200' includes a second character line dielectric layer 201', a second character line bottom conductive layer 203', a second character line top conductive layer 205', and a second character line capping layer 207'. The second character line bottom conductive layer 203' and the second character line top conductive layer 205' of the second character line structure 200' are respectively identical to... Figure 26 The word line bottom conductive layer 203 and word line top conductive layer 205 of the word line structure 200 within the middle trench TR2. (And...) Figure 26 Compared to the word line dielectric layer 201 and the word line capping layer 207 in the middle trench TR2, the second word line dielectric layer 201' includes two inclined top surfaces T1 and T2 that are opposite to each other, and the second word line capping layer 207' includes two conical sidewalls S1 and S2 that are opposite to each other.

[0180] In addition, see Figure 31The semiconductor device 1E also includes a plurality of impurity regions 107B, 107C disposed within a substrate 101. Each of the plurality of impurity regions 107B, 107C may include an upper portion 107B-1 / 107C-1 disposed within a top surface 101TS of the substrate 101, and a lower portion 107B-2 / 107C-2 disposed below the upper portion 107B-1 / 107C-1. In some embodiments, the top surface 107TS of the upper portions 107B-1, 107C-1 is substantially coplanar with the top surface 101TS of the substrate 101. The upper portions 107B-1, 107C-1 may be separated by a plurality of second character line structures 200', while the lower portions 107B-2, 107C-2 may be connected to each other, wherein the lower portions 107B-2, 107C-2 are the remaining portions after an etching process is performed on the impurity regions 105. The upper portion 107B-1 / 107C-1 may have two opposing conical sidewalls 107S1 and 107S2. The horizontal distance between the two conical sidewalls 107S1 and 107S2 may gradually decrease along the Z direction from the top surface 107TS of the upper portion 107B-1 and 107C-1 to the bottom surface 107BS of the upper portion 107B-1 and 107C-1. The angle α between either of the conical sidewalls S1 / S2 and the principal plane (i.e., the XY plane) of the base 101 may be between approximately 45 degrees and approximately 60 degrees. In some embodiments, the top surface 107TS of the upper portion 107B-1 and 107C-1 is substantially parallel to the principal plane (i.e., the XY plane) of the base 101. In some embodiments, the top surface 205'TS of the second character line top conductive layer 205' of the second character line structure 200' is lower than the top surface 107TS of the upper 107B-1, 107C-1, and the upper 107B-1 / 107C-1 of the impurity region 107B / 107C has a tapered profile.

[0181] According to various embodiments of this disclosure Figures 32 to 33 This is a cross-sectional schematic diagram showing the process of manufacturing semiconductor device 1E.

[0182] See Figure 32 , can be Figure 5 The intermediate structure shown in the image undergoes an etching process to remove a portion of the impurity region 105 in the substrate 101, and to remove a portion of the word line dielectric layer 201 and a portion of the word line capping layer 207 in the trench TR2. As a result, multiple recesses 901 and multiple first word line structures 200 (i.e., ...) are formed within the substrate 101. Figure 5The recess 901 includes a character line structure 200 within the trench TR1, multiple second character line structures 200' within the trench TR2, and the lower portions 107B-2 and 107C-2 of multiple impurity regions 107B and 107C (i.e., the remaining portions of impurity regions 105 after the etching process). The recess 901 may have two opposing tapered sidewalls 901S1 and 901S2. The recess 901 may have a bottom surface 901BS, the vertical position of which is defined by the intersection point 901P of the tapered sidewalls 901S1 / 901S2 and the outer surface of the trench TR2. The horizontal distance between the two tapered sidewalls 901S1 and 901S2 may gradually decrease along the Z-direction from the top surface 101TS of the substrate 101 to the bottom surface 901BS of the recess 901. The angle α between either of the tapered sidewalls 901S1 / 901S2 and the principal plane (i.e., the XY plane) of the substrate 101 can be between approximately 45 degrees and approximately 60 degrees. In some embodiments, the etching process can be an isotropic plasma dry etching process. In some embodiments, the etching process can be a wet etching process. In some embodiments, the top surface 101TS of the substrate 101 is substantially parallel to the principal plane (i.e., the XY plane) of the substrate 101.

[0183] See Figure 33 An epitaxial growth process can be performed to fill multiple recesses 901 and simultaneously form the upper portions 107B-1 and 107C-1 of multiple impurity regions 107B and 107C. The epitaxial growth process can be chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy. In some embodiments, a planarization process such as chemical mechanical polishing can be selectively performed to provide a generally flat surface for subsequent process steps.

[0184] The shape (or structure) of the upper portions 107B-1 and 107C-1 of the plurality of impurity regions 107B and 107C can be determined by the plurality of recesses 901. The upper portion 107B-1 may be located between two second character line structures 200'. In some embodiments, the upper portion 107C-1 may be respectively located on opposite sides of the upper portion 107B-1, and the two character line structures 200' are interposed between them. In other words, the upper portions 107B-1 and 107C-1 may be separated by the second character line structures 200'. In some embodiments, the upper portions 107B-1 and 107C-1 may have a top surface 107TS that is substantially coplanar with the top surface 101TS of the substrate 101, and a bottom surface 107BS that is substantially coplanar with the bottom surface 901BS of the recess 901.

[0185] For example, in some embodiments, the upper parts 107B-1 and 107C-1 may be made of silicon phosphide (SiP), phosphorus-doped silicon carbide (SiCP), silicon carbide (SiC), silicon germanium (SiGe), silicon germanium tin alloy (SiGeSn), silicon germanium boron alloy (SiGeB) or other suitable semiconductor materials.

[0186] In some embodiments, the upper 107B-1 / 107C-1 may be doped with a dopant such as phosphorus or boron. The dopant concentration of the upper 107B-1 / 107C-1 may be uniform. In some embodiments, the dopant concentration of the upper 107B-1 / 107C-1 may gradually increase from the bottom surface 107BS to the top surface 107TS. In some embodiments, the dopant concentration of the upper 107B-1 and 107C-1 may be greater than the dopant concentration of the lower 107B-2 and 107C-2.

[0187] The top surface 205'TS of the second character line top conductive layer 205' of the second character line structure 200' is lower than the top surface 107TS of the upper portions 107B-1 and 107C-1 of the impurity regions 107B and 107C, and the impurity regions 107B / 107C have a tapered cross-sectional profile. In some embodiments, the vertical position of the top surface 205'TS of the second character line top conductive layer 205' may be higher than the vertical position of the bottom surface 107BS of the upper portions 107B-1 and 107C-1. In some embodiments, the top surface 205'TS of the second character line top conductive layer 205' and the bottom surface 107BS of the upper portions 107B-1 and 107C-1 may be at the same vertical position.

[0188] One aspect of this disclosure provides a semiconductor device including a substrate; a word line structure including a word line electrode; an impurity region including an upper portion adjacent to the word line structure and a lower portion below the upper portion; and a contact structure including a body portion on the impurity region and an extension portion below the body portion. A top surface of the word line electrode of the word line structure is lower than a top surface of the upper portion of the impurity region, and the upper portion of the impurity region has a tapered cross-sectional profile.

[0189] Another aspect of this disclosure provides a semiconductor device including a substrate having an isolation layer disposed therein; a plurality of impurity regions disposed within an active region defined by the isolation layer; a plurality of first word line structures disposed within the isolation layer; and a plurality of second word line structures disposed within the active region.

[0190] Another aspect of this disclosure provides a semiconductor device including a substrate; a word line structure disposed within the substrate; an impurity region including an upper portion adjacent to the word line structure and a lower portion disposed below the upper portion; a bit line contact disposed within the substrate and protruding from the substrate; and a bit line disposed on the bit line contact. The word line structure includes a word line dielectric layer contacting the lower portion of the impurity region, a word line electrode disposed on the word line dielectric layer, and a word line capping layer disposed on the word line electrode. A top surface of the word line electrode of the word line structure is lower than a top surface of the upper portion of the impurity region. The upper portion of the impurity region has a tapered cross-sectional profile.

[0191] Due to the design of the semiconductor device disclosed herein, the extension can increase the contact area between the contact structure and the impurity region. Therefore, the performance of the semiconductor device 1A can be improved.

[0192] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0193] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this document that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor device, comprising: a substrate; a word line structure including a word line electrode; a dopant region including an upper portion adjacent to the word line structure and a lower portion below the upper portion; and a contact structure including a body portion on the dopant region and an extension portion below the body portion, wherein a top surface of the word line electrode of the word line structure is lower than a top surface of the upper portion of the dopant region, and the upper portion of the dopant region has a tapered profile.

2. The semiconductor device of claim 1, wherein the top surface of the upper portion is substantially coplanar with a top surface of the substrate.

3. The semiconductor device of claim 2, wherein the dopant region includes two tapered sidewalls connected to the top surface of the upper portion of the dopant region.

4. The semiconductor device of claim 3, wherein an angle between one of the two tapered sidewalls and the top surface of the upper portion of the dopant region is between about 45 degrees and about 60 degrees.

5. The semiconductor device of claim 1, wherein a dopant concentration of the upper portion is greater than a dopant concentration of the lower portion.

6. The semiconductor device of claim 5, wherein the dopant concentration of the upper portion increases gradually from a bottom surface of the upper portion to a top surface of the upper portion.

7. The semiconductor device of claim 1, wherein the word line structure further includes a word line dielectric layer contacting the lower portion of the dopant region, and a word line cap layer disposed on the word line electrode.

8. The semiconductor device of claim 7, wherein the word line dielectric layer includes two inclined top surfaces opposite to each other.

9. The semiconductor device of claim 7, wherein the word line cap layer includes two tapered sidewalls opposite to each other.

10. The semiconductor device of claim 7, wherein the word line electrode is disposed on the word line dielectric layer surrounded by the word line dielectric layer.

11. The semiconductor device of claim 10, wherein the word line electrode includes a word line top conductive layer, and a word line bottom conductive layer below the word line top conductive layer.

12. The semiconductor device of claim 1, wherein the extension portion of the contact structure extends from the body portion, and the extension portion of the contact structure includes a trench recessed into a bottom surface of the extension portion, the trench recessed toward the body portion and exposing the body portion.

13. The semiconductor device of claim 1, wherein a ratio between a height of the extension portion and a height of the contact structure is between about 0.05 and about 0.

3.

14. The semiconductor device of claim 12, wherein the body portion has a square profile in a top view.

15. The semiconductor device of claim 12, wherein the extension portion has a ring profile in a top view. ​

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