Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes: active patterns arranged in a first direction and a second direction to form rows and columns, the active patterns including first vertical semiconductor patterns and second vertical semiconductor patterns spaced apart from each other; a bit line extending in a second direction and connected to a lower surface of the first vertical semiconductor pattern and a lower surface of the second vertical semiconductor pattern of the active pattern of each of the columns; a word line extending in the first direction and between the first vertical semiconductor pattern and the second vertical semiconductor pattern of the active pattern of each of the rows; a word line insulating pattern between the word line and the active pattern, the word line insulating pattern not covering an upper surface of the word line; back gate lines extending in the first direction and between adjacent rows; and a back gate insulating pattern extending in the first direction between the back gate line and the active pattern.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0121859 filed on September 6, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The present application relates to a semiconductor memory device and a method of manufacturing a semiconductor memory device. BACKGROUND

[0003] A semiconductor device can be a key component for controlling or amplifying an electrical signal in an electronic device. Various types of semiconductor devices are being developed to perform various functions of an electronic device. As the design rule of a semiconductor device changes, the manufacturing technology of a semiconductor device is developing in the direction of improving integration, operating speed, and yield. Accordingly, a vertical channel transistor has been proposed to increase the integration of transistors in a semiconductor device. SUMMARY

[0004] The present application relates to a semiconductor memory device and a method of manufacturing a semiconductor memory device that provide improved integration and electrical characteristics.

[0005] A semiconductor memory device according to some example embodiments of the present application can include: active patterns arranged in a first direction and a second direction intersecting the first direction to form rows and columns, each of the active patterns including a first vertical semiconductor pattern and a second vertical semiconductor pattern, the first vertical semiconductor pattern and the second vertical semiconductor pattern spaced apart from each other and extending in a third direction perpendicular to the first direction and the second direction; bit lines arranged in the first direction, each extending in the second direction, and connected to lower surfaces of the first vertical semiconductor patterns and the second vertical semiconductor patterns of the active patterns of each of the columns; word lines arranged in the second direction, each extending in the first direction, and between the first vertical semiconductor patterns and the second vertical semiconductor patterns of the active patterns of each of the rows; word line insulating patterns each between each of the word lines and the active patterns of each of the rows, the word line insulating patterns not covering upper surfaces of the word lines; back gate lines arranged in the second direction, each extending in the first direction, and between adjacent rows; and back gate insulating patterns each between each of the back gate lines and the active patterns and extending in the first direction.

[0006] A semiconductor memory device according to some example embodiments of the present application can include: an active pattern arranged in a first direction and a second direction intersecting the first direction to form rows and columns, each of the active pattern including a first vertical semiconductor pattern, a second vertical semiconductor pattern, and a connection portion, the first vertical semiconductor pattern and the second vertical semiconductor pattern spaced apart from each other and extending in a third direction perpendicular to the first direction and the second direction, the connection portion between and integrally connected to upper end portions of the first vertical semiconductor pattern and the second vertical semiconductor pattern; bit lines arranged in the first direction, each extending in the second direction, and connected to lower surfaces of the first vertical semiconductor pattern and the second vertical semiconductor pattern of the active pattern of each of the columns; word lines arranged in the second direction, each extending in the first direction, and between the first vertical semiconductor pattern and the second vertical semiconductor pattern of the active pattern of each of the rows; word line insulating patterns each between each of the word lines and the active pattern of each of the rows; back gate lines arranged in the second direction, each extending in the first direction, and between adjacent rows; and back gate insulating patterns each between each of the back gate lines and the active pattern and extending in the first direction.

[0007] Each of the first vertical semiconductor pattern and the second vertical semiconductor pattern can include a channel region, a first source / drain region, and a second source / drain region, the first source / drain region can be in the upper end portion of each of the first vertical semiconductor pattern and the second vertical semiconductor pattern, the second source / drain region can be in a lower end portion of each of the first vertical semiconductor pattern and the second vertical semiconductor pattern, and the channel region can be between the first source / drain region and the second source / drain region.

[0008] The semiconductor memory device can further include: a data storage pattern on and electrically connected to upper surfaces of the first vertical semiconductor pattern and the second vertical semiconductor pattern of each of the active patterns.

[0009] The data storage pattern can be a capacitor.

[0010] The semiconductor memory device can further include: word line cover patterns each covering each of upper surfaces of the word lines and extending in the first direction, wherein the upper surfaces of the word line cover patterns can be coplanar or substantially coplanar with the upper surfaces of the first vertical semiconductor pattern and the second vertical semiconductor pattern.

[0011] The word line insulating patterns can include different materials from the word line cover patterns.

[0012] The semiconductor memory device can further include: back gate cover patterns each covering each of upper surfaces of the back gate lines and extending in the first direction.

[0013] The first vertical semiconductor pattern and the second vertical semiconductor pattern can be in a single-crystal state.

[0014] A semiconductor memory device according to some example embodiments of the present application can include: active patterns arranged in a first direction and a second direction intersecting the first direction to form rows and columns, each of the active patterns including a first vertical semiconductor pattern, a second vertical semiconductor pattern, and a connection portion, the first vertical semiconductor pattern and the second vertical semiconductor pattern spaced apart from each other and extending in a third direction perpendicular to the first direction and the second direction, the connection portion between and integrally connected to upper end portions of the first vertical semiconductor pattern and the second vertical semiconductor pattern; bit lines arranged in the first direction, each extending in the second direction, and connected to lower surfaces of the first vertical semiconductor pattern and the second vertical semiconductor pattern of the active pattern of each of the columns; word lines arranged in the second direction, each extending in the first direction, and between the first vertical semiconductor pattern and the second vertical semiconductor pattern of the active pattern of each of the rows; word line insulating patterns each between each of the word lines and the active pattern of each of the rows; back gate lines arranged in the second direction, each extending in the first direction, and between adjacent rows; and back gate insulating patterns each between each of the back gate lines and the active pattern and extending in the first direction.

[0015] The first vertical semiconductor pattern and the second vertical semiconductor pattern can include a channel region, a first source / drain region, and a second source / drain region, the first source / drain region can be in the upper end portion of the first vertical semiconductor pattern, the upper end portion of the second vertical semiconductor pattern, and the connection portion, the second source / drain region can each be in each of a lower portion of the first vertical semiconductor pattern and a lower portion of the second vertical semiconductor pattern, and the channel region can be defined between the first source / drain region and the second source / drain region.

[0016] The semiconductor memory device can further include: word line cover patterns each covering each of upper surfaces of the word lines and extending in the first direction, wherein the upper surfaces of the word line cover patterns can be coplanar or substantially coplanar with lower surfaces of the connection portions.

[0017] The semiconductor memory device can further include: back gate cover patterns each covering each of upper surfaces of the back gate lines and extending in the first direction.

[0018] A method of manufacturing a semiconductor memory device according to some example embodiments of the present application can include forming first trenches extending in a first direction within a substrate to define a preliminary active line, and forming back gate lines each filling each of the first trenches; forming second trenches crossing the first trenches and the preliminary active line within the substrate to form a preliminary active pattern, the preliminary active pattern being arranged in the first direction and a second direction intersecting the first direction to form rows and columns; patterning the preliminary active pattern to form third trenches extending in the first direction and active patterns each including first and second vertical semiconductor patterns spaced apart from each other, and each of the third trenches being formed between the first and second vertical semiconductor patterns of the active pattern of each of the rows; forming word line insulating films on the substrate having the third trenches and the active patterns; and forming word lines each filling each of the third trenches on the word line insulating films.

[0019] The method can further include, before the step of forming the third trenches, forming isolation insulating patterns within the second trenches, wherein the step of patterning the preliminary active pattern can include patterning the preliminary active pattern and the isolation insulating patterns to form the third trenches and the active patterns, and each of the third trenches can be formed between the first and second vertical semiconductor patterns of the active pattern of each of the rows and within the isolation insulating pattern of each of the rows.

[0020] The method can further include, before the step of forming the word lines, forming word line cover patterns covering upper surfaces of the word lines.

[0021] The method can further include, after the step of forming the word lines, grinding a lower surface of the substrate until lower surfaces of the first and second vertical semiconductor patterns are exposed; and forming bit lines on the lower surfaces of the first and second vertical semiconductor patterns.

[0022] The method can further include, after the step of forming the bit lines, forming data storage patterns on upper surfaces of the first and second vertical semiconductor patterns of each of the active patterns.

[0023] The data storage patterns can be capacitors.

[0024] A height of a bottom surface of the third trenches can be lower than a height of the lower surface of the first vertical semiconductor pattern and a height of the lower surface of the second vertical semiconductor pattern.

[0025] The height of the bottom surface of the third trench may be higher than the height of the lower surface of the first vertical semiconductor pattern and the lower surface of the second vertical semiconductor pattern, and each of the active patterns may also include a connecting portion that is integrally connected between the upper ends of the first vertical semiconductor pattern and the second vertical semiconductor pattern. Attached Figure Description

[0026] Figure 1 This is a perspective view illustrating a semiconductor memory device according to some example embodiments of the present application.

[0027] Figure 2 This is a plan view illustrating a semiconductor memory device according to some example embodiments of this application.

[0028] Figure 3 It is along Figure 2 A sectional view taken by line A-A'.

[0029] Figure 4 It is along Figure 2 The sectional view taken by line B-B'.

[0030] Figure 5 and Figure 6 Semiconductor memory devices according to some example embodiments of this application are shown. Figure 5 and Figure 6 Is it separate from Figure 2 The sectional views corresponding to lines A-A' and B-B'.

[0031] Figure 7 Semiconductor memory devices according to some example embodiments of this application are shown. Figure 7 Is with Figure 2 The sectional view corresponding to line A-A'.

[0032] Figure 8A , Figure 9A , Figure 10A to Figure 22A This is a plan view illustrating a method of manufacturing a semiconductor memory device according to some example embodiments of this application.

[0033] Figure 8B , Figure 9B , Figure 10B to Figure 22B They are respectively along Figure 8A to Figure 22A A sectional view taken from lines A-A' and B-B'.

[0034] Figure 23A , Figure 24A to Figure 28A This is a plan view illustrating a method of manufacturing a semiconductor memory device according to some example embodiments of this application.

[0035] Figure 23B , Figure 24B to Figure 28B They are respectively alongFigure 23A to Figure 28A A sectional view taken from lines A-A' and B-B'. Detailed Implementation

[0036] In the following description, some exemplary embodiments of this application will be described in more detail with reference to the accompanying drawings.

[0037] The semiconductor memory device according to some example embodiments of this application can be a memory device based on semiconductor elements. For example, the semiconductor memory device can be volatile memory (such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), low power double data rate SDRAM (LPDDR SDRAM), graphics double data rate SDRAM (GDDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, or thyristor random access memory (TRAM)) or non-volatile memory (such as phase change random access memory (PRAM), magnetic random access memory (MRAM), or resistive random access memory (RRAM)).

[0038] Semiconductor memory devices according to some example embodiments of this application may include memory cells comprising vertical channel transistors (VCTs). A vertical channel transistor can refer to a transistor in which a semiconductor pattern extends in a direction perpendicular to the upper surface of a semiconductor substrate.

[0039] Figure 1 This is a perspective view illustrating a semiconductor memory device according to some example embodiments of the present application. Figure 2 This is a plan view illustrating a semiconductor memory device according to some example embodiments of this application. Figure 3 It is along Figure 2 A sectional view taken by line A-A'. Figure 4 It is along Figure 2 The sectional view taken by line B-B'.

[0040] Reference Figure 1 to Figure 4 The semiconductor memory device according to some example embodiments of this application may include an active pattern 110, a bit line 210, a word line 130, a word line insulating pattern 131, a back gate line 150, a back gate insulating pattern 151, and a data storage pattern DSP.

[0041] Active patterns 110 may be configured. Active patterns 110 may be used as vertical channel transistors (VCTs) in semiconductor memory devices according to some example embodiments of this application. In some example embodiments, the semiconductor memory device may include a plurality of active patterns 110. Active patterns 110 may be arranged on a first direction D1 and a second direction D2 intersecting the first direction D1 to form rows and columns in a planar view.

[0042] The active pattern 110 may include a first vertical semiconductor pattern 111 and a second vertical semiconductor pattern 113. The first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 may extend in a third direction D3 perpendicular to the first direction D1 and the second direction D2. In some example embodiments, each of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 may have a rectangular shape in a planar view, but is not limited thereto. Each of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 may have, for example, a quadrilateral shape with rounded corners in a planar view.

[0043] The first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 may each include a first source / drain region SD1, a second source / drain region SD2, and a channel region CH. The first source / drain region SD1 may be formed in the upper end of each of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113, and the second source / drain region SD2 may be formed in the lower end of each of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113. Here, the upper end may be the end of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 in the third direction D3, and the lower end may be the end of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 in the opposite direction of the third direction D3.

[0044] In some example embodiments, a first source / drain region SD1 may be connected to a landing pad (or landing pad) LP, and a second source / drain region SD2 may be connected to bit line 210. Each of the first source / drain region SD1 and the second source / drain region SD2 may serve as a source and / or drain to supply and / or release current-carrying carriers. Here, the carriers may be electrons or holes. The channel region CH may serve as the path through which the carriers move. For example, the first source / drain region SD1 may serve as a source, the second source / drain region SD2 may serve as a drain, and the channel region CH may serve as the path through which the carriers move between the source and the drain. The first source / drain region SD1 and the second source / drain region SD2 may be regions doped with impurities having a conductivity type different from that of the channel region CH. For example, when the channel region CH includes impurities of a first conductivity type, the first source / drain region SD1 and the second source / drain region SD2 can be regions doped with impurities of a second conductivity type opposite to the first conductivity type. For example, the first conductivity type impurity can be a p-type impurity (such as boron (B) as a group III element), and the second conductivity type impurity can include an n-type impurity (such as phosphorus (P) and / or arsenic (As) as group V elements).

[0045] Active pattern 110 may include semiconductor materials (e.g., silicon (Si), germanium (Ge), silicon-germanium (Si-Ge), etc.). Active pattern 110 may include oxide semiconductor materials. The oxide semiconductor material may be, for example, In... x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O、Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O, Al x Zn y Snz O、Yb x Ga y Zn z O、In x Ga y At least one of O and IGZO (indium gallium zinc oxide). The active pattern 110 may comprise a single layer or multiple layers of oxide semiconductor material. The active pattern 110 may comprise, but is not limited to, amorphous or crystalline (e.g., single-crystal or polycrystalline) oxide semiconductor material. In some example embodiments, the active pattern 110 may comprise a single-crystal semiconductor material. Thus, the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 may be in a single-crystal state. In some example embodiments, the active pattern 110 may have a bandgap energy larger than that of silicon. In some example embodiments, the active pattern 110 may comprise a two-dimensional semiconductor material. The two-dimensional semiconductor material may comprise, for example, graphene, MoS2, WS2, MoSe2, WSe2, or combinations thereof.

[0046] Bit lines 210 may be configured to extend in a second direction D2. In some example embodiments, a semiconductor memory device may include multiple bit lines 210, and the bit lines 210 may be arranged in a first direction D1. The bit lines 210 may be spaced apart from each other at a regular interval in the first direction D1.

[0047] Each of the bit lines 210 may be disposed on the lower surface of the first vertical semiconductor pattern 111 and the lower surface of the second vertical semiconductor pattern 113 of each of the active patterns 110. More specifically, each of the bit lines 210 may be arranged in a first direction D1, may extend in a second direction D2, and may be connected to the lower surface of the first vertical semiconductor pattern 111 and the lower surface of the second vertical semiconductor pattern 113 of each column of active patterns 110.

[0048] In some example embodiments, each of the bit lines 210 may include buried conductive patterns, contact patterns, metal patterns, and hard mask patterns sequentially stacked in the opposite direction to the third direction D3. The buried conductive patterns may include polycrystalline silicon doped with impurities. The contact patterns may include at least one of, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and two-dimensional (2D) materials. The metallic pattern may include at least one of the following: metallic materials (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co), conductive metal nitrides (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, RuTiN), conductive metal silicides, and / or conductive metal oxides (e.g., PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCo). The hard mask pattern may include an insulating material (such as silicon nitride or silicon oxynitride).

[0049] Word lines 130 may be configured to extend in a first direction D1. In some example embodiments, a semiconductor memory device may include multiple word lines 130, and the word lines 130 may be arranged in a second direction D2. The word lines 130 may be spaced apart from each other at a regular interval in the second direction D2.

[0050] Each of the word lines 130 may be disposed between the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 of each of the active patterns 110. More specifically, each of the word lines 130 may be arranged in a second direction D2, may extend in a first direction D1, and may be disposed between the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 of each row of active patterns 110.

[0051] The word line 130 may include, for example, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, polysilicon doped with impurities, or a combination thereof.

[0052] A word line insulating pattern 131 may be disposed between the word line 130 and the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113, extending in a first direction D1. The word line insulating pattern 131 may electrically isolate the word line 130 from the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113. In some example embodiments, the semiconductor memory device may include a plurality of word line insulating patterns 131, and the word line insulating patterns 131 may be arranged in a second direction D2.

[0053] Each of the word line insulating patterns 131 may be disposed between each of the word lines 130 and each of the row of active patterns 110. More specifically, each of the word line insulating patterns 131 may be disposed between each of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 included in each of the row of active patterns 110 and each of the word lines 130. In some example embodiments, the word line insulating pattern 131 may not cover the upper surface of the word lines 130.

[0054] The word line insulation pattern 131 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, or a combination thereof.

[0055] In some example embodiments, a word line overlay pattern 133 may be disposed between adjacent first vertical semiconductor patterns 111 and second vertical semiconductor patterns 113, extending in a first direction D1. The word line overlay pattern 133 may electrically isolate adjacent first vertical semiconductor patterns 111 and second vertical semiconductor patterns 113 from each other. The word line overlay pattern 133 may be disposed on word lines 130. More specifically, a plurality of word line overlay patterns 133 may be arranged in a second direction D2, and each of the word line overlay patterns 133 may cover the upper surface of each of the word lines 130 and extend in the first direction D1. Furthermore, the upper surface of the word line overlay pattern 133 may be coplanar or substantially coplanar with the upper surfaces of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113.

[0056] The word line overlay pattern 133 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, or a combination thereof.

[0057] In some example embodiments, the word line insulating pattern 131 may include a material different from that of the word line overlay pattern 133. For example, when the word line insulating pattern 131 includes silicon oxide, the word line overlay pattern 133 may include a high dielectric constant material having a higher dielectric constant compared to silicon oxide.

[0058] Back gate lines 150 may be disposed between adjacent active patterns 110 to extend in a first direction D1. In some example embodiments, the semiconductor memory device may include multiple back gate lines 150, and the back gate lines 150 may be arranged in a second direction D2. The back gate lines 150 may be spaced apart from each other at a regular pitch in the second direction D2.

[0059] Each of the back gate lines 150 may be disposed between adjacent rows of active patterns 110. More specifically, each of the back gate lines 150 may be disposed between a first vertical semiconductor pattern 111 present in a row of active patterns 110 and a second vertical semiconductor pattern 113 present in another row of active patterns 110 adjacent to that row. Thus, active patterns 110 in each row of adjacent rows may share the back gate line 150.

[0060] The back gate line 150 may include, for example, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, doped polysilicon, or a combination thereof.

[0061] In some example embodiments, a negative voltage can be applied to the back gate line 150 during operation of the semiconductor memory device, thereby increasing the threshold voltage of the vertical channel transistor. As a result, since the back gate line 150 controls the threshold voltage, the threshold voltage can be reduced as the vertical channel transistor is miniaturized, thereby preventing or reducing leakage current characteristic degradation.

[0062] A back gate insulating pattern 151 may be disposed between the back gate line 150 and an adjacent active pattern 110. The back gate insulating pattern 151 may electrically isolate the back gate line 150 from the adjacent active pattern 110. In some example embodiments, the semiconductor memory device may include a plurality of back gate insulating patterns 151, and the back gate insulating patterns 151 may be arranged in a second direction D2.

[0063] Each of the back gate insulating patterns 151 may be disposed between each of the back gate lines 150 and the active pattern 110. More specifically, each of the back gate insulating patterns 151 may extend in a first direction D1 and be disposed between a first vertical semiconductor pattern 111 present in a row of active patterns 110, a second vertical semiconductor pattern 113 present in another row of active patterns 110 adjacent to the row, and the back gate line 150 disposed between the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113. In some example embodiments, the back gate insulating pattern 151 may not cover the upper surface of the back gate line 150.

[0064] The back gate insulating pattern 151 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, or a combination thereof.

[0065] In some example embodiments, a back gate cover pattern 153 may be disposed between adjacent active patterns 110 to extend in a first direction D1. The back gate cover pattern 153 may electrically isolate adjacent active patterns 110 from each other. The back gate cover pattern 153 may be disposed on a back gate line 150. More specifically, a plurality of back gate cover patterns 153 may be arranged in a second direction D2, and each of the back gate cover patterns 153 may cover the upper surface of each of the back gate lines 150 and the upper surface of the back gate insulating pattern 151, and extend in the first direction D1. Furthermore, the upper surface of the back gate cover pattern 153 may be coplanar or substantially coplanar with the upper surface of the first vertical semiconductor pattern 111 and the upper surface of the second vertical semiconductor pattern 113.

[0066] The back gate cover pattern 153 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, or a combination thereof.

[0067] In some example embodiments, the back gate insulating pattern 151 may include a material different from the material of the back gate cover pattern 153. For example, when the back gate insulating pattern 151 includes silicon oxide, the back gate cover pattern 153 may include a high dielectric constant material having a higher dielectric constant compared to silicon oxide.

[0068] In some example embodiments, the separator insulating pattern 120 may be disposed between the active patterns 110 in each row. More specifically, the separator insulating pattern 120 may be disposed between the active patterns 110 present in each row, between the first vertical semiconductor patterns 111 in the first direction D1, and between the second vertical semiconductor patterns 113 in the first direction D1. The lower surface of the separator insulating pattern 120 may be coplanar or substantially coplanar with the lower surfaces of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113. In some example embodiments, the separator insulating pattern 120 may comprise a material different from the material of the word line insulating pattern 131.

[0069] In some example embodiments, a first dielectric pattern 155 may be disposed between bit line 210 and back gate line 150. The lower surface of the first dielectric pattern 155 may contact bit line 210. In other words, the lower surface of the first dielectric pattern 155 may be coplanar or substantially coplanar with the upper surface of bit line 210. In some example embodiments, the height of the upper surface of the first dielectric pattern 155 may be greater than the height of the upper surface of the second dielectric pattern 135, but is not limited thereto. The first dielectric pattern 155 may extend in a first direction D1 to be parallel to the back gate line 150.

[0070] In some example embodiments, a second dielectric pattern 135 may be disposed between bit line 210 and word line 130. The lower surface of the second dielectric pattern 135 may contact bit line 210. In other words, the lower surface of the second dielectric pattern 135 may be coplanar or substantially coplanar with the upper surface of bit line 210. The second dielectric pattern 135 may be disposed between the lower portion of the first vertical semiconductor pattern 111 and the lower portion of the second vertical semiconductor pattern 113. The second dielectric pattern 135 may extend in a first direction D1 parallel to word line 130.

[0071] The separate insulating pattern 120, the first dielectric pattern 155, and the second dielectric pattern 135 may include an insulating material. The separate insulating pattern 120, the first dielectric pattern 155, and the second dielectric pattern 135 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0072] In some example embodiments, a bit line insulating pattern 220 may be disposed on the lower surface of the bit line 210. The bit line insulating pattern 220 may be a film in which insulating material is conformally formed on the lower surface of the bit line 210, the lower surface of the first dielectric pattern 155, the lower surface of the second dielectric pattern 135, the lower surface of the first vertical semiconductor pattern 111, and the lower surface of the second vertical semiconductor pattern 113. The bit line insulating pattern 220 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric constant insulating material.

[0073] In some example embodiments, a dielectric film 240 may be disposed on the lower surface of the bit line 210. The dielectric film 240 may be a film conformally formed on the lower surface of the bit line insulating pattern 220. The dielectric film 240 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or a high dielectric constant material containing metal.

[0074] In some example embodiments, gap structures 230 may be disposed between bit lines 210 and on dielectric film 240. In some example embodiments, gap structures 230 may serve as shielding lines of a semiconductor memory device to reduce coupling noise between adjacent bit lines 210. Gap structures 230 may extend in a second direction D2 between bit lines 210 and on dielectric film 240. Gap structures 230 may be made of a conductive material and may include (or define) air gaps.

[0075] In some example embodiments, pads LP may be disposed on each of the active patterns 110. More specifically, each of the pads LP may be disposed on the upper surface of the first vertical semiconductor pattern 111 and the upper surface of the second vertical semiconductor pattern 113. Each of the pads LP may be arranged in a matrix in the first direction D1 and the second direction D2 in a planar view. In some example embodiments, each of the pads LP may have a rectangular shape in the planar view, but is not limited thereto, and may have various shapes (e.g., circular, elliptical, rectangular, square, rhomboid, or hexagonal, etc.). In some example embodiments, pads LP may be omitted. Pads LP may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO, RuO, or combinations thereof, but is not limited thereto.

[0076] Data storage pattern DSPs may be disposed on pads LP. More specifically, data storage pattern DSPs may be disposed on the upper surfaces of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 of each of the active patterns 110, for electrical connection to the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113. Data storage pattern DSPs may be arranged in a matrix in a first direction D1 and a second direction D2. In some example embodiments, data storage pattern DSPs may be completely superimposed on pads LP, but are not limited thereto. Data storage pattern DSPs may, for example, be partially superimposed on pads LP. Data storage pattern DSPs may contact the entire upper surface of pads LP or a portion of the upper surface of pads LP.

[0077] In some example embodiments, the data storage pattern DSP can be a variable resistance pattern, which can be switched between two resistance states by an electrical pulse applied to the memory element. For example, the data storage pattern DSP may include phase change materials, perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials, and / or antiferromagnetic materials whose crystal state changes according to the amount of electricity. Furthermore, in some example embodiments, the data storage pattern DSP can be a capacitor.

[0078] Each memory cell in a semiconductor memory device according to some example embodiments of this application may include a selection element VT and a data storage pattern DSP. Here, the selection element VT may be a vertical channel transistor. Figure 3As shown, one of the selection elements VT may include a first vertical semiconductor pattern 111, a second vertical semiconductor pattern 113, a word line 130, and a portion of a back gate line 150. The selection elements VT in the memory cell may share the back gate line 150.

[0079] A semiconductor memory device according to some example embodiments of this application may be provided with active patterns, each including a first vertical semiconductor pattern and a second vertical semiconductor pattern, and each of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 may include a channel region CH. Furthermore, a word line 130 may be disposed between the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 included in the active pattern 110. Therefore, the channel regions CH may each be disposed on two side surfaces of the word line 130. Furthermore, a back gate line 150 may be disposed between adjacent active patterns 110. Therefore, since adjacent select elements VT may share the back gate line 150, leakage current that may occur in portions of the channel regions CH of the active pattern 110 can be controlled. Furthermore, since the number of word lines 130 and back gate lines 150 disposed in a memory cell can be reduced, the integration density in the process can be improved.

[0080] Figure 5 and Figure 6 Semiconductor memory devices according to some example embodiments of this application are shown. Figure 5 and Figure 6 Is it separate from Figure 2 The cross-sectional views corresponding to lines A-A' and B-B' are shown below. For ease of explanation, the following example embodiments will be described focusing on the differences from the example embodiments described above.

[0081] Reference Figure 5 and Figure 6 According to some example embodiments of this application, the data storage pattern DSP of the semiconductor memory device may be a capacitor 310.

[0082] Capacitor 310 may be disposed on the upper surface of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 in each of the active patterns 110. Here, the upper surface may be the surface of the first vertical semiconductor pattern 111 on the third direction D3 and the surface of the second vertical semiconductor pattern 113 on the third direction D3. Capacitor 310 may store signals transmitted from transistors in the peripheral circuitry of the semiconductor memory device (e.g., row decoder, column decoder, sense amplifier, etc.). Capacitor 310 may serve as an information storage element electrically connected to the transistor. For example, capacitor 310 may store charge under the control of the transistor. In some example embodiments, capacitor 310 may include a storage electrode 311, a capacitor dielectric film 313, and a plate electrode 315.

[0083] The storage electrode 311 can be formed as a plurality of electrodes spaced apart from each other in the first direction D1 and the second direction D2, and can contact the upper surface of each of the corresponding first vertical semiconductor pattern 111 and second vertical semiconductor pattern 113. The storage electrodes 311 can be spaced apart from each other at a regular interval in the first direction D1 and the second direction D2. That is, the storage electrodes 311 can be arranged in a planar view in the first direction D1 and the second direction D2. The storage electrodes 311 can include a conductive material. The storage electrodes 311 can include, for example, a metal, a metal nitride, a metal silicide, or a combination thereof. Therefore, the capacitor 310 can be electrically connected to the active pattern 110.

[0084] A capacitor dielectric film 313 may be disposed on the storage electrode 311 and the pad separation pattern 320. The capacitor dielectric film 313 may be conformally formed on the storage electrode 311 and the pad separation pattern 320. Unlike what is shown, the capacitor dielectric film 313 may comprise multiple films. The capacitor dielectric film 313 may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material containing a metal, or a combination thereof.

[0085] Plate electrodes 315 may be disposed on the capacitor dielectric film 313. Plate electrodes 315 may fill the empty spaces between storage electrodes 311. Plate electrodes 315 may include doped n-type or p-type impurities. Plate electrodes 315 may include, for example, metals, metal nitrides, metal silicides, impurity-doped silicon-germanium, or combinations thereof.

[0086] In some example embodiments, a pad separation pattern 320 may be disposed between pads LP. The pad separation pattern 320 may separate adjacent pads LP from each other. The upper surface of the pad separation pattern 320 may be coplanar or substantially coplanar with the upper surface of the pads LP. The pad separation pattern 320 may include an insulating material. The pad separation pattern 320 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0087] Each of the active patterns 110 in the semiconductor memory device according to some example embodiments of this application may have a first vertical semiconductor pattern 111 and a second vertical semiconductor pattern 113 that are separated from and spaced apart from each other, but is not limited thereto. The first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 of each of the active patterns 110 may be connected to each other, for example, by separate connection portions.

[0088] Figure 7 Semiconductor memory devices according to some example embodiments of this application are shown. Figure 7 Is with Figure 2 The cross-sectional view corresponding to line A-A'. For ease of explanation, the following example embodiment will be described focusing on the differences from the example embodiment described above.

[0089] Reference Figure 7 The active pattern 110a may further include a connecting portion 115. The connecting portion 115 may be disposed between the upper ends of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 of the active pattern 110a, and integrally connected to the upper ends. In some example embodiments, the upper surface of the connecting portion 115 may be coplanar or substantially coplanar with the upper surfaces of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113.

[0090] The connection portion 115 may include the same material as the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113. The connection portion 115 may include, for example, semiconductor materials (such as silicon (Si), germanium (Ge), silicon-germanium (Si-Ge)), oxide semiconductor materials and / or two-dimensional semiconductor materials.

[0091] In some example embodiments, a first source / drain region SD1 may be disposed in the connection portion 115. Therefore, in each of the active patterns 110a, the first source / drain region SD1 may be connected.

[0092] Figure 8A , Figure 9A , Figure 10A to Figure 22A This is a plan view illustrating a method of manufacturing a semiconductor memory device according to some example embodiments of this application. Figure 8B , Figure 9B , Figure 10B to Figure 22B They are respectively along Figure 8A to Figure 22A A sectional view taken from lines A-A' and B-B'.

[0093] Reference Figure 8A and Figure 8B A first substrate 100 can be prepared. The first substrate 100 can be, for example, a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. In addition, the first substrate 100 may have a silicon-on-insulator (SOI) structure.

[0094] Reference Figure 9A and Figure 9B A patterning process can be performed on the upper surface of the first substrate 100 to form a first trench TCH1. The first trench TCH1 can extend within the first substrate 100 in a first direction D1, and each first trench in the first trench TCH1 can be arranged in a second direction D2.

[0095] Adjacent first trenches TCH1 may define prepared active lines 100L. More specifically, a plurality of first trenches TCH1 arranged in the second direction D2 may be formed to define prepared active lines 100L between adjacent first trenches TCH1. That is, the prepared active lines 100L may be part of a patterned first substrate 100. The prepared active lines 100L may extend in the first direction D1, and each prepared active line in the prepared active lines 100L may be arranged in the second direction D2.

[0096] Reference Figure 10A and Figure 10B A back gate cover film can be formed on the inner surface of the prepared active line 100L and the first trench TCH1, and a portion of the back gate cover film can be removed to form a back gate cover pattern 153. The back gate cover pattern 153 can be formed by an etch-back process.

[0097] Subsequently, a back gate insulating film 151a can be formed on the prepared active line 100L and the back gate cover pattern 153. The back gate insulating film 151a can be formed by a thermal oxidation process, but is not limited thereto. The back gate insulating film 151a can be formed, for example, by a deposition process. Although not shown, the back gate insulating film 151a can be conformally formed on the prepared active line 100L and the back gate cover pattern 153 to cover the upper surface of the back gate cover pattern 153.

[0098] Reference Figure 11A and Figure 11B A back gate line film 150a can be formed on the back gate insulating film 151a and the back gate overlay pattern 153. The back gate line film 150a can fill the first trench TCH1. The formation of the back gate line film 150a can be performed by at least one of an oxidation process and a deposition process.

[0099] Reference Figure 12A and Figure 12B An etching process can be performed on the back gate line film 150a to form the back gate line 150 and the back gate insulating pattern 151. The etching process can be an etch-back process. The back gate lines 150 can be arranged between the back gate insulating patterns 151 in a planar view, and each of the back gate lines 150 can extend in a first direction D1.

[0100] Subsequently, a first dielectric film can be formed on the prepared active line 100L, the back gate insulating pattern 151, and the back gate line 150 to fill the first trench TCH1. The formation of the first dielectric film can be performed by at least one of an oxidation process and a deposition process. Afterward, an etching process can be performed on the first dielectric film to expose the prepared active line 100L. The etching process can be performed by a chemical mechanical polishing (CMP) process. Thus, a first dielectric pattern 155 can be formed. Each of the first dielectric patterns 155 can be formed on the back gate insulating pattern 151 and the back gate line 150 present in each first trench TCH1.

[0101] Reference Figure 13A and Figure 13B After forming an etch mask that partially covers the prepared active line 100L, a patterning process can be performed on the prepared active line 100L to form a second trench TCH2. The second trench TCH2 can extend from the upper surface of the prepared active line 100L toward the lower surface of the first substrate 100, and extend in the second direction D2 in a plan view. The second trench TCH2 can intersect (traverse) the first trench TCH1 and the prepared active line 100L. Therefore, a prepared active pattern 110P can be formed. The prepared active pattern 110P can be arranged in the first direction D1 and the second direction D2 to form rows and columns.

[0102] Reference Figure 14A and Figure 14B A separate insulating pattern 120 can be formed within the second trench TCH2. The formation of the separate insulating pattern 120 can be performed by at least one of an oxidation process and a deposition process.

[0103] Subsequently, a patterning process can be performed on the prepared active pattern 110P to form a third trench TCH3 and an active pattern 110. The third trench TCH3 may extend in a first direction D1, and each third trench in the third trench TCH3 may be arranged in a second direction D2. Furthermore, each of the active patterns 110 may include a first vertical semiconductor pattern 111 and a second vertical semiconductor pattern 113 spaced apart from each other. More specifically, the third trench TCH3 may extend in the first direction D1 to be formed between the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 in each row of active patterns 110. Simultaneously, the height of the bottom surface of the third trench TCH3 may be lower than the height of the lower surface of the first vertical semiconductor pattern 111 and the lower surface of the second vertical semiconductor pattern 113.

[0104] Here, patterning the prepared active pattern 110P may include patterning the prepared active pattern 110P and the separation insulating pattern 120 to form a third trench TCH3 and the active pattern 110. More specifically, each of the third trenches TCH3 may be formed between the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 of each row of the active pattern 110 and within the separation insulating pattern 120 of each row.

[0105] Reference Figure 15A and Figure 15B A word line cover film can be formed on the inner surface of the active pattern 110 and the third trench TCH3, and a portion of the word line cover film can be removed to form the word line cover pattern 133. The word line cover pattern 133 can be formed by an etching process.

[0106] Subsequently, a word line insulating film 131a can be formed on the active pattern 110 and the word line overlay pattern 133. The word line insulating film 131a can be formed by a thermal oxidation process, but is not limited thereto. The word line insulating film 131a can be formed, for example, by a deposition process. Although not shown, in some example embodiments, the word line insulating film 131a can be conformally formed on the active pattern 110 and the word line overlay pattern 133 to cover the upper surface of the word line overlay pattern 133.

[0107] A word line film 130a can be formed on the word line insulating film 131a and the word line overlay pattern 133. The word line film 130a can fill the third trench TCH3. The formation of the word line film 130a can be performed by at least one of an oxidation process and a deposition process.

[0108] Reference Figure 16A and Figure 16B An etching process can be performed to form word lines 130 and word line insulating patterns 131. The etching process can be an etch-back process. In some example embodiments, each of the word lines 130 may be filled with a third trench TCH3 on the word line insulating film 131a. The word lines 130 may be arranged between the word line insulating patterns 131 in a planar view, and each of the word lines 130 may extend in a first direction D1.

[0109] A second dielectric film can be formed on the active pattern 110, the first dielectric pattern 155, the word line insulating pattern 131, and the word line 130 to fill the third trench TCH3. The formation of the second dielectric film can be performed by at least one of an oxidation process and a deposition process.

[0110] Subsequently, an etching process can be performed on the first substrate 100 to expose the active pattern 110. That is, the upper surface of the first substrate 100 can be ground until the upper surfaces of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 are exposed. The etching process can be performed by a chemical mechanical polishing process. Thus, a second dielectric pattern 135 can be formed. Each of the second dielectric patterns 135 can be formed on the word line insulating pattern 131 and the word line 130 present in each third trench TCH3.

[0111] Subsequently, an ion implantation process can be performed on the upper end of each of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 to form a second source / drain region SD2.

[0112] Reference Figure 17A and Figure 17B Bit line films 210a can be formed on the first vertical semiconductor pattern 111, the second vertical semiconductor pattern 113, the first dielectric pattern 155, and the second dielectric pattern 135. Although not shown, the bit line film 210a may include an embedded conductive film, a contact film, a metal film, and / or a hard mask film. More specifically, the embedded conductive film, contact film, metal film, and hard mask film may be sequentially formed on the first vertical semiconductor pattern 111, the second vertical semiconductor pattern 113, the first dielectric pattern 155, and the second dielectric pattern 135. The formation of the bit line film 210a can be performed by at least one of an oxidation process and a deposition process.

[0113] Reference Figure 18A and Figure 18B A mask pattern having a line shape extending in the second direction D2 can be formed on the bit line film 210a, and the bit line film 210a can be anisotropically etched using the mask pattern. Therefore, a fourth trench TCH4 extending in the second direction D2 can be formed. As a result, a bit line 210 extending in the second direction D2 can be formed. In a plan view, each bit line in the bit line 210 can be spaced apart in the first direction D1 by the fourth trench TCH4.

[0114] Reference Figure 19A and Figure 19B After forming bit lines 210, bit line insulating patterns 220 can be conformally formed on bit lines 210 and the fourth trench TCH4. The thickness of the bit line insulating pattern 220 can be less than half the spacing between adjacent bit lines 210. Subsequently, a dielectric film 240 can be conformally formed on the bit line insulating pattern 220. Afterward, gap structures 230 can be formed on the dielectric film 240 to fill the fourth trench TCH4. The formation of the bit line insulating pattern 220, the dielectric film 240, and the gap structures 230 can be performed by at least one of an oxidation process and a deposition process.

[0115] ReferenceFigure 20A and Figure 20B After forming an interlayer insulating film 250 on the gap structure 230, a first bonding film 260 can be formed on the interlayer insulating film 250.

[0116] Furthermore, a second bonding film 270 may be formed on the second substrate 200, and after the second substrate 200 is flipped, the second bonding film 270 may be brought into contact with the first bonding film 260 to bond the first substrate 100 and the second substrate 200 to each other.

[0117] Reference Figure 21A and Figure 21B The first substrate 100 and the second substrate 200 are flip-fitted together. Thereafter, an etching process can be performed such that the upper surface of the first substrate 100 is polished to expose the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113. That is, the upper surface of the first substrate 100 can be ground until the upper surfaces of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 are exposed. The etching process can be performed using a chemical mechanical polishing process.

[0118] Subsequently, an ion implantation process can be performed on the upper end of each of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 to form a first source / drain region SD1. Therefore, the channel region CH can be defined between the first source / drain region SD1 and the second source / drain region SD2.

[0119] In some example embodiments, a conductive film may be formed on the first substrate 100, and a pad LP may be formed by patterning a portion of the conductive film.

[0120] More specifically, after forming the conductive film, a mask pattern can be used to form a recess, and an insulating material can be embedded in the recess to form a pad separation pattern 320. Here, the upper surface of the pad separation pattern 320 may be coplanar or substantially coplanar with the upper surface of the pad LP.

[0121] Reference Figure 22A and Figure 22B A capacitor 310, which serves as a data storage pattern DSP, can be formed on the pad LP.

[0122] More specifically, a storage electrode 311 may be formed on a pad LP. Subsequently, a capacitor dielectric film 313 may be formed to conformally cover the surface of the storage electrode 311. A plate electrode 315 may then be formed on the capacitor dielectric film 313. The sequentially stacked storage electrode 311 and capacitor dielectric film 313, together with the plate electrode 315, may form a capacitor 310.

[0123] Return to reference Figure 5 and Figure 6Semiconductor memory devices according to some example embodiments of this application can be manufactured by polishing away the bonded second substrate 200.

[0124] Figure 23A , Figure 24B to Figure 28A This is a plan view illustrating a method of manufacturing a semiconductor memory device according to some example embodiments of this application. Figure 23B , Figure 24B to Figure 28B They are respectively along Figure 23A to Figure 28A The cross-sectional views are taken along lines A-A' and B-B'. For ease of explanation, the differences from the method of manufacturing a semiconductor memory device described above will be described below.

[0125] Reference Figure 23A and Figure 23B A patterning process can be performed on the prepared active pattern 110P to form a third trench TCH3 and an active pattern 110a. The third trench TCH3 may extend in a first direction D1, and each third trench in the third trench TCH3 may be arranged in a second direction D2. Furthermore, each of the active patterns 110a may include a first vertical semiconductor pattern 111, a second vertical semiconductor pattern 113, and a connection portion 115. More specifically, the third trench TCH3 may extend in the first direction D1 to be formed between the first vertical semiconductor pattern 111, the second vertical semiconductor pattern 113, and the connection portion 115 of each row of active patterns 110a.

[0126] In some example embodiments, the height of the bottom surface of the third trench TCH3 may be higher than the height of the lower surface of the first vertical semiconductor pattern 111 and the lower surface of the second vertical semiconductor pattern 113. Therefore, in each of the active patterns 110a, a connection portion 115 may be disposed between the lower ends of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 to be integrally connected to the lower ends.

[0127] Reference Figure 24A and Figure 24B A word line cover film can be formed on the inner surface of the active pattern 110a and the third trench TCH3, and a portion of the word line cover film can be removed to form the word line cover pattern 133.

[0128] Subsequently, a word line insulating film 131a can be formed on the active pattern 110a and the word line overlay pattern 133, and a word line film 130a can be formed on the word line insulating film 131a and the word line overlay pattern 133.

[0129] Reference Figure 25A and Figure 25BAn etching process can be performed to form word lines 130 and word line insulating patterns 131. A second dielectric film can be formed on the active pattern 110a, the first dielectric pattern 155, the word line insulating pattern 131, and the word lines 130 to fill the third trench TCH3. Subsequently, a chemical mechanical polishing process can be performed on the first substrate 100 to expose the active pattern 110a. Thus, second dielectric patterns 135 can be formed. Each of the second dielectric patterns 135 can be formed on the word line insulating pattern 131 and the word lines 130 present in each third trench TCH3.

[0130] Subsequently, an ion implantation process can be performed on the upper end of each of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113 to form a second source / drain region SD2.

[0131] Reference Figure 26A and Figure 26B Bit line films 210a can be formed on the first vertical semiconductor pattern 111, the second vertical semiconductor pattern 113, the first dielectric pattern 155, and the second dielectric pattern 135. The bit line films 210a can be anisotropically etched to form bit lines 210 extending in the second direction D2.

[0132] A deposition or oxidation process can be performed on bit line 210 to form bit line insulation pattern 220, dielectric film 240 and gap structure 230.

[0133] Subsequently, after forming an interlayer insulating film 250 on the gap structure 230, a first bonding film 260 can be formed on the interlayer insulating film 250, and a second bonding film 270 can be made to contact the first bonding film 260 to bond the first substrate 100 and the second substrate 200 to each other.

[0134] Reference Figure 27A and Figure 27B The first substrate 100 and the second substrate 200 are flip-joined and a chemical mechanical polishing process can be performed to polish the upper surface of the first substrate 100, thereby exposing the first vertical semiconductor pattern 111, the second vertical semiconductor pattern 113 and the connecting portion 115.

[0135] Subsequently, an ion implantation process can be performed on the upper end of each of the first vertical semiconductor pattern 111 and the second vertical semiconductor pattern 113, as well as the connection portion 115, to form a first source / drain region SD1. Therefore, the channel region CH can be defined between the first source / drain region SD1 and the second source / drain region SD2 in each of the first and second vertical semiconductor patterns. Furthermore, the connection portion 115 may include the first source / drain region SD1.

[0136] Reference Figure 28A andFigure 28B A conductive film can be formed on the first substrate 100. A mask pattern can be used to form recesses on the conductive film, and an insulating material can be embedded in the recesses to form a pad separation pattern 320. In this case, a pad LP can be formed between the pad separation patterns 320. The upper surface of the pad separation pattern 320 can be coplanar or substantially coplanar with the upper surface of the pad LP.

[0137] Subsequently, a storage electrode 311 can be formed on the pad LP. Then, a capacitor dielectric film 313 can be formed to conformally cover the surface of the storage electrode 311. Subsequently, a plate electrode 315 can be formed on the capacitor dielectric film 313. The sequentially stacked storage electrode 311 and capacitor dielectric film 313, together with the plate electrode 315, can form a capacitor 310.

[0138] Return to reference Figure 7 Semiconductor memory devices according to some example embodiments of this application can be manufactured by polishing away the bonded second substrate 200.

[0139] According to some example embodiments of this application, active patterns including a first vertical semiconductor pattern and a second vertical semiconductor pattern can be provided, and the first and second vertical semiconductor patterns can include channel regions. Furthermore, word lines can be disposed between the first and second vertical semiconductor patterns in each of the active patterns. Therefore, channel regions can each be disposed on two side surfaces of the word line. Additionally, back gate lines can be disposed between adjacent active patterns. As a result, word lines and back gate lines can each be disposed on one of the two side surfaces of each of the first and second vertical semiconductor patterns, thereby allowing control of leakage current. Furthermore, adjacent selector devices in the memory cell can share back gate lines, thereby increasing integration density.

[0140] When the terms “about” or “basically” are used in conjunction with numerical values ​​in this specification, it is intended that the relevant numerical value includes manufacturing or operational tolerances centered on the stated numerical value (e.g., ±10%). Furthermore, when the terms “approximately (overall)” and “basically” are used in conjunction with geometry, it is intended that no precision of the geometry is required, but tolerance for the shape is within the disclosed range. Moreover, regardless of whether a numerical value or shape is modified to “about” or “basically,” it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances centered on the stated numerical value or shape (e.g., ±10%).

[0141] Although this application has been described above with reference to some exemplary embodiments, those skilled in the art or those of ordinary skill in the art will understand that this application can be modified and altered in various ways without departing from the spirit and technical scope of this application as set forth in the appended claims.

[0142] Therefore, the technical scope of this application should not be limited to the content described in the specific embodiments of the specification, but should be defined by the patent claims.

Claims

1. A semiconductor memory device, comprising: active patterns arranged in a first direction and a second direction intersecting the first direction to form rows and columns, each of the active patterns including a first vertical semiconductor pattern and a second vertical semiconductor pattern, the first and second vertical semiconductor patterns being spaced apart from each other and extending in a third direction perpendicular to the first and second directions; bit lines arranged in the first direction, each extending in the second direction, and each connected to a lower surface of the first vertical semiconductor pattern and a lower surface of the second vertical semiconductor pattern of the active pattern of each of the columns; word lines arranged in the second direction, each extending in the first direction, and each between the first and second vertical semiconductor patterns of the active pattern of each of the rows; word line insulating patterns each between each of the word lines and the active pattern of each of the rows, the word line insulating patterns not covering an upper surface of the word line; back gate lines arranged in the second direction, each extending in the first direction, and each between adjacent ones of the rows; and back gate insulating patterns each between each of the back gate lines and the active pattern of adjacent ones of the rows and extending in the first direction.

2. The semiconductor memory device according to claim 1, wherein each of the first and second vertical semiconductor patterns includes a channel region, a first source / drain region, and a second source / drain region, the first source / drain region is in an upper end portion of each of the first and second vertical semiconductor patterns, the second source / drain region is in a lower end portion of each of the first and second vertical semiconductor patterns, and the channel region is between the first and second source / drain regions.

3. The semiconductor memory device according to claim 1, further comprising: data storage patterns on the upper surface of the first vertical semiconductor pattern and the upper surface of the second vertical semiconductor pattern of each of the active patterns, and electrically connected to the first and second vertical semiconductor patterns.

4. The semiconductor memory device according to claim 3, wherein, the data storage patterns are capacitors.

5. The semiconductor memory device of claim 1, further comprising: word line covering patterns each covering the upper surface of each of the word lines and extending in the first direction, wherein an upper surface of the word line covering pattern is coplanar with the upper surfaces of the first and second vertical semiconductor patterns.

6. The semiconductor memory device of claim 5, wherein, the word line insulating patterns include a material different from a material of the word line covering patterns.

7. The semiconductor memory device of claim 1, further comprising: back gate covering patterns each covering the upper surface of each of the back gate lines and extending in the first direction.

8. The semiconductor memory device according to any one of claims 1 to 7, wherein, the first and second vertical semiconductor patterns are in a single crystalline state.

9. A semiconductor memory device, comprising: an active pattern arranged in a first direction and a second direction intersecting the first direction to form rows and columns, each of the active pattern including a first vertical semiconductor pattern, a second vertical semiconductor pattern, and a connection portion, the first vertical semiconductor pattern and the second vertical semiconductor pattern being spaced apart from each other and extending in a third direction perpendicular to the first direction and the second direction, the connection portion being between and integrally connected to upper end portions of the first vertical semiconductor pattern and the second vertical semiconductor pattern; bit lines arranged in the first direction, each extending in the second direction, and each connected to lower surfaces of the first vertical semiconductor pattern and the second vertical semiconductor pattern of the active pattern of each of the columns; word lines arranged in the second direction, each extending in the first direction, and each between the first vertical semiconductor pattern and the second vertical semiconductor pattern of the active pattern of each of the rows; word line insulating patterns each between each of the word lines and the active pattern of each of the rows; back gate lines arranged in the second direction, each extending in the first direction, and each between adjacent ones of the rows; and back gate insulating patterns each between each of the back gate lines and the active pattern of adjacent ones of the rows and extending in the first direction.

10. The semiconductor memory device of claim 9, wherein the first vertical semiconductor pattern, the second vertical semiconductor pattern, and the connection portion include a channel region, a first source / drain region, and a second source / drain region, the first source / drain region is in the upper end portion of the first vertical semiconductor pattern, the upper end portion of the second vertical semiconductor pattern, and the connection portion, the second source / drain regions are each in each of a lower portion of the first vertical semiconductor pattern and a lower portion of the second vertical semiconductor pattern, and the channel region is defined between the first source / drain region and the second source / drain region.

11. The semiconductor memory device of claim 9, further comprising: word line cover patterns each covering an upper surface of each of the word lines and extending in the first direction, wherein the upper surface of the word line cover pattern is coplanar with a lower surface of the connection portion.

12. The semiconductor memory device of any one of claims 9 to 11, further comprising: back gate cover patterns each covering an upper surface of each of the back gate lines and extending in the first direction.

13. A method of manufacturing a semiconductor memory device, comprising: forming first trenches extending in a first direction within a substrate to define preliminary active lines, and forming back gate lines each to fill each of the first trenches; forming second trenches intersecting the first trenches and the preliminary active lines within the substrate to form a preliminary active pattern, the preliminary active pattern being arranged in the first direction and a second direction intersecting the first direction to form rows and columns; patternizing the preliminary active pattern to form third trenches extending in the first direction and active patterns, each of the active patterns including a first vertical semiconductor pattern and a second vertical semiconductor pattern spaced apart from each other, and each of the third trenches being formed between the first vertical semiconductor pattern and the second vertical semiconductor pattern of the active pattern of each of the rows; forming a word line insulating film on the substrate having the third trenches and the active patterns; and forming word lines each filling each of the third trenches on the word line insulating film.

14. The method of claim 13, further comprising: forming a separation insulating pattern within the second trenches before the step of forming the third trenches, wherein the step of patterning the preliminary active patterns includes patterning the preliminary active patterns and the separation insulating pattern to form the third trenches and the active patterns, and each of the third trenches is formed within the separation insulating pattern of each of the rows and between the first vertical semiconductor pattern and the second vertical semiconductor pattern of the active pattern of each of the rows.

15. The method according to claim 13, further comprising, forming a word line cover pattern covering an upper surface of the word lines before the step of forming the word lines.

16. The method according to claim 13, further comprising: polishing a lower surface of the substrate after the step of forming the word lines until lower surfaces of the first vertical semiconductor pattern and the second vertical semiconductor pattern are exposed; and forming bit lines on the lower surfaces of the first vertical semiconductor pattern and the second vertical semiconductor pattern of the active pattern of each of the columns.

17. The method of claim 16, further comprising: forming data storage patterns on upper surfaces of the first vertical semiconductor pattern and the second vertical semiconductor pattern of each of the active patterns after the step of forming the bit lines.

18. The method of claim 17, wherein, The data storage patterns are capacitors.

19. The method of any one of claims 13 to 18, wherein, A height of a bottom surface of the third trenches is lower than a height of the lower surface of the first vertical semiconductor pattern and a height of the lower surface of the second vertical semiconductor pattern.

20. The method according to any one of claims 13 to 18, wherein, a height of a bottom surface of the third trenches is higher than a height of the lower surface of the first vertical semiconductor pattern and a height of the lower surface of the second vertical semiconductor pattern, and each of the active patterns further includes a connection portion connected integrally to the upper end portions of the first vertical semiconductor pattern and the second vertical semiconductor pattern between the upper end portions of the first vertical semiconductor pattern and the second vertical semiconductor pattern.

Images