Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and electronic equipment, and the method comprises the steps: forming a first storage unit and a second storage unit which are arranged at an interval on a storage region of a substrate, and enabling a conductive contact region to be arranged between a first word line grid of the first storage unit and a second word line grid of the second storage unit; forming an auxiliary diffusion layer on the conductive contact region; forming at least one metal material layer on the auxiliary diffusion layer; and executing annealing operation, and forming a metal silicide layer generated based on the auxiliary diffusion layer and the at least one metal material layer on the substrate. According to the invention, programming interference in the storage unit of the flash memory at a high temperature can be inhibited, and the integrity of stored data is protected.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] Non-volatile memory (NVM) is a kind of semiconductor technology, which does not need continuous power supply to keep the data stored in the device, and flash memory is one of the non-volatile memories.

[0003] In a split-gate flash memory structure, the storage of electrons is realized by a floating gate, and the coupling gate controls the bias on the floating gate, thereby controlling the amount of storage charge in the floating gate. For the representation of data, the voltage of the internal storage charge in a single storage cell is compared with a certain threshold voltage Vth, and if it is greater than the Vth value, it represents "1" (i.e. erase state), otherwise it represents "0" (i.e. program state).

[0004] However, in a high-temperature environment, when a certain bit of a storage cell needs to be written, other bits in the same region may be converted from the state "1" to the state "0" due to program disturb, which will change the stored information and thus destroy the integrity of the stored data. SUMMARY

[0005] In view of at least one technical problem in the related art, the present application aims to provide a semiconductor device and a manufacturing method thereof.

[0006] In order to solve the above technical problems, on the one hand, the present application provides a manufacturing method of a semiconductor device, comprising:

[0007] forming a first storage cell and a second storage cell arranged at intervals on a storage area of a substrate, the first storage cell having a first word line gate and the second storage cell having a second word line gate, and the first word line gate and the second word line gate having a conductive contact area therebetween;

[0008] forming an auxiliary diffusion layer on the conductive contact area;

[0009] forming at least one layer of metal material on the auxiliary diffusion layer;

[0010] performing an annealing operation to form a metal silicide layer on the substrate based on the auxiliary diffusion layer and the at least one layer of metal material.

[0011] In some embodiments, the forming of the auxiliary diffusion layer on the conductive contact area comprises:

[0012] An auxiliary silicon material layer is formed on the substrate, the auxiliary silicon material layer covering the first memory cell, the second memory cell and the conductive contact area;

[0013] A mask layer is formed on the auxiliary silicon material layer, and the mask layer is patterned.

[0014] Using the patterned mask layer as a mask, a portion of the auxiliary silicon material layer, excluding the conductive contact area, is removed to form an auxiliary diffusion layer on the conductive contact area.

[0015] In some embodiments, the auxiliary diffusion layer satisfies at least one of the following conditions:

[0016] The material of the auxiliary diffusion layer includes amorphous silicon;

[0017] The thickness of the auxiliary diffusion layer is 20 angstroms to 100 angstroms.

[0018] In some embodiments, performing the annealing operation to form a metal silicide layer on the substrate based on the auxiliary diffusion layer and the at least one metal material layer includes:

[0019] Perform a first annealing operation to form an intermediate metal silicide layer on the substrate, which is based on the auxiliary diffusion layer and the at least one metal material layer;

[0020] Remove unreacted residual metal material from the at least one layer of metal material;

[0021] A second annealing operation is performed to transform the intermediate metal silicide layer into the metal silicide layer.

[0022] In some embodiments, the first annealing operation is a rapid thermal annealing operation, with an annealing temperature of 400°C to 600°C and an annealing time of 20 to 60 seconds;

[0023] And / or, the second annealing operation is a rapid thermal annealing operation, with an annealing temperature of 800℃~900℃ and an annealing time of 20 seconds~60 seconds.

[0024] In some embodiments, the material of the at least one metal material layer includes at least one of cobalt, titanium, and nickel.

[0025] In some embodiments, after forming at least one metallic material layer on the auxiliary diffusion layer, the method includes:

[0026] A diffusion barrier layer is formed on the metal material layer;

[0027] The diffusion barrier layer is made of titanium nitride.

[0028] In some embodiments, prior to forming the auxiliary diffusion layer on the conductive contact region, the method further includes:

[0029] A protective layer is formed on the substrate, the protective layer covering the first memory cell, the second memory cell and the conductive contact area;

[0030] Remove part of the protective layer on the conductive contact area.

[0031] In some embodiments, the protective layer satisfies at least one of the following conditions:

[0032] The material of the protective layer includes oxygen-rich silicon dioxide;

[0033] The thickness of the protective layer is 300 to 400 angstroms.

[0034] In some embodiments, the method further includes:

[0035] A conductive structure is formed on the conductive contact area, and the conductive structure is electrically connected to the source / drain region below the conductive contact area through the metal silicide layer.

[0036] On the other hand, this application provides a semiconductor device manufactured based on the method described in any embodiment of this application, the semiconductor device comprising:

[0037] A first memory cell and a second memory cell are formed in a memory region on a substrate; the first memory cell includes a first word line gate, and the second memory cell includes a second word line gate disposed opposite to the first word line gate, and a conductive contact region is provided between the first word line gate of the first memory cell and the second word line gate of the second memory cell;

[0038] A metal silicide layer is formed on the conductive contact area, the metal silicide layer being generated based on an auxiliary diffusion layer and at least one layer of metal material formed on the conductive contact area.

[0039] In some embodiments, the semiconductor device further satisfies at least one of the following conditions:

[0040] A first spacer and a second spacer are respectively formed on the sidewalls of the first word grid and the second word grid, and the metal silicide layer is formed between the first spacer and the second spacer;

[0041] The first storage cell includes a first floating gate and a first control gate stacked together, and a first isolation layer is provided between the first floating gate and the first control gate and the first word line gate;

[0042] The second storage cell includes a second floating gate and a second control gate stacked together, and a second isolation layer is provided between the second floating gate and the second control gate and the second word line gate.

[0043] On the other hand, this application also provides an electronic device, including the semiconductor device and the printed circuit board described above, wherein the semiconductor device and the printed circuit board are electrically connected.

[0044] The semiconductor device and its manufacturing method disclosed in this application have at least the following beneficial effects:

[0045] A first and second memory cells are formed spaced apart on a memory region of a substrate, with a conductive contact region between the first word line gate of the first memory cell and the second word line gate of the second memory cell; an auxiliary diffusion layer is formed on the conductive contact region; at least one metal material layer is formed on the auxiliary diffusion layer; and an annealing operation is performed to form a metal silicide layer on the substrate based on the auxiliary diffusion layer and the at least one metal material layer. Thus, by forming an auxiliary diffusion layer between the metal material layer and the substrate, the metal in the metal material layer can be controlled to prevent easy diffusion into the substrate during the annealing operation, especially to the channel region below the word line gate. This allows the formed metal silicide layer to be well retained above the substrate, increasing the contact resistance between the substrate and the metal while reducing agglomeration defects similar to clusters in the channel region. This suppresses programming interference in the memory cells of flash memory at high temperatures, protects the integrity of stored data, and improves product yield. Attached Figure Description

[0046] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 These are electron microscope images of sections taken from the failure area in related technologies.

[0048] Figure 2 This is a flowchart of a method for manufacturing a semiconductor device according to some embodiments.

[0049] Figures 3 to 8 These are cross-sectional views of corresponding intermediate structures in the process of manufacturing semiconductor devices, provided according to some embodiments.

[0050] Figure 9 This is a schematic diagram of the structure of a semiconductor device according to some embodiments. Detailed Implementation

[0051] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0052] The terms "an embodiment" or "embodiment" as used herein refer to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. In the description of the present invention, unless otherwise expressly specified and limited, the terms "upper," "lower," "left," "right," "top," "bottom," etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are used only for the convenience of describing the present invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein.

[0053] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, the layer or region will be located "below" or "under" the other layer or region.

[0054] In a split-gate flash memory structure, electrons are stored through a floating gate (FG), and a coupling gate (CG) controls the bias voltage on the floating gate, thereby controlling the amount of charge stored in the floating gate. For data representation, the voltage of the charge stored within a single memory cell is compared to a specific threshold voltage Vth. If it is greater than Vth, it represents "1" (erased state); otherwise, if it is less than Vth, it represents "0" (programmed state).

[0055] However, in high-temperature environments, when a bit needs to be written to a specific storage cell, other bits in the same area may be affected by programming disturbance and change from state "1" to state "0". This can alter the stored information and compromise the integrity of the stored data.

[0056] The inventors discovered that by slicing and observing the faulty bits affected by interference, they found that there were clumping defects in the channel region below the word line (WL). Figure 1 These are electron microscope images of sections taken from the failure area in related technologies, such as... Figure 1 As shown, three clump defects 120, selected by the dashed circle, exist in the channel region below word line 110. Furthermore, under high-temperature conditions and when the word line is pressurized, these clump defects promote band-to-band tunneling (BTB), generating electrons on the channel surface of the word line. If enough electrons enter the floating gate, the stored signal of that bit will change from "1" to "0," forming a programmable disturbance (CTR), which in turn alters the stored information and compromises the integrity of the stored data.

[0057] In view of this, this application provides a semiconductor device and a method for manufacturing the same. The method involves forming a first memory cell and a second memory cell spaced apart on a memory region of a substrate, with a conductive contact region between a first word line gate of the first memory cell and a second word line gate of the second memory cell; forming an auxiliary diffusion layer on the conductive contact region; forming at least one metal material layer on the auxiliary diffusion layer; and performing an annealing operation to form a metal silicide layer on the substrate based on the auxiliary diffusion layer and the at least one metal material layer. Thus, by forming an auxiliary diffusion layer between the metal material layer and the substrate, the metal in the metal material layer can be controlled to prevent easy diffusion into the substrate during the annealing operation, especially to prevent diffusion into the channel region below the word line gate. This allows the formed metal silicide layer to be well retained above the substrate, increasing the contact resistance between the substrate and the metal while reducing agglomeration defects similar to clusters in the channel region. This suppresses programming interference in the memory cells of flash memory at high temperatures, protects the integrity of stored data, and improves product yield.

[0058] It should be noted that the following figures are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the purpose of illustrating the embodiments of this application.

[0059] Figure 2 This is a flowchart of a method for manufacturing a semiconductor device according to some embodiments. Figures 3-8These are cross-sectional views of corresponding intermediate structures during the manufacturing process of semiconductor devices, provided according to some embodiments. It should be understood that... Figures 3 to 8 Additional operations are provided before, during, and after the operations shown, and some of the following operations can be replaced or eliminated to obtain additional implementations of the method. Furthermore, the order of some of the following operations can be interchanged. See also Figure 2 As shown, the semiconductor device manufacturing method 200 includes the following steps:

[0060] In operation 202, a first memory cell 300 and a second memory cell 400 are formed on a memory region of a substrate, with a conductive contact region 520 between a first word line gate 310 of the first memory cell 300 and a second word line gate 410 of the second memory cell 400.

[0061] See Figure 3 The substrate includes a storage region for storing data. First storage cells 300 and second storage cells 400 are formed spaced apart on the storage region of the substrate. The first storage cell 300 includes a first word line gate 310, and the second storage cell 400 includes a second word line gate 410. The first word line gate 310 and the second word line gate 410 are arranged facing each other and spaced apart on the substrate, and a conductive contact region 520 is formed between the first word line gate 310 and the second word line gate 410.

[0062] In one embodiment, a drain 510 may be formed in the substrate below the conductive contact region 520. Since the drain is located between the first memory cell 300 and the second memory cell 400, the drain may be shared by both memory cells. Of course, in other embodiments, a source may be formed in the substrate below the conductive contact region 520.

[0063] In some embodiments, the first memory cell 300 further includes a first floating gate 320 and a first control gate 330 stacked together. The first floating gate 320 and the first control gate 330 may be disposed on the side of the first word line gate 310 away from the conductive contact region 520. The first floating gate 320 is disposed close to the substrate, and a gate oxide layer (not shown) is disposed between it and the substrate; the first control gate 330 is disposed away from the substrate, and a gate dielectric layer (not shown) is disposed between it and the first floating gate 320.

[0064] Similarly, the second memory cell 400 also includes a stacked second floating gate 420 and a second control gate 430. The second floating gate 420 and the second control gate 430 may be disposed on the side of the second word line gate 410 away from the conductive contact region 520. The second floating gate 420 is disposed close to the substrate, and a gate oxide layer (not shown) is disposed between it and the substrate; the second control gate 430 is disposed away from the substrate, and a gate dielectric layer (not shown) is disposed between it and the second floating gate 420.

[0065] In one embodiment, a first spacer 340 is formed on the sidewall of the first word grid 310 near the conductive contact area 520, and a second spacer 440 is formed on the upper sidewall of the second word grid 410 near the conductive contact area 520. The second sidewall is disposed opposite to the first sidewall. Both the first spacer 340 and the second spacer 440 can extend to the surface of the substrate.

[0066] In some embodiments, the substrate may further include a peripheral logic region (not shown) which can be used to form a circuit structure for an external interconnect memory region.

[0067] For example, the substrate can be a bulk semiconductor, a silicon-on-insulator (SOI), a silicon-on-insulator (SSOI), a silicon-germanium-on-insulator (SiGeOI), or a germanium-on-insulator (GeOI), etc., which can be p-type doped, n-type doped, or undoped. The SOI substrate is a semiconductor material layer formed on an insulating layer, which can be, for example, a buried oxide layer or a silicon oxide layer, disposed on a silicon substrate or a glass substrate. Specifically, the semiconductor material of the substrate can include one or more of silicon, germanium, compound semiconductors, and alloy semiconductors. The compound semiconductor can be one or more of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide. The alloy semiconductor can be one or more of silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and gallium arsenide phosphide.

[0068] For example, the first word line gate 310 and the second word line gate 410 may be made of semiconductor materials, such as polysilicon. In other examples, the first control gate 330 and the second control gate 430 may be made of metal, metal alloy, monocrystalline silicon, or a combination thereof.

[0069] The first floating gate 320 and the second floating gate 420 may be made of semiconductor materials, such as polysilicon. Specifically, the first floating gate 320 and the second floating gate 420 may be made of P-type or N-type polysilicon. In other exemplary cases, the first floating gate 320 and the second floating gate 420 may be made of metal, metal alloy, monocrystalline silicon, or combinations thereof.

[0070] The first control gate 330 and the second control gate 430 may be made of semiconductor materials, such as polycrystalline silicon. In other exemplary embodiments, the first control gate 330 and the second control gate 430 may be made of metal, metal alloy, monocrystalline silicon, or a combination thereof.

[0071] The gate oxide layer can be made of a suitable dielectric material, such as silicon oxide or other oxide materials. The gate dielectric layer can be made of a suitable dielectric material, such as silicon oxide or other oxide materials.

[0072] The first spacer 340 and the second spacer 440 may be made of suitable dielectric materials, such as oxide materials or nitride materials, such as silicon oxide, silicon nitride, and silicon oxynitride.

[0073] In this embodiment, the gate structures in the first memory cell 300 and the gate structures in the second memory cell 400 formed on the substrate can be formed using suitable deposition processes. Suitable deposition processes may include, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), low-pressure CVD, metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), sputtering, laser ablation, etc. The process of forming the first memory cell 300 and the second memory cell 400 on the memory region of the substrate is not specifically limited here.

[0074] It should be noted that, Figure 3 As an example only, in actual applications, the number of storage areas contained in the substrate, the number of first storage cells 300 and second storage cells 400, etc., are not limited to those shown in the figure.

[0075] In operation 204, an auxiliary diffusion layer 530 is formed on the conductive contact area 520.

[0076] In an embodiment, the material of the auxiliary diffusion layer 530 may include amorphous silicon.

[0077] In this embodiment, the thickness of the auxiliary diffusion layer 530 can range from 20 angstroms to 100 angstroms, such as 22 angstroms, 30 angstroms, 45 angstroms, 50 angstroms, 52 angstroms, 58 angstroms, 65 angstroms, 70 angstroms, 80 angstroms, 88 angstroms, 95 angstroms, etc. The thickness range of the auxiliary diffusion layer 530 needs to be set within a reasonable range to ensure that at least one subsequent metal material layer 540 can effectively diffuse into the auxiliary diffusion layer 530, thereby reducing the probability of diffusion into the substrate.

[0078] In some embodiments, forming the auxiliary diffusion layer 530 on the conductive contact region 520 includes: forming an auxiliary silicon material layer on the substrate, the auxiliary silicon material layer covering the first memory cell 300, the second memory cell 400, and the conductive contact region 520; forming a mask layer on the auxiliary silicon material layer and patterning the mask layer; using the patterned mask layer as a mask, removing a portion of the auxiliary silicon material layer other than the conductive contact region 520 to form the auxiliary diffusion layer 530 on the conductive contact region 520.

[0079] like Figure 4 As shown, an auxiliary silicon material layer is formed on the substrate, which covers the surfaces of the first memory cell 300, the second memory cell 400, and the conductive contact area 520.

[0080] Next, a mask layer (not shown) is formed on the auxiliary silicon material layer, and the mask layer is patterned to obtain a patterned mask layer (not shown). The process of patterning the mask layer may include: depositing a photoresist material layer on the mask layer, and photolithographically patterning the photoresist material to form a patterned mask layer. The patterned mask layer may form openings in various regions except for the conductive contact region 520. Through exposure and development operations, the patterned mask layer can be used as a mask to transfer the patterned mask layer onto the auxiliary silicon material layer, and by removing a portion of the auxiliary silicon material layer except for the conductive contact region 520, an opening is formed on the conductive contact region 520 as shown. Figure 5 The auxiliary diffusion layer 530 is shown.

[0081] For example, the mask layer may consist of at least one layer of dielectric material, such as a nitride material like silicon nitride.

[0082] In operation 206, at least one layer of metallic material 540 is formed on the auxiliary diffusion layer 530.

[0083] In some embodiments, the material of the at least one metal material layer 540 includes one or more of cobalt, titanium, nickel, and nickel-platinum. Of course, in some other embodiments, the material of the metal material layer 540 may also be other metals or metal alloys that do not react with the dielectric material but only with the auxiliary diffusion layer 530.

[0084] The materials of each metal material layer 540 in the multilayer metal material layer 540 can be different or the same.

[0085] In this embodiment, the material of the metal material layer 540 includes cobalt. The formation of at least one metal material layer 540 may include forming a cobalt metal layer on the auxiliary diffusion layer 530.

[0086] In some embodiments, after forming at least one metal material layer 540 on the auxiliary diffusion layer 530, the method includes forming a diffusion barrier layer 550 on the metal material layer 540.

[0087] In an embodiment, such as Figure 6 As shown, at least one metal material layer 540 is first formed on the auxiliary diffusion layer 530, and then at least one diffusion barrier layer 550 is formed on the surface of the uppermost metal material layer 540. For example, a diffusion barrier layer 550 is deposited on the surface of a cobalt metal layer. Exemplarily, the material of the diffusion barrier layer 550 may include titanium nitride.

[0088] The purpose of the deposited diffusion barrier layer 550 is to prevent the metal in the metal material layer 540 from diffusing or flowing during subsequent annealing operations. It can also protect the metal material layer 540 from the diffusion of surrounding impurities into the metal material layer 540 or to other locations through the metal material layer 540, thus preventing adverse effects.

[0089] For example, the metal material layer 540 and the diffusion barrier layer 550 can be formed using suitable deposition processes. Suitable deposition processes may include, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), low-pressure CVD, metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), sputtering, laser ablation, etc.

[0090] It should be noted that if the first word line grid 310 and the second word line grid 410 are respectively formed on the sidewalls of the first spacer 340 and the second spacer 440, which are respectively arranged opposite to each other, the auxiliary diffusion layer 530, the metal material layer 540 and the subsequent metal silicide layer are formed between the first spacer 340 and the second spacer 440.

[0091] In operation 206, an annealing operation is performed to form a metal silicide layer on the substrate based on the auxiliary diffusion layer 530 and the at least one metal material layer 540.

[0092] In one embodiment, an annealing operation is performed at least once to promote the reaction between the auxiliary diffusion layer 530 and at least one metal material layer 540 to generate a metal silicide layer on the substrate.

[0093] In some embodiments, such as Figure 7 and Figure 8 As shown, the annealing operation, forming a metal silicide layer on the substrate based on the auxiliary diffusion layer 530 and the at least one metal material layer 540, includes:

[0094] A first annealing operation is performed to form an intermediate metal silicide layer 710 on the substrate, which is based on the auxiliary diffusion layer 530 and the at least one metal material layer 540.

[0095] Remove unreacted residual metal material from the at least one metal material layer 540;

[0096] A second annealing operation is performed to transform the intermediate metal silicide layer 710 into the metal silicide layer 810.

[0097] In this process, the annealing temperature of the first annealing operation is lower than that of the second annealing operation. For example, the first annealing operation is a low-temperature annealing, and the second annealing operation is a high-temperature annealing.

[0098] In some embodiments, the first annealing operation is a rapid thermal annealing operation, with an annealing temperature of 400°C to 600°C and an annealing time of 20 to 60 seconds.

[0099] In some embodiments, the second annealing operation is a rapid thermal annealing operation, with an annealing temperature of 800°C to 900°C and an annealing time of 20 to 60 seconds.

[0100] In this embodiment, taking the metal material layer 540 as including cobalt and the auxiliary diffusion layer 530 as including amorphous silicon as an example, during the first annealing operation, cobalt is the main diffusing agent. The cobalt diffuses into the auxiliary diffusion layer 530 and reacts with the amorphous silicon in the auxiliary diffusion layer 530 to form... Figure 7 The intermediate metal silicide layer 710 (e.g., a Co2Si layer) is shown. After performing the first annealing operation, unreacted residual cobalt metal material in at least one metal material layer 540 can be removed by an etching process. During the second annealing operation, silicon is the main diffusing agent, and silicon diffuses into the intermediate metal silicide layer 710 to transform the intermediate metal silicide layer 710 (e.g., the Co2Si layer) into the desired metal silicide layer 810 (CoSi2), as shown. Figure 8 As shown in the image.

[0101] It should be noted that during or after the annealing operation, the amorphous silicon in the auxiliary diffusion layer 530 can be transformed into crystalline silicon.

[0102] In some embodiments, before forming the auxiliary diffusion layer 530 on the conductive contact region 520, the method further includes: forming a protective layer on the substrate, the protective layer covering the first memory cell 300, the second memory cell 400 and the conductive contact region 520; and removing a portion of the protective layer on the conductive contact region 520.

[0103] One or more protective layers (not shown) are first formed on the substrate, covering the first memory cell 300, the second memory cell 400, and the conductive contact region 520. Then, a portion of the protective layer on the conductive contact region 520 is removed, leaving only the protective layer at other locations. By forming a protective layer on the non-conductive contact region 520, damage to the non-conductive contact region 520 during subsequent operations can be prevented, and diffusion of dopants from the first memory cell 300 and the second memory cell 400 on the substrate into the conductive contact region 520 can also be prevented.

[0104] In one embodiment, the protective layer is made of oxygen-rich silicon dioxide. Of course, in other embodiments, the protective layer may be made of silicon nitride or other suitable materials.

[0105] In this embodiment, the thickness of the protective layer ranges from 300 angstroms to 400 angstroms. For example, the thickness of the protective layer can be 310 angstroms, 330 angstroms, 350 angstroms, 360 angstroms, 375 angstroms, or 390 angstroms.

[0106] In some embodiments, the method further includes: forming a conductive structure on the conductive contact region 520, the conductive structure being electrically connected to a source / drain region below the conductive contact region 520 via the metal silicide layer.

[0107] In an embodiment, a conductive structure (not shown) is formed on the conductive contact area 520. The conductive structure may protrude from the groove where the conductive contact area 520 is located. The conductive structure is electrically connected to the source / drain region below the conductive contact area 520 through the metal silicide layer.

[0108] In some embodiments, the conductive structure may include a conductive via and a conductive layer. The conductive via may be at least partially disposed in the groove where the conductive contact area 520 is located. One end of the conductive via is electrically connected to the metal silicide layer, and the other end is connected to the conductive layer. The conductive layer does not directly contact the first memory cell 300 and the second memory cell 400. A dielectric layer may be disposed below the conductive layer for electrical isolation. The conductive via at least partially passes through an opening in the dielectric layer and extends to the conductive layer.

[0109] For example, the filling material for conductive vias includes, but is not limited to, conductive materials such as copper, nickel, titanium, aluminum, and their alloys. The conductive layer can be a wire, which can be selected from conductive materials similar to those used in the conductive via. The dielectric layer material can include, but is not limited to, silicon oxide, silicon nitride, silicon carbide, phosphosilicate glass, silicate glass, or combinations thereof.

[0110] It should be noted that the accompanying drawings provided in the above embodiments have been simplified for better understanding of this application. In the embodiments of this application, the semiconductor device may be included in a microprocessor, a memory cell, and / or an integrated circuit. Furthermore, in the embodiments of this application, the method may further include subsequent manufacturing processes to form various components required for the semiconductor device, such as contact components, metal interconnect components, etc.

[0111] This application also provides a semiconductor device that can be manufactured using the above-described method. See also Figures 3 to 9 As shown, the semiconductor device includes a substrate, a first memory cell 300, a second memory cell 400, and a metal silicide layer.

[0112] A first memory cell 300 and a second memory cell 400 are formed in a memory region of a substrate. The first memory cell 300 includes a first word line gate 310, and the second memory cell 400 includes a second word line gate 410 disposed opposite to the first word line gate 310. A conductive contact region 520 is provided between the first word line gate 310 of the first memory cell 300 and the second word line gate 410 of the second memory cell 400.

[0113] A metal silicide layer 810 is formed on the conductive contact region 520, the metal silicide layer being generated based on an auxiliary diffusion layer 530 and at least one metal material layer 540 formed on the conductive contact region 520.

[0114] For example, the substrate can be a bulk semiconductor, a silicon-on-insulator (SOI), a silicon-on-insulator (SSOI), a silicon-germanium-on-insulator (SiGeOI), or a germanium-on-insulator (GeOI), etc., which can be p-type doped, n-type doped, or undoped. The SOI substrate is a semiconductor material layer formed on an insulating layer, which can be, for example, a buried oxide layer or a silicon oxide layer, disposed on a silicon substrate or a glass substrate. Specifically, the semiconductor material of the substrate can include one or more of silicon, germanium, compound semiconductors, and alloy semiconductors. The compound semiconductor can be one or more of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide. The alloy semiconductor can be one or more of silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and gallium arsenide phosphide.

[0115] For example, the first word line gate 310 and the second word line gate 410 may be made of semiconductor materials, such as polysilicon. In other examples, the first control gate 330 and the second control gate 430 may be made of metal, metal alloy, monocrystalline silicon, or a combination thereof.

[0116] In an embodiment, the material of the auxiliary diffusion layer 530 may include amorphous silicon.

[0117] In this embodiment, the thickness of the auxiliary diffusion layer 530 can range from 20 angstroms to 100 angstroms.

[0118] The material of the at least one metal material layer 540 includes one or more of cobalt, titanium, nickel, and nickel-platinum. In one embodiment, the material of the metal material layer 540 includes cobalt. Of course, in some other embodiments, the material of the metal material layer 540 may also be other metals or metal alloys that do not react with the dielectric material but only with the auxiliary diffusion layer 530.

[0119] In some embodiments, see Figure 6 The semiconductor device also includes a diffusion barrier layer 550 formed on a metal material layer 540. In embodiments, the material of the diffusion barrier layer 550 may include titanium nitride.

[0120] In some embodiments, a first spacer 340 and a second spacer 440 are respectively formed on the sidewalls of the first word line gate 310 and the second word line gate 410, and the metal silicide layer is formed between the first spacer 340 and the second spacer 440.

[0121] For example, the first spacer 340 and the second spacer 440 may be made of a suitable dielectric material, such as an oxide material or a nitride material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0122] In some embodiments, the first memory cell 300 includes a first floating gate 320 and a first control gate 330 stacked together, with a first isolation layer (not shown) between the first floating gate 320 and the first control gate 330 and the first word line gate 310. The second memory cell 400 includes a second floating gate 420 and a second control gate 430 stacked together, with a second isolation layer (not shown) between the second floating gate 420 and the second control gate 430 and the second word line gate 410.

[0123] For example, the first floating gate 320 and the second floating gate 420 may be made of semiconductor materials, such as polysilicon. Specifically, the first floating gate 320 and the second floating gate 420 may be made of P-type or N-type polysilicon. In other examples, the first floating gate 320 and the second floating gate 420 may be made of metal, metal alloy, monocrystalline silicon, or combinations thereof.

[0124] The first control gate 330 and the second control gate 430 may be made of semiconductor materials, such as polycrystalline silicon. In other exemplary embodiments, the first control gate 330 and the second control gate 430 may be made of metal, metal alloy, monocrystalline silicon, or a combination thereof.

[0125] In some embodiments, the semiconductor device further includes a conductive structure. As an example only, the conductive structure may include a conductive via and a conductive layer. The conductive via may be at least partially disposed in the groove containing the conductive contact area 520. One end of the conductive via is electrically connected to a metal silicide layer, and the other end is connected to the conductive layer. The conductive layer does not directly contact the first memory cell 300 and the second memory cell 400. A dielectric layer may be disposed below the conductive layer for electrical isolation. The conductive via at least partially passes through an opening in the dielectric layer and extends to the conductive layer.

[0126] For example, the filling material for conductive vias includes, but is not limited to, conductive materials such as copper, nickel, titanium, aluminum, and their alloys. The conductive layer can be a wire, which can be selected from conductive materials similar to those used in the conductive via. The dielectric layer material can include, but is not limited to, silicon oxide, silicon nitride, silicon carbide, phosphosilicate glass, silicate glass, or combinations thereof.

[0127] Some embodiments of this application also provide an electronic device, which includes the semiconductor device and printed circuit board (PCB) described in any of the above embodiments. The semiconductor device and the printed circuit board are electrically connected to enable signal communication.

[0128] In some embodiments, the electronic device is, for example, a consumer electronics product, a home electronics product, or an in-vehicle electronics product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and drones. Home electronics products include smart door locks, televisions, remote controls, refrigerators, and rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners). In-vehicle electronics products include car navigation systems and car DVDs. Of course, the electronic device can also be any intermediate product including semiconductor devices. This application does not impose any special limitations on the specific form of the above-described electronic device.

[0129] After being packaged, semiconductor devices can be used in electronic devices in the form of chips. Of course, they can also be used directly in electronic devices without packaging.

[0130] The technical effects achievable by the electronic device provided in this application are the same as those achievable by the semiconductor device described in any of the above embodiments, and will not be repeated here.

[0131] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0132] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for device, apparatus, or equipment embodiments, since they are basically similar to the method embodiments, the description is relatively simple; relevant parts can be referred to the description of the method embodiments.

[0133] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises: forming first memory cells and second memory cells arranged in intervals on a memory area of a substrate, the first memory cells having first word line gates and the second memory cells having second word line gates, and the first word line gates and the second word line gates having a conductive contact area therebetween; forming an auxiliary diffusion layer on the conductive contact area; forming at least one metal material layer on the auxiliary diffusion layer; performing an annealing operation to form a metal silicide layer on the substrate based on the auxiliary diffusion layer and the at least one metal material layer.

2. The method of claim 1, wherein, The forming of the auxiliary diffusion layer on the conductive contact area comprises: forming an auxiliary silicon material layer on the substrate, the auxiliary silicon material layer covering the first memory cells, the second memory cells and the conductive contact area; forming a mask layer on the auxiliary silicon material layer and patterning the mask layer; using the patterned mask layer as a mask, removing part of the auxiliary silicon material layer other than the conductive contact area to form an auxiliary diffusion layer on the conductive contact area.

3. The method of claim 1, wherein, The auxiliary diffusion layer satisfies at least one of the following conditions: the material of the auxiliary diffusion layer comprises amorphous silicon; the thickness of the auxiliary diffusion layer is 20 angstroms to 100 angstroms.

4. The method according to any of claims 1 to 3, characterized in that, The performing of the annealing operation to form a metal silicide layer on the substrate based on the auxiliary diffusion layer and the at least one metal material layer comprises: performing a first annealing operation to form an intermediate metal silicide layer on the substrate based on the auxiliary diffusion layer and the at least one metal material layer; removing residual metal material in the at least one metal material layer that has not reacted; performing a second annealing operation to convert the intermediate metal silicide layer into the metal silicide layer.

5. The method of claim 4, wherein, The first annealing operation is a rapid thermal annealing operation, the annealing temperature is 400 DEG C to 600 DEG C, and the annealing time is 20 seconds to 60 seconds; and / or, the second annealing operation is a rapid thermal annealing operation, the annealing temperature is 800 DEG C to 900 DEG C, and the annealing time is 20 seconds to 60 seconds.

6. The method according to any one of claims 1 to 3, characterized in that, The material of the at least one metal material layer comprises at least one of cobalt, titanium and nickel.

7. The method according to any one of claims 1 to 3, characterized in that, After the forming of the at least one metal material layer on the auxiliary diffusion layer, the method comprises: forming a diffusion barrier layer on the metal material layer; wherein the material of the diffusion barrier layer comprises titanium nitride.

8. The method of any one of claims 1-3, wherein, Before the forming of the auxiliary diffusion layer on the conductive contact area, the method further comprises: forming a protective layer on the substrate, the protective layer covering the first memory cells, the second memory cells and the conductive contact area; removing part of the protective layer on the conductive contact area.

9. The method of claim 9, wherein, The protective layer satisfies at least one of the following conditions: the material of the protective layer comprises oxygen-rich silicon dioxide; the thickness of the protective layer is 300 angstroms to 400 angstroms.

10. The method of any one of claims 1-3, wherein, The method further comprises: forming a conductive structure on the conductive contact area, the conductive structure being electrically connected to a source / drain region below the conductive contact area through the metal silicide layer.

11. A semiconductor device, characterized by comprising: The semiconductor device comprises: forming a first memory cell and a second memory cell in a memory region of a substrate; the first memory cell comprises a first word line gate, the second memory cell comprises a second word line gate oppositely arranged with the first word line gate, and the first word line gate of the first memory cell and the second word line gate of the second memory cell have a conductive contact region therebetween; forming a metal silicide layer on the conductive contact region, the metal silicide layer is formed based on an auxiliary diffusion layer and at least one layer of metal material layer formed on the conductive contact region.

12. The semiconductor device of claim 11, wherein, The semiconductor device also satisfies at least one of the following conditions: a first spacer and a second spacer are respectively formed on the sidewalls of the first word line gate and the second word line gate, and the metal silicide layer is formed between the first spacer and the second spacer; the first memory cell comprises a first floating gate and a first control gate which are arranged in a stack, and the first floating gate and the first control gate are provided with a first isolation layer between the first floating gate and the first control gate and between the first floating gate and the first word line gate; the second memory cell comprises a second floating gate and a second control gate which are arranged in a stack, and the second floating gate and the second control gate are provided with a second isolation layer between the second floating gate and the second control gate and between the second floating gate and the second word line gate.

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