Semiconductor device

Abstract

A semiconductor device may include: a bit line extending in a first horizontal direction; a plurality of vertical channel patterns on the bit line and spaced apart from each other in a first horizontal direction; two word lines extending in a second horizontal direction between adjacent vertical channel patterns of the plurality of vertical channel patterns, the second horizontal direction intersecting the first horizontal direction; a plurality of contact plugs contacting upper portions of the plurality of vertical channel patterns; and an isolation insulation structure between the plurality of contact plugs, in which the isolation insulation structure includes: a lower insulation pattern; an upper insulating pattern on the lower insulating pattern; and insulating spacers on sidewalls of the upper insulating pattern and upper sidewalls of the lower insulating pattern.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more specifically, to semiconductor devices including vertical channel transistors. Background Technology

[0002] Increasing the integration density of integrated circuit devices can help achieve high performance and economic viability. Specifically, the integration density of memory devices is a crucial factor determining the economic viability of a product. The integration density of two-dimensional (2D) memory devices is primarily determined by the area of ​​the memory cell unit, and is therefore greatly influenced by the level of micropatterning technology. However, due to the need for expensive equipment to form micropatterns and the limited area of ​​the chip die, the integration density of 2D memory devices remains limited, although it is increasing. Summary of the Invention

[0003] One or more embodiments of this disclosure provide semiconductor devices including vertical channel transistors, which can have high electrical reliability and high device stability.

[0004] The embodiments disclosed herein are not limited to those mentioned above, and those skilled in the art will clearly understand from the following description other aspects not mentioned.

[0005] According to one aspect of this disclosure, a semiconductor device includes: a bit line extending in a first horizontal direction; a plurality of vertical channel patterns spaced apart from each other on the bit line and in the first horizontal direction; two word lines extending in a second horizontal direction between adjacent vertical channel patterns of the plurality of vertical channel patterns, the second horizontal direction intersecting the first horizontal direction; a plurality of contact plugs contacting upper portions of the plurality of vertical channel patterns; and an insulating structure between the plurality of contact plugs, wherein the insulating structure includes: a lower insulating pattern; an upper insulating pattern on the lower insulating pattern; and insulating spacers on the sidewalls of the upper insulating pattern and the upper sidewalls of the lower insulating pattern. The upper width of each of the plurality of contact plugs in the first horizontal direction may be smaller than the lower width of each of the plurality of contact plugs in the first horizontal direction, and the upper width of the insulating structure in the first horizontal direction may be greater than the lower width of the insulating structure in the first horizontal direction.

[0006] According to one aspect of this disclosure, a semiconductor device includes: a bit line extending in a first horizontal direction; a plurality of vertical channel patterns spaced apart from each other on the bit line in the first horizontal direction; two word lines extending in a second horizontal direction between adjacent vertical channel patterns of the plurality of vertical channel patterns, the second horizontal direction intersecting the first horizontal direction; a plurality of contact plugs contacting upper portions of the plurality of vertical channel patterns; and an isolation insulating structure between the plurality of contact plugs, wherein the isolation insulating structure includes: a lower insulating pattern having a first width in the first horizontal direction; and an upper insulating pattern on the lower insulating pattern and having a second width greater than the first width. The bottom surface of the lower insulating pattern may be curved.

[0007] According to one aspect of this disclosure, a semiconductor device includes: a bit line extending in a first horizontal direction; a plurality of vertical channel patterns spaced apart from each other on the bit line and in the first horizontal direction; two word lines extending in a second horizontal direction between a first vertical channel pattern and a second vertical channel pattern of the plurality of vertical channel patterns, the first vertical channel pattern and the second vertical channel pattern being adjacent to each other, the second horizontal direction intersecting the first horizontal direction; a back gate electrode extending in a second horizontal direction between a second vertical channel pattern and a third vertical channel pattern of the plurality of vertical channel patterns, the second vertical channel pattern and the third vertical channel pattern being adjacent to each other; a plurality of contact plugs contacting upper portions of the plurality of vertical channel patterns; an isolation insulating structure between the plurality of contact plugs; and a capacitor structure on the plurality of contact plugs and the isolation insulating structure. The plurality of contact plugs may include: a first conductive pattern comprising doped polysilicon; a second conductive pattern comprising a metal silicide on the first conductive pattern; and a third conductive pattern comprising a metal on the second conductive pattern. The insulating structure may include: a lower insulating pattern; an upper insulating pattern on the lower insulating pattern; and insulating spacers on the sidewalls of the upper insulating pattern and the upper sidewalls of the lower insulating pattern. Attached Figure Description

[0008] The above and / or other aspects will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 This illustrates a planar layout of a semiconductor device according to one or more embodiments;

[0010] Figure 2 It is according to one or more embodiments along Figure 1 A cross-sectional view taken by line X1-X1' in the diagram;

[0011] Figure 3 It is based on one or more implementation methods. Figure 2 A magnified view of region CX in the image;

[0012] Figure 4 It is a cross-sectional view of a semiconductor device according to one or more embodiments;

[0013] Figure 5 It is a cross-sectional view of a semiconductor device according to one or more embodiments;

[0014] Figure 6 It is a cross-sectional view of a semiconductor device according to one or more embodiments;

[0015] Figure 7 It is a cross-sectional view of a semiconductor device according to one or more embodiments;

[0016] Figure 8A It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0017] Figure 8B It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0018] Figure 9A It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0019] Figure 9B It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0020] Figure 10A It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0021] Figure 10B It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0022] Figure 11A It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0023] Figure 11B It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0024] Figure 12A It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0025] Figure 12B It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0026] Figure 13A It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0027] Figure 13B It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0028] Figure 14A It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0029] Figure 14B It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0030] Figure 15A It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0031] Figure 15B It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0032] Figure 16A It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0033] Figure 16B It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0034] Figure 17A It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0035] Figure 17B It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0036] Figure 18A It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0037] Figure 18B It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0038] Figure 19A It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0039] Figure 19B It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0040] Figure 20A It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0041] Figure 20B It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0042] Figure 21A It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0043] Figure 21B It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0044] Figure 22A It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0045] Figure 22B It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0046] Figure 23A It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0047] Figure 23B It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0048] Figure 24A It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0049] Figure 24B It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0050] Figure 25 It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0051] Figure 26 It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0052] Figure 27 It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0053] Figure 28 It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0054] Figure 29 It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0055] Figure 30 It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0056] Figure 31 It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments;

[0057] Figure 32 It is a diagram of the sequential stages in a method of manufacturing a semiconductor device according to one or more embodiments; and

[0058] Figure 33 It is a block diagram of a system including semiconductor devices according to one or more embodiments. Detailed Implementation

[0059] In the following description, exemplary embodiments are described in detail with reference to the accompanying drawings.

[0060] In the specification, spatial relative terms such as "top," "bottom," "upper part," "lower part," "above," "below," "horizontal," and "vertical" are used to easily explain the positional relationship of each component when viewed from the direction shown in the accompanying drawings. Therefore, when viewed from a direction different from that shown in the accompanying drawings, the spatial relative terms representing the positional relationship of each component can be interpreted differently.

[0061] Figure 1 This illustrates a planar layout of a semiconductor device according to one or more embodiments. Figure 2 It is along Figure 1 The cross-sectional view taken by line X1-X1' in the diagram. Figure 3 yes Figure 2 A magnified view of region CX in the image.

[0062] Reference Figures 1 to 3 The semiconductor device 10 may include multiple bit lines BL, which extend longitudinally in a first horizontal direction (X direction) and are repeatedly arranged spaced apart from each other in a second horizontal direction (Y direction) that intersects with the first horizontal direction (X direction).

[0063] Multiple vertical channel patterns CHL can be arranged above each bit line BL. Multiple contact plugs 130 can be arranged above the vertical channel patterns CHL respectively. The vertical channel patterns CHL can be arranged repeatedly between each bit line BL and contact plug 130, spaced apart from each other in the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0064] Bit line BL may include metal, conductive metal nitride, metal silicide, doped polysilicon, or a combination thereof. In one or more embodiments, bit line BL may include a first conductive line 162, a second conductive line 164, and a third conductive line 166 sequentially stacked under the vertical channel pattern CHL. For example, the first conductive line 162 may include doped polysilicon, the second conductive line 164 may include metal silicide, and the third conductive line 166 may include metal, but the embodiments are not limited thereto.

[0065] Each vertical channel pattern CHL may have one end connected to the bit line BL and the opposite end connected to one of the contact plugs 130. In other words, each vertical channel pattern CHL may contact one bit line BL and one contact plug 130.

[0066] In one or more embodiments, the vertical channel pattern CHL may include silicon, such as monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In one or more embodiments, the vertical channel pattern CHL may include at least one selected from the group consisting of Ge, SiGe, SiC, GaAs, InAs, and InP.

[0067] Contact plugs 130 may be separated from bit lines BL in the vertical direction (Z direction), and a vertical channel pattern CHL may be located between contact plugs 130 and bit lines BL. Contact plugs 130 may be spaced apart in a matrix in a first horizontal direction (X direction) and a second horizontal direction (Y direction). Contact plugs 130 may be individually connected to the vertical channel pattern CHL.

[0068] Contact plugs 130 may include metals, conductive metal nitrides, metal silicides, doped polysilicon, or combinations thereof. For example, each contact plug 130 may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, doped silicon, or combinations thereof. In one or more embodiments, each contact plug 130 may include a first conductive pattern 132, a second conductive pattern 134, and a third conductive pattern 136 sequentially stacked on one of the vertical channel patterns CHL. For example, the first conductive pattern 132 may include doped polysilicon, the second conductive pattern 134 may include a metal silicide, and the third conductive pattern 136 may include a metal, but the embodiments are not limited thereto.

[0069] In the semiconductor device 10, the upper width of each contact plug 130 in the first horizontal direction (X direction) may be smaller than its lower width in the first horizontal direction (X direction). Specifically, the maximum width of the first conductive pattern 132 in the first horizontal direction (X direction) may be greater than the width of the second conductive pattern 134 in the first horizontal direction (X direction). The width of the second conductive pattern 134 in the first horizontal direction (X direction) may be substantially the same as the width of the third conductive pattern 136 in the first horizontal direction (X direction).

[0070] In one or more embodiments, the bottom surface of the first conductive pattern 132 may have a raised (recessed) shape that contacts the top surface and two sidewalls of one of the vertical channel patterns CHL. Alternatively, the bottom surface of the first conductive pattern 132 may have a flat shape.

[0071] Each contact plug 130 can pass through the insulating structure 140 and contact one of the vertical channel patterns CHL.

[0072] In the semiconductor device 10, the isolation insulation structure 140 may include a lower insulation pattern 144, an upper insulation pattern 146 on the lower insulation pattern 144, and an insulating spacer 142 arranged along the entire sidewall of the upper insulation pattern 146 and the upper sidewall of the lower insulation pattern 144.

[0073] In one or more embodiments, the insulating spacer 142 may comprise the same material as the upper insulating pattern 146. For example, the insulating spacer 142 and the upper insulating pattern 146 may include, but are not limited to, a SiN film, a SiOC film, a SiOCN film, a SiCN film, or a SiBN film. The insulating spacer 142 and the upper insulating pattern 146 may comprise an insulating material with excellent resistance to wet etching processes.

[0074] In one or more embodiments, the lower insulating pattern 144 may include a material different from the upper insulating pattern 146. For example, the lower insulating pattern 144 may include a silicon oxide film, a low-k film, or a combination thereof. A low-k film is a film having a lower dielectric constant than a silicon oxide film. For example, a low-k film may include a SiOC film or a SiCOH film, but is not limited thereto. The lower insulating pattern 144 may include an insulating material that suppresses the occurrence of parasitic capacitance.

[0075] In the semiconductor device 10, the upper width W1 of the isolation insulation structure 140 in the first horizontal direction (X direction) may be greater than its lower width W2 in the first horizontal direction (X direction).

[0076] The lower width W2 of the insulating structure 140 can correspond to the horizontal width of the lower insulating pattern 144 and can be significantly smaller than the distance W3 between two adjacent vertical channel patterns CHL. Therefore, during the process of forming the insulating structure 140, it is possible to prevent the insulating structure 140 from contacting the vertical channel patterns CHL due to undesirable uneven distribution. Furthermore, the upper width W1 of the insulating structure 140 can be smaller than the distance W3 between two adjacent vertical channel patterns CHL.

[0077] The upper width W1 of the insulating structure 140 can correspond to the sum of the horizontal widths of the insulating spacer 142 and the upper insulating pattern 146 and can be greater than the lower width W2 of the insulating structure 140. Therefore, the insulating spacer 142 and the upper insulating pattern 146 can be effectively used as barriers to prevent the penetration of etching solution in the wet etching process performed after the formation of the insulating structure 140.

[0078] In one or more embodiments, the length of the lower insulating pattern 144 in the vertical direction (Z direction) may be greater than the length of the upper insulating pattern 146 in the vertical direction (Z direction). The length of the insulating spacer 142 in the vertical direction (Z direction) may be greater than the length of the upper insulating pattern 146 in the vertical direction (Z direction).

[0079] In one or more embodiments, the vertical height of the uppermost surface of the upper insulating pattern 146 may be the same as the vertical height of the uppermost surface of the insulating spacer 142, and the bottom surface 142B of the insulating spacer 142 may be inclined (tapered). The vertical height of the lowermost (bottom) surface of the lower insulating pattern 144 may be lower than the vertical height of the uppermost (top) surface of each vertical channel pattern CHL. The bottom surface 144B of the lower insulating pattern 144 may be circular (curved).

[0080] In the semiconductor device 10, the first conductive pattern 132 of each contact plug 130 may contact the insulating spacer 142 and the lower insulating pattern 144. The second conductive pattern 134 and the third conductive pattern 136 of each contact plug 130 may contact the insulating spacer 142, but not the lower insulating pattern 144.

[0081] Multiple back gate electrodes BG and multiple word lines WL can be arranged above the bit line BL. The back gate electrodes BG and word lines WL can extend longitudinally in a second horizontal direction (Y direction) between the bit line BL and the contact plug 130. The back gate electrodes BG and word lines WL can be spaced apart from each other in a first horizontal direction (X direction).

[0082] In a first horizontal direction (X direction), a back gate electrode BG and a word line WL are arranged parallel above the bit line BL. One back gate electrode BG may be arranged alternately with a pair of word lines WL, and the back gate electrode BG may be separated from the pair of word lines WL. A vertical channel pattern CHL lies between the back gate electrode BG and the pair of word lines WL. In other words, the multiple word lines WL can be arranged such that a pair of adjacent word lines WL lies between two adjacent back gate electrodes BG.

[0083] A back gate electrode BG may extend longitudinally in a second horizontal direction (Y direction) between a pair of vertical channel patterns CHL that are adjacent to each other in a first horizontal direction (X direction). The plurality of back gate electrodes BG may be separated from the bit line BL and the contact plug 130 in a vertical direction (Z direction).

[0084] The back gate electrode (BG) may include metal, conductive metal nitride, doped polysilicon, or combinations thereof. For example, each back gate electrode (BG) may include, but is not limited to, Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, doped polysilicon, or combinations thereof.

[0085] The multiple word lines WL may include metals, conductive metal nitrides, or combinations thereof. For example, word lines WL may include, but are not limited to, Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, or combinations thereof.

[0086] The semiconductor device 10 may include a plurality of back gate dielectric films 152, each covering a surface of a back gate electrode BG. Each back gate dielectric film 152 may be located between a pair of vertical channel patterns CHL, each on an opposite side of a back gate electrode BG between the vertical channel patterns CHL. Each back gate dielectric film 152 may be in contact with the pair of vertical channel patterns CHL.

[0087] A first cover insulating pattern 110 may be located between a pair of adjacent vertical channel patterns CHL and between the top surface of a back gate dielectric film 152 and a plurality of contact plugs 130. A second cover insulating pattern 158 may be located between a pair of adjacent vertical channel patterns CHL and between the back gate electrode BG and the bit line BL. The first cover insulating pattern 110, the back gate electrode BG, and the second cover insulating pattern 158 may overlap each other in the vertical direction (Z direction).

[0088] The first insulating cover pattern 110 and the second insulating cover pattern 158 may each comprise a silicon oxide film, a silicon nitride film, or a combination thereof. In one or more embodiments, the first insulating cover pattern 110 and the second insulating cover pattern 158 may comprise different materials from each other. For example, the first insulating cover pattern 110 may comprise a silicon oxide film, and the second insulating cover pattern 158 may comprise a silicon nitride film. In one or more embodiments, the first insulating cover pattern 110 and the second insulating cover pattern 158 may comprise the same material. For example, the first insulating cover pattern 110 and the second insulating cover pattern 158 may comprise a silicon oxide film or a silicon nitride film.

[0089] Each word line WL can be separated from the bit line BL and each contact plug 130 in the vertical direction (Z direction). A pair of word lines WL can be located between two adjacent back gate electrodes BG in the first horizontal direction (X direction). The pair (two) word lines WL can be separated from their adjacent back gate electrodes BG in the first horizontal direction (X direction), and a vertical channel pattern CHL is located between the pair of word lines WL and the back gate electrodes BG.

[0090] The interlayer pattern 124 may be located between the pair of word lines WL between a pair of adjacent vertical channel patterns CHL. A first buried insulating pattern 126 may be located between the pair of word lines WL and a plurality of contact plugs 130. A second buried insulating pattern 160 may be located between the pair of word lines WL and the bit line BL. The pair of word lines WL, the first buried insulating pattern 126, and the second buried insulating pattern 160 located between a pair of adjacent vertical channel patterns CHL may overlap each other in the vertical direction (Z direction).

[0091] The pair of letter lines WL can be separated from the contact plug 130, and a first buried insulating pattern 126 is located between the pair of letter lines WL and the contact plug 130. The pair of letter lines WL can be separated from the bit line BL, and a second buried insulating pattern 160 is located between the pair of letter lines WL and the bit line BL. The length of the second covering insulating pattern 158 in the vertical direction (Z direction) can be substantially the same as or similar to the length of the second buried insulating pattern 160 in the vertical direction (Z direction).

[0092] For example, the interlayer pattern 124, the first buried insulating pattern 126, and the second buried insulating pattern 160 may each comprise a silicon oxide film, a silicon nitride film, or a combination thereof. In one or more embodiments, the interlayer pattern 124, the first buried insulating pattern 126, and the second buried insulating pattern 160 may comprise the same or similar materials. In one or more embodiments, at least one selected from the group consisting of the interlayer pattern 124, the first buried insulating pattern 126, and the second buried insulating pattern 160 may comprise a different material than the others. For example, each of the interlayer pattern 124, the first buried insulating pattern 126, and the second buried insulating pattern 160 may comprise a silicon nitride film, but is not limited thereto.

[0093] Gate dielectric films 120 may be located between each of the plurality of word lines WL and the vertical channel pattern CHL adjacent to each word line WL. A pair of gate dielectric films 120 may be located between a pair of adjacent vertical channel patterns CHL, and a pair of word lines WL may be located between the pair of gate dielectric films 120. Each gate dielectric film 120 may include one end in contact with a bit line BL and the opposite end in contact with one of the contact plugs 130.

[0094] In one or more embodiments, the gate dielectric film 120 and the back gate dielectric film 152 may each comprise a silicon oxide film, a high-k film, or a combination thereof. A high-k film may refer to a dielectric film having a higher dielectric constant than a silicon oxide film. In an embodiment, the gate dielectric film 120 and the back gate dielectric film 152 may each comprise at least one material selected from the group consisting of silicon oxide, hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium nitride (HfON), hafnium silicon nitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium nitride (ZrON), zirconium silicon nitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0095] Multiple back gate electrodes BG, multiple word lines WL, multiple channel patterns CHL, multiple back gate dielectric films 152 and multiple gate dielectric films 120 can be formed between the bit lines BL and the contact plugs 130, and can form multiple vertical channel transistors.

[0096] A capacitor structure CS can be arranged on contact plugs 130 and isolation insulation structure 140. The capacitor structure CS may include multiple lower electrodes LE, a capacitor dielectric film DL conformally covering the surface of the lower electrodes LE, and an upper electrode UE covering the lower electrodes LE, with the capacitor dielectric film DL positioned between the upper electrode UE and the lower electrodes LE. Each lower electrode LE can be connected to one of the vertical channel patterns CHL via one of the contact plugs 130. A third conductive pattern 136 of each contact plug 130 can serve as a landing pad for contacting one of the lower electrodes LE.

[0097] According to one or more embodiments of this disclosure, even when the components required to form a vertical channel transistor are arranged in a relatively narrow and long space as the semiconductor device 10 is miniaturized and has a high integration density, it is possible to prevent the components of the vertical channel transistor (e.g., the isolation insulation structure 140) from contacting the vertical channel pattern CHL during the process of forming the isolation insulation structure 140 due to undesirable non-uniform distribution. Therefore, a structure can be provided that can sufficiently ensure the contact area between the vertical channel pattern CHL and the contact plug 130.

[0098] Ultimately, by arranging an insulating structure 140 (which has an upper width W1 different from the lower width W2) between adjacent contact plugs 130, the semiconductor device 10 of one or more embodiments of this disclosure can have high electrical reliability and device stability.

[0099] Figures 4 to 7 It is a cross-sectional view of a semiconductor device according to one or more embodiments.

[0100] The semiconductor devices 20, 30, 40, and 50 described below, as well as the materials of the components, are consistent with the above references. Figures 1 to 3 Most of those are essentially the same or similar. Therefore, for ease of description, the differences from semiconductor device 10 will be described below.

[0101] Reference Figure 4 The semiconductor device 20 may include an insulating structure 240 that separates the contact plugs 130 from each other.

[0102] In the semiconductor device 20 of this embodiment, the isolation insulation structure 240 may include a lower insulation pattern 244, an upper insulation pattern 246 on the lower insulation pattern 244, and an insulating spacer 242 disposed on the entire sidewall of the upper insulation pattern 246 and the upper sidewall of the lower insulation pattern 244.

[0103] In the semiconductor device 20 of this embodiment, the vertical height of the uppermost surface of the upper insulating pattern 246 can be the same as the vertical height of the uppermost surface of the insulating spacer 242, and the vertical height of the lowermost surface of the upper insulating pattern 246 can be higher than the vertical height of the lowermost surface of the insulating spacer 242. The vertical height of the lowermost surface of the upper insulating pattern 246 can be lower than the vertical height of the uppermost surface of the first conductive pattern 132 of each contact plug 130.

[0104] Reference Figure 5 The semiconductor device 30 may include an insulating structure 340 that separates the contact plugs 130 from each other.

[0105] In the semiconductor device 30 of this embodiment, the isolation insulating structure 340 may include a lower insulating pattern 344 and an upper insulating pattern 346 on the lower insulating pattern 344. The upper width of the isolation insulating structure 340 in the first horizontal direction (X direction) may be greater than the lower width of the isolation insulating structure 340 in the first horizontal direction (X direction). The lower width of the isolation insulating structure 340 may correspond to the horizontal width of the lower insulating pattern 344, and the upper width of the isolation insulating structure 340 may correspond to the horizontal width of the upper insulating pattern 346. The lower insulating pattern 344 may include a material different from the material of the upper insulating pattern 346.

[0106] In the semiconductor device 30 of this embodiment, the first conductive pattern 132 of each contact plug 130 may contact the lower insulating pattern 344 and the upper insulating pattern 346 of the isolation insulating structure 340. The second conductive pattern 134 and the third conductive pattern 136 of each contact plug 130 may contact the upper insulating pattern 346, but may not contact the lower insulating pattern 344.

[0107] Reference Figure 6 The semiconductor device 40 may include a plurality of contact plugs 430, which pass through the isolation insulation structure 140 and respectively contact a plurality of vertical channel patterns CHL.

[0108] In the semiconductor device 40 of this embodiment, the contact plug 430 may comprise a single structure of doped polysilicon. The upper width of each contact plug 430 in the first horizontal direction (X direction) may be smaller than the lower width of each contact plug 430 in the first horizontal direction (X direction). The contact plug 430 may contact the insulating spacer 142 and the lower insulating pattern 144 of the insulating structure 140.

[0109] In the semiconductor device 40 of this embodiment, the bottom surface of each contact plug 430 may have an uneven shape, which contacts the top surface and two sidewalls of one of the vertical channel patterns CHL. Alternatively, the bottom surface of each contact plug 430 may have a flat shape.

[0110] Reference Figure 7 The semiconductor device 50 may include a plurality of contact plugs 530, which pass through the isolation insulation structure 140 and respectively contact a plurality of vertical channel patterns CHL.

[0111] In the semiconductor device 50 of this embodiment, each contact plug 530 may include a lower conductive pattern 534 and an upper conductive pattern 536 sequentially stacked on one of the vertical channel patterns CHL. For example, the lower conductive pattern 534 may include a metal silicide, and the upper conductive pattern 536 may include a metal. However, embodiments of this disclosure are not limited thereto.

[0112] In the semiconductor device 50 of this embodiment, the upper width of each contact plug 530 in the first horizontal direction (X direction) may be smaller than the lower width of each contact plug 530 in the first horizontal direction (X direction). Specifically, the upper width of the upper conductive pattern 536 may be smaller than the lower width of the upper conductive pattern 536. The width of the lower conductive pattern 534 in the first horizontal direction (X direction) may be substantially the same as the lower width of the upper conductive pattern 536 in the first horizontal direction (X direction).

[0113] In the semiconductor device 50 of this embodiment, the bottom surface of the lower conductive pattern 534 may have an uneven shape, which contacts the top surface and two sidewalls of one of the vertical channel patterns CHL. Alternatively, the bottom surface of the lower conductive pattern 534 may have a flat shape.

[0114] In the semiconductor device 50 of this embodiment, the upper conductive pattern 536 may contact the insulating spacer 142 and the lower insulating pattern 144 of the isolation insulating structure 140. The lower conductive pattern 534 may contact the lower insulating pattern 144 of the isolation insulating structure 140, but may not contact the insulating spacer 142.

[0115] Figures 8A to 32 This is a diagram of the sequential stages in a method for manufacturing a semiconductor device according to one or more embodiments.

[0116] Specifically, Figure 8A , Figure 9A , Figure 10A ... Figure 23A and Figure 24AThis is a planar layout showing some elements of a semiconductor device in sequential stages of a process for manufacturing a semiconductor device. In the accompanying drawing, portions marked with dashed lines are shown to aid understanding, although these portions are at the bottom and not shown from the top.

[0117] Figure 8B , Figure 9B , Figure 10B ... Figure 23B and Figure 24B as well as Figures 25 to 32 Along the sequential stages in the process of manufacturing semiconductor devices Figure 1 The cross-sectional view taken by line X1-X1' in the figure, where Figure 8B , Figure 9B , Figure 10B ... Figure 23B and Figure 24B They are respectively along Figure 8A , Figure 9A , Figure 10A ... Figure 23A and Figure 24A The cross-sectional view taken by line X1-X1' in the diagram.

[0118] exist Figures 1 to 3 and Figures 8A to 32 In this drawing, the same elements are represented by the same reference numerals, and repeated descriptions of them will be omitted below.

[0119] Reference Figure 8A and Figure 8B A substrate structure including a substrate 102, a buried insulating layer 104, and an active layer 106 can be prepared.

[0120] The substrate structure may correspond to a silicon-on-insulator (SOI) substrate. Substrate 102 may include a silicon substrate. Buried insulating layer 104 may include a silicon oxide film. Active layer 106 may include at least one selected from the group consisting of Ge, SiGe, SiC, GaAs, InAs, and InP. In one or more embodiments, active layer 106 may include an impurity-doped trap or an impurity-doped structure.

[0121] A mask pattern MP1 can be formed on the active layer 106 of the substrate structure. The mask pattern MP1 may include a silicon nitride film. In one or more embodiments, a silicon oxide film may be located between the active layer 106 and the mask pattern MP1.

[0122] By using a mask pattern MP1 as an etching mask to etch some portions of the substrate structure, a plurality of first trenches T1 can be formed. The first trenches T1 can be formed to pass through the active layer 106 and the buried insulating layer 104 in the vertical direction (Z direction) and extend longitudinally in the second horizontal direction (Y direction).

[0123] Reference Figure 9A and Figure 9B It can form separate fillings Figure 8A and Figure 8B The resulting structure contains multiple sacrificial membranes 108 in the first trench T1 portion.

[0124] The sacrificial film 108 may include a material that is etch-selective relative to the material of each of the active layer 106 and the mask pattern MP1. In one or more embodiments, the sacrificial film 108 may include, but is not limited to, metals, metal nitrides, or combinations thereof.

[0125] Reference Figure 10A and Figure 10B This can form separate fillings and separate retentions. Figure 9A and Figure 9B The resulting structure has a plurality of first covering insulating patterns 110 on the first trench T1 on the sacrificial membrane 108.

[0126] Reference Figure 11A and Figure 11B By removing Figure 10A and Figure 10B The mask pattern MP1 in the resulting structure can be exposed in the active layer 106 surrounding the first covering insulating pattern 110.

[0127] Reference Figure 12A and Figure 12B Multiple sacrificial spacer layers (SPLs) can be formed, each SPL covering a portion of one of the first overlay insulating patterns 110 and a portion of the active layer 106 surrounding said portion of the first overlay insulating pattern 110. Each sacrificial spacer layer (SPL) may comprise a silicon oxide film.

[0128] Reference Figure 13A and Figure 13B Multiple sacrificial spacers SP can be formed by etching back the sacrificial spacer layer SPL, each sacrificial spacer SP covering an opposite sidewall of one of the first overlay insulating patterns 110 in the first horizontal direction (X direction). Some portions of the active layer 106 adjacent to the first overlay insulating pattern 110 may be covered by the sacrificial spacers SP.

[0129] Reference Figure 14A and Figure 14B Multiple second trenches T2 can be formed by etching the active layer 106 using the first covering insulating pattern 110 and the sacrificial spacer SP as an etching mask.

[0130] As a result, the portion of the active layer 106 below the sacrificial spacer SP can be retained as a plurality of vertical channel patterns CHL. During the etching process of the active layer 106, the buried insulating layer 104 can be partially etched due to over-etching, thus forming a plurality of recesses 104R in the top surface of the buried insulating layer 104 respectively connected to the second trench T2.

[0131] Reference Figure 15A and Figure 15B It can form a conformal coverage Figure 14A and Figure 14B The resulting gate dielectric film 120. After forming a conductive layer that conformally covers the gate dielectric film 120, the conductive layer can be divided into multiple initial word lines PWL by partially etching the conductive layer in the recess 104R of the insulating layer 104.

[0132] Subsequently, a sandwich pattern 124 can be formed to fill the space above the initial word lines PWL. The sandwich pattern 124 can be formed to fill the space between the initial word lines PWL and cover the top surface of the initial word lines PWL. The material of the conductive layer can be the same as the material of the word lines WL.

[0133] Reference Figure 16A and Figure 16B Through back etching Figure 15A and Figure 15B The upper part of the sandwich pattern 124 in the obtained structure can be removed to expose a portion of the initial word line PWL, and multiple word lines WL can be formed by etching the exposed portion of the initial word line PWL.

[0134] Reference Figure 17A and Figure 17B It can form a coverage Figure 16A and Figure 16B The resulting structure is a first buried insulating film 126L. The material of the first buried insulating film 126L can be the same as the material of the first buried insulating pattern 126 described above.

[0135] Reference Figure 18A and Figure 18B Through the Figure 17A and Figure 17B The exposed top surface of the first buried insulating film 126L in the resulting structure is planarized to expose the vertical channel pattern CHL, and the first buried insulating pattern 126 can be formed from the first buried insulating film 126L.

[0136] In one or more embodiments, after the vertical channel pattern CHL is exposed, the height of the top of each of the first overlay insulating pattern 110, the gate dielectric film 120, and the first buried insulating pattern 126 can be reduced. Therefore, the upper portion of each vertical channel pattern CHL can be exposed.

[0137] Subsequently, a first conductive pattern 132, a second conductive pattern 134, and a third conductive pattern 136 may be sequentially stacked on the vertical channel pattern CHL. For example, the first conductive pattern 132 may include doped polysilicon, the second conductive pattern 134 may include metal silicide, and the third conductive pattern 136 may include metal, but the implementation is not limited thereto.

[0138] Reference Figure 19A and Figure 19B By using Figure 18A and Figure 18B The mask pattern on the resulting structure is used as an etching mask to partially etch each of the first conductive pattern 132, the second conductive pattern 134 and the third conductive pattern 136, which can form a third trench T3.

[0139] The third trench T3 can be formed to pass through the third conductive pattern 136, the second conductive pattern 134, and a portion of the first conductive pattern 132 in the vertical direction (Z direction). In a plan view, the third trench T3 can be presented as a single trench.

[0140] Reference Figure 20A and Figure 20B It can be seen from Figure 19A and Figure 19B The resulting structure removes the mask pattern and can form a spacer forming layer 142L. The spacer forming layer 142L can be conformally formed on the inner wall of the third trench T3 and the top surface of the third conductive pattern 136.

[0141] Reference Figure 21A and Figure 21B Through further etching Figure 20A and Figure 20B The third groove T3 in the obtained structure can form multiple fourth grooves T4.

[0142] Each fourth trench T4 can pass through the first conductive pattern 132 and through one of the first covering insulating patterns 110 or a portion of the first buried insulating pattern 126 in the vertical direction (Z direction). Therefore, a plurality of insulating spacers 142 can be formed by the spacer forming layer 142L. The first conductive pattern 132, the second conductive pattern 134, and the third conductive pattern 136 can be node-separated from each other to form a plurality of contact plugs 130.

[0143] Reference Figure 22A andFigure 22B It can form separate fillings Figure 23A and Figure 23B The resulting structure comprises a plurality of lower insulating patterns 144 for a portion of the fourth trench T4. In one or more embodiments, the lower insulating pattern 144 may comprise a silicon oxide film.

[0144] Reference Figure 24A and Figure 24B It can form a filler Figure 25 and Figure 24A The remaining portion of the fourth trench T4 in the obtained structure is the upper insulating pattern 146 on the lower insulating pattern 144.

[0145] Therefore, the insulating spacer 142, the lower insulating pattern 144, and the upper insulating pattern 146 can form an insulating structure 140. In one or more embodiments, the insulating spacer 142 and the upper insulating pattern 146 may comprise a silicon nitride film. In a plan view, the upper insulating pattern 146 may be represented as a single element.

[0146] Reference Figure 24B and Figure 26 , can Figure 25 and Figure 27 The resulting structure forms a capacitor structure CS connected to the contact plug 130 and including multiple lower electrodes LE, a capacitor dielectric film DL, and an upper electrode UE.

[0147] Reference Figure 26 It can Figure 28 and Figure 27 The resulting structure is flipped so that the vertical direction (Z direction) is reversed and the substrate 102 is facing upwards in the vertical direction (Z direction). A polishing process and a wet etching process can be sequentially performed on the substrate 102 from the exposed back side of the substrate 102, so that the buried insulating layer 104 and the sacrificial film 108 are exposed.

[0148] Reference Figure 29 , through from Figure 28 The resulting structure removes the sacrificial membrane 108, and the first covering insulation pattern 110 can be exposed through multiple fifth trenches T5.

[0149] Reference Figure 30 A back gate dielectric film 152 can be formed to conformally cover the surface of the vertical channel pattern CHL and the surface of the first covering insulating pattern 110 (which is in Figure 29 The resulting structure is exposed by the fifth trench T5, and the conductive layer 154 can be formed on the back gate dielectric film 152 to fill the remaining space of the fifth trench T5.

[0150] Reference Figure 31 Through Figure 30In the resulting structure, a portion of the conductive layer 154 is etched back, and multiple back gate electrodes BG can be formed from the conductive layer 154.

[0151] Reference Figure 32 It can form a coverage Figure 31 The second cover insulating layer 158L is used in the resulting structure for the back gate electrode BG. The material of the second cover insulating layer 158L can be the same as the second cover insulating pattern 158 described above.

[0152] Reference Figure 32 Through the Figures 1 to 3 The exposed surface of the second cover insulation layer 158L in the resulting structure is planarized to expose the vertical channel pattern CHL. As a result, the second cover insulation layer 158L can be divided into a plurality of second cover insulation patterns 158, and the exposed surface of each of the second cover insulation patterns 158, word lines WL, and a plurality of interlayer patterns 124 can be coplanar with the exposed surface of the vertical channel pattern CHL.

[0153] Reference Figure 33 , through from Figure 33 The exposed surfaces of the word line WL and the interlayer pattern 124 in the obtained structure are partially removed, and a space can be formed in the upper part of the word line WL and the upper part of the interlayer pattern 124, and a second buried insulation pattern 160 can be formed to fill the space.

[0154] Reference ​ , can ​ The resulting structure forms bit lines BL, which sequentially include a first conductive line 162, a second conductive line 164, and a third conductive line 166.

[0155] Then, can ​ The resulting structure is flipped so that the vertical direction (Z direction) is reversed and the bit line BL is facing down in the vertical direction (Z direction). As a result, it is possible to manufacture... ​ Semiconductor devices 10.

[0156] ​ It is a block diagram of a system including semiconductor devices according to one or more embodiments.

[0157] Reference ​ The system 1000 may include a controller 1010, an input / output device 1020, a storage device 1030, an interface 1040, and a bus 1050.

[0158] System 1000 may correspond to a mobile system or a system for sending or receiving information. In one or more embodiments, the mobile system may include a portable computer, a network tablet, a mobile phone, a digital music player, or a memory card.

[0159] The controller 1010 can control the executable program in the system 1000 and may include a microprocessor, digital signal processor, microcontroller, etc.

[0160] Input / output device 1020 can be used to input data to or output data to system 1000. System 1000 can be connected to external devices (such as personal computers (PCs) or networks) via input / output device 1020 and can exchange data with external devices. For example, input / output device 1020 may include a touch screen, touchpad, keyboard, or display.

[0161] Storage device 1030 may store data for operation of controller 1010 or data processed by controller 1010. Storage device 1030 may include one of the semiconductor devices 10, 20, 30, 40 and 50 of the present disclosure described above.

[0162] Interface 1040 can correspond to the data transmission channel between system 1000 and external devices. Controller 1010, input / output device 1020, storage device 1030 and interface 1040 can communicate with each other via bus 1050.

[0163] Although this disclosure has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0164] This application is based on and claims priority to Korean Patent Application No. 10-2024-0122583, filed on September 9, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device comprising: a bit line extending in a first horizontal direction; a plurality of vertical channel patterns spaced apart from each other on the bit line and in the first horizontal direction; two word lines extending in a second horizontal direction between adjacent ones of the plurality of vertical channel patterns, the second horizontal direction intersecting the first horizontal direction; a plurality of contact plugs contacting upper portions of the plurality of vertical channel patterns; and an isolation insulating structure between the plurality of contact plugs, wherein the isolation insulating structure comprises: a lower insulating pattern; an upper insulating pattern on the lower insulating pattern; and an insulating spacer on sidewalls of the upper insulating pattern and upper sidewalls of the lower insulating pattern, wherein an upper width of each of the plurality of contact plugs in the first horizontal direction is less than a lower width of each of the plurality of contact plugs in the first horizontal direction, and wherein an upper width of the isolation insulating structure in the first horizontal direction is greater than a lower width of the isolation insulating structure in the first horizontal direction.

2. The semiconductor device of claim 1, wherein a length of the lower insulating pattern in a vertical direction is greater than a length of the upper insulating pattern in the vertical direction, and wherein a length of the insulating spacer in the vertical direction is greater than the length of the upper insulating pattern in the vertical direction.

3. The semiconductor device of claim 1, wherein a bottom surface of the lower insulating pattern is lower in a vertical direction than a top surface of the plurality of vertical channel patterns, and wherein the bottom surface of the lower insulating pattern is curved.

4. The semiconductor device of claim 1, wherein a top surface of the upper insulating pattern is at a same height in a vertical direction as a top surface of the insulating spacer, and wherein a bottom surface of the insulating spacer is tapered.

5. The semiconductor device of claim 1, wherein the upper insulating pattern and the insulating spacer comprise a same material, and wherein the lower insulating pattern comprises a different material than the upper insulating pattern.

6. The semiconductor device of claim 1, wherein each of the plurality of contact plugs comprises: a first conductive pattern comprising doped polysilicon; a second conductive pattern on the first conductive pattern and comprising a metal silicide; and a third conductive pattern on the second conductive pattern and comprising a metal, wherein a width of the second conductive pattern in the first horizontal direction is equal to a width of the third conductive pattern in the first horizontal direction, and wherein a maximum width of the first conductive pattern in the first horizontal direction is greater than the width of the second conductive pattern in the first horizontal direction and the width of the third conductive pattern in the first horizontal direction.

7. The semiconductor device of claim 6, wherein a bottom surface of the first conductive pattern has a shape with a recess and contacts a top surface and sidewalls of the plurality of vertical channel patterns. ​ ​ 8. The semiconductor device of claim 6, wherein the first conductive pattern contacts the insulating spacer and the lower insulating pattern, and wherein each of the second and third conductive patterns contacts the insulating spacer and does not contact the lower insulating pattern.

9. The semiconductor device of claim 1, wherein each of the plurality of contact plugs comprises: a first conductive pattern comprising a metal silicide; and a second conductive pattern on the first conductive pattern and comprising a metal, and wherein the insulating spacer contacts the second conductive pattern and does not contact the first conductive pattern.

10. The semiconductor device of claim 1, wherein each of the plurality of contact plugs comprises doped polysilicon, wherein a top surface of the doped polysilicon is at a same height in a vertical direction as a top surface of the upper insulating pattern, and wherein the doped polysilicon contacts the insulating spacer and the lower insulating pattern.

11. A semiconductor device, comprising: a bit line extending in a first horizontal direction; a plurality of vertical channel patterns separated from each other in the first horizontal direction on the bit line; two word lines extending in a second horizontal direction between adjacent ones of the plurality of vertical channel patterns, the second horizontal direction intersecting the first horizontal direction; a plurality of contact plugs contacting upper portions of the plurality of vertical channel patterns; and an isolation insulating structure between the plurality of contact plugs, wherein the isolation insulating structure comprises: a lower insulating pattern having a first width in the first horizontal direction; and an upper insulating pattern on the lower insulating pattern and having a second width greater than the first width, wherein a bottom surface of the lower insulating pattern is curved.

12. The semiconductor device of claim 11, wherein each of the plurality of contact plugs comprises: a first conductive pattern comprising doped polysilicon; a second conductive pattern on the first conductive pattern and comprising a metal silicide; and a third conductive pattern on the second conductive pattern and comprising a metal, wherein the first conductive pattern contacts the lower insulating pattern and the upper insulating pattern, and wherein each of the second and third conductive patterns contacts the upper insulating pattern and does not contact the lower insulating pattern.

13. The semiconductor device of claim 12, wherein a width of the second conductive pattern in the first horizontal direction is equal to a width of the third conductive pattern in the first horizontal direction, and wherein a maximum width of the first conductive pattern in the first horizontal direction is greater than the width of the second conductive pattern in the first horizontal direction and the width of the third conductive pattern in the first horizontal direction.

14. The semiconductor device of claim 13, wherein a top surface of the first conductive pattern is higher in a vertical direction than a top surface of the lower insulating pattern, and wherein a bottom surface of the first conductive pattern is higher in the vertical direction than a bottom surface of the lower insulating pattern. ​ ​ ​ 15. The semiconductor device of claim 11, wherein the lower insulating pattern comprises silicon oxide, and wherein the upper insulating pattern comprises silicon nitride.

16. A semiconductor device, comprising: a bit line extending in a first horizontal direction; a plurality of vertical channel patterns spaced apart from each other on the bit line and in the first horizontal direction; two word lines extending in a second horizontal direction between a first vertical channel pattern and a second vertical channel pattern of the plurality of vertical channel patterns, the first vertical channel pattern and the second vertical channel pattern being adjacent, the second horizontal direction intersecting the first horizontal direction; a back gate electrode extending in the second horizontal direction between the second vertical channel pattern and a third vertical channel pattern of the plurality of vertical channel patterns, the second vertical channel pattern and the third vertical channel pattern being adjacent; a plurality of contact plugs contacting upper portions of the plurality of vertical channel patterns; an isolation insulating structure between the plurality of contact plugs; and a capacitor structure on the plurality of contact plugs and the isolation insulating structure, wherein the plurality of contact plugs comprise: a first conductive pattern comprising doped polysilicon; a second conductive pattern on the first conductive pattern and comprising metal silicide; and a third conductive pattern on the second conductive pattern and comprising metal, and wherein the isolation insulating structure comprises: a lower insulating pattern; an upper insulating pattern on the lower insulating pattern; and an insulating spacer on sidewalls of the upper insulating pattern and upper sidewalls of the lower insulating pattern.

17. The semiconductor device of claim 16, wherein an upper width of each of the plurality of contact plugs in the first horizontal direction is less than a lower width of each of the plurality of contact plugs in the first horizontal direction, and wherein an upper width of the isolation insulating structure in the first horizontal direction is greater than a lower width of the isolation insulating structure in the first horizontal direction.

18. The semiconductor device of claim 17, wherein a distance between the first vertical channel pattern and the second vertical channel pattern in the first horizontal direction is greater than the upper width and the lower width of the isolation insulating structure.

19. The semiconductor device of claim 16, wherein a bottom surface of the lower insulating pattern is lower than a top surface of the plurality of vertical channel patterns in a vertical direction, wherein a top surface of the upper insulating pattern is at a same height as a top surface of the insulating spacer in the vertical direction, and wherein a bottom surface of the upper insulating pattern is higher than a bottom surface of the insulating spacer in the vertical direction.

20. The semiconductor device of claim 19, wherein a vertical distance from the bottom surface of the lower insulating pattern to a top surface of the two word lines is less than a vertical distance from the bottom surface of the lower insulating pattern to a top surface of the back gate electrode. ​

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