Semiconductor device, manufacturing method thereof, and memory system

Abstract

The embodiment of the invention provides a semiconductor device, a preparation method thereof and a memory system. The semiconductor device includes a memory array structure and a peripheral circuit structure located on one side of the memory array structure in a first direction. The peripheral circuit structure includes a semiconductor device, a conductive layer, and a pad structure. The conductive layer is located at one side of the semiconductor device away from the memory array structure, and the pad structure is located at one side of the conductive layer away from the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a method for fabricating a semiconductor device, and a memory system. Background Technology

[0002] As the integration of semiconductor devices continues to increase, their functionality is enhanced and their size is reduced. The goal is to optimize the performance and energy efficiency of semiconductor devices to meet design requirements. Summary of the Invention

[0003] In a first aspect, some embodiments of this application provide a semiconductor device. The semiconductor device includes a memory array structure and a peripheral circuit structure located on one side of the memory array structure in a first direction. The peripheral circuit structure includes a semiconductor device, a conductive layer, and a pad structure. The conductive layer is located on the side of the semiconductor device facing away from the memory array structure, and the pad structure is located on the side of the conductive layer facing away from the semiconductor device.

[0004] In an exemplary embodiment, the peripheral circuit structure includes a substrate and an N-well region located in the substrate, with a conductive layer in contact with the substrate.

[0005] In an exemplary embodiment, the peripheral circuit structure further includes a substrate, an N-well region, and an insulating layer. The N-well region is located in the substrate and penetrates the substrate. The insulating layer is located between the substrate and the conductive layer and is in contact with the N-well region and the conductive layer.

[0006] In an exemplary embodiment, the conductive layer extends continuously in a plane perpendicular to the first direction.

[0007] In an exemplary embodiment, the peripheral circuit structure further includes one or more insulating structures that penetrate the conductive layer.

[0008] In an exemplary embodiment, the shape of the conductive layer on a plane perpendicular to the first direction includes a grid pattern or a stripe pattern.

[0009] In an exemplary embodiment, the peripheral circuit structure further includes a substrate and an N-well region located in the substrate, wherein the conductive layer extends in a region other than the region corresponding to the N-well region on a plane perpendicular to the first direction.

[0010] In an exemplary embodiment, the peripheral circuit structure further includes a substrate and a P-well region located in the substrate, wherein a conductive layer extends in the region corresponding to the P-well region on a plane perpendicular to the first direction.

[0011] In an exemplary embodiment, the peripheral circuit structure further includes a first interconnect layer and a second interconnect layer. The first interconnect layer is located on the side of the semiconductor device facing the memory array structure, and the second interconnect layer is located on the side of the conductive layer away from the semiconductor device. The first interconnect layer is connected to the semiconductor device, and the second interconnect layer is connected to the semiconductor device.

[0012] In an exemplary embodiment, the peripheral circuit structure further includes a first contact structure extending along a first direction, wherein the first contact structure is connected to a second interconnect layer and to a semiconductor device.

[0013] In an exemplary embodiment, the first contact structure extends through the conductive layer, and the peripheral circuit structure further includes an isolation layer surrounding at least a portion of the first contact structure.

[0014] In an exemplary embodiment, the first contact structure passes through the conductive layer and extends to the first interconnect layer.

[0015] In an exemplary embodiment, the semiconductor device includes a field-effect transistor, with a first contact structure passing through a conductive layer and extending to the source or drain of the field-effect transistor.

[0016] In an exemplary embodiment, the peripheral circuit structure further includes a substrate and a power rail located in the substrate and extending along a second direction, a first contact structure passing through the conductive layer and extending to the power rail, the first direction intersecting the second direction.

[0017] In an exemplary embodiment, the peripheral circuit structure further includes a substrate and a conductive pillar located in the substrate. A first contact structure passes through the conductive layer and extends to the conductive pillar. In a plane perpendicular to the first direction, the dimension of the end of the conductive pillar near the conductive layer is smaller than the dimension of the end of the conductive pillar near the first interconnect layer, and the dimension of the end of the first contact structure near the conductive layer is smaller than the dimension of the end of the first contact structure near the second interconnect layer.

[0018] In an exemplary embodiment, the peripheral circuit structure further includes a second contact structure that extends along a first direction, wherein the second contact structure is connected to a second interconnect layer and to a conductive layer.

[0019] In an exemplary embodiment, the second contact structure extends to the conductive layer.

[0020] In an exemplary embodiment, the semiconductor device includes a field-effect transistor, and a second contact structure passes through the conductive layer and extends to the source or drain of the field-effect transistor.

[0021] In an exemplary embodiment, in the first direction, the first distance between the end face of the second contact structure away from the conductive layer and the conductive layer is greater than or equal to the second distance between the end face of the first contact structure away from the conductive layer and the conductive layer.

[0022] In an exemplary embodiment, the size of the first contact structure is larger than the size of the second contact structure on a plane perpendicular to the first direction.

[0023] In an exemplary embodiment, the second interconnect layer includes interconnects and interconnect channels stacked together, wherein the interconnects furthest from the conductive layer have a larger dimension in the first direction than the other interconnects in the first direction.

[0024] In an exemplary embodiment, the conductive layer is configured to apply a ground voltage.

[0025] Secondly, some embodiments of this application provide a memory system. The memory system includes a memory and a controller. The memory includes semiconductor devices as mentioned in any of the embodiments described above. The controller is coupled to the memory and is used to control the memory to store data.

[0026] Thirdly, some embodiments of this application provide a method for fabricating a semiconductor device. The method includes: forming an initial peripheral circuit structure, wherein the initial peripheral circuit structure includes a semiconductor device; connecting a memory array structure to one side of the initial peripheral circuit structure in a first direction; forming a conductive layer on the side of the semiconductor device facing away from the memory array structure; and forming a pad structure on the side of the conductive layer facing away from the semiconductor device.

[0027] In an exemplary embodiment, the preparation method further includes forming an insulating layer between the semiconductor device and the conductive layer.

[0028] In an exemplary embodiment, the preparation method further includes forming one or more insulating structures that penetrate the conductive layer.

[0029] In an exemplary embodiment, the fabrication method further includes: forming a first interconnect layer on the side of the semiconductor device facing the memory array structure; and forming a second interconnect layer on the side of the conductive layer away from the semiconductor device; wherein the first interconnect layer is connected to the semiconductor device, and the second interconnect layer is connected to the semiconductor device.

[0030] In an exemplary embodiment, before forming a conductive layer on the side of the semiconductor device away from the memory array structure, the fabrication method further includes: connecting a support structure to the side of the memory array structure away from the semiconductor device.

[0031] In an exemplary embodiment, the fabrication method further includes: forming a first contact structure and a second contact structure extending along a first direction from the side of the conductive layer away from the semiconductor device.

[0032] In an exemplary embodiment, the first contact structure and the second contact structure are formed in the same process, or the second contact structure is formed after the first contact structure is formed. Attached Figure Description

[0033] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0034] Figure 1 This is a schematic cross-sectional view of the semiconductor device provided in the embodiments of this application;

[0035] Figures 2A to 2D This is a top view schematic diagram of a conductive layer in a semiconductor device provided in some embodiments of this application;

[0036] Figure 3 This is a top view schematic diagram of a semiconductor device including a conductive layer, an insulating structure, a first contact structure, and a second contact structure, provided in an embodiment of this application.

[0037] Figure 4 This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of this application;

[0038] Figure 5 This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of this application;

[0039] Figure 6 This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of this application;

[0040] Figure 7 This is a cross-sectional schematic diagram provided in an embodiment of the present application, including a conductive layer, a substrate, a power rail, a semiconductor device, a first interconnect layer, and a first contact structure in a semiconductor device.

[0041] Figure 8 This is a cross-sectional schematic diagram provided in an embodiment of the present application, including a conductive layer, a substrate, conductive pillars, a semiconductor device, a first interconnect layer, and a first contact structure in a semiconductor device;

[0042] Figure 9 This is a schematic flowchart of the method for fabricating a semiconductor device provided in the embodiments of this application;

[0043] Figures 10A to 10E This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application during the fabrication process;

[0044] Figure 11 This is a schematic block diagram of a system with a memory system provided in the embodiments of this application; and

[0045] Figure 12A and Figure 12BThis is a schematic block diagram of a memory system provided in an embodiment of this application. Detailed Implementation

[0046] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0047] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first interconnect layer discussed herein may also be referred to as the second interconnect layer, and the first contact structure may be referred to as the second contact structure, and vice versa.

[0048] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0049] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0050] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0051] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0052] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or can be inferred from the context.

[0053] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0054] Some embodiments of this application provide a semiconductor device. Figure 1 This is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this application. It should be noted that the D1 direction (corresponding to the first direction), D2 direction (corresponding to the second direction), and D3 direction (corresponding to the third direction) in each figure illustrate the spatial relationship of the components in the semiconductor device. For example, the D1 direction may be the stacking direction of the memory array structure and the peripheral circuit structure, and the D2 and D3 directions may be two directions that intersect (e.g., are perpendicular) to each other on a plane that intersects (e.g., is perpendicular) to the D3 direction. Throughout this application, the same concepts will be used to describe the spatial relationship of the components in the semiconductor device.

[0055] like Figure 1 As shown, the semiconductor device 100 may include a memory array structure 112 and a peripheral circuit structure 111 located on one side of the memory array structure 112 in the D1 direction. The peripheral circuit structure 111 may include a semiconductor device 113, a conductive layer 114, and a pad structure 115. The conductive layer 114 may be located on the side of the semiconductor device 113 opposite to the memory array structure 112. The pad structure 115 may be located on the side of the conductive layer 114 opposite to the semiconductor device 113. For example, the conductive layer 114 may be configured to apply a ground voltage. It should be noted that the "ground voltage" referred to in this application may be a voltage value close to 0V, for example, the voltage value may be in the range of -1V to 1V.

[0056] According to the semiconductor device 100 provided in the embodiments of this application, vertical integration of the memory array structure 112 and the peripheral circuit structure 111 is beneficial for reducing the planar area and improving the transmission speed between the peripheral circuit and the memory cell array. The conductive layer 114 is disposed on the side of the semiconductor device 113 facing away from the memory array structure 112, which can improve the dynamic interference of external signals from the pad structure 115 on the semiconductor device 113, thereby providing a shielding effect. The conductive layer 114 can also improve the heat dissipation of the semiconductor device 113.

[0057] In some embodiments, the memory array structure 112 may include an array of memory cells consisting of one or more of the following: multiple NAND memory cells, multiple DRAM memory cells, multiple PCM memory cells, multiple RRAM memory cells, multiple FeRAM memory cells, multiple FeFET memory cells, multiple MRAM memory cells, or any other type of memory cells. For example, the memory array structure 112 may be a NAND memory cell array.

[0058] In some embodiments, the number of semiconductor devices 113 in the peripheral circuit structure 111 may be multiple. These multiple semiconductor devices (e.g., 113) may be arranged in a plane perpendicular to the D1 direction. The types of semiconductor devices 113 may include, but are not limited to, field-effect transistors (e.g., planar field-effect transistors or fin field-effect transistors), diodes, resistors, capacitors, other active devices, or other passive devices. Some of the multiple semiconductor devices (e.g., 113) may be used to construct any suitable digital, analog, and / or mixed-signal functional circuitry supporting the memory cell array function, such as row decoders (or word line drivers), column decoders (or bit line drivers), page buffers (or sense amplifiers), voltage generators, logic control circuitry, input / output (I / O) circuitry, and data buses, etc.

[0059] In some embodiments, the semiconductor device 100 may further include a substrate 116. For example, the substrate 116 may extend along both the D2 and D3 directions. The substrate 116 may be made of silicon, germanium, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), glass, III-V compound materials (e.g., gallium nitride, gallium arsenide, indium arsenide, etc.), or any other suitable semiconductor material. For example, the substrate 116 may be a silicon substrate. As another example, the substrate 116 may be a P-type substrate.

[0060] In some embodiments, the N-well region 117 may be disposed in the substrate 116. The N-well region 117 may have N-type doped elements such as phosphorus, arsenic, or antimony. For example, a semiconductor device 113 implemented as a P-type planar field-effect transistor may be disposed in the N-well region 117. The conductive layer 114 may be in contact with the substrate 116. For example, in the D1 direction, the N-well region 117 may be spaced apart from the surface of the substrate 116 facing the conductive layer 114. In other words, the conductive layer 114 and the N-well region 117 may be isolated from each other by the substrate 116. As described above, the conductive layer 114 may be configured to apply a ground voltage to achieve a shielding function. In the case where the substrate 116 is a P-type substrate, the P-type substrate is typically also configured to apply a ground voltage. The conductive layer 114 is in contact with the substrate 116, so that voltage can be applied synchronously to the conductive layer 114 and the substrate 116 through a single lead structure.

[0061] In some embodiments, the P-well region 118 may be disposed in the substrate 116. The P-well region 118 may have P-type doped elements such as boron, gallium, or indium. For example, a semiconductor device 113 implemented as an N-type planar field-effect transistor may be disposed in the P-well region 118. In other embodiments, the peripheral circuit structure 111 may not include the P-well region 118. The semiconductor device 113 implemented as an N-type planar field-effect transistor may be disposed in the substrate 116.

[0062] In some embodiments, the conductive layer 114 may extend along the D2 and D3 directions (e.g., continuously) on the side of a plurality of semiconductor devices (e.g., 113) away from the memory array structure 112.

[0063] In some embodiments, one or more insulating structures penetrate the conductive layer 114. Viewed from the D1 direction, the conductive layer 114 may be formed into shapes with different patterns.

[0064] Figures 2A to 2D Examples of structures containing conductive layers and insulating structures are shown. For example... Figure 2A As shown, multiple insulating structures 119 are separated from each other and all penetrate the conductive layer 114 along the D1 direction. In a plane perpendicular to the D1 direction, the conductive layer 114 can be in the shape of a grid.

[0065] like Figure 2B As shown, multiple insulating structures 119 are separated from each other and all penetrate the conductive layer 114 along the D1 direction. The conductive layer 114 can be striped in shape on a plane perpendicular to the D1 direction. When the conductive layer 114 is grid-like or striped, it helps to optimize the structural stress of the conductive layer 114.

[0066] It should be noted that the grid size of each grid in the grid-like conductive layer 114 may be the same or different, and the stripe size of each stripe in the striped conductive layer 114 may be the same or different. The size of the above patterns can be determined according to actual design requirements, and this application does not impose any specific restrictions on this.

[0067] like Figure 2C As shown, one or more insulating structures 119 may penetrate the conductive layer 114 along the D1 direction. In a plane perpendicular to the D1 direction, the conductive layer 114 extends beyond the N-well region 117 (reference). Figure 1 The insulating structure 119 extends into the region outside the corresponding region. For example, viewed from the D1 direction, a single insulating structure 119 may approximately coincide with the N-well region 117. In the case where the peripheral circuit structure 111 does not include the P-well region 118 and the substrate 116 is a P-type substrate, the conductive layer 114 is in contact with the substrate 116, and the conductive layer 114 and the substrate 116 can be configured to apply a ground voltage synchronously. The insulating structure 119 helps to reduce the impact of the conductive layer 114 on the N-well region 117 during operation.

[0068] like Figure 2D As shown, an insulating structure 119 can penetrate the conductive layer 114 along the D1 direction. In a plane perpendicular to the D1 direction, the conductive layer 114 can extend into the P-well region 118 (reference). Figure 1 Extending within the corresponding region. For example, viewed from the D1 direction, the conductive layer 114 can be divided into islands, and a single conductive layer 114 can approximately overlap with the P-well region 118. When the peripheral circuit structure 111 includes the P-well region 118, the P-well region 118 is typically also configured to apply a ground voltage, the conductive layer 114 contacts the P-well region 118, and can be configured to apply voltage synchronously. The insulating structure 119 helps to reduce the impact of the conductive layer 114 on the N-well region 117 and the substrate 116 during operation.

[0069] In some embodiments, the material of the conductive layer 114 may include one or more of tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable metallic material. For example, the material of the conductive layer 114 may be tungsten. In this case, an adhesive layer (not shown) may be provided between the conductive layer 114 and, for example, the substrate 116 to improve contact performance. The material of the adhesive layer may include, but is not limited to, titanium, titanium nitride, tantalum, and tantalum nitride. The material of the conductive layer 114 may also include polycrystalline silicon, amorphous silicon, germanium silicon, or any other suitable semiconductor material. For example, when the conductive layer 114 and the substrate 116 are made of the same material, they may be a single structure without a distinct interface. When the conductive layer 114 is made of a metallic material, it helps to improve heat dissipation.

[0070] In some implementations, refer again Figure 1The material of the pad structure 115 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material. The pad structure 115 can be used to connect to external devices and transmit signals. For example, the pad structure 115 may be located on the same side of the semiconductor device 113 in the D1 direction as the power line. The number of pad structures 115 may be one or more; this application does not impose a specific limitation on this, and the number can be set according to actual needs.

[0071] In some embodiments, the peripheral circuit structure 111 may further include a first interconnect layer 120 and a second interconnect layer 121. The first interconnect layer 120 may be located on the side of the semiconductor device 113 facing the memory array structure 112. The second interconnect layer 121 may be located on the side of the conductive layer 114 away from the semiconductor device 113. For example, the second interconnect layer 121 may be located on the side of the semiconductor device 113 facing the pad structure 115. The first interconnect layer 120 is connected to the semiconductor device 113, and the second interconnect layer 121 is connected to the semiconductor device 113. The specific connection methods of the semiconductor device 113 with the first interconnect layer 120 and the second interconnect layer 121 will be illustrated below. Compared to placing the interconnect layers used to interconnect the semiconductor device 113 on one side of the semiconductor device 113 in the D1 direction, in this embodiment, placing the first interconnect layer 120 and the second interconnect layer 121 on opposite sides of the semiconductor device 113 in the D1 direction reduces the number of stacked interconnect layers on each side, alleviates wiring congestion on each side, shortens the signal transmission path, reduces voltage drop loss, and improves signal transmission efficiency. Furthermore, stacking the first interconnect layer 120 and the second interconnect layer 121 in the D1 direction helps accommodate the increased demands of high memory density on peripheral circuitry.

[0072] The following examples illustrate the first interconnect structure 120, the second interconnect structure 121, and their connection to the semiconductor device 113.

[0073] In some embodiments, the first interconnect layer 120 may include alternating layers of first interconnect lines 1201 and first interconnect channels 1202. The first interconnect lines 1201 may extend along the D2 and / or D3 directions, and the first interconnect channels 1202 may extend along the D1 direction. The first interconnect channels 1202 in the first interconnect layer 120 may extend to and connect to the semiconductor device 113. For example, if the semiconductor device 113 is implemented as a field-effect transistor, the first interconnect channel 1202 may extend to the source, drain, and gate of the field-effect transistor. The materials of the first interconnect lines 1201 and the first interconnect channels 1202 include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, copper, aluminum, molybdenum, ruthenium, or any other suitable conductive material.

[0074] In some embodiments, the second interconnect layer 121 may include alternately stacked second interconnect lines 1211 and second interconnect channels 1212. The second interconnect lines 1211 may extend along the D2 direction and / or the D3 direction, and the second interconnect channels 1212 may extend along the D1 direction. The second interconnect layer 121 may be connected to the semiconductor device 113 via a first contact structure 122. The first contact structure 122 will be described by example below. The materials of the second interconnect lines 1211 and the second interconnect channels 1212 include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, copper, aluminum, molybdenum, ruthenium, or any other suitable conductive material.

[0075] In some embodiments, in the second interconnect layer 121, the second interconnect line 1211 furthest from the conductive layer 114 has a larger dimension in the D1 direction than the other second interconnect lines 1211. The second interconnect line 1211 furthest from the conductive layer 114 may be the layer with the largest distance from the conductive layer 114 among the multiple layers of second interconnect lines 1211. For example, the second interconnect line 1211 furthest from the conductive layer 114 may serve as a power line. This power line may be disposed in the same layer as the pad structure 115; for example, the opposing surfaces of the power line in the D1 direction relative to the conductive layer 114 are at the same height as the opposing surfaces of the pad structure 115 in the D1 direction. The conductive layer 114 can also mitigate dynamic interference from the power line to the semiconductor device 113, thereby providing a shielding effect.

[0076] In some embodiments, the first contact structure 122 may extend along the D1 direction. The first contact structure 122 may be connected to the second interconnect layer 121 and to the semiconductor device 113. For example, the second interconnect layer 121 may have a spacing distance from the conductive layer 114 in the D1 direction. The conductive layer 114 and the second interconnect layer 121 may be isolated by an insulating material. When the semiconductor device 113 is implemented as a field-effect transistor, one end of the first contact structure 122 may contact the second interconnect layer 121 (e.g., the second interconnect line 1211 or the second interconnect channel 1212), and the first contact structure 122 may extend along the D1 direction through the conductive layer 114 until it reaches the source or drain of the field-effect transistor. In other words, the other end of the first contact structure 122 may contact the semiconductor device 113.

[0077] In some embodiments, the peripheral circuit structure 111 may further include an isolation layer 123. The isolation layer 123 may surround at least a portion of the first contact structure 122. For example, the isolation layer 123 may surround the portion of the first contact structure 122 that extends through the conductive layer 114 to electrically isolate the first contact structure 122 from the conductive layer 114, thereby preventing crosstalk between the first contact structure 122 and the conductive layer 114. Optionally, the isolation layer 123 may also surround the portion of the first contact structure 122 that extends through the substrate 116, the N-well region 117 (or the P-well region 118). The material of the isolation layer 123 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material.

[0078] In some embodiments, the peripheral circuit structure 111 may further include a second contact structure 124 extending along the D1 direction. The second contact structure 124 may be connected to the second interconnect layer 121 and to the conductive layer 114. The material of the second contact structure 124 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material. For example, one end of the second contact structure 124 may contact the second interconnect layer 121 (e.g., the second interconnect line 1211 or the second interconnect channel 1212), and the second contact structure 124 may extend along the D1 direction through the conductive layer 114. The conductive layer 114 may surround and contact the second contact structure 124. Thus, the second contact structure 124 and the conductive layer 114 can achieve electrical conductivity, and the second contact structure 124 can be used to lead out the conductive layer 114.

[0079] In some embodiments, where the second contact structure 124 extends through the conductive layer 114 along the D1 direction, the second contact structure 124 may further extend to the source or drain of the field-effect transistor semiconductor device 113. In this embodiment, the second contact structure 124 can simultaneously lead out the conductive layer 114 and the semiconductor device 113.

[0080] In some embodiments, in the D1 direction, the first distance l1 between the end face of the second contact structure 124 facing away from the conductive layer 114 and the conductive layer 114 is equal to the second distance l2 between the end face of the first contact structure 122 facing away from the conductive layer 114 and the conductive layer 114. The first contact structure 122 and the second contact structure 124 can be formed in the same process, which helps to save costs.

[0081] It should be noted that, as mentioned above, viewed from the D1 direction, the conductive layer 114 can be a continuous extension or have a shape with different patterns. Based on the shape of the conductive layer 114, the first contact structure 122 and the second contact structure 124 can have different relative positions. Figure 3This is a top view schematic diagram of a semiconductor device including a conductive layer, an insulating structure, a first contact structure, and a second contact structure, provided in an embodiment of this application. Figure 3 As shown, viewed from direction D1, multiple insulating structures 119 penetrate the conductive layer 114, which is in a mesh-like pattern. A first contact structure 122 can penetrate the insulating structures 119, and a second contact structure 124 can penetrate the conductive layer 114. In this case, the insulating layer 123 surrounding at least a portion of the first contact structure 122 can be omitted (see reference). Figure 1 ).

[0082] Figure 4 This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of this application. The same reference numerals refer to the same components. For the purpose of brevity, the same content as in the previous embodiment in this embodiment and the following embodiments will not be repeated here.

[0083] In some implementations, such as Figure 4 As shown, the N-well region 117 located in substrate 116 can penetrate substrate 116. Similarly, the P-well region 118 located in substrate 116 can also penetrate substrate 116. In other words, the N-well region 117 and the P-well region 118 can be exposed on the surface of substrate 116 away from the memory array structure 112. For example, the N-well region 117 and the P-well region 118 penetrating substrate 116 can be obtained by a "back-side thinning" process, which allows substrate 116 to have a smaller size in the D1 direction compared to the previous embodiment.

[0084] In some embodiments, the peripheral circuit structure 111 may further include an insulating layer 125. The insulating layer 125 may be located between the substrate 116 and the conductive layer 114, and contact the N-well region 117 and the conductive layer 114. For example, the insulating layer 125 may extend continuously along the D2 and D3 directions. The material of the insulating layer 125 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. For example, the material of the insulating layer 125 is silicon oxide. As described above, the conductive layer 114 may be configured to apply a ground voltage to achieve a shielding function. In the case where the N-well region 117 penetrates the substrate 116, since the N-well region 117 is typically configured with an ungrounded voltage (e.g., a high voltage), the insulating layer 125 can electrically isolate the N-well region 117 and the conductive layer 114, preventing crosstalk between them when a voltage is applied.

[0085] In some embodiments, one end of the second contact structure 124 may be connected to the second interconnect layer 121, and the other end may extend to the conductive layer 114. For example, the second contact structure 124 may remain on the surface of the conductive layer 114 away from the memory array structure 112 or extend into the conductive layer 114, but not into the insulating layer 125.

[0086] In some embodiments, the dimension (e.g., outer diameter) of the first contact structure 122 is larger than the dimension (e.g., outer diameter) of the second contact structure 124 in a plane perpendicular to the D1 direction. It should be noted that the dimensions of the first contact structure 122 and the second contact structure 124 mentioned above refer to dimensions taken from the same plane perpendicular to the D1 direction. The smaller dimension of the second contact structure 124 ensures that it is formed in the same process as the first contact structure 122 and extends to the surface or interior of the conductive layer 114.

[0087] Figure 5 This is a schematic cross-sectional view of a semiconductor device provided in yet another embodiment of this application. In some embodiments, such as... Figure 5 As shown, in the D1 direction, the first distance l1 between the end face of the second contact structure 124 facing away from the conductive layer 114 and the conductive layer 114 is greater than the second distance l2 between the end face of the first contact structure 122 facing away from the conductive layer 114 and the conductive layer 114. In other words, compared to the conductive layer 114, the end face of the second contact structure 124 facing away from the memory array structure 112 can be higher than the end face of the first contact structure 122 facing away from the memory array structure 112. Therefore, the second contact structure 124 and the first contact structure 122 can be formed in different processes, which helps to improve the dimensional accuracy of the second contact structure 124 in the D1 direction.

[0088] Figure 6 This is a schematic cross-sectional view of a semiconductor device provided in another embodiment of this application. In some embodiments, such as Figure 6 As shown, one end of the first contact structure 122 contacts the second interconnect layer 121 (e.g., the second interconnect line 1211 or the second interconnect channel 1212), and the first contact structure 122 can extend along the D1 direction through the conductive layer 114 until it reaches the first interconnect layer 120 (e.g., the first interconnect line 1201 or the first interconnect channel 1202). That is, the other end of the first contact structure 122 is connected to the semiconductor device 113 through the first interconnect layer 120.

[0089] Figure 7 This is a cross-sectional schematic diagram provided in the embodiments of this application, which includes a conductive layer, substrate, power rail, semiconductor device, first interconnect layer, and first contact structure in a semiconductor device.

[0090] In some implementers, such as Figure 7As shown, the peripheral circuit structure 111 may further include a power rail 126. The power rail 126 may be located in the substrate 116 and extend along the D2 direction. The material of the power rail 126 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material. Optionally, an insulating layer (not shown) may also be provided between the power rail 126 and the substrate 116. For example, the end of the power rail 126 in the D1 direction contacts a first interconnect channel 1202 in the first interconnect layer 120. A first contact structure 122 passes through the conductive layer 114 and extends to the other end of the power rail 126 in the D1 direction. The power rail 126 can be used to provide low-resistance signal interconnects and to provide wiring space for the first interconnect layer 120.

[0091] Figure 8 This is a cross-sectional schematic diagram provided in the embodiments of this application, which includes a conductive layer, substrate, conductive pillar, semiconductor device, first interconnect layer, and first contact structure in a semiconductor device.

[0092] In some implementations, such as Figure 8 As shown, the peripheral circuit structure 111 may further include a conductive post 127. The conductive post 127 may be located in the substrate 116, for example, penetrating the substrate 116. In a plane perpendicular to the D1 direction, the dimension d1 of the end of the conductive post 127 near the conductive layer 114 is smaller than the dimension d2 of the end of the conductive post 127 near the first interconnect layer 120, and the dimension d3 of the end of the first contact structure 122 near the conductive layer 114 is smaller than the dimension d4 of the end of the first contact structure 122 near the second interconnect layer (not shown). For example, along the D1 direction, the dimension of the conductive post 127 decreases in the plane perpendicular to the D1 direction, and the dimension of the first contact structure 122 increases in the plane perpendicular to the D1 direction. For example, the end of the conductive post 127 in the D1 direction contacts the first interconnect channel 1202 in the first interconnect layer 120. The first contact structure 122 passes through the conductive layer 114 and extends to the other end of the conductive post 127 in the D1 direction. The material of the conductive post 127 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material. Optionally, an insulating layer (not shown) may also be provided between the conductive post 127 and the substrate 116.

[0093] Some embodiments of this application also provide a method for fabricating a semiconductor device. Figure 9 This is a schematic flowchart of the method for fabricating a semiconductor device provided in an embodiment of this application. Figure 9 As shown, the method for fabricating a semiconductor device 200 (hereinafter referred to as fabrication method 200) may include the following steps.

[0094] S210, forming an initial peripheral circuit structure, wherein the initial peripheral circuit structure includes semiconductor devices.

[0095] S220, the storage array structure is connected to one side of the initial peripheral circuit structure in the first direction.

[0096] S230, a conductive layer is formed on the side of the semiconductor device away from the memory array structure.

[0097] S240 forms a pad structure on the side of the conductive layer away from the semiconductor device.

[0098] According to the fabrication method provided in this application, connecting the memory array structure to one side of the initial peripheral circuit structure in the first direction enables vertical integration of the memory cell array and the peripheral circuit, which helps to reduce the planar area and improve the transmission speed between the memory cell array and the peripheral circuit. The conductive layer formed on the side of the semiconductor device away from the memory array structure can improve the dynamic interference of external signals from the pad structure on the semiconductor device, thereby providing a shielding effect. The conductive layer can also improve the heat dissipation of the semiconductor device.

[0099] Figures 10A to 10E This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application during the fabrication process. The following is in conjunction with... Figures 10A to 10E The preparation method 200, which includes steps S210 to S240, will be described by way of example.

[0100] S210

[0101] Figure 10A The intermediate structure 300a is shown after the formation of the initial peripheral circuit structure 311' containing the semiconductor device 313.

[0102] like Figure 10A As shown, semiconductor devices 313 may be formed in the initial peripheral circuit structure 311'. For example, multiple semiconductor devices (e.g., 313) may be arranged in a plane perpendicular to the D1 direction. The types of semiconductor devices 313 may include, but are not limited to, field-effect transistors (e.g., planar field-effect transistors or fin field-effect transistors), diodes, resistors, capacitors, other active devices, or other passive devices. Some of the multiple semiconductor devices (e.g., 313) may be used to construct any suitable digital, analog, and / or mixed-signal functional circuitry supporting the memory cell array function, such as row decoders (or word line drivers), column decoders (or bit line drivers), page buffers (or sense amplifiers), voltage generators, logic control circuits, input / output (I / O) circuits, and data buses, etc.

[0103] In some embodiments, the semiconductor device 313 may be formed in a substrate 316. The substrate 316 may extend along both the D2 and D3 directions. The substrate 316 may be made of silicon, germanium, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), glass, III-V compounds (e.g., gallium nitride, gallium arsenide, indium arsenide, etc.), or any other suitable semiconductor material. For example, the substrate 316 may be a silicon substrate. As another example, the substrate 316 may be a P-type substrate. The substrate 316 may be used to provide mechanical support during fabrication.

[0104] In some embodiments, an N-well region 317 and / or a P-well region 318 may be formed in the substrate 316. The N-well region 317 may be exposed on one surface of the substrate 316 in the D1 direction and spaced apart from the other surface. Similarly, the P-well region 318 may be exposed on one surface of the substrate 316 in the D1 direction and spaced apart from the other surface. For example, a semiconductor device 313 implemented as a P-type planar field-effect transistor may be disposed in the N-well region 317. As another example, a semiconductor device 313 implemented as an N-type planar field-effect transistor may be disposed in the P-well region 318.

[0105] In some embodiments, after forming the semiconductor device 313, a first interconnect layer 320 may be formed on one side of the semiconductor device 313. The first interconnect layer 320 may face the memory array structure 312 to be connected (see reference). Figure 10B On one side of the semiconductor device 313, the first interconnect layer 320 may be connected to the semiconductor device 313. For example, at least one first interconnect channel 3202 and at least one first interconnect line 3201 may be formed alternately.

[0106] S220

[0107] Figure 10B An intermediate structure 300b is shown following the connection of the memory array structure 312. (See diagram.) Figure 10B As shown, the memory array structure 312 can be connected to one side of the initial peripheral circuit structure 311' in the D1 direction. For example, the memory array structure 312 and the initial peripheral circuit structure 311' can be bonded together using a "bonding technique". The "bonding technique" referred to in this application may include, but is not limited to, hybrid bonding, anodic bonding, fusion bonding, eutectic bonding, etc.

[0108] In some embodiments, the memory array structure 312 may include an array of memory cells consisting of one or more of the following: multiple NAND memory cells, multiple DRAM memory cells, multiple PCM memory cells, multiple RRAM memory cells, multiple FeRAM memory cells, multiple FeFET memory cells, multiple MRAM memory cells, or any other type of memory cells. For example, the memory array structure 312 may be a NAND memory cell array. The memory array structure 312 may be fabricated in parallel with the initial peripheral circuit structure 311', thereby helping to improve fabrication efficiency and reduce the mutual influence of thermal stress during the fabrication of both.

[0109] In some implementations, such as Figure 10B As shown, prior to performing step S230, fabrication method 200 may further include connecting a carrier structure 328 to the side of the memory array structure 312 facing away from the semiconductor device 313. The carrier structure 328 may be made of silicon, germanium, germanium-silicon, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), glass, III-V compound materials (e.g., gallium nitride, gallium arsenide, indium arsenide, etc.), or any other suitable semiconductor material. For example, the carrier structure 328 and the memory array structure 312 may be connected in a separable manner.

[0110] S230

[0111] Figure 10C The intermediate structure 300c is shown after the formation of the conductive layer 314.

[0112] In some implementations, such as Figure 10B and Figure 10C As shown, the intermediate structure 300b can be flipped 180°, with the support structure 328 positioned below the memory array structure 312 to provide mechanical support for the memory array structure 312 and the initial peripheral circuit structure 311'. Next, a chemical mechanical polishing (CMP) process can be used to thin the substrate 316 from the side facing away from the memory array structure 312. For example, the substrate 316 can be thinned to the point where the N-well region 317 and / or the P-well region 318 are not exposed, such as... Figure 10C As shown. For example, the substrate 316 can be thinned to expose the N-well region 317 and / or the P-well region 318 (not shown) to further meet the dimensional design requirements of the substrate 316 in the D1 direction.

[0113] In some embodiments, when the substrate 316 is thinned to expose the N-well region 317 and / or the P-well region 318, such as Figure 10CAs shown, thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used. First, an insulating layer 325 is formed on the side of the semiconductor device 313 facing away from the memory array structure 312. Then, a conductive layer 314 is formed on the side of the insulating layer 325 facing away from the semiconductor device 313. The insulating layer 325 is located between the semiconductor device 313 and the conductive layer 314. The two surfaces of the insulating layer 325 in the D1 direction are in contact with the N-well region 317 and the conductive layer 314, respectively.

[0114] In other embodiments, when the substrate 316 is thinned to the point where the N-well region 317 and / or P-well region 318 are not exposed, a conductive layer 314 may be formed on the side of the semiconductor device 313 away from the memory array structure 312 using a thin film deposition process or an epitaxial growth process such as CVD, PVD, ALD, or any combination thereof. This conductive layer 314 is in contact with the substrate 316 (not shown).

[0115] In some embodiments, the fabrication method 200 further includes the step of forming an insulating structure. For example, after forming the conductive layer 314, etching and thin film deposition processes may be used to form one or more insulating structures penetrating the conductive layer 314. Figures 2A to 2D An example of forming an insulating structure is shown. Since the location and shape of the insulating structure have been described in detail above, this application will not repeat them here.

[0116] In some embodiments, the preparation method 200 may further include the step of forming a first contact structure and a second contact structure. Figure 10D The intermediate structure 300d is shown after the formation of the first contact structure 322. Figure 10E An intermediate structure 300e is shown after the formation of the second contact structure 324, the second interconnect layer 321, and the pad structure 315.

[0117] In some embodiments, after forming the conductive layer 314, a first insulating material layer 329 may be formed on the side of the conductive layer 314 away from the semiconductor device 313 using a thin film deposition process of CVD, PVD, ALD, or any combination thereof. The material of the first insulating material layer 329 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. Then, an etching process may be used to form a first contact hole (not shown) penetrating the first insulating material 329 and the conductive layer 314. The first contact hole may extend along the D1 direction. Next, an isolation layer 323 may be formed on the sidewall of the first contact hole using a thin film deposition process of CVD, PVD, ALD, or any combination thereof. Subsequently, a conductive material may be filled inside the isolation layer 323 using a thin film deposition process of CVD, PVD, ALD, or any combination thereof to form a first contact structure 322. The first contact structure 322 extends from the conductive layer 314 away from the semiconductor device 313 along the D1 direction. For example, the end of the first contact structure 322 facing the conductive layer 314 can be connected to the source or drain of the semiconductor device 313 implemented as a field-effect transistor, such as... Figure 10D As shown. For example, the end of the first contact structure 322 facing the conductive layer 314 can be connected to the first interconnect layer 320, thereby connecting to the semiconductor device 313 through the first interconnect layer 320. As another example, the end of the first contact structure 322 facing the conductive layer 314 can be connected to a power rail or conductive post, thereby connecting to the semiconductor device 313 through the source rail or conductive post.

[0118] It should be noted that when one or more contact structures penetrate the conductive layer 314, the first contact structure 322 can be disposed through the insulating structure, thus omitting the isolation layer 323.

[0119] In some embodiments, after forming the conductive layer 314, a second contact structure (not shown) can be formed during the process of forming the first contact structure 322. For example, the first contact hole and the second contact hole can be formed using the same mask. In this case, the size of the first contact hole can be larger than the size of the second contact hole in a plane perpendicular to the D1 direction, allowing the first contact hole to extend through the conductive layer 314, while the second contact hole remains on the surface or inside the conductive layer 314. Next, conductive material can be filled into the first and second contact holes in the same thin film deposition process. The second contact structure can be connected to the conductive layer 314 and used to lead the conductive layer 314 out from the D1 direction.

[0120] In other implementations, such as Figure 10EAs shown, after forming the first contact structure 322, a second insulating material layer 330 can be formed on the side of the first insulating material layer 329 away from the conductive layer 314 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The material of the second insulating material layer 330 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. If the materials of the first insulating material layer 329 and the second insulating material layer 330 are the same, they can be a single structure without a distinct interface. Then, an etching process can be used to form a second contact hole (not shown) penetrating the second insulating material layer 330 and the first insulating material 329. For example, the second contact hole may extend along the D1 direction and may penetrate or extend to the conductive layer 314. Next, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to fill the inside of the second contact hole with conductive material to form a second contact structure 324. The second contact structure 324 extends from the conductive layer 314 away from the semiconductor device 313 along the D1 direction.

[0121] In some embodiments, after the first contact structure 322 is formed, a second interconnect layer 321 may be formed on the side of the conductive layer 314 opposite to the semiconductor device 313. The second interconnect layer 321 may be connected to the semiconductor device 313 through the first contact structure 322. For example, at least one second interconnect channel 3212 and at least one second interconnect line 3211 may be formed alternately.

[0122] S240

[0123] In some implementations, such as Figure 10E As shown, during the formation of the final layer of the second interconnect 3211, a pad structure 315 can be formed on the side of the conductive layer 314 facing away from the semiconductor device 313. For example, the pad structure 315 can be connected to the final layer of the second interconnect 3211. The final layer of the second interconnect 3211 can serve as a power line. In the D1 direction, the power line has a larger dimension than the other second interconnect 3211 lines. The pad structure 315 can be used to connect to external devices and transmit signals.

[0124] This application also provides a memory system. Figure 11 This is a schematic block diagram of a system with a memory system provided in the embodiments of this application. Figure 12A and Figure 12B This is a schematic block diagram of a memory system provided in an embodiment of this application.

[0125] like Figure 11As shown, system 40 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 41 located therein). Figure 11 As shown, system 40 may include a host 44 and a memory system 41, the memory system 41 having one or more memories 42 and a controller 43. The host 44 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 44 may be configured to send or receive data to and from the memory 42.

[0126] Memory 42 may include the semiconductor devices described in any embodiment of this application. According to some embodiments, controller 43 is coupled to memory 42 and host 44 and is configured to control memory 42. Controller 43 may manage data stored in memory 42 and communicate with host 44. In some embodiments, controller 43 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 43 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc. Controller 43 may be configured to control operations of memory 42, such as read, erase, and program operations. Controller 43 may also be configured to manage various functions related to data stored in or to be stored in memory 42, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 43 is further configured to process error correction codes (ECCs) related to data read from or written to memory 42. Controller 43 may also perform any other appropriate functions, such as formatting memory 42. Controller 43 may communicate with external devices (e.g., host 44) according to a specific communication protocol. For example, controller 43 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0127] The controller 43 and one or more memories 42 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 41 can be implemented and packaged into different types of end electronic products. Figure 12AIn one example shown, the controller 43 and a single memory 42 may be integrated into a memory card 45. The memory card 45 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 45 may further include a connector for connecting the memory card 45 to a host computer (e.g., Figure 11 The host 44) is coupled to the memory card connector 46. In such a way... Figure 12B In another example shown, the controller 43 and multiple memories 42 may be integrated into the SSD 47. The SSD 47 may further include a connection between the SSD 47 and the host (e.g., Figure 11 The SSD connector 48 is coupled to the host 44. In some embodiments, the storage capacity and / or operating speed of the SSD 47 is higher than that of the memory card 45.

[0128] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor device comprising: a memory array structure; a peripheral circuit structure located on one side of the memory array structure in a first direction and comprising: a semiconductor device; a conductive layer located on a side of the semiconductor device facing away from the memory array structure; and a pad structure located on a side of the conductive layer facing away from the semiconductor device.

2. The semiconductor device according to claim 1, wherein The peripheral circuit structure comprises a substrate and an N-well region located in the substrate, the conductive layer being in contact with the substrate.

3. The semiconductor device according to claim 1, wherein The peripheral circuit structure further comprises: a substrate; an N-well region located in the substrate and extending through the substrate; and an insulating layer located between the substrate and the conductive layer and in contact with the N-well region and the conductive layer.

4. The semiconductor device according to claim 1, wherein The conductive layer extends continuously in a plane perpendicular to the first direction.

5. The semiconductor device according to claim 1, wherein The peripheral circuit structure further comprises one or more insulating structures extending through the conductive layer.

6. The semiconductor device according to claim 5, wherein The shape of the conductive layer in a plane perpendicular to the first direction comprises a grid-like or a stripe-like shape.

7. The semiconductor device according to claim 5, wherein The peripheral circuit structure further comprises a substrate and an N-well region located in the substrate, wherein the conductive layer extends in a region other than a region corresponding to the N-well region in a plane perpendicular to the first direction.

8. The semiconductor device according to claim 5, wherein The peripheral circuit structure further comprises a substrate and a P-well region located in the substrate, wherein the conductive layer extends in a region corresponding to the P-well region in a plane perpendicular to the first direction.

9. The semiconductor device according to claim 1, wherein The peripheral circuit structure further comprises: a first interconnect layer located on a side of the semiconductor device facing the memory array structure; and a second interconnect layer located on a side of the conductive layer facing away from the semiconductor device; wherein the first interconnect layer is connected to the semiconductor device and the second interconnect layer is connected to the semiconductor device.

10. The semiconductor device according to claim 9, wherein The peripheral circuit structure further comprises: a first contact structure extending along the first direction, wherein the first contact structure is connected to the second interconnect layer and to the semiconductor device.

11. The semiconductor device according to claim 10, wherein The first contact structure passes through the conductive layer, and the peripheral circuit structure further comprises an isolation layer surrounding at least part of the first contact structure.

12. The semiconductor device according to claim 10, wherein The first contact structure passes through the conductive layer and extends to the first interconnect layer.

13. The semiconductor device according to claim 10, wherein The semiconductor device comprises a field effect transistor, and the first contact structure passes through the conductive layer and extends to a source or a drain of the field effect transistor.

14. The semiconductor device according to claim 10, wherein The peripheral circuit structure further comprises a substrate and a power rail located in the substrate and extending in a second direction, the first contact structure passing through the conductive layer and extending to the power rail, the first direction intersecting the second direction.

15. The semiconductor device according to claim 10, wherein The peripheral circuit structure further comprises a substrate and a conductive pillar located in the substrate, the first contact structure passing through the conductive layer and extending to the conductive pillar, wherein in a plane perpendicular to the first direction, a dimension of the conductive pillar near an end of the conductive pillar is smaller than a dimension of the conductive pillar near an end of the first interconnect layer, and a dimension of the first contact structure near an end of the conductive layer is smaller than a dimension of the first contact structure near an end of the second interconnect layer.

16. The semiconductor device according to claim 10, wherein The peripheral circuit structure further comprises: a second contact structure extending in the first direction, wherein the second contact structure is connected with the second interconnection layer and connected with the conductive layer.

17. The semiconductor device according to claim 16, wherein The second contact structure extends to the conductive layer.

18. The semiconductor device according to claim 16, wherein The semiconductor device includes a field effect transistor, the second contact structure passes through the conductive layer and extends to a source or a drain of the field effect transistor.

19. The semiconductor device according to claim 16, wherein In the first direction, a first distance between an end surface of the second contact structure facing away from the conductive layer and the conductive layer is greater than or equal to a second distance between an end surface of the first contact structure facing away from the conductive layer and the conductive layer.

20. The semiconductor device of Claim 16, wherein, In a plane perpendicular to the first direction, a size of the first contact structure is greater than a size of the second contact structure.

21. The semiconductor device according to claim 9, wherein The second interconnection layer includes interconnection lines and interconnection channels arranged in a stack, A size of the interconnection line most facing away from the conductive layer in the first direction is greater than a size of other interconnection lines in the first direction.

22. The semiconductor device according to any one of Claims 1 to 21, wherein The conductive layer is configured to apply a ground voltage.

23. A memory system, comprising: a memory including the semiconductor device according to any one of claims 1 to 22; and a controller coupled to the memory and configured to control the memory to store data.

24. A method of manufacturing a semiconductor device, wherein, including: forming an initial peripheral circuit structure, wherein the initial peripheral circuit structure includes a semiconductor device; connecting a memory array structure to one side of the initial peripheral circuit structure in a first direction; forming a conductive layer on a side of the semiconductor device facing away from the memory array structure; and forming a pad structure on a side of the conductive layer facing away from the semiconductor device.

25. The method of manufacturing according to claim 24, wherein, The manufacturing method further includes: forming an insulating layer between the semiconductor device and the conductive layer.

26. The method of manufacturing according to claim 24, wherein, The manufacturing method further includes: forming one or more insulating structures passing through the conductive layer.

27. The method of manufacturing according to claim 24, wherein, The manufacturing method further includes: forming a first interconnection layer on a side of the semiconductor device facing toward the memory array structure; and forming a second interconnection layer on a side of the conductive layer facing away from the semiconductor device; wherein the first interconnection layer is connected with the semiconductor device and the second interconnection layer is connected with the semiconductor device.

28. The method of manufacturing according to claim 27, wherein, Before forming the conductive layer on a side of the semiconductor device facing away from the memory array structure, the manufacturing method further includes: connecting a support structure on a side of the memory array structure facing away from the semiconductor device.

29. The method of making according to claim 27, wherein, The manufacturing method further includes: forming a first contact structure and a second contact structure extending in the first direction from a side of the conductive layer facing away from the semiconductor device.

30. The method of manufacturing according to claim 29, wherein, The first contact structure and the second contact structure are formed in the same process or the second contact structure is formed after the first contact structure.

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