Semiconductor device

Abstract

The invention provides a semiconductor device capable of realizing high integration. A semiconductor device includes a plurality of first resistive elements, an insulating layer, and a plurality of second resistive elements. The plurality of first resistance elements include a plurality of diffusion layers provided on the main surface side of the semiconductor substrate, extending in a first direction parallel to the main surface of the semiconductor substrate, arranged in a second direction parallel to the main surface of the semiconductor substrate and intersecting the first direction, and each having a first connection terminal portion on an end portion side in the first direction. The insulating layer is provided on the main surface side of the semiconductor substrate between the plurality of first resistive elements, and has an electrode placement surface in contact with the electrode layer. The plurality of second resistive elements include a plurality of conductive layers provided on an electrode placement surface of the insulating layer between the plurality of first resistive elements, extending in the first direction, arranged in the second direction, and each having a second connection terminal portion on an end portion side in the first direction.

Description

TECHNICAL FIELD

[0001] The present embodiment relates to a semiconductor device. BACKGROUND

[0002] A semiconductor device is known, which is provided with a first resistance element including a diffusion layer and a second resistance element including a conductive layer on a substrate. SUMMARY

[0003] The semiconductor device of the embodiment provides a semiconductor device capable of achieving high integration.

[0004] A semiconductor device of one embodiment includes a semiconductor substrate including a main surface including a first direction and a second direction intersecting the first direction; an electrode layer provided on the main surface side; a plurality of first resistance elements including a plurality of diffusion layers provided on the main surface side of the semiconductor substrate, extending in the first direction, arranged in the second direction, and each including a first connection terminal on an end portion side in the first direction; and an insulating layer provided on the main surface side of the semiconductor substrate between each of the plurality of first resistance elements, including an electrode placement surface in contact with the electrode layer. The electrode layer includes a plurality of second resistance elements including a plurality of conductive layers provided on the electrode placement surface of the insulating layer between the plurality of first resistance elements, extending in the first direction, arranged in the second direction, and each including a second connection terminal portion on an end portion side in the first direction. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 is a schematic block diagram showing the configuration of the memory die MD of the first embodiment.

[0006] Figure 2 is a schematic circuit diagram showing part of the configuration of the memory die MD.

[0007] Figure 3 is a schematic exploded perspective view showing an example of the configuration of the memory die MD.

[0008] Figure 4 is a schematic bottom view showing an example of the configuration of the chip C M .

[0009] Figure 5 is a schematic cross-sectional view showing part of the configuration of the memory die MD.

[0010] Figure 6 is a schematic cross-sectional view showing part of the configuration of the memory die MD.

[0011] Figure 7 is a schematic bottom view showing an example of the configuration of the chip C PA schematic top view of the constituent examples.

[0012] Figure 8 It is Figure 7 The peripheral circuit region R shown PC A schematic top view of circuit region A after enlargement.

[0013] Figure 9 R represents the diffusion resistance in the first embodiment. DIFF and GC resistance R GC Top view.

[0014] Figure 10 R represents the diffusion resistance in the first embodiment. DIFF and GC resistance R GC A sectional view.

[0015] Figure 11 This refers to variations of the first embodiment. Figure 10 The corresponding sectional view.

[0016] Figure 12 The diffusion resistor R is used to illustrate this embodiment. DIFF and GC resistance R GC A cross-sectional view of the manufacturing method.

[0017] Figure 13 The diffusion resistor R is used to illustrate this embodiment. DIFF and GC resistance R GC A cross-sectional view of the manufacturing method.

[0018] Figure 14 The diffusion resistor R is used to illustrate this embodiment. DIFF and GC resistance R GC A cross-sectional view of the manufacturing method.

[0019] Figure 15 The diffusion resistor R is used to illustrate this embodiment. DIFF and GC resistance R GC A cross-sectional view of the manufacturing method.

[0020] Figure 16 The diffusion resistor R is used to illustrate this embodiment. DIFF and GC resistance R GC A cross-sectional view of the manufacturing method.

[0021] Figure 17 The diffusion resistor R is used to illustrate this embodiment. DIFF and GC resistance R GC A cross-sectional view of the manufacturing method.

[0022] Figure 18 R represents the diffusion resistance in the second embodiment.DIFF and GC resistor R GC is a plan view of the diffusion resistor R

[0023] Figure 19 is a sectional view of the diffusion resistor R DIFF and GC resistor R GC .

[0024] Figure 20 is a plan view of the diffusion resistor R DIFF and GC resistor R GC .

[0025] Figure 21 is a sectional view of the diffusion resistor R DIFF and GC resistor R GC .

[0026] Figure 22 is a plan view of the diffusion resistor R DIFF and GC resistor R GC .

[0027] Figure 23 is a sectional view of the diffusion resistor R DIFF and GC resistor R GC .

[0028] Figure 24 is a plan view of the diffusion resistor R DIFF and GC resistor R GC .

[0029] Figure 25 is a plan view of the diffusion resistor R DIFF and GC resistor R GC . DETAILED DESCRIPTION

[0030] Next, the semiconductor device of the embodiments will be described in detail with reference to the drawings.

[0031] Further, in the following embodiments, a "semiconductor memory device" is exemplified as an example of the semiconductor device and will be described. However, the following embodiments are only one example and are not intended to limit the present application. In addition, the following drawings are schematic views and a part of the configuration or the like can be omitted for convenience of explanation. In addition, for the portions common to the plurality of embodiments, the same symbols are sometimes labeled and the explanation is omitted.

[0032] In addition, in this specification, when referring to a "semiconductor storage device", sometimes means a memory die, and sometimes means a memory chip, a memory card, an SSD (Solid State Drive), or the like including a controller die. Furthermore, sometimes means a smartphone, a tablet terminal, a personal computer, or the like including a host.

[0033] In addition, in this specification, when referring to a first configuration being "electrically connected" to a second configuration, the first configuration can be directly connected to the second configuration, or the first configuration can be connected to the second configuration via a wiring, a semiconductor component, or a transistor, or the like. For example, in the case where three transistors are connected in series, even if a second transistor is in an OFF state, a first transistor is "electrically connected" to a third transistor.

[0034] In addition, in this specification, when referring to a first configuration being "connected to" between a second configuration and a third configuration, sometimes means that the first configuration, the second configuration, and the third configuration are connected in series, and the second configuration is connected to the third configuration via the first configuration.

[0035] In addition, in this specification, when referring to a circuit or the like making two wirings or the like "conductive", for example, sometimes means that the circuit or the like includes a transistor or the like, the transistor or the like is provided in a current path between the two wirings, and the transistor or the like is in an ON state.

[0036] In addition, in this specification, a prescribed direction parallel to an upper surface of a substrate is referred to as an X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as a Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as a Z direction.

[0037] In addition, in this specification, sometimes a direction along a prescribed surface is referred to as a first direction, a direction intersecting the first direction along the prescribed surface is referred to as a second direction, and a direction intersecting the prescribed surface is referred to as a third direction. The first direction, the second direction, and the third direction can or can not correspond to any one of the X direction, the Y direction, and the Z direction.

[0038] In addition, in this specification, "upper", "lower", and the like are based on a substrate. For example, an orientation away from the substrate along the Z direction is referred to as upper, and an orientation close to the substrate along the Z direction is referred to as lower. In addition, when referring to a lower surface or a lower end with respect to a certain configuration, a surface or an end portion of the substrate side of the configuration is meant, and when referring to an upper surface or an upper end, a surface or an end portion of the side opposite to the substrate of the configuration is meant. In addition, a surface intersecting the X direction or the Y direction is referred to as a side surface or the like.

[0039] ​​​​​​​In addition, in the present specification, when "width", "length", or "thickness" and the like of a constitution, a component, and the like are mentioned with respect to a prescribed direction, it sometimes means width, length, or thickness and the like in a cross section and the like observed with SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy) and the like.

[0040] In addition, in the present specification, when "wiring" is mentioned, it sometimes includes a wiring, a via contact electrode, a connection portion for connecting the wiring and the via contact electrode, and a bonding electrode and the like.

[0041] [1st Embodiment]

[0042] [Circuit Constitution of Memory Die MD]

[0043] Figure 1 is a schematic block diagram showing the constitution of the memory die MD of the 1st embodiment. Figure 2 is a schematic circuit diagram showing a part of the constitution of the memory die MD.

[0044] As shown in Figure 1 , the memory die MD is provided with a memory cell array MCA and a peripheral circuit PC. The peripheral circuit PC is provided with a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC. In addition, the peripheral circuit PC is provided with a cache memory CM, an address register ADR, an instruction register CMR, and a status register STR. In addition, the peripheral circuit PC is provided with an input / output control circuit I / O and a logic circuit CTR.

[0045] [Circuit Constitution of Memory Cell Array MCA]

[0046] As shown in Figure 2 , the memory cell array MCA is provided with the plurality of memory blocks BLK. The plurality of memory blocks BLK are respectively provided with a plurality of string units SU. The plurality of string units SU are respectively provided with a plurality of memory strings MS. One end of the plurality of memory strings MS is respectively connected to the peripheral circuit PC via a bit line BL. In addition, the other end of the plurality of memory strings MS is respectively connected to the peripheral circuit PC via a common source line SL.

[0047] The memory string MS is provided with a drain side selection transistor STD, a plurality of memory cells MC (memory transistors), and a source side selection transistor STS. The drain side selection transistor STD, the plurality of memory cells MC, and the source side selection transistor STS are connected in series between the bit line BL and the source line SL. Hereinafter, the drain side selection transistor STD and the source side selection transistor STS are sometimes simply referred to as selection transistors (STD, STS).

[0048] The memory cell MC is a field effect transistor. The memory cell MC includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge accumulation film. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge accumulation film. The memory cell MC stores one or more bits of data. Further, the gate electrodes of the plurality of memory cells MC corresponding to one memory string MS are connected to a word line WL, respectively. These word lines WL are commonly connected to all the memory strings MS in one memory block BLK, respectively.

[0049] The selection transistor (STD, STS) is a field effect transistor. The selection transistor (STD, STS) includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film can also include a charge accumulation layer. The gate electrodes of the selection transistors (STD, STS) are connected to a selection gate line (SGD, SGS), respectively. One drain side selection gate line SGD is commonly connected to all the memory strings MS in one string unit SU. One source side selection gate line SGS is commonly connected to all the memory strings MS in one memory block BLK. Further, the drain side selection gate line SGD and the source side selection gate line SGS are sometimes referred to as selection gate lines SG, respectively.

[0050] [Structure of Memory Die MD]

[0051] Figure 3 is a schematic exploded perspective view showing a configuration example of the semiconductor storage device according to the first embodiment. As shown in Figure 3 , the memory die MD includes a chip C M on the memory cell array MCA side and a chip C P on the peripheral circuit PC side.

[0052] A plurality of external pad electrodes P X capable of being connected to bonding wires not shown are provided on the upper surface of the chip C M . In addition, a plurality of land electrodes P I1 are provided on the lower surface of the chip C M . In addition, a plurality of land electrodes P I2 are provided on the upper surface of the chip C P . Hereinafter, with respect to the chip C M , the surface on which the plurality of land electrodes P I1 are provided is referred to as the front surface, and the surface on which the plurality of external pad electrodes P X are provided is referred to as the back surface. In addition, with respect to the chip C P , the surface on which the plurality of land electrodes P I2The side facing out is called the front side, and the side opposite the front side is called the back side. In the example shown, chip C... P The front side is set higher than the chip C. P The back is further up, where the chip C is located. M The back is set at a higher position than chip C M The front is further up.

[0053] Chip C M and chip C P With chip C M The front of the chip C P The electrodes are arranged in a front-facing configuration. Multiple bonding electrodes P I1 Corresponding to multiple bonding electrodes P I2 The setting is configured to allow for contact with multiple bonding electrodes P. I2 The bonding location. Bonding electrode P I1 With the attached electrode P I2 As used to connect chip C M With chip C P The bonding electrodes, which are both in contact with the substrate and electrically conductive, perform their function.

[0054] In addition, Figure 3 In the example, chip C M The corners a1, a2, a3, and a4 are respectively connected to chip C P The corners b1, b2, b3, and b4 correspond.

[0055] Figure 4 This indicates that chip C M A schematic bottom view of the composition example. Figure 4 In the text, the bonding electrode P is omitted. I1 It is a part of etc. Figure 5 and Figure 6 It is a schematic cross-sectional view representing a portion of the memory die (MD). Figure 7 This indicates that chip C P A schematic top view of the constituent examples. Figure 7 In the text, the bonding electrode P is omitted. I2 It consists of a number of parts.

[0056] [Chip C] M [Structure]

[0057] exist Figure 4 In the example, chip C M It has four storage planes MP0 to MP3 arranged in the X direction. Sometimes, the four storage planes MP0 to MP3 are simply referred to as storage planes MP. Furthermore, each of the four storage planes MP0 to MP3 has multiple storage blocks BLK arranged in the Y direction. Additionally, in... Figure 4In the example, the four storage planes MP0 to MP3 each have wiring areas R located at both ends in the X direction. HU and provided in the wiring area R HU The memory hole area R between MH (Memory region). Additionally, in Figure 4 In the example, the memory hole region R MH It is divided into 4 regions R in the X direction. MHU The four regions R MHU The widths in the X direction can be all the same or different. Additionally, chip C... M It has an outer region R located on the side further in the Y direction than the four storage planes MP0 to MP3. P .

[0058] Furthermore, in the illustrated example, the wiring area R HU It is positioned at both ends of the storage plane MP in the X direction. However, this configuration is merely illustrative, and the specific configuration can be adjusted accordingly. For example, the wiring area R... HU Alternatively, it can be located at one end in the X direction, instead of at both ends of the storage plane MP in the X direction. Additionally, the wiring area R... HU It can also be set at the center or near the center of the storage plane MP in the X direction.

[0059] For example, Figure 5 As shown, chip C M With matrix layer L SB Set in the substrate layer L SB The lower storage cell array layer L MCA , set in the storage cell array layer L MCA The via contact electrode layer CH below the via contact electrode layer CH, the multiple wiring layers M0, M1 disposed below the via contact electrode layer CH, and the chip bonding electrode layer MB disposed below the wiring layers M0, M1.

[0060] [Chip C] M The base layer L SB [Structure]

[0061] For example, Figure 5 As shown, the matrix layer L SB Equipped with storage cell array layer L MCA The conductive layer 100 on the upper surface, the insulating layer 101 disposed on the upper surface of the conductive layer 100, the back wiring layer MA disposed on the upper surface of the insulating layer 101, and the insulating layer 102 disposed on the upper surface of the back wiring layer MA.

[0062] The conductive layer 100 may include, for example, a semiconductor layer such as silicon (Si) implanted with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), or a metal such as tungsten (W), or a silicide such as tungsten silicide (WSi).

[0063] Conductive layer 100 serves as the source line SL ( Figure 2 It functions as part of the ) conductive layer 100. The conductive layer 100 corresponds to the four storage planes MP0 to MP3 ( Figure 4 Four are provided. At the ends of the storage plane MP in the X and Y directions, regions VZ that do not contain the conductive layer 100 are provided.

[0064] The insulating layer 101 may contain, for example, silicon oxide (SiO2).

[0065] The back-side wiring layer MA comprises multiple wiring layers MA. These multiple wiring layers MA may, for example, contain aluminum (Al).

[0066] A portion of multiple wiring ma serves as the source line SL ( Figure 2 It functions as part of the system. For example, four wiring ma are provided corresponding to four storage planes. Each wiring ma is electrically connected to the conductive layer 100.

[0067] Additionally, a portion of the multiple wiring ma serves as the external solder pad electrode P. X To fulfill its function. This wiring harness is located in the peripheral area R. P The wiring ma is connected to the memory cell array layer L in the region VZ that does not contain the conductive layer 100. MCA The through-hole contact electrode CC is located in the memory. Additionally, a portion of the wiring ma is exposed to the outside of the memory die MD through an opening TV provided in the insulating layer 102.

[0068] The insulating layer 102 is, for example, a passivation layer containing an insulating material such as polyimide.

[0069] [Chip C] M Storage cell array layer L MCA In wiring area R HU [Structure in]

[0070] like Figure 6 As shown, in the wiring area R HU It is provided with multiple through-hole contact electrodes CC. The multiple through-hole contact electrodes CC extend along the Z direction and are connected to the conductive layer 110 (WL, SGD, SGS) at their upper ends.

[0071] [Chip C] M Storage cell array layer L MCA In the outer area R P [Structure in]

[0072] For example, Figure 5 As shown, in the outer region R P Corresponding to the external pad electrode P X It is equipped with multiple through-hole contact electrodes CC. The multiple through-hole contact electrodes CC are connected at their upper ends to an external solder pad electrode P. X .

[0073] [Structure of the through-hole contact electrode layer CH]

[0074] The via contact electrode layer CH contains multiple via contact electrodes ch, which are electrically connected to the memory cell array layer L, for example. MCA The composition and chip C in P At least one of the components in.

[0075] The via contact electrode layer CH includes multiple via contact electrodes ch serving as multiple wirings. These multiple via contact electrodes ch may, for example, comprise a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The via contact electrodes ch are disposed corresponding to the multiple semiconductor layers 120 and connected to the lower ends of the multiple semiconductor layers 120.

[0076] [Chip C] M [Structure of wiring layers M0 and M1]

[0077] The multiple wirings contained in wiring layers M0 and M1 are electrically connected to the memory cell array layer L, for example. MCA The composition and chip C in P At least one of the components.

[0078] The wiring layer M0 comprises multiple wirings m0. These multiple wirings m0 may, for example, comprise barrier conductive films such as titanium nitride (TiN), tantalum nitride (TaN), a multilayer film of tantalum nitride (TaN) and tantalum (Ta), or a multilayer film of metal films such as copper (Cu). Furthermore, a portion of the multiple wirings m0 functions as bit lines BL. The bit lines BL are, for example, arranged in the X direction and extending along the Y direction.

[0079] For example, Figure 5 As shown, the wiring layer M1 includes multiple wirings m1. The multiple wirings m1 may also include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0080] [Structure of the chip bonding electrode layer (MB)]

[0081] The chip bonding electrode layer MB contains multiple wirings, for example, electrically connected to the memory cell array layer L. MCA The composition and chip C in P At least one of the components in.

[0082] The chip bonding electrode layer MB contains multiple bonding electrodes P I1 (Lamination pads). The plurality of bonding electrodes P I1 For example, it can also include barrier conductive films such as titanium nitride (TiN), tantalum nitride (TaN), or multilayer films of tantalum nitride (TaN) and tantalum (Ta). I1B and metal films such as copper (Cu) p I1M Laminated films, etc.

[0083] [Chip C] P [Structure]

[0084] For example, Figure 7 As shown, chip C P It has regions MP0' to MP3' that overlap with four storage planes MP0 to MP3 arranged in the X direction. At both ends of these four regions MP0' to MP3' in the X direction, a row control circuit region R is respectively provided. RC Additionally, in the two line control circuit regions R RC Between them, two block decoder regions R are arranged in the X direction. BD Additionally, in the two block decoder regions R BD Between them, the peripheral circuit area R is set. PC In the peripheral circuit region R PC It has four columns of control circuit areas R arranged in the X and Y directions. CC Additionally, although the diagram is omitted, the peripheral circuit region R... PC Other areas within it are also equipped with circuitry. Additionally, in relation to chip C... M The outer area R P ( Figure 4 The opposing chip C P The area is where the circuit area R is located. C .

[0085] In addition, for example, Figure 5 As shown, chip C P The device includes a semiconductor substrate 200, an electrode layer GC disposed above the semiconductor substrate 200, wiring layers D0, D1, D2, D3, and D4 disposed above the electrode layer GC, and a chip bonding electrode layer DB disposed above the wiring layers D0, D1, D2, D3, and D4.

[0086] [Chip C] P [Structure of semiconductor substrate 200]

[0087] Semiconductor substrate 200, for example, comprises P-type silicon (Si) containing P-type impurities such as boron (B). Semiconductor substrate 200 has a main surface S on the electrode layer GC and wiring layers D0, D1, D2, D3, and D4 sides. M On the main surface S of semiconductor substrate 200 M The side surface, for example, has an N-type diffusion layer 200N containing N-type impurities such as phosphorus (P), a P-type diffusion layer 200P containing P-type impurities such as boron (B), a semiconductor substrate region 200S without the N-type diffusion layer 200N and the P-type diffusion layer 200P, and an insulating layer STI. A portion of the P-type diffusion layer 200P is disposed in the semiconductor substrate region 200S, and a portion of the P-type diffusion layer 200P is disposed in the N-type diffusion layer 200N. The N-type diffusion layer 200N, the P-type diffusion layer 200P disposed in the N-type diffusion layer 200N and the semiconductor substrate region 200S, and the semiconductor substrate region 200S function as part of multiple transistors Tr and multiple capacitors constituting the peripheral circuit PC, respectively. Furthermore, a portion of the multiple transistors Tr functions as a word line switch WLSW and a select gate line switch SGSW.

[0088] [Chip C] P [Structure of the electrode layer GC]

[0089] An electrode layer GC is disposed on the upper surface of the semiconductor substrate 200, separated by an insulating layer 200G. The electrode layer GC contains multiple electrodes gc. Furthermore, each region of the semiconductor substrate 200 and the multiple electrodes gc contained in the electrode layer GC are respectively connected to the via contact electrode CS.

[0090] The N-type diffusion layer 200N of the semiconductor substrate 200, the P-type diffusion layer 200P disposed in the N-type diffusion layer 200N and the semiconductor substrate region 200S, and the semiconductor substrate region 200S respectively function as channel regions for multiple transistors Tr constituting the peripheral circuit PC, and as one electrode of multiple capacitors, etc. Additionally, as... Figure 6 As shown, a portion of the P-type diffusion layer 200P of the semiconductor substrate 200 serves as the first resistive element, namely the diffusion resistor R. DIFF To fulfill its function.

[0091] The multiple electrodes gc contained in the electrode layer GC function as the gate electrodes of multiple transistors Tr that constitute the peripheral circuit PC, and as the other electrodes of multiple capacitors, etc. Additionally, as... Figure 6 As shown, a portion of the multiple electrodes gc contained in the electrode layer GC serves as the second resistive element, namely the GC resistor R. GC To fulfill its function.

[0092] The through-hole contact electrode CS extends along the Z direction and is connected at its lower end to the upper surface of the semiconductor substrate 200 or the electrode gc. The through-hole contact electrode CS may also include, for example, a multilayer film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0093] [Chip C] P [Structure of wiring layers D0, D1, D2, D3, D4]

[0094] For example, Figure 7 As shown, the multiple connection parts and multiple wirings contained in D0, D1, D2, D3, and D4 are electrically connected to the memory cell array layer L, for example. MCA The composition and chip C in P At least one of the components in.

[0095] The wiring layers D0, D1, and D2 each include multiple connection portions d0, d1, and d2 and multiple wirings. These multiple connection portions d0, d1, and d2 and the multiple wirings may, for example, comprise laminated films of barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W).

[0096] Wiring layers D3 and D4 each include multiple connection portions d3 and d4 and multiple wirings. These multiple connection portions d3 and d4 and multiple wirings may, for example, include barrier conductive films such as titanium nitride (TiN), tantalum nitride (TaN), multilayer films of tantalum nitride (TaN) and tantalum (Ta), or multilayer films of metal films such as copper (Cu).

[0097] [Structure of the chip bonding electrode layer DB]

[0098] The chip bonding electrode layer DB contains multiple wirings, for example, electrically connected to the memory cell array layer L. MCA The composition and chip C in P At least one of the components in.

[0099] The chip bonding electrode layer DB contains multiple bonding electrodes P I2 The plurality of bonding electrodes P I2 For example, it can also include barrier conductive films such as titanium nitride (TiN), tantalum nitride (TaN), or multilayer films of tantalum nitride (TaN) and tantalum (Ta). I2B and metal films such as copper (Cu) p I2M Laminated films, etc.

[0100] Furthermore, if a metal film such as copper (Cu) is applied... I1M p I2M Used for bonding electrode P I1 With the attached electrode P I2 Then the metal film p I1M With metal film p I2MThey will become integrated, making it difficult to define their boundaries. However, based on the bonding electrode P caused by the offset of the bonding position... I1 With the attached electrode P I2 Deformation of the shape after bonding, blocking the conductive film p I1B p I2B The positional offset (creating discontinuities on the side) is used to confirm the bonding structure. Additionally, the bonding electrode P is formed using an inlay method. I1 and bonding electrode P I2 In this case, their respective sides have an inclined shape. Therefore, regarding the bonding electrode P I1 With the attached electrode P I2 The cross-sectional shape of the bonded portion along the Z-direction shows that the sidewalls are not straight, but rather non-rectangular. Furthermore, when bonding electrode P... I1 With the attached electrode P I2 In the case of bonding, the structure consists of the bottom, side, and top surfaces of each Cu layer covered by a barrier metal. In contrast, in conventional wiring layers using Cu, an insulating layer (such as SiN or SiCN) that prevents Cu oxidation is placed on the top surface of the Cu layer, without a barrier metal. Therefore, even if no positional shift occurs during bonding, it can be distinguished from conventional wiring layers.

[0101] [Diffusion resistance R] DIFF and GC resistance R GC [Pattern]

[0102] Figure 8 It is Figure 7 The peripheral circuit region R shown PC The image shows a magnified top view of circuit region A. Alternatively, circuit region A can also be located in the peripheral region R. P Other areas.

[0103] Circuit region A comprises three circuit modules MDA, MDB, and MDC, and a resistive element region RES surrounding them. In the resistive element region RES, a diffused resistor R is formed as the first resistive element. DIFF and GC resistor R, which serves as the second resistive element. GC Diffusion resistance R DIFF and GC resistance R GC It is connected as part of the circuit elements to the three circuit modules MDA, MDB, and MDC. Furthermore, the number and configuration of the circuit modules are not limited to those illustrated.

[0104] Figure 9 and Figure 10 R represents the diffusion resistance in the first embodiment. DIFF and GC resistance R GC The pattern is shown in the image.Figure 9 yes Figure 8 An enlarged top view of circuit region B in the resistive element region RES. Figure 10 It is along Figure 9 The cross-sectional view obtained by cutting along the C-C' line and viewing from the direction of the arrow.

[0105] The resistor circuit of this embodiment has a semiconductor substrate 200 and a main surface S disposed on the semiconductor substrate 200. M The electrode layer GC on the side. On the main surface S of the semiconductor substrate 200. M On the side, multiple diffusion resistors R are installed. DIFF In this example, multiple diffusion resistors R DIFF It includes multiple P-type diffusion layers 200P formed within an N-type diffusion layer 200N (N-well). Multiple diffusion resistors R DIFF Along the main surface S of the semiconductor substrate 200 respectively M Extending parallel to the Y direction, and along the main surface S of the semiconductor substrate 200 M The X directions, parallel to and intersecting the Y direction, are arranged at a specified spacing P1. Each diffusion resistor R... DIFF On the end side in the Y direction, for example at both ends, there is a first connecting terminal portion T. DIFF .

[0106] Multiple diffusion resistors R on semiconductor substrate 200 DIFF An insulating layer STI is placed between them. The insulating layer STI surrounds multiple diffusion resistors R. DIFF Multiple diffusion resistors R are respectively placed along the sides in the X and Y directions. DIFF They are mutually insulated. The surface of the electrode layer GC side of the insulating layer STI serves as the electrode mounting surface S. G Functional operation. Electrode mounting surface S G From diffusion resistance R DIFF The upper surface (main surface S) M It protrudes until it contacts the lower surface of the electrode layer GC.

[0107] Electrode layer GC in multiple diffusion resistances R DIFF Electrode mounting surface S of the insulating layer STI between G It has multiple GC resistors R including electrodes gc. GC .also, Figure 9 In order to distinguish the GC resistor R GC With diffusion resistance R DIFF GC resistor R GC Shown with additional shading. For Figure 18 , Figure 20 , Figure 22 , Figure 24 and Figure 25The same applies. Multiple GC resistors R GC Electrode setting surfaces S of the insulating layer STI G Extending upwards along the Y direction and along the X direction to intersect with multiple diffusion resistors R DIFF The resistors are arranged with substantially equal, predetermined spacing P1. Each GC resistor R... GC On the end side in the Y direction, for example at both ends, there is a second connecting terminal portion T. GC .

[0108] In this embodiment, multiple diffusion resistors R DIFF With multiple GC resistors R GC They are configured alternately in the X direction.

[0109] Furthermore, in this embodiment, the diffusion resistance R DIFF The width W1 in the X direction is greater than the resistance R of GC. GC The width W2 in the X direction. Additionally, the width W3 in the X direction of the insulating layer STI is greater than the GC resistance R. GC The width W2 in the X direction. However, widths W1 and W2 can also be substantially equal.

[0110] [Effects of this implementation method]

[0111] On the surface of the semiconductor substrate 200, the area covered by the electrode gc (hereinafter referred to as "GC coverage") and the area not covered by the electrode gc (hereinafter referred to as "AA coverage") within a certain area must be ensured to be above 15% to 30% respectively to prevent unevenness in the planarization process. Assume that only a diffusion resistor R is formed in the resistive element region RES. DIFF When creating the pattern, it is necessary to use the diffusion resistor R. DIFF A fill pattern of electrode GC is formed around the GC to ensure the required GC coverage. Similarly, it is assumed that only GC resistance R is formed in the resistive element region RES. GC When creating the pattern, it is necessary to use the GC resistor R. GC A filling pattern is formed around the area where there is no electrode gc to ensure the required AA coverage.

[0112] In this case, any instance requires an additional fill area besides the resistive element, which in turn leads to a larger cell size.

[0113] In contrast, in this embodiment, the diffusion resistor R is... DIFF With GC resistance R GC By configuring them alternately, both GC coverage and AA coverage can be satisfied simultaneously without setting a fill area. Therefore, the area of ​​the resistive element region RES can be reduced.

[0114] [Examples of variations of the first embodiment]

[0115] Figure 11 This refers to variations of the first embodiment. Figure 10 The corresponding sectional view.

[0116] In this variation, the electrode mounting surface S of the insulating layer STI G The width W2 in the X direction and the GC resistance R GC The widths W2 in the X direction are substantially equal. In this case, due to the electrode mounting surface S of the insulating layer STI... G Specific diffusion resistance R DIFF The upper surface (main surface S) M The amount by which the electrode protrudes a further distance D towards the GC side increases the GC resistance R. GC and diffusion resistance R DIFF They can also be configured to be spaced apart from each other. Therefore, mutual insulation is ensured. According to this variation, the GC resistor R can be made... GC and diffusion resistance R DIFF The spacing P1' in the X direction is smaller than the spacing P1 in the first embodiment, which can further reduce the chip area.

[0117] [Diffusion resistance R] DIFF and GC resistance R GC Manufacturing method

[0118] Figures 12-17 The diffusion resistor R is used to illustrate this embodiment. DIFF and GC resistance R GC A cross-sectional view of the manufacturing method. Figures 12-17 The middle diagram shows the peripheral circuit region R. PC The resistive element region RES and other regions, such as the memory hole region R. MH The region that provides the form of transistor Tr.

[0119] In manufacturing diffusion resistor R DIFF and GC resistance R GC For example, Figure 12 As shown, an insulating layer 200G is formed on the surface of a semiconductor substrate 200 on which an N-type diffusion layer 200N (N-well) has been selectively formed in advance. This step is performed, for example, by thermal oxidation.

[0120] Next, for example, Figure 13 As shown, in relation to the reference Figure 10An opening 200A is formed at the location corresponding to the insulating layer STI, as described above. The opening 200A extends along the Z and Y directions, and at both ends of the Y direction, extends along the X direction. The opening 200A penetrates the insulating layer 200G and the N-type diffusion layer 200N in the Z direction, thus dividing a portion of the surface of the semiconductor substrate 200. This step is performed, for example, by a method such as RIE.

[0121] Next, for example, Figure 14 As shown, an insulating layer 200H is formed on a semiconductor substrate 200. This step is performed, for example, by CVD. Here, the opening 200A is embedded in the insulating layer 200H.

[0122] Next, for example, Figure 15 As shown, a portion of the insulating layer 200H is removed until the surface of the insulating layer 200G is exposed, forming an electrode setting surface S. G The insulating layer STI. This step is performed, for example, by methods such as CMP.

[0123] Next, for example, Figure 16 As shown, a conductive layer gcA comprising polycrystalline silicon or tungsten (W), or a two-layer structure of polycrystalline silicon and tungsten (W) gcA, is formed on the surfaces of the insulating layer STI and the insulating layer 200G. This step is performed, for example, by CVD, thermal oxidation, or sputtering.

[0124] Next, for example, Figure 17 As shown, a portion of the conductive layer gcA is removed to expose the surface of the semiconductor substrate 200, forming multiple electrodes gc. This step is performed, for example, by a resonant electrode assembly (RIE).

[0125] Therefore, in the resistive element region RES, the electrode setting surface S of the insulating layer STI G Above this, a GC resistor R containing the electrode gc is formed. GC Additionally, in the memory hole region R MH The region for forming the transistor Tr has a gate containing the electrode gc formed on the insulating layer 200G.

[0126] Next, P-type impurities such as boron (B) are implanted onto the surface of the exposed N-type diffusion layer 200N of the semiconductor substrate 200. This step is performed, for example, by ion implantation.

[0127] Therefore, in the resistive element region RES, an N-type diffusion layer 200N is formed between the insulating layers STI to create a diffusion resistor R formed by a P-type diffusion layer. DIFF Additionally, in the memory hole region R MH In the region of the transistor Tr, P-type diffusion layers serving as drain and source are formed on both sides of the gate electrode gc in the Y direction.

[0128] [Second Implementation]

[0129] Figure 18 and Figure 19 R represents the diffusion resistance in the second embodiment. DIFF and GC resistance R GC The pattern is shown in the image. Figure 18 Is with Figure 9 An enlarged top view of the area shown. Figure 19 It is along Figure 18 Cut along line D-D' and view the cross-section from the direction of the arrow.

[0130] In this embodiment, the diffusion resistance R DIFF With GC resistance R GC They are arranged alternately in multiple units (6 units in this example) along the X direction. Adjacent diffusion resistors R along the X direction... DIFF The width W4 of the insulating layer STI in the X direction is set to be smaller than the GC resistance R. GC The width W2 in the X direction is such that the diffusion resistance R is increased. DIFF Minimum width of inter-insulation. For configuring GC resistor R. GC The insulating layer STI is configured to be larger than the width W4 and to allow for the configuration of 6 GC resistors R. GC The width is W5.

[0131] diffusion resistance R DIFF Arranged in the X direction at a specified spacing P2, GC resistor R GC They are arranged in the X direction at a specified spacing P3. In the GC resistor R... GC The width W2 in the X direction is less than the diffusion resistance R. DIFF Given a width W1 in the X direction, as long as the diffusion resistance R DIFF and GC resistance R GC If the spacing in the X direction is of a certain width, then the spacing P3 can be made smaller than the spacing P2. Furthermore, the diffusion resistance R... DIFF The spacing P2 and GC resistance R GC The spacing P3 can also be the same. Regarding other configurations, since they are the same as in the first embodiment, detailed descriptions of repeated parts are omitted.

[0132] In this embodiment, in addition to the same effects as in the first embodiment, due to the multiple diffusion resistors R DIFF With multiple GC resistors R GC By alternating multiple units, the connection pattern can be simplified based on the shape of the wiring pattern for the circuit units to be connected. Furthermore, multiple diffused resistors R are constructed. DIFF With multiple GC resistors RGC The number is not limited to 6; it can be arbitrarily determined within the range of satisfying the AA coverage rate and GC coverage rate.

[0133] [Third Implementation]

[0134] Figure 20 and Figure 21 R represents the diffusion resistance in the third embodiment. DIFF and GC resistance R GC The pattern is shown in the image. Figure 20 Is with Figure 9 An enlarged top view of the area shown. Figure 21 It is along Figure 20 The cross-sectional view obtained by cutting along the E-E' line and viewing from the direction of the arrow.

[0135] In this embodiment, there are 3 diffusion resistors R DIFF With 1 GC resistor R GC Alternating configurations in the X direction. Adjacent diffusion resistances R in the X direction. DIFF The width W4 of the insulating layer STI in the X direction is set to be smaller than the GC resistance R. GC The width W2 in the X direction is such that the diffusion resistance R is increased. DIFF Minimum width of inter-insulation. For configuring GC resistor R. GC The insulating layer STI is set to be greater than the width W4 and to allow for the configuration of one GC resistor R. GC The width W3. Regarding other components, since they are the same as in the first embodiment, detailed descriptions of repeated parts are omitted.

[0136] Alternatively, as in this embodiment, different numbers of diffusion resistors R can be alternately configured. DIFF With GC resistance R GC In this embodiment, compared to the GC resistor R GC More use of diffusion resistor R DIFF In certain situations, it can be used as a pattern.

[0137] In this case, there is no need to set a filling area, so the area of ​​the resistive element region RES can be reduced.

[0138] [Fourth Implementation]

[0139] Figure 22 and Figure 23 R represents the diffusion resistance in the fourth embodiment. DIFF and GC resistance R GC The pattern is shown in the image. Figure 22 Is with Figure 9 An enlarged top view of the area shown. Figure 23 It is along Figure 22Cut along line F-F' and view the resulting cross-section from the direction of the arrow.

[0140] In this embodiment, one diffusion resistor R DIFF With 3 GC resistors R GC Alternately configured in the X direction. GC resistor R is provided for configuration. GC The insulating layer STI is configured to allow for the configuration of 3 GC resistors R GC The width W6. Regarding other components, since they are the same as in the first embodiment, detailed descriptions of repeated parts are omitted.

[0141] As in this embodiment, different numbers of diffusion resistors R can also be configured alternately. DIFF With GC resistance R GC In this embodiment, compared to the diffusion resistance R DIFF More use of GC resistor R GC In certain situations, it can be used as a pattern.

[0142] In this case, there is no need to set a filling area, so the area of ​​the resistive element region RES can be reduced.

[0143] [Fifth Implementation]

[0144] Figure 24 R represents the diffusion resistance in the fifth embodiment. DIFF and GC resistance R GC The pattern is shown in the image. Figure 24 Is with Figure 9 An enlarged top view of the area shown.

[0145] In this embodiment, multiple diffusion resistors R DIFF With multiple GC resistors R GC They are arranged alternately in the X direction. Diffusion resistance R DIFF The length L1 in the Y direction is less than the resistance R in the GC direction. GC The length L2 in the Y direction. Multiple diffusion resistors R DIFF At one end in the Y direction, via the odd-numbered first connection terminal T DIFF and the first connecting terminal T adjacent to its X-direction side DIFF Interconnection wiring extending along the X direction W DIFF The series connection, at the other end in the Y direction, is via the even-numbered first connection terminal T. DIFF and the first connecting terminal T adjacent to its X-direction side DIFF Interconnection wiring extending along the X direction W DIFF And connected in series. Multiple GC resistors R GC At one end in the Y direction, via the odd-numbered second connection terminal TGC and the second connecting terminal T adjacent to its X-direction side GC Interconnection wiring extending along the X direction W GC The series connection, at the other end in the Y direction, is via the even-numbered second connection terminal T. GC and the second connecting terminal T adjacent to its X-direction side GC Interconnection wiring extending along the X direction W GC The components are connected in series. Regarding other configurations, since they are the same as in the first embodiment, detailed descriptions of repeated parts are omitted.

[0146] As in this embodiment, the diffusion resistance R DIFF With GC resistance R GC They don't necessarily have to be the same length. For example, the diffusion resistance R DIFF The length L1 in the Y direction can also be greater than the GC resistance R. GC The length L2 in the Y direction is longer. Additionally, by increasing the diffusion resistance R... DIFF and GC resistance R GC These components, connected in series, can provide resistive elements with the desired resistance value.

[0147] [Sixth Implementation]

[0148] Figure 25 R represents the diffusion resistance in the sixth embodiment. DIFF and GC resistance R GC The pattern is shown in the image. Figure 25 Is with Figure 9 An enlarged top view of the area shown.

[0149] In this embodiment, when viewed from the Z direction, multiple diffusion resistors R DIFF With multiple GC resistors R GC They are arranged alternately in the X direction. Multiple diffusion resistors R DIFF and multiple GC resistors R GC At one end in the Y direction, via a second connecting terminal T that is adjacent to each other and will be disposed on one side in the X direction. GC The first connection terminal T, which is located on the other side in the X direction DIFF The connection is a wiring W extending along the X direction. DG And at the other end in the Y direction, via the first connecting terminal T which is adjacent to each other and will be arranged on one side in the X direction. DIFF The second connection terminal T is located on the other side in the X direction. GC The connection is a wiring W extending along the X direction. DG They are connected in series one after another, alternatingly. Regarding other configurations, since they are the same as in the first embodiment, detailed descriptions of repeated parts are omitted.

[0150] According to this embodiment, by using the diffusion resistor R DIFF With GC resistance R GC Alternating series connections can provide resistive elements with the desired resistance value.

[0151] [Other Implementation Methods]

[0152] The semiconductor memory devices according to the first to sixth embodiments have been described above. However, the configurations described above are merely illustrative, and the specific configurations can be adjusted appropriately.

[0153] For example, in each of the embodiments described, a P-type diffusion layer 200P formed within an N-type diffusion layer 200N (N-well) is used as the diffusion resistance R. DIFF However, an N-type diffusion layer 200N formed within a P-type diffusion layer 200P (P-well) can also be used as the diffusion resistance R. DIFF .

[0154] In addition, the diffusion resistance R shown in the above embodiments DIFF and GC resistance R GC They can also be used as a dummy resistor that is not connected to any circuit.

[0155] Furthermore, the above embodiments have described an example applied to NAND flash memory. However, the techniques described in this specification can also be applied to other configurations besides NAND flash memory, such as three-dimensional NOR flash memory. Additionally, the techniques described in this specification can also be applied to semiconductor memory devices other than flash memory, such as three-dimensional DRAM, and to semiconductor devices other than semiconductor memory devices.

[0156] [other]

[0157] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in many other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0158] [Explanation of Symbols]

[0159] 100, 110: Conductive layer

[0160] 120: Semiconductor layer

[0161] 200: Semiconductor substrate

[0162] C M :chip

[0163] C P :chip

[0164] BL: Bitline

[0165] WL: Word Line

[0166] SG, SGD, SGS: Select gate line

[0167] CC: Through-hole contact electrode

[0168] MC: Storage Unit

[0169] M0, M1, D0, D1, D2, D3, D4: Wiring layers

[0170] GC: Electrode layer

[0171] gc: electrode

[0172] MB, DB: Chip bonding electrode layer

[0173] RES: Resistor element area

[0174] MDA, MDB, MDC: Circuit Modules

[0175] R DIFF Diffusion resistance

[0176] R GC GC resistor

[0177] STI: Insulating Layer

[0178] T DIFF : First connecting terminal section

[0179] T GC : Second connecting terminal section.

Claims

1. A semiconductor device comprising: a semiconductor substrate having a main surface including a first direction and a second direction intersecting the first direction; an electrode layer provided on the main surface side; a plurality of first resistance elements including a plurality of diffusion layers provided on the main surface side of the semiconductor substrate, extending in the first direction, arranged in the second direction, and each having a first connection terminal on an end portion side in the first direction; and an insulating layer provided on the main surface side of the semiconductor substrate between each of the plurality of first resistance elements, having an electrode-arranging surface in contact with the electrode layer, and the electrode layer including a plurality of second resistance elements including a plurality of conductive layers provided on the electrode-arranging surface of the insulating layer between the plurality of first resistance elements, extending in the first direction, arranged in the second direction, and each having a second connection terminal portion on an end portion side in the first direction.

2. The semiconductor device according to claim 1, wherein the plurality of first resistance elements and the plurality of second resistance elements are alternately arranged one by one in the second direction.

3. The semiconductor device according to claim 1, wherein the plurality of first resistance elements and the plurality of second resistance elements are alternately arranged in units of a plurality in the second direction.

4. The semiconductor device according to claim 1, wherein one of the plurality of second resistance elements is arranged between a part of the plurality of first resistance elements and another part of the plurality of first resistance elements.

5. The semiconductor device according to claim 1, wherein one of the plurality of first resistance elements is arranged between a part of the plurality of second resistance elements and another part of the plurality of second resistance elements.

6. The semiconductor device according to claim 1, wherein the plurality of diffusion layers are P-type diffusion layers.

7. The semiconductor device according to claim 1, wherein the plurality of diffusion layers are N-type diffusion layers.

8. The semiconductor device according to claim 1, wherein at least two of the plurality of first resistance elements are electrically connected in series via the first connection terminal portions, and at least two of the plurality of second resistance elements are electrically connected in series via the second connection terminal portions.

9. The semiconductor device according to claim 1, wherein at least two of the plurality of first resistance elements and at least two of the plurality of second resistance elements are alternately electrically connected in series via the first connection terminal portions and the second connection terminal portions.

10. The semiconductor device according to claim 1, further comprising: a transistor having a gate electrode, and the electrode layer further including the gate electrode.

11. The semiconductor device according to claim 1, wherein the electrode-arranging surface of the insulating layer protrudes more toward the electrode layer side than the main surface of the semiconductor substrate.

12. The semiconductor device according to claim 11, wherein a width of the electrode-arranging surface of the insulating layer in the second direction is equal to a width of the second resistance elements in the second direction. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 13. The semiconductor device according to claim 1, wherein a width of the second direction of the first resistive element is larger than a width of the second direction of the second resistive element.

14. The semiconductor device according to claim 3, wherein a pitch of the second direction of the plurality of first resistive elements is larger than a pitch of the second direction of the plurality of second resistive elements.

15. The semiconductor device according to claim 1, wherein a length of the first direction of the first resistive element is different from a length of the first direction of the second resistive element.

16. A semiconductor device comprising: a memory cell array layer; a semiconductor substrate having a main surface facing the memory cell array layer, the main surface extending in a first direction and a second direction intersecting the first direction, forming at least a part of a peripheral circuit controlling the memory cell array layer; and an electrode layer provided between the main surface of the memory cell array layer and the semiconductor substrate; wherein the peripheral circuit has a resistive element region, the resistive element region comprises: a plurality of first resistive elements including a plurality of diffusion layers provided on the main surface side of the semiconductor substrate, extending in the first direction, arranged in the second direction, and each having a first connection terminal at an end portion side in the first direction; and an insulating layer provided on the main surface side of the semiconductor substrate between each of the plurality of first resistive elements, having an electrode placement surface in contact with the electrode layer; and the electrode layer includes: a plurality of second resistive elements including a plurality of conductive layers provided on the electrode placement surface of the insulating layer between the plurality of first resistive elements, extending in the first direction, arranged in the second direction, and each having a second connection terminal portion at an end portion side in the first direction.

17. The semiconductor device according to claim 16, wherein the peripheral circuit further has a transistor having a gate electrode, the electrode layer further includes the gate electrode.

18. The semiconductor device according to claim 16, wherein the electrode placement surface of the insulating layer protrudes more toward the electrode layer side than the main surface of the semiconductor substrate.

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