Semiconductor device, manufacturing method thereof, and memory system

Abstract

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and a memory system. The semiconductor device includes a first stack structure, a first insulating structure and a select gate cut structure. The first stack structure comprises dielectric layers and gate layers which are alternately arranged, and the gate layers comprise a first gate layer and a second gate layer located on one side of the first gate layer; the first insulating structure passes through the first gate layer; the selection gate cutting line structure passes through the first gate layer and extends to the first insulation structure along the first direction.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and more particularly, to a semiconductor device, a manufacturing method of the semiconductor device, and a memory system. BACKGROUND

[0002] In the manufacturing process of the semiconductor device, the manufacturing flow is complex, and the process control is difficult, thereby affecting the reliability of the semiconductor device and the reduction of the manufacturing cost. SUMMARY

[0003] In a first aspect, some embodiments of the present application provide a semiconductor device. The semiconductor device includes a first stack structure, a first insulating layer, and a select gate cutline structure. The first stack structure includes dielectric layers and gate layers arranged alternately, wherein the gate layers include a first gate layer and a second gate layer located on one side of the first gate layer. The first insulating structure passes through the first gate layer. The select gate cutline structure passes through the first gate layer and extends to the first insulating structure along a first direction.

[0004] In an example embodiment, the semiconductor device further includes a gate line isolation structure passing through the first stack structure and extending along the first direction.

[0005] In an example embodiment, one or more select gate cutline structures are located between the gate line isolation structures adjacent in a second direction, the first insulating structure continuously extends along the second direction and contacts at least one gate line isolation structure adjacent in the second direction, and the first direction intersects the second direction.

[0006] In an example embodiment, a plurality of select gate cutline structures are located between the gate line isolation structures adjacent in a second direction, the first insulating structure includes a first insulating portion and a second insulating portion arranged in the second direction, wherein the first insulating portion and the second insulating portion respectively contact the gate line isolation structures adjacent in the second direction, and the first direction intersects the second direction.

[0007] In an example embodiment, the select gate cutline structures are all in contact with the first insulating structure.

[0008] In an example embodiment, the semiconductor device further includes a connection structure. The connection structure passes through the first gate layer, is located on one side of the first insulating structure in the first direction, and is located between the select gate cutline structures adjacent in a second direction or between the select gate cutline structures and the gate line isolation structure, and the first direction intersects the second direction.

[0009] In an example embodiment, the semiconductor device further includes a first channel structure and a second channel structure. The first channel structure extends in the first stack structure and is located at a side of the connection structure close to the first insulating structure in the first direction. The second channel structure extends in the first stack structure and is located at a side of the connection structure away from the first insulating structure in the first direction, wherein the second channel structure is connected with the bit line structure.

[0010] In an example embodiment, the semiconductor device further includes a second stack structure. The first stack structure is located at opposite sides of the second stack structure in a second direction and at least one side of the first stack structure in the first direction, and the second stack structure includes dielectric layers and insulating layers alternately arranged, wherein the insulating layers are connected with the gate layers, and the first direction intersects the second direction.

[0011] In an example embodiment, the semiconductor device includes an array region and a connection region in a plane perpendicular to the stacking direction, the connection region is located at a side of the array region in the first direction, the first insulating structure and the select gate cutline structure are located in the array region, and the second stack structure is located in the connection region.

[0012] In an example embodiment, the gate line isolation structure includes a first gate line isolation portion, a second insulating structure, and a second gate line isolation portion connected with each other in the first direction. The first gate line isolation portion extends in the array region along the first direction, and the second gate line isolation portion extends in the connection region along the first direction.

[0013] In an example embodiment, a material of the first insulating structure includes silicon oxide.

[0014] In a second aspect, some embodiments of the present application provide a memory system. The memory system includes a memory and a controller. The memory includes the semiconductor device mentioned in any of the embodiments above, and the controller is coupled with the memory and configured to control the memory to store data.

[0015] In a third aspect, some embodiments of the present application provide a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes: forming a first stack structure, wherein the first stack structure includes dielectric layers and gate layers alternately arranged, and the gate layers include a first gate layer and a second gate layer located at a side of the first gate layer; forming a first insulating structure, wherein the first insulating structure passes through the first gate layer; and forming a select gate cutline structure extending to the first insulating structure along a first direction, wherein the select gate cutline structure passes through the first gate layer.

[0016] In an example embodiment, forming the first stack structure includes: forming an initial stack structure, wherein the initial stack structure includes dielectric layers and insulating layers alternately arranged; and replacing a portion of the insulating layers with the gate layers, wherein the dielectric layers and the gate layers alternately arranged are the first stack structure.

[0017] In an example embodiment, the first insulating structure is formed before replacing a portion of the insulating layer with the gate layer.

[0018] In an example embodiment, the select gate cutline structure is formed after replacing a portion of the insulating layer with the gate layer.

[0019] In an example embodiment, forming the first insulating structure includes forming a first trench from a side of the initial stack structure in the stacking direction, and filling the first trench with an insulating material to form the first insulating structure.

[0020] In an example embodiment, the manufacturing method further includes forming a first gate line slit portion, at least one first opening, and a second gate line slit portion through the initial stack structure, wherein the first gate line slit portion, the at least one first opening, and the second gate line slit portion are arranged in the first direction; removing a portion of the insulating layer via the at least one first opening, and forming a plurality of gaps; filling the plurality of gaps with an insulating material to form a second insulating structure; and forming a first gate line isolation portion at the first gate line slit portion, and forming a second gate line isolation portion at the second gate line slit portion.

[0021] In an example embodiment, the first trench and the plurality of gaps are formed using a same mask.

[0022] In an example embodiment, the manufacturing method further includes forming a connection structure through the first gate layer, wherein the connection structure is located at a side of the first insulating structure in the first direction. BRIEF DESCRIPTION OF DRAWINGS

[0023] Other features, objects, and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments thereof as taken in conjunction with the accompanying drawings. In the drawings:

[0024] FIG. 1A is a schematic cross-sectional view of a semiconductor device provided by an embodiment of the present application;

[0025] FIG. 1B is a schematic cross-sectional view of a semiconductor device provided by an embodiment of the present application, taken in another plane;

[0026] FIG. 1C is a schematic cross-sectional view of a semiconductor device provided by an embodiment of the present application, taken in yet another plane;

[0027] FIG. 2 is a schematic cross-sectional view of a second channel structure and a bit line structure in a semiconductor device provided by an embodiment of the present application;

[0028] FIG. 3 is a schematic cross-sectional view of a semiconductor device provided by another embodiment of the present application;

[0029] FIG. 4 to FIG. 6 is a cross-sectional schematic view of a semiconductor device provided by some embodiments of the present application;

[0030] FIG. 7 is a flowchart schematic view of a manufacturing method of a semiconductor device provided by embodiments of the present application;

[0031] FIG. 8A to FIG. 16B is a schematic view of a structure of a semiconductor device in a manufacturing process provided by embodiments of the present application;

[0032] FIG. 17 is a schematic block diagram of a system having a memory system provided by embodiments of the present application; and

[0033] FIG. 18A and FIG. 18B is a schematic block diagram of a memory system provided by embodiments of the present application. DETAILED DESCRIPTION

[0034] For a better understanding of the present application, various aspects of the present application will be described in greater detail below with reference to the accompanying drawings. It should be understood that these detailed description is merely descriptive of exemplary embodiments of the present application and is not intended in any way to limit the scope of the present application. Throughout the specification, like reference numerals will refer to like elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] It should be noted that in this specification, the expressions first, second, third and the like are used only to distinguish one feature from another, and do not denote any limitation on the features, especially do not denote any sequential order. Thus, the first gate layer discussed in the present application can also be referred to as the second gate layer, and vice versa, without departing from the teachings of the present application.

[0036] In the drawings, the thickness, size, and shape of components have been slightly adjusted for ease of illustration. The drawings are merely schematic and are not drawn to scale. As used in this document, the terms "substantially", "approximately", and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in a measuring or computing process.

[0037] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0038] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0039] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0040] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or can be inferred from the context.

[0041] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0042] Some embodiments of this application provide a semiconductor device. FIG. 1A This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application. FIG. 1B This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application, taken on another plane. FIG. 1C This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application, taken on another plane. FIG. 2 This is a cross-sectional schematic diagram of the second channel structure and bit line structure in the semiconductor device provided in the embodiments of this application. For example, FIG. 1B This can be a cross-sectional schematic diagram taken from the plane containing the surface of the first gate layer. FIG. 1C This can be a cross-sectional schematic diagram taken from the plane containing the surface of the second gate layer.

[0043] It should be noted that the D1 direction (corresponding to the first direction), D2 direction (corresponding to the second direction), and D3 direction in the various figures illustrate the spatial relationships of the components in the semiconductor device. For example, the D3 direction may be the stacking direction, and the D1 and D2 directions may be two directions that intersect (e.g., are perpendicular) to each other on a plane that intersects (e.g., are perpendicular) to the D3 direction. For example, the D1 direction may be the extension direction of the selected gate tangent structure. The same concepts will be used throughout this application to describe the spatial relationships of the components in the semiconductor device.

[0044] like FIG. 1A to FIG. 1C As shown, the semiconductor device 100 may include a first stacked structure 111, a first insulating structure 114, and a select gate tangent structure 115. The first stacked structure 111 may include alternating dielectric layers 112 and gate layers 113. The gate layer 113 may include a first gate layer 1131 and a second gate layer 1132 located on one side of the first gate layer 1131. The first insulating structure 114 may pass through the first gate layer 1131. The select gate tangent structure 115 may pass through the first gate layer 1131 and extend along the D1 direction to the first insulating structure 114.

[0045] The semiconductor device 100 provided in this application embodiment has a selected gate tangent structure 115 extending along the D1 direction to a first insulating structure 114, which can electrically isolate the portions of the first gate layer 1131 located on both sides of the selected gate tangent structure 115 in the D2 direction. The first insulating structure 114 passes through the first gate layer 1131 and does not extend to the second gate layer 1132. If the selected gate tangent structure 115 extends to the second gate layer 1132 near the first gate layer 1131, such as... FIG. 1C The dashed box shown may represent the portion of the selected gate tangent structure 115 extending into the second gate layer 1132, since the second gate layer 1132 can be arranged according to... FIG. 1C The path indicated by the arrows extends continuously, so as not to affect the electrical connection between the second gate layers 1132, and thus not to affect the electrical connection requirements of the second gate layers 1132 through which the selected gate tangent structure 115 passes, which helps to improve the reliability of the semiconductor device 100.

[0046] In some implementations, reference continues. FIG. 1A to FIG. 1CThe dielectric layer 112 may be located between adjacent gate layers 113 in the D3 direction. For example, a dielectric layer 112 may be located between adjacent first gate layers 1131 in the D3 direction, or between adjacent first gate layers 1131 and second gate layers 1132 in the D3 direction, or between adjacent second gate layers 1132 in the D3 direction. The outermost layer of the first stacked structure 111 in the D3 direction may be the dielectric layer 112. The dielectric layer 112 may extend along the D1 and D2 directions, and the gate layers 113 (e.g., first gate layer 1131 and second gate layer 1132) may also extend along the D1 and D2 directions. For example, the number of stacked layers of dielectric layer 112 and gate layer 113 may include 32 layers, 64 layers, 128 layers, 258 layers, and more, and this application does not impose a specific limitation on this. The first gate layer 1131 may serve as a select line, and its number may be one or more (e.g., 3 to 5), and this application does not impose a specific limitation on this.

[0047] In some embodiments, the material of dielectric layer 112 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. For example, the material of dielectric layer 112 may be silicon oxide.

[0048] In some embodiments, the material of the first gate layer 1131 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, silicon, germanium, germanium silicon, or any other suitable conductive material. The material of the second gate layer 1132 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, silicon, germanium, germanium silicon, or any other suitable conductive material.

[0049] In some embodiments, the first gate layer 1131 may be made of a single conductive material, and the second gate layer 1132 may also be made of a single material. In other embodiments, the first gate layer 1131 may include a first metal layer and a first adhesive layer (not shown) covering at least a portion of the surface of the first metal layer. For example, the material of the first metal layer may include one or more of tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable metallic material. The material of the first adhesive layer may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, or any other suitable adhesive material. Optionally, at least a portion of the surface of the first adhesive layer may be covered with a first high dielectric constant layer (not shown). The material of the first high dielectric constant layer may include, but is not limited to, alumina, titanium oxide, tantalum oxide, hafnium oxide, zirconium oxide, etc. Similarly, the second gate layer 1132 may include a second metal layer and a second adhesive layer (not shown) covering at least a portion of the surface of the second metal layer. For example, the material of the second metal layer may include one or more of tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable metallic material. The material of the second adhesive layer may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, or any other suitable adhesive material. Optionally, at least a portion of the surface of the second adhesive layer may be covered with a second high-dielectric-constant layer (not shown). The material of the second high-dielectric-constant layer may include, but is not limited to, alumina, titanium oxide, tantalum oxide, hafnium oxide, zirconium oxide, etc. For example, the materials of the first gate layer 1131 and the second gate layer 1132 may be the same or different, and this application does not impose specific limitations in this regard.

[0050] In some embodiments, the semiconductor device 100 may further include a second stacked structure 116. A first stacked structure 111 may be located on opposite sides of the second stacked structure 116 in the D2 direction and on at least one side in the D1 direction. The second stacked structure 116 may include alternating dielectric layers 112 and insulating layers 117. The insulating layer 117 is connected to the gate layer 113. For example, the first stacked structure 111 contacts opposite sides of the second stacked structure 116 in the D2 direction and on one side in the D1 direction. Alternatively, the first stacked structure 111 contacts opposite sides of the second stacked structure 116 in the D2 direction and on opposite sides in the D1 direction (not shown). In other words, viewed from the D3 direction, the first stacked structure 111 is disposed around the second stacked structure 116. The dielectric layers 112 in the second stacked structure 116 and the first stacked structure 111 may be a single, integral structure. The insulating layer 117 may be embedded between adjacent dielectric layers 112 in the D3 direction. The material of the insulating layer 117 may be different from that of the dielectric layer 112. If the dielectric layer 112 is made of silicon oxide, the material of the insulating layer 117 may include silicon nitride.

[0051] In some embodiments, the semiconductor device 100 includes an array region AR and a connection region CR in a plane perpendicular to the D3 direction. The connection region CR may be located on one side of the array region AR in the D1 direction. For example, when a first stacked structure 111 surrounds a second stacked structure 116, the two array regions AR may be located on opposite sides of a connection region CR in the D1 direction. The second stacked structure 116 may be located within the connection region CR. The portion of the first stacked structure 111 located on one side of the second stacked structure 116 in the D1 direction may be located within the array region AR, and the portions of the first stacked structure 111 located on opposite sides of the second stacked structure 116 in the D2 direction may be located within the connection region CR. The array region AR may have a plurality of arrayed first channel structures 120 and second channel structures 121. The first channel structures 120 and second channel structures 121 will be described below. The connection region CR may have a plurality of contact structures (not shown). For example, each contact structure may extend along the D3 direction into each insulating layer 117 and connect to the second gate layer 1132, thereby leading the second gate layer 1132 out from the D3 direction.

[0052] In some embodiments, the semiconductor device 100 may further include a gate isolation structure 118. The gate isolation structure 118 may extend through the first stacked structure 111 and along the D1 direction. For example, the gate isolation structure 118 may extend within the array region AR and the connection region CR, and may be used to electrically isolate the gate layers 113 located on either side of it in the D2 direction. Multiple gate isolation structures 118 may be spaced apart in the D2 direction. Adjacent gate isolation structures 118 in the D2 direction may divide the first stacked structure 111 and the second stacked structure 116 into memory blocks BLK. The material of the gate isolation structure 118 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. Alternatively, the gate isolation structure 118 may include a polysilicon body extending along the D1 direction, and a silicon oxide layer covering the sidewalls and bottom of the polysilicon body. When the gate isolation structure 118 is manufactured using both polysilicon and silicon oxide, it helps to optimize the structural stress of the semiconductor device 100.

[0053] In some embodiments, a single gate isolation structure 118 may include a first gate isolation portion 1181, a second insulating structure 1183, and a second gate isolation portion 1182 interconnected in the D1 direction. The first gate isolation portion 1181 may extend in the D1 direction within the array region AR, and the second gate isolation portion 1182 may extend in the D1 direction within the connection region CR. For example, a portion of the second insulating structure 1183 may be located within the array region AR, and another portion may be located within the connection region CR. The material of the second insulating structure 1183 may be different from the material of the insulating layer 117. If the material of the insulating layer 117 is silicon nitride, the material of the second insulating structure 1183 may include silicon oxide. In this embodiment, the gate layer 113 may be formed by a "gate replacement" process. Since the shape of the portion of the gate layer 113 located in the array region AR is different from that of the portion of the gate layer 113 located in the connection region CR, the second insulating structure 1183 may be used to block etching materials (e.g., etchants) during the partitioning process of forming the gate layer 113.

[0054] In some embodiments, one surface of the first insulating structure 114 in the D3 direction may be substantially flush with the surface of the first stacked structure 111 and extend along the D3 direction through the first gate layer 1131. The material of the first insulating structure 114 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. For example, the material of the first insulating structure 114 may be different from the material of the insulating layer 117. If the material of the insulating layer 117 is silicon nitride, the material of the first insulating structure 114 may include silicon oxide. Optionally, the insulating material forming the first insulating structure 114 may cover the surfaces of the first stacked structure 111 and the second stacked structure 116, such as the surface of the outermost dielectric layer 112. When the insulating material is the same as the dielectric layer 112, there is no obvious interface between the insulating material film covering the surfaces of the first stacked structure 111 and the second stacked structure 116 and the dielectric layer 112.

[0055] In some embodiments, the first insulating structure 114 may be located within the array region AR. For example, the first insulating structure 114 may be spaced apart from the connection region CR in the D1 direction.

[0056] In some implementations, one surface of the selected gate tangent structure 115 in the D3 direction may be flush with the surface of the first stacked structure 111 and extend along the D3 direction through the first gate layer 1131. For example, due to process limitations, the selected gate tangent structure 115 may further extend along the D3 direction through one or more second gate layers 1132 near the first gate layer 1131, such as... FIG. 1CThe portion corresponding to the dashed box shown. For example, the selected gate tangent structure 115 may extend along the D1 direction within the array region AR to the surface or interior of the first insulating structure 114. The material of the selected gate tangent structure 115 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. For example, the material of the selected gate tangent structure 115 may be silicon oxide. When the material of the first insulating structure 114 is the same as the material of the selected gate tangent structure 115, there is no obvious interface between the portion of the selected gate tangent structure 115 extending into the interior of the first insulating structure 114 and the first insulating structure 114.

[0057] In some implementations, multiple select gate tangent structures 115 may be spaced apart in the D2 direction, and the multiple select gate tangent structures 115 may be located between adjacent gate isolation structures 118 in the D2 direction. For example, viewed from the D3 direction, the region between the gate isolation structure 118 and the select gate tangent structure 115, or the region between adjacent select gate tangent structures 115 in the D2 direction, may be referred to as a pointer memory region FR. For example, the array region AR in a memory block BLK may be further divided into at least two pointer memory regions FR.

[0058] The following is based on FIG. 1A to FIG. 1C The adjacent gate isolation structures 118 shown have two selected gate tangent structures 115, which further illustrate the components in the semiconductor device 100.

[0059] In some embodiments, the memory block BLK can be divided into three finger memory regions FR. A first insulating structure 114 extends continuously along the D2 direction to two adjacent gate line isolation structures 118 in the D2 direction. In other words, the first insulating structure 114 is in contact with both adjacent gate line isolation structures 118 in the D2 direction. All selected gate tangent structures 115 between adjacent gate line isolation structures 118 in the D2 direction extend along the D1 direction into the interior of the first insulating structure 114, thereby contacting the first insulating structure 114. The portions of each first gate layer 1131 located within each finger memory region FR are electrically isolated from each other, allowing control signals to be applied individually.

[0060] In some embodiments, the semiconductor device 100 may further include a connection structure 119. The connection structure 119 may pass through the first gate layer 1131. The connection structure 119 may be located on one side of the first insulating structure 114 in the D1 direction and between adjacent select gate tangent structures 115 in the D2 direction, or between the select gate tangent structure 115 and the gate isolation structure 118. For example, the connection structure 119 may be generally columnar. A connection structure 119 may be provided within each finger memory region FR. Multiple connection structures 119 within each finger memory region FR may be arranged generally collinearly along the D2 direction. The connection structure 119 may be used to lead the first gate layer 1131 out in the D3 direction. In some exemplary embodiments, the semiconductor device does not have a first insulating structure, multiple first gate layers form steps near the edges of the connection region CR, and multiple connection structures extend to the multiple steps to lead the multiple first gate layers out in the D3 direction, and then interconnect the multiple connection structures through a back-end interconnect structure. Compared to this exemplary embodiment, the multiple first gate layers do not require the formation of steps, thereby simplifying the process steps. Furthermore, the connection structure 119 passes through and contacts the multiple first gate layers 1131, eliminating the need for additional back-end interconnect structures and further simplifying the structure.

[0061] It should be noted that the provision of one connection structure 119 in each finger storage area FR is merely an example. In other examples, more connection structures 119 may be provided in each finger storage area FR. In this case, redundant design can be achieved and the reliability of the semiconductor device 100 can be improved.

[0062] In some embodiments, the semiconductor device 100 may further include a first channel structure 120 and a second channel structure 121. The first channel structure 120 may extend in the first stacked structure 111 and is located on the side of the connection structure 119 adjacent to the first insulating structure 114 in the D1 direction. The second channel structure 121 may also extend in the first stacked structure 111 and is located on the side of the connection structure 119 opposite to the first insulating structure 114 in the D1 direction. The second channel structure 121 may be connected to the bit line structure 122, such as... FIG. 2 As shown. For example, in the case where multiple connection structures 119 within each pointer memory area FR are arranged substantially collinearly along the D2 direction, multiple first channel structures 120 may be arrayed on one side of the multiple connection structures 119 in the D1 direction. A portion of the multiple first channel structures 120 may also pass through the first insulating structure 114. The multiple first channel structures 120 are not connected to the bit line structure 122 and can be used to provide mechanical support and / or load balancing. Multiple second channel structures 121 may be arrayed on the other side of the multiple connection structures 119 in the D1 direction. The multiple second channel structures 121 are connected to the bit line structure 122 for use as data storage.

[0063] In some embodiments, the first channel structure 120 and the second channel structure 121 may have the same outline shape and internal structure. The second channel structure 121 is used as an example below for illustration. For example, as... FIG. 1A and FIG. 2 As shown, the second channel structure 121 may be generally columnar. The second channel structure 121 may extend along the D3 direction through the first gate layer 1311 and the second gate layer 1132. The second channel structure 121 may include an insulating pillar 123, a channel layer 124, and a storage function layer 125. The insulating pillar 123 may extend along the D3 direction in the first stack structure 111 and protrude from the first stack structure 111 on the side of the second gate layer 1132 opposite to the first gate layer 1131. The channel layer 124 may surround the portion of the insulating pillar 123 located in the first stack structure 111. The storage function layer 125 may surround the channel layer 124. For example, the storage function layer 125 may include a tunneling layer 1251, a charge trapping layer 1252, and a barrier layer 1253. The tunneling layer 1251 may surround the channel layer 124, the charge trapping layer 1252 may surround the tunneling layer 1251, and the barrier layer 1253 may surround the charge trapping layer 1252.

[0064] In some embodiments, the insulating pillar 123 may be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. The channel layer 124 may be made of one or more of polycrystalline silicon, amorphous silicon, germanium silicon, or any other suitable semiconductor material. The tunneling layer 1251, the charge trapping layer 1252, and the barrier layer 1253 may be made of silicon oxide, silicon nitride, and silicon oxide, respectively.

[0065] In some embodiments, a portion of the second channel structure 121 surrounded by a second gate layer 1132 and a portion of the second gate layer 1132 may constitute a memory cell. Other portions of the second gate layer 1132 may serve as word lines. A portion of the second channel structure 121 surrounded by a first gate layer 1131 and a portion of the first gate layer 1131 may constitute a select transistor. Other portions of the first gate layer 1131 may serve as select lines. Multiple memory cells and at least one select transistor are arranged in series along the extension direction of the second channel structure 121 (e.g., the D3 direction) to form a memory string and share the channel layer 124.

[0066] FIG. 3 This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of this application. In this embodiment and the following embodiments, the same reference numerals refer to the same components. Furthermore, for the purpose of brevity, the same components will not be described again in this embodiment and the following embodiments.

[0067] likeFIG. 3 As shown, two select gate tangent structures 115 may be located between adjacent gate isolation structures 118 in the D2 direction. The memory block BLK may be divided into three finger memory regions FR. The first insulating structure 114 may include a first insulating portion 1141 and a second insulating portion 1142 arranged in the D2 direction. The first insulating portion 1141 may contact one of the adjacent gate isolation structures 118 in the D2 direction, and the second insulating portion 1142 may contact one of the adjacent gate isolation structures 118 in the D2 direction. All select gate tangent structures 115 between adjacent gate isolation structures 118 in the D2 direction extend into the interior of the first insulating structure 114 along the D1 direction, thereby all contacting the first insulating structure 114. The portions of the first gate layer 1131 located within each finger memory region FR are electrically isolated from each other.

[0068] FIG. 4 to FIG. 6 This is a cross-sectional schematic diagram of a semiconductor device provided in some embodiments of this application.

[0069] like FIG. 4 As shown, four select gate tangent structures 115 are located between adjacent gate isolation structures 118 in the D2 direction. The memory block BLK can be divided into five finger memory regions FR. The first insulating structure 114 may include a first insulating portion 1141 and a second insulating portion 1142 arranged in the D2 direction. The first insulating portion 1141 contacts one of the adjacent gate isolation structures 118 in the D2 direction, and the second insulating portion 1142 contacts one of the adjacent gate isolation structures 118 in the D2 direction. All select gate tangent structures 115 between adjacent gate isolation structures 118 in the D2 direction extend along the D1 direction to the first insulating structure 114, thereby all contacting the first insulating structure 114. The portions of the first gate layer 1131 located within each finger memory region FR are electrically isolated from each other.

[0070] It should be noted that the dimensions of the first insulating portion 1141 in the D2 direction may be the same as or different from the dimensions of the second insulating portion 1142 in the D2 direction. The portion of the first gate layer 1131 located between the first insulating portion 1141 and the second insulating portion 1142 (the portion within the dashed box) may be located in any one of the five finger memory regions FR, without spanning two or more finger memory regions FR.

[0071] like FIG. 5As shown, four select gate tangent structures 115 are located between adjacent gate isolation structures 118 in the D2 direction. The memory block BLK can be divided into five finger memory regions FR. The first insulating structure 114 extends continuously along the D2 direction to one of the two adjacent gate isolation structures 118 in the D2 direction, and is spaced apart from the other of the two adjacent gate isolation structures 118 in the D2 direction. All select gate tangent structures 115 between adjacent gate isolation structures 118 in the D2 direction extend along the D1 direction to the first insulating structure 114, thereby all contacting the first insulating structure 114. The portions of the first gate layer 1131 located within the five finger memory regions FR are electrically isolated from each other.

[0072] It should be noted that the dimensions of the first insulating structure 114 in the D1 direction are not specifically limited in this application. The portion of the first gate layer 1131 located between the first insulating structure 114 and the gate line isolation structure 118 that is not in contact with it (the portion within the dashed box) may be located in one finger memory region FR, without spanning two or more finger memory regions FR.

[0073] like FIG. 6 As shown, a select gate tangent structure 115 is located between adjacent gate isolation structures 118 in the D2 direction. The memory block BLK can be divided into two finger memory regions FR. A first insulating structure 114 extends continuously along the D2 direction to one of the two adjacent gate isolation structures 118 in the D2 direction, and is spaced apart from the other of the two adjacent gate isolation structures 118 in the D2 direction. All select gate tangent structures 115 between adjacent gate isolation structures 118 in the D2 direction extend along the D1 direction to the first insulating structure 114, thereby all contacting the first insulating structure 114. The portions of the first gate layer 1131 located in the two finger memory regions FR are electrically isolated from each other.

[0074] It should be noted that the dimensions of the first insulating structure 114 in the D1 direction are not specifically limited in this application. The portion of the first gate layer 1131 located between the first insulating structure 114 and the gate line isolation structure 118 that is not in contact with it (the portion within the dashed box) does not span two memory regions FR.

[0075] Some embodiments of this application also provide a method for manufacturing a semiconductor device. FIG. 7 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application. FIG. 7 As shown, a semiconductor device manufacturing method 200 (hereinafter referred to as manufacturing method 200) may include the following steps.

[0076] S210, forming a first stacked structure, wherein the first stacked structure includes alternating dielectric layers and gate layers, and the gate layer includes a first gate layer and a second gate layer located on one side of the first gate layer.

[0077] S220, forming a first insulating structure, wherein the first insulating structure passes through the first gate layer.

[0078] S230, a select gate tangent structure is formed extending along a first direction to a first insulating structure, wherein the select gate tangent structure passes through the first gate layer.

[0079] According to the manufacturing method provided in the embodiments of this application, by forming a select gate tangent structure extending along a first direction, the portions of the first gate layer located on both sides of the select gate tangent structure in a second direction can be electrically isolated. By forming a first insulating structure that passes through the first gate layer and does not extend to the second gate layer, the risk of difficulty in achieving electrical connection of the second gate layer can be reduced, which helps to improve the reliability of the semiconductor device after manufacturing. FIG. 8A to FIG. 16B This is a schematic diagram of the semiconductor device provided in the embodiments of this application during the manufacturing process. FIG. 8A and FIG. 8B An intermediate structure 300a is shown after the initial stacked structure 326 is formed. Among them, FIG. 8A This could be a cross-sectional schematic diagram of the intermediate structure 300a. FIG. 8B This can be a top view of the intermediate structure 300a. FIG. 9A and FIG. 9B An intermediate structure 300b is shown after the formation of the first channel structure 320 and the second channel structure 321. Among them, FIG. 9A This could be a cross-sectional schematic diagram of the intermediate structure 300b. FIG. 9B This can be a top view of the intermediate structure 300b. FIG. 10A and FIG. 10B An intermediate structure 300c is shown after the formation of the first gate line slot portion 3271, the second gate line slot portion 3272, and the first opening 3273. Among them, FIG. 10A This could be a cross-sectional schematic diagram of the intermediate structure 300c. FIG. 10B This can be a top view of the intermediate structure 300c. FIG. 11A and FIG. 11B The intermediate structure 300d after the formation of the mask layer 328 is shown. FIG. 11A This could be a cross-sectional schematic diagram of the intermediate structure 300d. FIG. 11B This can be a top view of the intermediate structure 300d. FIG. 12 The intermediate structure 300e is shown after the formation of the first trench 329. FIG. 13A and FIG. 13B An intermediate structure 300f is shown after the formation of the first insulating structure 314. Among them,FIG. 13A and FIG. 13B These are schematic cross-sectional views of the intermediate structure 300f taken from different planes. FIG. 14A and FIG. 14B The intermediate structure 300g after the formation of the gate layer 313 is shown. FIG. 14A and FIG. 14B These are schematic diagrams of cross-sections taken from different planes for the 300g intermediate structure. FIG. 15 The intermediate structure 300h is shown after the formation of the selected gate tangent structure 315. FIG. 16A and FIG. 16B The semiconductor device 300 after the interconnection structure 319 is formed is shown. Among them, FIG. 16A and FIG. 16B These are schematic cross-sectional views of the semiconductor device 300 taken from different planes.

[0080] In some embodiments, step S210 may include: S211, forming an initial stacked structure, wherein the initial stacked structure includes alternating dielectric layers and insulating layers. S212, replacing a portion of the insulating layer with a gate layer, wherein the alternating dielectric layers and gate layers constitute a first stacked structure.

[0081] The following is combined with FIG. 8A to FIG. 16B A manufacturing method 200 including steps S210 to S230 will be described by way of example.

[0082] S211

[0083] In some implementations, such as FIG. 8A and FIG. 8B As shown, the dielectric layer 312 and the insulating layer 317 can be alternately formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, to form the initial stacked structure 326. For example, during the formation of the initial stacked structure 326, the dielectric layer 312 can be formed last, making it the outermost layer of the initial stacked structure 326. As another example, both the dielectric layer 312 and the insulating layer 317 extend along the D1 and D2 directions, respectively. Viewed from the D3 direction, the intermediate structure 300a (i.e., the initial stacked structure 326) can be divided into an array region AR and a connection region CR. The connection region CR can be located on one side of the array region AR in the D1 direction.

[0084] In some embodiments, the material of the dielectric layer 312 is different from the material of the insulating layer 317. For example, the material of the dielectric layer 312 may include silicon oxide, and the material of the insulating layer 317 may include silicon nitride.

[0085] In some implementations, such as FIG. 9A and FIG. 9B As shown, the manufacturing method 200 may further include forming a first channel structure 320 and a second channel structure 321. The first channel structure 320 and the second channel structure 321 may penetrate the initial stacked structure 326. For example, FIG. 9B The area within the dashed box shown may be the connection structure 319 to be formed (see reference). FIG. 16B Region ①. Multiple first channel structures 320 may be formed in region ① on the side of the connection region CR in the D1 direction, and multiple second channel structures 321 may be formed in region ① on the other side of the connection region CR in the D1 direction. The first channel structures 320 and the second channel structures 321 may have the following characteristics: FIG. 2 The internal structure shown is not described in detail here.

[0086] In some implementations, such as FIG. 10A and FIG. 10B As shown, after forming the first channel structure 320 and the second channel structure 321, an insulating material can be deposited on the surface of the outermost dielectric layer 312 of the initial stacked structure 326 to cover the first channel structure 320 and the second channel structure 321. This insulating material can be the same as the material of the dielectric layer 312. In this case, there is no obvious interface between the two, and the insulating material can be part of the initial stacked structure 326.

[0087] In some implementations, reference continues. FIG. 10A and FIG. 10BThe first gate line slot portion 3271, at least one first opening 3273, and the second gate line slot portion 3272 can be formed through the initial stacked structure 326 using an etching process (e.g., dry etching and / or wet etching). The first gate line slot portion 3271, at least one first opening 3273, and the second gate line slot portion 3272 are arranged in the D1 direction. For example, the first gate line slot portion 3271 may extend in the D1 direction within the array region AR. The second gate line slot portion 3272 may extend in the D1 direction within the connection region CR. The plurality of first openings 3273 may be a plurality of vias arranged in the D1 direction, with a portion of the vias located within the array region AR and another portion located within the connection region CR. Alternatively, the first opening may be a trench (not shown) that is spaced apart from both the first gate line slot portion 3271 and the second gate line slot portion 3272, and may extend in the D1 direction within both the array region AR and the connection region CR. Optionally, the first grid line portion 3271 and the second grid line gap portion 3272 may be filled with sacrificial material 330 (see reference). FIG. 13B The sacrificial material 330 may include, but is not limited to, one or more of carbon, polycrystalline silicon, or any other suitable removable material.

[0088] S220

[0089] In some implementations, such as FIG. 11A and FIG. 11B As shown, a mask layer 328 can be formed on the surface of the initial stacked structure 326. For example, the mask layer 328 can cover the sacrificial material 330 in the first gate line slot portion 3271 and the second gate line slot portion 3272 (see reference). FIG. 13B ).

[0090] In some embodiments, the mask layer 328 may have a second opening 331. The shape of the second opening 331 may correspond to that of the first insulating structure 314 to be formed (see reference). FIG. 13A The shape corresponds to the plane perpendicular to the D3 direction. In other embodiments, FIG. 2 to FIG. 6 Other shapes of the first insulating structure 114 in a plane perpendicular to the D3 direction are shown. The second opening 331 can be patterned to have a shape corresponding to each of the aforementioned first insulating structures 114.

[0091] In some embodiments, the mask layer 328 may also have a third opening 332. The third opening 332 can expose... FIG. 10B At least one first opening 3273 is shown through the initial stacked structure 326.

[0092] In some embodiments, the mask layer 328 may be a photoresist layer or a hard mask layer. The second opening 331 and the third opening 332 of the mask layer 328 may be formed using the same mask and through a photolithography process.

[0093] In some implementations, such as FIG. 12 As shown, at least one pair (e.g., three pairs) of dielectric layers 312 and insulating layers 317 can be etched from one side of the initial stacked structure 326 in the D3 direction using a mask layer 328 to form a first trench 329. Optionally, after forming the first trench 329, some first channel structures 320 may protrude from the first trench 329. In this embodiment, the first trench 329 is formed by etching the dielectric layer 312 and the insulating layer 317. The dielectric layer 312 and the insulating layer 317 have similar material properties, which can ensure the etching accuracy of the first trench 329 and ensure that the first trench 329 passes through a predetermined number of insulating layers 317 in the D3 direction, reducing the risk of over-etching.

[0094] In some embodiments, during the formation of the first trench 329, a third opening 332 (see reference) can be utilized. FIG. 11B The mask layer 328 is exposed through its first opening 3273 (reference). FIG. 10B A portion of the insulating layer 317 is removed, forming multiple gaps (not shown). For example, in the case where the multiple first openings 3273 are multiple vias, under the masking effect of the mask layer 328, an etching material (e.g., an etchant) removes a portion of the insulating layer 317 surrounding the outside of each via through the multiple vias, thereby forming multiple gaps located between adjacent dielectric layers 312. A single gap may extend continuously along the D1 and D2 directions, for example exposing sacrificial material 330 in the first gate line portion 3271 and the second gate line gap portion 3272.

[0095] As described above, since the first trench 329 and the multiple gaps can both be formed by a mask layer 328 having a second opening 331 and a third opening 332, and the second opening 331 and the third opening 332 can be formed using the same mask, in other words, the first trench 329 and the multiple gaps can be formed using the same mask, which helps to reduce process costs.

[0096] In some implementations, such as FIG. 12 to FIG. 13BAs shown, a first insulating structure 314 can be formed by filling the first trench 329 with an insulating material using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. For example, the insulating material may also cover the surface of the initial stacked structure 326. For example, the insulating material forming the first insulating structure 314 may be different from the material of the insulating layer 317. If the material of the insulating layer 317 is silicon nitride, the material of the first insulating structure 314 may be silicon oxide. Optionally, insulating material can be filled in multiple gaps to form a second insulating structure 3183. The insulating material forming the second insulating structure 3183 may be different from the material of the insulating layer 317. If the material of the insulating layer 317 is silicon nitride, the material of the second insulating structure 3183 may be silicon oxide.

[0097] S212

[0098] In some implementations, such as FIG. 13A to 14B As shown, the insulating layer 317 located in the array region AR can be removed and replaced with a portion of the gate layer 313 via the first gate line gap portion 3271 after removing the sacrificial material 330. A portion of the insulating layer 317 located in the connection region CR near the second gate line gap portion 3272 can be removed and replaced with another portion of the gate layer 313 via the second gate line gap portion 3272 after removing the sacrificial material 330. It should be noted that the order of removing the insulating layer 317 located in the array region AR and removing a portion of the insulating layer 317 located in the array region AR is not specifically limited in this application. For example, after sequentially removing the aforementioned portions of the insulating layer 317, the gate layer 313 can be formed in the same thin film deposition process. In this embodiment, since the extent to which the insulating layer 317 is removed in the array region AR and the connection region CR is different, during the partitioned removal process, the second insulating structure 3183 can prevent etching material (e.g., etchant) from entering the gate line gap portion in another region outside the currently removed area, thereby ensuring the removal range of the insulating layer 317.

[0099] After the above process, the alternating dielectric layer 312 and gate layer 313 can form a first stacked structure 311, and the alternating dielectric layer 312 and insulating layer 317 can form a second stacked structure 316. One or more gate layers 313 that are penetrated by the first insulating structure 314 can be referred to as the first gate layer 3131, and the other gate layers 313 can be referred to as the second gate layer 3132.

[0100] In some implementations, reference continues. FIG. 13A to 14BAfter forming the first stacked structure 311, a first gate isolation portion 3181 can be formed in the first gate gap portion 3271, and a second gate isolation portion 3182 can be formed in the second gate gap portion 3272. For example, a silicon oxide layer can be formed on the sidewalls and bottom of the first gate gap portion 3271 and the second gate gap portion 3272, and then a polysilicon body can be formed inside the silicon oxide layer. Alternatively, one or more insulating materials can be filled in the first gate gap portion 3271 and the second gate gap portion 3272. After the above process, the first gate isolation portion 3181, the second insulating structure 3183, and the second gate isolation portion 3182 can constitute the gate isolation structure 318.

[0101] S230

[0102] like FIG. 15 As shown, after replacing a portion of the insulating layer 317 with the gate layer 313, a select gate tangent structure 315 extending along the D1 direction to the first insulating structure 314 can be formed. The select gate tangent structure 315 can pass through the first gate layer 3131. For example, an etching process (e.g., dry etching and / or wet etching) can be used to etch a select gate groove (not shown) through the first gate layer 3131. The select gate groove can extend along the D1 direction to the edge or interior of the first insulating structure 314. Next, insulating material can be filled into the select gate groove to form the select gate tangent structure 315. For example, one or more select gate tangent structures 315 can be present between adjacent gate line isolation structures 318 in the D2 direction. Since the select gate tangent structure 315 is formed by etching the first gate layer 3131 and the dielectric layer 312 (see reference 313), the select gate tangent structure 315 is formed by etching the first gate layer 3131 and the dielectric layer 312 (see reference 313). FIG. 14A The first gate layer 3131 and the dielectric layer 312 have different material properties. Due to the limitations of the etching process, the gate selection tangent structure 315 may extend to one or more second gate layers 3132 near the first gate layer 3131. As described above, the first insulating structure 314 does not extend to the second gate layer 3132 in the D3 direction. In this way, the second gate layer 3132 can extend on both sides of the gate selection tangent structure 315 in the D2 direction, so as not to affect the electrical connection of the second gate layer 3132 cut off by the gate selection tangent structure 315.

[0103] In some implementations, such as FIG. 16A and FIG. 16BAs shown, the manufacturing method 200 may further include forming a connection structure 319 through the first gate layer 3131. The connection structure 319 may be located on one side of the first insulating structure 314 in the D1 direction. For example, one or more connection structures 319 may be formed between adjacent select gate tangent structures 315 in the D2 direction, or between adjacent select gate tangent structures 315 and gate line isolation structures 318 in the D2 direction, using etching and thin film deposition processes. The connection structure 319 may be used to lead the first gate layer 3131 out in the D3 direction.

[0104] This application also provides a memory system. FIG. 17 This is a schematic block diagram of a system with a memory system provided in the embodiments of this application. FIG. 18A and FIG. 18B This is a schematic block diagram of a memory system provided in an embodiment of this application.

[0105] like FIG. 17 As shown, system 40 can be a mobile phone, desktop computer, laptop computer, tablet computer, onboard computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 41 located therein). FIG. 17 As shown, system 40 may include a host 44 and a memory system 41, the memory system 41 having one or more memories 42 and a controller 43. The host 44 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 44 may be configured to send or receive data to and from the memory 42.

[0106] Memory 42 may include the semiconductor devices described in any embodiment of this application. According to some embodiments, controller 43 is coupled to memory 42 and host 44 and is configured to control memory 42. Controller 43 may manage data stored in memory 42 and communicate with host 44. In some embodiments, controller 43 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 43 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc. Controller 43 may be configured to control the operation of memory 42, such as read, erase, and program operations. Controller 43 may also be configured to manage various functions related to data stored in or to be stored in memory 42, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 43 is further configured to process error correction codes (ECCs) related to data read from or written to memory 42. Controller 43 may also perform any other appropriate functions, such as formatting memory 42. Controller 43 may communicate with external devices (e.g., host 44) according to a specific communication protocol. For example, controller 43 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0107] The controller 43 and one or more memories 42 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 41 can be implemented and packaged into different types of end electronic products. FIG. 18AIn one example shown, the controller 43 and a single memory 42 may be integrated into a memory card 45. The memory card 45 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 45 may further include a connector for connecting the memory card 45 to a host computer (e.g., FIG. 17 The host 44) is coupled to the memory card connector 46. In such a way... FIG. 18B In another example shown, the controller 43 and multiple memories 42 may be integrated into the SSD 47. The SSD 47 may further include a connection between the SSD 47 and the host (e.g., FIG. 17 The SSD connector 48 is coupled to the host 44. In some embodiments, the storage capacity and / or operating speed of the SSD 47 is higher than that of the memory card 45.

[0108] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor device, comprising: a first stack structure comprising dielectric layers and gate layers arranged alternately, the gate layers comprising a first gate layer and a second gate layer located at one side of the first gate layer; a first insulating structure passing through the first gate layer; and a select gate cutline structure passing through the first gate layer and extending to the first insulating structure in a first direction. The semiconductor device further comprises:

2. The semiconductor device of claim 1, wherein, a gate line isolation structure passing through the first stack structure and extending in the first direction. One or more of the select gate cutline structures are located between the gate line isolation structures adjacent in a second direction, the first insulating structure extending continuously in the second direction and contacting at least one of the gate line isolation structures adjacent in the second direction, the first direction intersecting the second direction.

3. The semiconductor device of claim 2, wherein, A plurality of the select gate cutline structures are located between the gate line isolation structures adjacent in a second direction, the first insulating structure comprising a first insulating portion and a second insulating portion arranged in the second direction, wherein the first insulating portion and the second insulating portion contact the gate line isolation structures adjacent in the second direction respectively, the first direction intersecting the second direction.

4. The semiconductor device of claim 2, wherein, The select gate cutline structures all contact the first insulating structure.

5. The semiconductor device according to any one of claims 2 to 4, wherein, The semiconductor device further comprises:

6. The semiconductor device of claim 2, wherein, a connection structure passing through the first gate layer, located at one side of the first insulating structure in a first direction, and located between the select gate cutline structures adjacent in a second direction or between the select gate cutline structures and the gate line isolation structure, the first direction intersecting the second direction. The semiconductor device further comprises:

7. The semiconductor device of claim 6, wherein, a first channel structure extending in the first stack structure and located at one side of the connection structure in the first direction close to the first insulating structure; and a second channel structure extending in the first stack structure and located at one side of the connection structure in the first direction away from the first insulating structure, wherein the second channel structure is connected with a bit line structure. The semiconductor device further comprises a second stack structure, the first stack structure being located at opposite sides of the second stack structure in a second direction and at least one side of the first stack structure in a first direction, the second stack structure comprising the dielectric layers and insulating layers arranged alternately, wherein the insulating layers are connected with the gate layers, the first direction intersecting the second direction.

8. The semiconductor device of claim 2, wherein, In a plane perpendicular to a stacking direction, the semiconductor device comprises an array region and a connection region, the connection region being located at one side of the array region in the first direction, the first insulating structure and the select gate cutline structure being located in the array region, and the second stack structure being located in the connection region.

9. The semiconductor device of claim 8, wherein, The gate line isolation structure comprises a first gate line isolation portion, a second insulating structure and a second gate line isolation portion connected with each other in the first direction, 10. The semiconductor device of claim 9, wherein, wherein the first gate line isolation portion extends in the first direction within the array region, and the second gate line isolation portion extends in the first direction within the connection region. The material of the first insulating structure comprises silicon oxide.

11. The semiconductor device of claim 1, wherein, ​ 12.A memory system, comprising: a memory including the semiconductor device according to any one of claims 1 to 11; and a controller coupled to the memory and configured to control the memory to store data. 13.A method of manufacturing a semiconductor device, comprising: forming a first stack structure, wherein the first stack structure includes dielectric layers and gate layers arranged alternately, the gate layers including a first gate layer and a second gate layer located on a side of the first gate layer; forming a first insulating structure, wherein the first insulating structure penetrates the first gate layer; and forming a select gate cutline structure extending to the first insulating structure in a first direction, wherein the select gate cutline structure penetrates the first gate layer.

14. The manufacturing method according to claim 13, wherein, Forming the first stack structure includes: forming an initial stack structure, wherein the initial stack structure includes the dielectric layers and insulating layers arranged alternately; and replacing a portion of the insulating layers with the gate layers, wherein the dielectric layers and the gate layers arranged alternately are the first stack structure.

15. The manufacturing method of claim 14, wherein, The first insulating structure is formed before replacing the portion of the insulating layers with the gate layers.

16. The manufacturing method of claim 15, wherein, The select gate cutline structure is formed after replacing the portion of the insulating layers with the gate layers.

17. The manufacturing method of claim 15, wherein, Forming the first insulating structure includes: forming a first trench from a side of the initial stack structure in a stacking direction; and filling an insulating material in the first trench to form the first insulating structure.

18. The manufacturing method of claim 17, wherein, The method further includes: forming a first gate line slit portion, at least one first opening, and a second gate line slit portion penetrating the initial stack structure, wherein the first gate line slit portion, the at least one first opening, and the second gate line slit portion are arranged in the first direction; removing a portion of the insulating layers via the at least one first opening and forming a plurality of gaps; filling an insulating material in the plurality of gaps to form a second insulating structure; and forming a first gate line isolation portion in the first gate line slit portion and a second gate line isolation portion in the second gate line slit portion.

19. The manufacturing method of claim 18, wherein, The first trench and the plurality of gaps are formed using a same mask.

20. The manufacturing method according to any one of claims 13 to 19, wherein, The method further includes: forming a connection structure penetrating the first gate layer, wherein the connection structure is located on a side of the first insulating structure in the first direction.

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