Semiconductor device

Abstract

The invention provides a semiconductor device. The first insulator and the second insulator are arranged at an interval in the first direction. The storage column extends in the first direction and penetrates through the first insulator and the second insulator. The third insulator extends over a surface of the first insulator, a surface of the second insulator, and a first portion between the first insulator and the second insulator in a surface of the memory pillar. Each of the plurality of dot structures on the surface of the third insulator contains a metal element or a carbon element. The first conductor extends across the surface of the third insulator and the surface of the plurality of dot structures. The second conductor on the surface of the first conductor contains molybdenum.

Description

Technical Field

[0001] The implementation methods generally involve semiconductor devices. Background Technology

[0002] A storage device is known to have storage cells arranged in three dimensions. This storage device may include a film made of a material different from conventional ones for the purpose of improving performance. Summary of the Invention

[0003] A high-performance and high-strength semiconductor device is provided.

[0004] A semiconductor device according to one embodiment includes a first insulator, a second insulator, a storage pillar, a third insulator, a plurality of dot structures, a first conductor, and a second conductor. The first and second insulators are arranged at intervals in a first direction. The storage pillar extends in the first direction, penetrating the first and second insulators. The third insulator is distributed across a first portion between the first and second insulators on the surfaces of the first, second, and storage pillars. Each of the plurality of dot structures on the surface of the third insulator contains a metal element or carbon. The first conductor is distributed across the surface of the third insulator and the surfaces of the plurality of dot structures. The second conductor on the surface of the first conductor contains molybdenum. Attached Figure Description

[0005] Figure 1 Examples of the components of the semiconductor device according to the first embodiment and the connections of the components are shown.

[0006] Figure 2 The components of a block of the semiconductor device according to the first embodiment and the connections between the components are shown.

[0007] Figure 3 The structure shown is a cross-sectional view of a portion of the memory cell array of the semiconductor device according to the first embodiment.

[0008] Figure 4 An example of the structure of a cross-section of the storage column of the semiconductor device of the first embodiment is shown schematically.

[0009] Figure 5 An example of a cross-sectional structure of a portion of the wiring structure of the semiconductor device according to the first embodiment is shown schematically.

[0010] Figure 6 An example of a state during the manufacturing process of the semiconductor device of the first embodiment is shown schematically.

[0011] Figure 7An example of a state during the manufacturing process of the semiconductor device of the first embodiment is shown schematically.

[0012] Figure 8 An example of a state during the manufacturing process of the semiconductor device of the first embodiment is shown schematically.

[0013] Figure 9 An example of a state during the manufacturing process of the semiconductor device of the first embodiment is shown schematically.

[0014] Figure 10 An example of a state during the manufacturing process of the semiconductor device of the first embodiment is shown schematically.

[0015] Figure 11 An example of a state during the manufacturing process of the semiconductor device of the first embodiment is shown schematically.

[0016] Figure 12 An example of a state during the manufacturing process of the semiconductor device of the first embodiment is shown schematically.

[0017] Figure 13 An example of a state during the manufacturing process of the semiconductor device of the first embodiment is shown schematically.

[0018] Figure 14 This shows the relationship between temperature during the deposition of molybdenum nitrides and the strength of the deposited molybdenum.

[0019] Explanation of reference numerals in the attached figures

[0020] 20…Substrate,

[0021] 21, 25, 53, 54… conductors,

[0022] 22, 23, 24… wiring structure,

[0023] 30, 31, 32, 33, 34, 51… Insulators,

[0024] 40…core,

[0025] 41…Semiconductors,

[0026] 42…Layered structure,

[0027] 43…Tunnel insulators,

[0028] 44…charge storage film,

[0029] 45…blocking insulator,

[0030] 52… point structure. Detailed Implementation

[0031] Hereinafter, embodiments will be described with reference to the accompanying drawings. For multiple constituent elements having substantially the same function and structure in a certain embodiment or different embodiments, numbers or characters are sometimes added to the end of the reference numerals to distinguish them from each other.

[0032] The accompanying drawings are schematic; the relationship between thickness and planar dimensions, the ratio of thicknesses of different layers, etc., may differ from reality. Furthermore, the drawings may also contain portions with different dimensional relationships, configurations, and / or ratios.

[0033] In this specification and claims, "connection" of a first element to other second elements includes: the first element being directly or always or selectively connected to the second element via an element having conductivity.

[0034] The following implementation method is described using a three-dimensional orthogonal coordinate system. The x-axis extends in the X direction. The y-axis extends in the Y direction. The z-axis extends in the Z direction.

[0035] 1. First Implementation Method

[0036] As an example of a semiconductor device, a memory device is described below. Other examples of semiconductor devices include semiconductor devices having integrated circuits that include logic circuits.

[0037] 1.1. Composition (Structure)

[0038] Figure 1 The following diagram illustrates the constituent elements of the semiconductor device according to the first embodiment, and an example of the connection between the constituent elements. The storage device 1 is a device that uses storage cells to store data. The storage device 1 operates based on commands CMD and address information ADD received from outside the storage device 1, in one example from a memory controller. The storage device 1 accepts data DAT to be written and outputs the data DAT stored in the storage device 1. The storage device 1 is configured, for example, as a single semiconductor chip.

[0039] like Figure 1 As shown, the storage device 1 includes components such as a storage cell array 10, a row decoder 11, a register 12, a sequencer 13, a driver 14, and a sense amplifier 15.

[0040] The memory cell array 10 is a collection of arranged memory cells. The memory cell array 10 includes multiple memory blocks (BLKs) (BLK_0, BLK_1, ...). Each BLK includes multiple memory cell transistors MT (not shown). Word lines WL (not shown) and bit lines BL (not shown) are also configured in the area where the memory cell array 10 is set.

[0041] The row decoder 11 is a circuit used to select a block BLK. The row decoder 11 transmits the voltage supplied from the driver 14 to a block BLK selected based on the block address received from the register 12.

[0042] Register 12 is a circuit that holds the command CMD and address information ADD received from storage device 1. The command CMD instructs sequencer 13 to perform various actions, including data reading, data writing, and data erasure. The address information ADD specifies the object to be accessed in storage cell array 10.

[0043] The sequencer 13 is a circuit that controls the overall operation of the storage device 1. Based on the command CMD received from the register 12, the sequencer 13 controls the row decoder 11, the driver 14, and the sense amplifier 15 to perform various operations including data reading, data writing, and data erasure.

[0044] Driver 14 is a circuit that generates multiple voltages of different magnitudes and applies the generated voltages to several components. Driver 14 supplies the voltage selected from the multiple generated voltages based on the control of sequencer 13 and address information ADD to row decoder 11.

[0045] The sensing amplifier 15 is a circuit that outputs a signal based on the data stored in the memory cell array 10. The sensing amplifier 15 senses the state of the memory cell transistor MT and generates read data or write data to the memory cell transistor MT based on the sensed state.

[0046] Figure 2 The diagram illustrates the constituent elements of a single block BLK in the semiconductor device of the first embodiment, and the connections between these constituent elements. Multiple blocks BLKs, in one example, include... Figure 2 The constituent elements and connections are shown.

[0047] A block BLK consists of multiple string units SU. Figure 2 Examples of five string units SU_0 to SU_4 are shown.

[0048] like Figure 2 As shown, each of the m bit lines BL_0 to BL_m-1 is connected in each block BLK to one NAND string NS from each of the string units SU_0 to SU_4. m is a positive integer.

[0049] Each NAND string NS includes one select-gate transistor ST, n memory cell transistors MT (MT_0 to MT_n-1), and one select-gate transistor DT (DT_0, DT_1, DT_2, DT_3, or DT_4). n is a positive integer. The memory cell transistor MT is a device that includes a control gate electrode and a charge storage film insulated from the surroundings, and non-volatilely stores data based on the amount of charge in the charge storage film. The select-gate transistor ST, the memory cell transistor MT, and the select-gate transistor DT are connected in series in this order between the source line SL and one bit line BL.

[0050] Multiple NAND strings NS, each connected to different bit lines BL, constitute a string unit SU. Within each string unit SU, the control gate electrodes of memory cell transistors MT_0 to MT_n-1 are connected to word lines WL_0 to WL_n-1, respectively. A group of memory cell transistors MT that share word lines WL within a single string unit SU is called a cell unit CU.

[0051] The gate transistors DT_0 to DT_4 are selected to belong to the string units SU_0 to SU_4, respectively. Figure 2 In this diagram, the select gate transistors DT_2, DT_3, and DT_4 are not illustrated. The gates of the select gate transistors DT_0 for each of the multiple NAND strings NS in string unit SU_0 are connected to the select gate line SGDL0. Similarly, the gates of the select gate transistors DT_1, DT_2, DT_3, and DT_4 for each of the multiple NAND strings NS in string units SU_1, SU_2, SU_3, and SU_4 are connected to the select gate lines SGDL_1, SGDL_2, SGDL_3, and SGDL_4, respectively.

[0052] The gate of the select gate transistor ST is connected to the select gate line SGSL.

[0053] Figure 3 The structure shown is a cross-sectional view of a portion of the memory cell array of the semiconductor device according to the first embodiment, showing the structure along the yz plane.

[0054] like Figure 3 As shown, the memory cell array 10 includes a substrate 20, a conductor 21, a wiring structure 22, n wiring structures 23, a wiring structure 24, a conductor 25, and insulators 30-34. In one example, the insulators 30-34 comprise silicon oxide or are substantially formed of silicon oxide. The description "substantially formed (or constituted)" and similar descriptions mean that a constituent element "substantially formed" by a certain material is allowed to contain unintended impurities.

[0055] Substrate 20 is a semiconductor substrate. In one example, substrate 20 comprises p-type silicon or is substantially formed of p-type silicon.

[0056] The insulator 30 is located on the surface (upper surface) of the substrate 20 in the Z direction.

[0057] Conductor 21 is located on the upper surface of insulator 30. Conductor 21 extends along the xy plane and has a plate-like shape. Conductor 21 functions as at least part of source line SL. In one example, conductor 21 comprises phosphorus-doped silicon, or is substantially formed of phosphorus-doped silicon.

[0058] Insulator 31 is located on the upper surface of conductor 21.

[0059] Wiring structure 22 is located on the upper surface of insulator 31. Wiring structure 22 extends along the xy plane and has a plate-like shape. Wiring structure 22 includes a conductor. In one example, wiring structure 22 includes a conductor containing molybdenum, or substantially formed of molybdenum. Wiring structure 22 functions as at least a portion of the select gate line SGSL.

[0060] Multiple insulators 32 and multiple wiring structures 23 are alternately arranged, one each in the Z direction, on the upper surface of the wiring structure 22. Thus, the wiring structures 23 are separated from each other or arranged at intervals in the Z direction. The insulators 32 and wiring structures 23 extend along the xy plane and have a plate-like shape. The wiring structure 23 includes a conductor. The wiring structure 23 will be described in detail later. The multiple wiring structures 23, starting from the substrate 20 side, function as at least a portion of word lines WL_0 to WL_n-1 respectively.

[0061] Insulator 33 is located on the upper surface of the uppermost wiring structure 23.

[0062] Wiring structure 24 is located on the upper surface of insulator 33. Wiring structure 24 extends along the xy plane and has a plate-like shape. Wiring structure 24 includes a conductor. In one example, wiring structure 24 includes a conductor comprising molybdenum or substantially formed of molybdenum. Wiring structure 24 functions as at least a portion of the select gate line SGDL.

[0063] Insulator 34 is located on the upper surface of wiring structure 24.

[0064] Conductor 25 is located on the upper surface of insulator 34. Conductor 25 has a linear shape and extends in the Y direction. Conductor 25 functions as at least a portion of a bit line BL. Figure 3Conductors 25 are also disposed on different yz planes shown, and thus the conductors 25 are arranged at intervals in the X direction. In one example, the conductors 25 include conductors containing copper or substantially formed of copper.

[0065] The memory pillar MP extends in the Z direction and has a pillar shape. The memory pillar MP is located in a stacked structure composed of insulators 31-34 and wiring structures 22-24, penetrating or passing through insulators 31-34 and wiring structures 22-24. The upper surface of the memory pillar MP is located further Z-direction than wiring structure 24. The lower surface of the memory pillar MP is located in conductor 21. The portion of the memory pillar MP connected to wiring structure 22 functions as a select gate transistor ST. The portion of the memory pillar MP connected to one wiring structure 23 functions as a memory cell transistor MT. The portion of the memory pillar MP connected to wiring structure 24 functions as a select gate transistor DT.

[0066] The memory column MP includes a core 40, a semiconductor 41, and a stack 42. The core 40 is substantially formed of an insulator, and in one example, comprises silicon oxide or is substantially formed of silicon oxide. The core 40 extends in the Z direction and has a column shape. In one example, the semiconductor 41 comprises silicon or is substantially formed of silicon. The semiconductor 41 covers the surface of the core 40. The stack 42 covers the sides and the lower surface of the semiconductor 41. The stack 42 has an opening in a conductor 21, with the conductor 21 partially located within the opening. The conductor 21 is connected to the semiconductor 41 within the opening.

[0067] Each storage column MP is connected to a conductor 25 via a contact plug CV.

[0068] The component SLT extends along the xz plane, truncating the wiring structures 22-24. The upper surface of the component SLT is located above the upper surface of the storage column MP. The component SLT includes a conductor LI and a spacer SP. The lower surface of the conductor LI is in contact with the conductor 21. The spacer SP is located between the conductor LI and the wiring structures 22-24, insulating the conductor LI from the wiring structures 22-24. The conductor LI functions as part of the source line SL.

[0069] The insulator SHE extends along the xz plane and in the Z direction, truncating the wiring structure 24. The lower surface of the insulator SHE lies within the insulator 33. In one example, the insulator SHE comprises silicon oxide or is substantially formed of silicon oxide.

[0070] Figure 4 An example of the cross-sectional structure of the storage column of the semiconductor device according to the first embodiment is schematically shown. Specifically, Figure 4 Show along Figure 3A cross-section of line IV-IV. For example... Figure 4 As shown, the laminate 42 includes a tunnel insulator 43, a charge storage film 44, and a block insulator 45.

[0071] Tunnel insulator 43 surrounds the sides of semiconductor 41. Charge storage film 44 surrounds the sides of tunnel insulator 43. Barrier insulator 45 surrounds the sides of charge storage film 44. Wiring structure 23 surrounds the sides of barrier insulator 45.

[0072] Semiconductor 41 functions as the channel (current path) for the memory cell transistor MT and the select gate transistors DT and ST. In one example, tunnel insulator 43 and barrier insulator 45 each comprise silicon oxide or are substantially formed of silicon oxide. Charge storage film 44 stores charge. In one example, charge storage film 44 comprises silicon nitride or is substantially formed of silicon nitride.

[0073] Figure 5 An example of a cross-sectional structure of a portion of the wiring structure of the semiconductor device according to the first embodiment is shown schematically. Figure 5 Show Figure 3 Region A5 in the diagram shows the area where a wiring structure 23 is bounded to the storage column MP.

[0074] like Figure 5 As shown, the storage device 1 also includes an insulator 51, and the wiring structure 23 includes a dot structure 52, as well as conductors 53 and 54.

[0075] The insulator 51 has a film-like shape. The insulator 51 surrounds the surface of the wiring structure 23. Specifically, the insulator 51 covers the upper surface of the insulator 32 located in the -Z direction of the two insulators 32 arranged along the Z direction. The insulator 51 covers the lower surface (-Z direction side) of the insulator 32 located in the Z direction of the two insulators 32 arranged along the Z direction. The insulator 51 covers the portion of the surface of the blocking insulator 45 between the two insulators 32 arranged in the Z direction. In one example, the insulator 51 comprises aluminum oxide or is substantially formed of aluminum oxide.

[0076] Point structures 52 are located on the surface of insulator 51. Point structures 52 are clusters of elements contained within point structures 52, having an irregular shape. Point structures 52 are irregularly distributed. The groups of point structures 52 are discretely distributed, covering most of the surface of insulator 51. On the other hand, point structures 52 do not have a layered shape, and there is no need for them to cover the entire insulator 51. Therefore, point structures 52 comprise pairs of point structures 52 spaced apart therebetween. In the Z-direction of point structures 52, for example, the height of point structures 52 in the Z-direction is less than 1 nm.

[0077] In one example, point structure 52 contains a metallic element or carbon (C). In more specific examples, point structure 52 contains aluminum (Al), zirconium (Zr), niobium (Nb), hafnium (Hf), titanium (Ti), chromium (Cr), and carbon. Aluminum, zirconium, niobium, hafnium, and titanium are metals with ionization energies lower than those of molybdenum. In other examples, point structure 52 contains metal nitrides, including aluminum nitrides, zirconium nitrides, niobium nitrides, hafnium nitrides, titanium nitrides, and chromium nitrides.

[0078] In one example, the surface density of the metallic element in point structure 52 is 1 × 10⁻⁶. 13 [atoms / cm 2 Above and 1×10 15 [atoms / cm 2 ]the following.

[0079] Conductor 53 is located on the portion of the surface of insulator 51 not covered by dot structure 52, and on the surface of dot structure 52. Conductor 53 covers the portion of the surface of insulator 51 not covered by dot structure 52, and on the surface of dot structure 52. In other words, conductor 53 internally includes dot structure 52, and the surface of insulator 51 is covered by the combination of conductor 53 and dot structure 52. In one example, conductor 53 comprises or is substantially formed of molybdenum nitride.

[0080] Conductor 54 covers the surface of conductor 53, filling most of the area surrounded by conductor 53. In other words, conductor 54 fills most of the area in wiring structure 23 where there are no point structures 52 and conductor 53. Conductor 54 may also fill the entire area surrounded by conductor 53. In one example, conductor 54 comprises molybdenum or is substantially formed of molybdenum.

[0081] Wiring structures 22 and 24 may have the same structure as wiring structure 23, that is, they may include dot structure 52, conductors 53 and 54.

[0082] 1.2. Manufacturing Method

[0083] Figures 6 to 13 Examples of a state during the manufacturing process of the semiconductor device of the first embodiment are shown schematically. Figures 6-10 ,as well as Figure 13 Showing with Figure 3 The same area shown. Figure 11 as well as Figure 12 Showing with Figure 5 The same area shown.

[0084] like Figure 6As shown, insulator 30, conductor 21A, insulator 31A, 61, 32A, 62, 33A, 63, and 34A are deposited on the upper surface of substrate 20. That is, firstly, insulator 30, conductor 21A, insulator 31A, and 61 are deposited on the upper surface of substrate 20. Conductor 21A occupies a layer in a predetermined region where conductor 21 is to be formed. Insulator 31A occupies a layer in a predetermined region where insulator 31 is to be formed. Insulator 31A is substantially formed of the material of insulator 31. Insulator 61 occupies a layer in a predetermined region where wiring structure 22 is to be formed. In one example, insulator 61 comprises silicon nitride or is substantially formed of silicon nitride. Examples of methods for depositing insulator 30, conductor 21A, insulator 31A, and 61 include CVD (Chemical Vapor Deposition).

[0085] On the upper surface of insulator 61, a plurality of insulators 32A and insulator 62 are stacked alternately, one of each. Each insulator 62 occupies a layer in a predetermined area to form a wiring structure 23. In one example, the insulator 62 comprises or is substantially formed of silicon nitride. Examples of methods for stacking insulators 32A and insulator 62 include CVD.

[0086] Insulators 33A, 63, and 34A are deposited on the upper surface of the uppermost insulator 62. Insulator 33A occupies a layer in the predetermined region where insulator 33 is to be formed. Insulator 33A is substantially formed of the same material as insulator 33. Insulator 63 occupies a layer in the predetermined region where wiring structure 24 is to be formed. In one example, insulator 63 comprises or is substantially formed of silicon nitride. Insulator 34A constitutes part of insulator 34. Examples of methods for depositing insulators 33A, 63, and 34A include CVD.

[0087] like Figure 7 As shown, a memory aperture MH is formed. The memory aperture MH occupies a predetermined area where the memory pillar MP is to be formed, penetrating insulators 31A, 61, 32A, 62, 33A, 63, and 34A, and reaching conductor 21A. Examples of methods for forming the memory aperture MH include photolithography and anisotropic etching methods such as RIE (Reactive Ion Etching).

[0088] like Figure 8 As shown, a storage column MP is formed. That is, firstly, a stack 42, namely a barrier insulator 45, a tunnel insulator 43, and a charge storage film 44 are deposited on the surface of the storage hole MH. Examples of methods for depositing the stack 42 include CVD.

[0089] A portion of the conductor 21A in the laminate 42 is removed. A semiconductor 41 is deposited on the surface of the laminate 42. Examples of deposition methods include CVD.

[0090] By depositing a core 40 on the surface of semiconductor 41, the center of the storage hole MH is filled by the core 40. Examples of deposition methods include CVD. The top portion of the core 40 is then removed, and the semiconductor 41 is formed in the removed portion. This forms the storage pillar MP.

[0091] like Figure 9 As shown, a slotted surface area (SLI) is formed. The slotted surface area occupies a predetermined area where the component structure (SLT) is to be formed. The slotted surface area (SLI) penetrates conductor 21A, insulators 31A, 61, 32A, 62, 33A, 63, and 34A. Through the formation of the slotted surface area (SLI), insulators 31A, 32A, and 33A and conductor 21A become insulators 31, 32, and 33, and conductor 21, respectively. Examples of methods for forming the slotted surface area (SLI) include photolithography and anisotropic etching methods such as refractive indexing (RIE).

[0092] like Figure 10 As shown, insulators 61, 62, and 63 are removed. An example of the removal method includes wet etching. As the wet etching solution, a solution with a selectivity ratio for groups of insulators 61, 62, and 63 and groups of insulators 31, 32, 33, and 34 can be used. The solution reaches insulators 61, 62, and 63 through the gap SLI, removing insulators 61, 62, and 63. Through removal, spaces 65, 66, and 67 are formed in the regions where insulators 61, 62, and 63 are located, respectively.

[0093] like Figure 11 As shown, insulators 51 are deposited on the surfaces of each space 66, namely, on the upper surface of the insulator 32 in the -Z direction of the two insulators 32 arranged in the Z direction, the lower surface of the insulator 32 in the Z direction of the two insulators 32 arranged in the Z direction, and on the portion of the surface of the blocking insulator 45 between the two insulators 32 arranged in the Z direction. Examples of deposition methods include CVD. Insulators 51 can also be deposited on the surfaces of spaces 65 and 67.

[0094] like Figure 12 As shown, a dot structure 52 is formed on the surface of the insulator 51. Examples of methods for forming this structure include ALD (Atomic Layer Deposition). The dot structure 52 can also be formed on the surface of the insulator 51 in spaces 65 and 67.

[0095] like Figure 5 as well as Figure 13As shown, a wiring structure 23 is formed. That is, a conductor 53 is deposited on the surface of the insulator 51 and the dot structure 52. An example of a deposition method is an ALD. An example of a raw material used in an ALD is MoO2Cl2. In one example, the flow temperature of the ALD is above 300°C.

[0096] Conductor 54 is deposited on the surface of conductor 53. Examples of deposition methods include CVD. Conductor 53 can function as a seed layer when conductor 54 is formed.

[0097] like Figure 3 As shown, spacer SP, conductor LI, and insulator SHE are formed. Next, the remaining portion of insulator 34, contact plug CV, and conductor 25 are formed, thereby obtaining... Figure 3 The structure shown.

[0098] 1.3. Advantages (Effects)

[0099] According to the first embodiment, as described below, a memory device including a memory cell transistor with suppressed characteristic degradation and a high-strength conductor can be realized.

[0100] For the purpose of effectively forming the molybdenum conductor 54, a molybdenum nitride film can be formed between the insulator 51 and the conductor 54. When the temperature (flow temperature) of MoO2Cl2 used as the raw material for the molybdenum nitride film is low, the film contains many impurities (oxygen and chlorine). The oxygen in the molybdenum nitride film combines with the hydrogen in the subsequently deposited molybdenum, functioning as a defect at the interface between the insulator 51 and the barrier insulator 45. These defects replenish electrons, which degrades the characteristics of the memory cell transistor MT.

[0101] At high flow temperatures of MoO2Cl2, impurities in the molybdenum nitride film are suppressed. However, the higher the flow temperature, the easier it is for MoO2Cl2 temporarily adsorbed onto insulator 51 to detach from it. As a countermeasure, the incubation period (i.e., cycle time) of the ALD can be increased. However, this deteriorates the coverage of the molybdenum nitride film; specifically, the molybdenum nitride is not a film but rather formed from discretely distributed clumps. As a result, the coverage of the conductor 54 is poor, and the strength of the conductor 54 is low. Thus, it is difficult to simultaneously suppress the degradation of the memory cell transistor MT and ensure the strength of the conductor 54 using molybdenum nitride.

[0102] According to the first embodiment, the wiring structure 23 includes a dot structure 52 on the surface of the insulator 51 and a conductor 53 on the surface of the insulator 51 and the dot structure 52. The dot structure 52 suppresses the detachment of molybdenum nitride temporarily deposited at a high flow temperature. Therefore, by depositing at a high flow temperature, it is possible to suppress the characteristic degradation of the memory cell transistor MT and form a high-strength conductor 53. Figure 14 Experimental results are shown regarding the relationship between the flow temperature and the strength of molybdenum deposited on molybdenum nitride in the case of molybdenum nitride deposited on aluminum oxide. Figure 14 Use any unit (AU). Figure 14 This illustrates both the case of directly depositing molybdenum nitride on aluminum oxide and the case of depositing molybdenum nitride on aluminum oxide (51) and dot structure (52) as in the first embodiment. Figure 14 As shown and as described above, when molybdenum nitride is deposited on aluminum oxide, the higher the flow temperature of the molybdenum nitride feedstock, the lower the strength of the deposited molybdenum film. On the other hand, when molybdenum nitride is deposited on aluminum oxide using a dot structure, the higher the flow temperature of the feedstock, the higher the strength of the molybdenum film.

[0103] According to the first embodiment, since the conductor 53 can be deposited using raw materials at high flow temperatures (above 300°C), the oxygen concentration at the interface between the insulator 51 and the barrier insulator 45 is low. More specifically, the oxygen concentration at the interface between the insulator 51 and the barrier insulator 45 is 5 × 10⁻⁶. 18 [atoms / cm 3 ] and above and 5×10 20 [atoms / cm 3 The following applies. For example, as described above, the low oxygen concentration in the case of molybdenum nitride deposition at low temperatures suppresses the degradation of the characteristics of the memory cell transistor (MT).

[0104] According to the first embodiment, a non-film-like dot structure 52 is disposed between the insulator 51 and the conductor 53. Due to its shape, the dot structure 52 does not necessarily have the thickness required when the material of the dot structure 52 is formed as a film. Generally, to give the material a film-like shape, a thickness of 1 nm or more is required; conversely, the height of the dot structure 52 can be formed even if it is less than 1 nm. As a result, the volume of the dot structure 52 occupies a low proportion of the volume of the wiring structure 23. Therefore, the increase in resistance of the wiring structure 23 due to the dot structure 52 can be suppressed, and a wiring structure 23 with low resistance can be achieved.

[0105] 1.4. Variations

[0106] As described above, conductor 53 can function as a seed layer when forming conductor 54. For this purpose, conductor 53 can cover point structures 52. However, if conductor 54 can be formed without using conductor 53 as a seed layer, conductor 53 may not cover point structures 52. In this case, the thickness of conductor 53 is smaller than the height of point structures 52, and some point structures 52 are exposed from the surface of conductor 53.

[0107] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and / or variations thereof are included within the scope and spirit of the invention, as well as within the scope of the claims and their equivalents.

Claims

1. A semiconductor device comprising: a first insulator and a second insulator arranged at intervals in a first direction; a storage pillar extending in the first direction and penetrating the first insulator and the second insulator; a third insulator present on a first portion between the first insulator and the second insulator among a surface of the first insulator, a surface of the second insulator, and a surface of the storage pillar; a plurality of dot structures each containing a metal element or a carbon element on a surface of the third insulator; a first conductive body present on a surface of the third insulator and on surfaces of the plurality of dot structures; and a second conductive body containing molybdenum on a surface of the first conductive body.

2. The semiconductor device according to claim 1, the plurality of dot structures each contain a metal nitride.

3. The semiconductor device according to claim 1, the plurality of dot structures each contain aluminum, zirconium, niobium, hafnium, or titanium.

4. The semiconductor device according to claim 1, the plurality of dot structures each contain a nitride of aluminum, a nitride of zirconium, a nitride of niobium, a nitride of hafnium, or a nitride of titanium.

5. The semiconductor device according to claim 1, 6. The semiconductor device according to claim 1, the storage pillar includes a fourth insulator in contact with the third insulator, 7. The semiconductor device according to claim 1, the first conductive body contains a nitride of molybdenum.

8. The semiconductor device according to claim 7, the third insulator contains an oxide of aluminum. The surface density of the metal element is 1 x 10 13 [atoms / cm 2 ] or more and 1 x 10 15 [atoms / cm 2 ] or less.

9. The semiconductor device according to claim 2, the first conductive body contains a nitride of molybdenum. The oxygen concentration at the boundary of the third insulator and the fourth insulator is 5 x 1019 [atoms / cm2] or more and 5 x 1020 [atoms / cm2] or less. 18 [atoms / cm2] or more and 5 x 1020 [atoms / cm2] or less. 3 ] or more and 5 x 1020 [atoms / cm2] or less. 20 [atoms / cm2] or more and 5 x 1020 [atoms / cm2] or less. 3 [atoms / cm2] or more and 10. The semiconductor device according to claim 9, the third insulator contains an oxide of aluminum.

11. The semiconductor device according to claim 3, the first conductive body contains a nitride of molybdenum.

12. The semiconductor device according to claim 11, the third insulator contains an oxide of aluminum.

13. The semiconductor device according to claim 4, the first conductive body contains a nitride of molybdenum.

14. The semiconductor device according to claim 13, the third insulator contains an oxide of aluminum.

15. The semiconductor device according to claim 5, the first conductive body contains a nitride of molybdenum.

16. The semiconductor device according to claim 15, the third insulator contains an oxide of aluminum. ​ ​ ​ ​ ​ ​

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