Memory circuitry and methods for forming memory circuitry

Abstract

The invention relates to memory circuitry and methods for forming memory circuitry. In one embodiment, a method includes forming pillars protruding upwardly from a substrate and including a conductive doped single crystal semiconductive material. The pillar includes one source / drain region or another source / drain region of a transistor of an individual memory cell of the memory circuitry being formed. A conductive doped single crystal semiconductor material is grown from the tops and sidewalls of the struts to form conductive single crystal coverings, the conductive single crystal coverings individually located directly over the tops of the individual struts and circumferentially surrounding the sidewalls of the individual struts. Digital lines are formed that are individually located over the plurality of individual pillars of the other source / drain region and are directly electrically coupled to the plurality of individual pillars by an epitaxially grown conductive single crystal cover located directly over the plurality of individual pillars. Storage elements are formed so as to be over and electrically coupled to individual pillars of one source / drain region by an epitaxially grown conductive single crystal cover directly over the individual pillars. Structures are disclosed.

Description

Technical Field

[0001] The embodiments disclosed herein relate to memory circuit systems and methods for forming memory circuit systems. Background Technology

[0002] Memory is a type of integrated circuit system used in computer systems to store data. Memory can be manufactured as one or more individual memory cell arrays. Memory cells can be written to or read from using digital lines (also referred to as bit lines, data lines, or sense lines) and access lines (also referred to as word lines). Digital lines electrically interconnect memory cells along the columns of the array, and access lines electrically interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of digital lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods without power. Non-volatile memory is typically specified as memory with a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of a few milliseconds or less. In any case, memory cells are configured to retain or store memory in at least two different selectable states. In binary systems, these states are considered either "0" or "1". In other systems, at least some individual memory cells can be configured to store information in more than two levels or states.

[0004] A capacitor is a type of electronic component that can be used in memory cells. A capacitor has two electrical conductors separated by an electrically insulating material. Energy as an electric field can be stored electrostatically within this material. Depending on the composition of the insulating material, that stored field will be volatile or non-volatile. For example, a capacitor insulating material containing only SiO2 will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor having at least a portion of a ferroelectric material as the insulating material. The ferroelectric material is characterized by having two stable polarization states and thus can be a programmable material that includes capacitors and / or memory cells. The polarization states of the ferroelectric material can be changed by applying a suitable programming voltage and remain unchanged (at least for a period of time) after the programming voltage is removed. Each polarization state has a charge storage capacitance different from the other polarization state, and ideally, it can be used to write (i.e., store) and read the memory state without reversing the polarization state until a reversal is desired. Less desirable is that in some memories with ferroelectric capacitors, the behavior of reading the memory state can reverse the polarization. Therefore, when the polarization state is determined, the memory cell is rewritten to immediately place the memory cell in a pre-fetch state after its determination. Regardless, due to the bistable nature of the ferroelectric material that forms part of the capacitor, the memory cells incorporated into the ferroelectric capacitor are ideally non-volatile. Other programmable materials can be used as capacitor insulators to make the capacitor exhibit non-volatility.

[0005] Field-effect transistors (FETs) are another type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semi-conductive channel region therebetween. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. The application of a suitable voltage to the gate allows current to flow from one of the source / drain regions through the channel region to the other source / drain region. When the voltage is removed from the gate, current flow through the channel region is largely prevented. FETs may also include additional structures (e.g., a reversible programmable charge storage region) as part of the gate construction between the gate insulator and the conductive gate. In any case, the gate insulator may be programmable, such as ferroelectric. Summary of the Invention

[0006] On one hand, this disclosure provides a method for forming a memory circuit system, comprising: forming pillars that protrude upward from a substrate and include conductive-doped single-crystal semiconducting material, wherein individual pillars include a source / drain region or another source / drain region of a transistor for an individual memory cell of the memory circuit system being formed; epitaxially growing conductive-doped single-crystal semiconductor material from the top and sidewalls of the individual pillars to form a conductive single-crystal cap, the conductive single-crystal cap being individually located directly above the top of the individual pillars and circumferentially surrounding the sidewalls of the individual pillars; forming digital lines that are individually located above a plurality of the individual pillars for another source / drain region and directly electrically coupled to the plurality of individual pillars through the epitaxially grown conductive single-crystal cap located directly above the plurality of individual pillars; and forming memory elements for the individual memory cells, the memory elements being individually located above the individual pillar for one source / drain region and electrically coupled to the individual pillar through the epitaxially grown conductive single-crystal cap located directly above the individual pillars.

[0007] On the other hand, this disclosure provides a memory circuit system comprising: a transistor, individually including: a source / drain region and another source / drain region, the one and the other source / drain regions individually including a pillar, the pillar comprising a conductive doped single-crystal semiconducting material, the pillar including a pillar top and a pillar sidewall; a channel region located between the one and the other source / drain regions; and a conductive gate operatively adjacent to the channel region; a conductive path configuration, individually located directly above and electrically coupled to the pillar of one of the other source / drain regions; and a digital line, individually located above and directly electrically coupled to the plurality of conductive path configurations; and a conductive... A conductive path structure, individually located directly above and electrically coupled to the pillar of one of the individual source / drain regions; a storage element, individually electrically coupled to the individual in the conductive path structure; and the individual in the conductive path structure and the individual conductive path structure include a conductive single-crystal capping, the conductive single-crystal capping being located directly above and abutting the top of the pillar and circumferentially surrounding and abutting the sidewall of the pillar, the conductive single-crystal capping having the same crystallinity as the conductive doped single-crystal semiconducting material of the pillar, the conductive single-crystal capping having at least primarily a conductivity-enhancing dopant therein than at least primarily in the top of the pillar.

[0008] On the other hand, this disclosure provides a memory circuit system comprising: a transistor, individually including: a source / drain region and another source / drain region, the one and the other source / drain regions individually including a pillar, the pillar comprising a conductive doped single-crystal semiconducting material, the pillar including a pillar top and a pillar sidewall; a channel region located between the one and the other source / drain regions; and a conductive gate operatively adjacent to the channel region; a conductive path configuration, individually located directly above and electrically coupled to the pillar of one of the other source / drain regions; and a digital line, individually located above a plurality of the conductive path configurations and Directly electrically coupled to multiple said conductive path structures; conductive path structures, individually located directly above and electrically coupled to the pillars of each of the individual source / drain regions; memory elements, individually electrically coupled to each of the individual conductive path structures; and each of the individual conductive path structures and the individual conductive path structures includes: a conductive single-crystal overlay located directly above and abutting the top of the pillar and circumferentially surrounding and abutting the sidewalls of the pillar; and an intermediate region located at the interface between the conductive single-crystal overlay and the top of the pillar and the sidewalls of the pillar, the intermediate region including individual regions located at 1 x 10 15 atoms / cm 3 Up to 5x 10 21 atoms / cm 3 Chlorine, fluorine and nitrogen. Attached Figure Description

[0009] Figures 1 to 7 This is a schematic cross-sectional view of a portion of a DRAM construction in the manufacture of some embodiments of the present invention.

[0010] Figures 8 to 47 This is in subsequent processing or alternative embodiments according to some embodiments of the present invention. Figures 1 to 7 A schematic sequential cross-sectional view of the structure. Detailed Implementation

[0011] refer to Figures 1 to 47 Describe an example implementation. Figures 1 to 7 This illustration shows an example fragment of a substrate structure 8 comprising an array or array region 10 in a fabrication process relative to a substrate 11. The substrate 11 may comprise any one or more of conductive / conductive / conductive, semiconductive / semiconductor / semiconductive, and insulating / insulator / insulator (i.e., electrical in this context) materials. The materials may be located in… Figures 1 to 7The material being depicted may be located beside, vertically inside, or vertically outside the substrate. For example, components manufactured in other parts or all of the integrated circuit system may be disposed somewhere above, around, or within the substrate 11. Control and / or other peripheral circuitry systems for operating components within the memory array may also be manufactured and may or may not be located entirely or partially within the memory array or subarray. Furthermore, multiple subarrays may be manufactured and operated independently, in series, or otherwise relative to each other. As used in this document, "subarray" may also be considered an array.

[0012] The substrate 11 includes a semiconducting material 12 (e.g., suitable and differently doped single-crystal and / or polycrystalline silicon, Ge, SiGe, GaAs, and / or other existing or future-developed semiconducting materials), a trench isolation region 14 (e.g., silicon nitride and / or silicon dioxide), and an active region 16 comprising suitable and differently doped semiconducting material 12. The configuration 8 includes a transistor 25, which individually includes a source / drain region 24 and another source / drain region 26, a channel region 27 located between the one and the other source / drain region, and a conductive gate 22 operatively adjacent to the channel region 27 (e.g., a conductive doped semiconductor material and / or metallic material, comprising, for example, elements W, Ru, and / or Mo) (e.g., a gate insulator 20 located between the conductive gate 22 and the channel region 27, such as silicon dioxide and / or silicon nitride). The conductive gate 22 includes a portion of one of a plurality of conductive gate lines 75 extending in the substrate 11 along a row direction 55. Transistor 25 is shown as a recessed access device, wherein example configuration 8 illustrates such recessed access devices grouped individually in pairs. Each recessed access device / transistor 25 includes, for example, an embedded access line configuration 18 located within a trench 19 in a semiconductive material 12. Configuration 18 includes a conductive gate 22. A gate insulator 20 is located between the conductive gate 22 and the semiconductive material 12 along the sidewalls 21 and substrate 23 of the individual trench 19. An insulating material 17 (e.g., silicon dioxide and / or silicon nitride) is located above materials 20 and 22 within the trench 19. A source / drain region 24 and another source / drain region 26 are located on opposite sides of the individual trench 19 in the upper portion of the semiconductive material 12 (e.g., regions 24, 26 are located laterally outside and above the access line configuration 18). Each of the source / drain regions 24, 26 has at least a portion in which a conductivity-enhancing dopant is present, said portion having a maximum concentration of this conductivity-enhancing dopant within the respective source / drain region 24, 26, for example, to make this portion conductive (e.g., having at least 10). 18 atoms / cm 3The maximum dopant concentration. Therefore, all or only a portion of each source / drain region 24, 26 may have this maximum concentration of conductivity-enhancing dopant. One source / drain region 24 and the other source / drain region 26 comprise a conductive-doped single-crystal semiconducting material 15 (e.g., the conductive-doped portion of single-crystal semiconducting material 12; for example, primarily at least one of silicon or germanium with n-type or p-type conductivity). Source / drain regions 24 and / or 26 may contain other doped regions (not shown), such as halo regions, LDD regions, etc.

[0013] In an exemplary embodiment, one of the source / drain regions in the individual source / drain region pairs of transistors 25 (e.g., another source / drain region 26) is laterally located between the conductive gates 22 and shared by the device / transistor pair 25. Other source / drain regions in the source / drain region pairs (e.g., one source / drain region 24) are not shared by the transistor pair 25. Therefore, in an exemplary embodiment, each active region 16 includes two transistors 25 (e.g., a pair of transistors 25), wherein each transistor shares the central source / drain region 26.

[0014] Example channel region 27 is located in the semiconducting material 12 below the source / drain regions 24, 26, along the trench sidewall 21 and surrounding the trench substrate 23. Channel region 27 may be undoped or suitably doped with a conductivity-enhancing dopant, which may have a conductivity type opposite to the dopant in the source / drain regions 24, 26. When a suitable voltage is applied to the gate material 22 of the access line configuration 18, a conductive channel is formed within channel region 27 near the gate insulator 20 (e.g., along the channel current flow line / path 29). Figure 7 This allows current to flow beneath the internal access line configuration 18 within the individual active regions 16 between a pair of source / drain regions 24 and 26. Dot patterns are schematically shown to indicate the primary conductivity-modifying dopant concentrations (regardless of type), with denser dots indicating higher dopant concentrations and sparser dots indicating lower dopant concentrations. Conductivity-modifying dopant may and most likely be located in other portions of material 12, as shown. For simplicity, only two different dot densities are shown in material 12, and additional dopant concentrations can be used; a constant dopant concentration is not required in any region.

[0015] refer to Figures 8 to 11The pillar 13* has been formed to project upward from the substrate 77 and includes conductive doped single-crystal semiconducting material 15 (* is used as a suffix to include all such identically numbered structures or portions thereof that may or may not have other suffixes). Individual pillars 13* include one source / drain region 24 (13x) or another source / drain region (13y) of a transistor 25 of an individual memory cell in a memory circuit system being formed. The pillar 13* individually includes a top 30 and sidewalls 31. In one embodiment and as shown, the formation of the pillar 13* includes removing (e.g., by etching) the insulating material surrounding the conductive doped single-crystal semiconducting material 15 (e.g., 14 and 17) and, in one embodiment, the insulating material located on top of the conductive doped single-crystal semiconducting material 15 (e.g., 32). In one embodiment where removal is performed by etching, the insulating material comprises silicon nitride (e.g., 17) and silicon dioxide (e.g., 14 and / or 32), and the etching comprises selectively etching both silicon nitride and silicon dioxide relative to the conductive-doped single-crystal semiconducting material 15 simultaneously using the same etching chemicals. A person skilled in the art can select suitable etching chemicals and conditions to perform this etching. For example, and by way of example only, silicon dioxide and silicon nitride (e.g., at a volume ratio of at least 10:1 relative to each other) can be selectively etched together / simultaneously relative to the conductive-doped single-crystal silicon 15 (e.g., at a volume ratio of at least 10:1 relative to each other) under plasma conditions using SF6 and Ar at 100°C to 500°C and 10 mTorr to 5 Torr.

[0016] For example, see reference Figures 12 to 19 and Figures 8 to 11 An alternative example of forming the pillar 13* is described, wherein etching is used and the insulating material includes silicon nitride. This includes first, second, and third etching. Etching can occur before, after, and / or between such etching. Figures 12 to 15 The results of the first etching are shown, which selectively remove some silicon nitride (e.g., 17) relative to silicon dioxide (e.g., 14 and 32) and conductive doped single-crystal semiconducting material 15 (e.g., using CF4 and He with or without plasma generation). Figure 16 and 19 The results of the second etching are shown, which selectively remove some silicon dioxide (e.g., 14 and 32) relative to silicon nitride (e.g., 17) and conductive doped single-crystal semiconducting material 15 (e.g., NH3 and NF3 in the case of plasma generation). Figures 8 to 11 The results of the third etching are shown, which selectively removes some additional silicon nitride (e.g., 17) relative to silicon dioxide (e.g., 14) and conductive doped single-crystal semiconducting material 15 (e.g., using CF4 and He with or without plasma generation).

[0017] refer to Figures 20 to 23 Conductive doped single-crystal semiconductor material 33 has been epitaxially grown from the top 30 and sidewalls 31 of individual pillars 13* to form conductive single-crystal caps 37, which are individually located directly above the top 30 of the individual pillars 13* and circumferentially surround the sidewalls 31 of the individual pillars 13*. In structural embodiments, and unless so stated in the claims, regardless of method attributes or limitations, the conductive single-crystal cap 37 located above the individual pillars 13x is at least part of the conductive path construction, and the conductive single-crystal silicon cap 37 located above the individual pillars 13y is at least part of the conductive path construction. In one embodiment, the conductive single-crystal cap 37 is epitaxially grown to have a conductivity-enhancing dopant that is at least primarily therein greater (e.g., at least 10 times) than at least primarily in the top 30 of the individual pillars 13*. In one such embodiment, the conductive doped single-crystal semiconductor material 33 and the conductive doped single-crystal silicon semiconductor material 15 have the same composition, but different amounts of conductivity-enhancing dopant (e.g., this same composition at least primarily comprises elemental silicon). As an example, the concentration of conductive dopant in one and the other source / drain regions 24, 26 is 1 x 10⁻⁶. 18 atoms / cm 3 To 1x 10 20 atoms / cm 3 Furthermore, in conductive single-crystal capping material 37, it is 1 x 10 21 atoms / cm 3 Up to 1x10 23 atoms / cm 3 .

[0018] The skillful craftsman can select conditions suitable for the epitaxial growth of the conductive doped single-crystal semiconductor material 33, depending on the composition of the material. For example, and by way of example only, the single-crystal silicon surface of the pillar 13* can be prepared for epitaxial growth using remote plasma exposure to NH3 and NF3 to form a precursor, which reacts with the silicon on such a surface to form an adhered [NH4]2SiF6. Using a suitable etchant, and then using dichlorosilane, HCl, and phosphine at a temperature of 500°C to 800°C and a pressure of 5 Torr to 500 Torr, most (if not all) of the [NH4]2SiF6 can be removed from the pillar 13* to form a conductive n-type doped single-crystal silicon 33.

[0019] In one embodiment and reference Figure 22 and 24 An intermediate region 50 is formed epitaxially at the interface 52 of the top 30 and sidewall 31 of an individual conductive single crystal cap 37 and its pillar 13*, wherein the intermediate region 50 includes an individual region located at 1 x 10 15 atoms / cm 3Up to 5x 10 21 atoms / cm 3 The chlorine, fluorine, and nitrogen in the intermediate region 50 may be caused by incomplete removal of the [NH4]2SiF6 example and by epitaxial growth using dichlorosilane and HCl as mentioned above. For example, the thickness of the intermediate region 50 is 2 to 3 nanometers.

[0020] In one embodiment and as shown, epitaxial growth forms a conductive single-crystal overlay 37 along the total vertical length of the sidewall 31 of the pillar 13* located above the substrate 77. Figures 25 to 28 The section on constructing 8a illustrates alternative examples. Similar numbers from the above embodiments are used where appropriate, with some construction differences indicated by the suffix "a". Figures 25 to 28 In this process, epitaxial growth forms a conductive single-crystal cap 37a only along the uppermost portion 81 of the sidewall 31 of the pillar 13* located above the substrate 77, and thus along less than the total vertical length of the sidewall 31 of the pillar 13* located above the substrate 77. For example, this situation may occur if less than all sidewalls are prepared for epitaxial growth using NH3 and NF3, if such sidewalls do not reach the bottom of the pillar 13* and / or if the epitaxial growth precursor does not reach the bottom of the pillar 13*.

[0021] refer to Figures 29 to 34 In one embodiment, a digital line structure 35 has been formed. This digital line structure 35 individually includes conductive digital lines 40 (e.g., including conductive metal material 45), which are located above a plurality of individual pillars 13y of another source / drain region 26 and are directly electrically coupled to the plurality of individual pillars 13y by conductive single-crystal caps 37 epitaxially grown directly above (i.e., directly above) their pillars 13y. The example digital line structure 35 includes an insulating material 90 (e.g., silicon nitride and / or silicon dioxide) along adjacent conductive single-crystal caps 37. The example digital line structure 35 also includes an example conductive material 34 (e.g., conductive metal material) that directly electrically couples the digital lines 40 to the individual conductive single-crystal caps 37, and thereby includes a conductive path structure 89, which includes the conductive material 34 and the conductive single-crystal caps 37. The example digital line structure 35 also includes an insulating material 38 located on top of the digital line 40 and anisotropically etched insulating sidewall spacers 41 (e.g., silicon nitride and / or silicon dioxide) located on each side thereof. The spacers 41 may individually comprise a variety of different composition materials, some or each of which may be anisotropically etched individually.

[0022] This ultimately forms individual memory elements. These memory elements are individually located above individual pillars of a source / drain region and electrically coupled (e.g., directly electrically coupled) to the individual pillars via an epitaxially grown conductive single-crystal cap 37 located directly above the individual pillars. In one embodiment, a conductive material is formed prior to forming the memory element, such that this conductive material is vertically positioned between one of the memory elements and its conductive single-crystal cap 37, wherein the conductive material is located directly above and electrically coupled to its conductive single-crystal cap 37, and has a composition different from that of its conductive single-crystal cap 37. The following discusses… Figures 35 to 46 Describe one of these instances.

[0023] refer to Figures 35 to 38 In one embodiment, a conductive-doped semiconducting material 42 is formed on top of the conductive-doped single-crystal semiconductor material 33 of the individual conductive single-crystal cap 37. For example, the material 42 can be deposited and subtractively etched directly against the material 33, or the material 42 can be epitaxially grown from the material 33 (ideally). The materials 42 and 33 may have the same or different (some) compositions relative to each other. In any case, and in one embodiment as shown, the conductive-doped semiconducting material 42 extends laterally outward beyond the sides 43 of the epitaxially grown conductive-doped single-crystal semiconductor material 33 of the conductive single-crystal cap 37 (e.g., more than two opposite sides 43, as shown).

[0024] refer to Figures 39 to 42 An insulating material 44 (e.g., silicon dioxide and / or silicon nitride) has been formed between the digital line structures 35, and a contact opening 57 has then been formed through the insulating material 44 to the conductive doped semiconducting material 42. The insulating material 44 may be planarized back to the top of the material 38 (as shown). The contact opening 57 may be laterally inward and / or laterally outward tapered (not shown). The contact opening 57 may have the same size and / or shape in a horizontal cross-section as the material 42 and / or 33 (generally the same shape as the material 42 shown, but different in size). In embodiments in which the conductive doped semiconducting material 42 is formed, the conductive doped semiconducting material 42 may be formed together with its contact opening 57 before or after the formation of the insulating material 44.

[0025] refer to Figures 43 to 46A conductive metal material 80 has been formed directly above and against the conductive doped semiconducting material 42, thus forming an individual conductive path structure 82 (e.g., including materials 80, 42, and 33 / cover 37). A memory element 85 (e.g., a capacitor) has been formed (e.g., directly electrically coupled to the individual conductive path structure 82), thereby forming an individual memory cell 95 (e.g., including transistor 25 and memory element 85). This is only one example embodiment, in which the memory element 85 is individually located above an individual source / drain region 24 and electrically coupled (e.g., directly coupled) to an individual source / drain region 24 through an individual conductive single-crystal cover 37 comprising epitaxially grown conductive doped single-crystal semiconductor material 33.

[0026] Figure 47 An example alternative construction 8b is shown, comprising a conductive pathway construction 82b (e.g., including materials 80 and 33 / covering 37) without conductive doped semiconducting material 42 (which is therefore not shown). Similar figures from the above embodiments are used where appropriate, with some construction differences indicated by the suffix "b".

[0027] Any other properties or aspects as shown and / or described herein with reference to the embodiments described and illustrated above may be used in the embodiments shown and described above with reference to other embodiments.

[0028] Alternative embodiments may be constructed using the method embodiments described above or otherwise. In any case, embodiments of the invention cover memory arrays independent of manufacturing methods. However, such memory arrays may have any of the properties described herein in the method embodiments. Similarly, the method embodiments described above may incorporate, form, and / or have any of the properties described with respect to the device embodiments.

[0029] In one embodiment, a memory circuit system (e.g., 8, 8b) includes a transistor (e.g., 25), each transistor individually including a source / drain region (e.g., 24) and another source / drain region (e.g., 26). Each of the one and other source / drain regions individually includes a pillar (e.g., 13*), the pillar comprising a conductive-doped single-crystal semiconducting material (e.g., 15). The pillar includes a pillar top (e.g., 30) and pillar sidewalls (e.g., 31). A channel region (e.g., 27) is located between the one and the other source / drain regions. A conductive gate (e.g., 22) is operatively adjacent to the channel region. A conductive path structure (e.g., 89) is individually located directly above and electrically coupled to one of the pillars in the other source / drain region. Digital lines (e.g., 40) are individually located above and directly electrically coupled to multiple conductive path structures. A pillar containing a conductive path structure (e.g., 82) is individually located directly above and electrically coupled to the pillar of one of the individual source / drain regions. A storage element (e.g., 85) is individually electrically coupled to the individual in the conductive path structure. The individual in the conductive path structure and the individual conductive path structure include a conductive single-crystal capping (e.g., 37) located directly above and abutting the top of the pillar and circumferentially surrounding and abutting the sidewalls of the pillar. The conductive single-crystal capping has the same crystallinity as the conductive doped single-crystal semiconducting material of the pillar. The conductive single-crystal capping has, at least primarily therein, a conductivity-enhancing dopant that is at least primarily present in the top of the pillar than in the top of the pillar.

[0030] In one embodiment, the individual conductive pathway configuration includes a conductive material (e.g., 42) vertically positioned between one of the memory elements and its conductive single-crystal cap. This conductive material is located directly above and electrically coupled to its conductive single-crystal cap. The conductive material has a composition different from that of its conductive single-crystal cap.

[0031] Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0032] In one embodiment, a memory circuit system (e.g., 8, 8b) includes a transistor (e.g., 25), each transistor individually including a source / drain region (e.g., 24) and another source / drain region (e.g., 26). Each of the one and other source / drain regions individually includes a pillar (e.g., 13*), the pillar comprising a conductive-doped single-crystal semiconducting material (e.g., 15). The pillar includes a pillar top (e.g., 30) and pillar sidewalls (e.g., 31). A channel region (e.g., 27) is located between the one and the other source / drain regions. A conductive gate (e.g., 22) is operatively adjacent to the channel region. A conductive path structure (e.g., 89) is individually located above and directly electrically coupled to the pillar of each of the other source / drain regions. Digital lines (e.g., 40) are individually located above and directly electrically coupled to the plurality of conductive path structures. A pillar containing a conductive path structure (e.g., 82) is individually located directly above and electrically coupled to the pillar of one of the individual source / drain regions. A storage element (e.g., 85) is individually electrically coupled to the individual of the individual conductive path structures. The individual of the conductive path structures and the individual conductive path structures include a conductive single-crystal capping (e.g., 37) located directly above and abutting the top of the pillar and circumferentially surrounding and abutting the sidewalls of the pillar. An intermediate region (e.g., 50) is located at the interface (e.g., 52) between the conductive single-crystal capping and the top of the pillar and the sidewalls of the pillar. The intermediate region includes areas individually located at 1 x 10 15 atoms / cm 3 Up to 5x 10 21 atoms / cm 3 Chlorine, fluorine and nitrogen.

[0033] Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0034] When forming the conductive single-crystal cap 37 as shown and described herein, epitaxial growth material 33 can be used to expand the target area for subsequent patterning to form materials 34 and 80, thereby potentially increasing the ohmic contact area between another source / drain region 26 and the digital line structure 35, as well as a source / drain region 24 and the memory element 85. Although Figures 29 to 34 The digital line structure 35 is shown to be perfectly aligned with the original pillar 13y, but this may not occur in practice, and the conductive single-crystal overlay 37 provides additional margin in the x and y directions. The forming material 42 can be used to further expand the x and y area for the final formation of the conductive material 80.

[0035] (Several) of the above processing or (several) constructions can be considered relative to an array of components formed as a single stack or single layer of such components above or as part of an underlying substrate, or formed within a single stack or single layer (although a single stack / layer may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed anywhere as part of the finished construction, and in some embodiments may be under the array (e.g., under-array CMOS). In any case, one or more additional stacks / layers of this type may be disposed or fabricated above and / or below the locations shown in the figures or described above. Furthermore, (several) arrays of components may be identical or different from each other in different stacks / layers, and the different stacks / layers may have the same or different thicknesses relative to each other. Intermediate structures may be disposed vertically adjacent to the stacks / layers (e.g., additional circuitry and / or dielectric layers). Moreover, the different stacks / layers may be electrically coupled relative to each other. Multiple stacks / layers can be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / layers can be manufactured substantially simultaneously.

[0036] The assemblies and structures discussed above can be used in integrated circuit / circuit systems and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and special-purpose modules, and can include multi-layered, multi-chip modules. Electronic systems can be any of a wide range of systems, such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting devices, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0037] In this document, unless otherwise indicated, “vertical,” “higher,” “up,” “lower,” “top,” “top,” “bottom,” “above,” “below,” “under,” “upward,” and “downward” generally refer to the vertical direction. “Horizontal” means along the general direction of the substrate surface (i.e., within 10 degrees) and relative to the direction in which the substrate is handled during manufacturing, while vertical is generally orthogonal to the horizontal. “Fully horizontal” means along the direction of the substrate surface (i.e., not at an angle to the substrate surface) and relative to the direction in which the substrate is handled during manufacturing and as shown in the accompanying drawings (if any). Furthermore, as used herein, “vertical” and “horizontal” generally refer to directions perpendicular to each other and are independent of the substrate’s orientation in three-dimensional space during manufacturing and / or in the finished product construction. Additionally, “elevationally-extending” and “extend(ing)elevationally” mean a direction at an angle of at least 45° to the fully horizontal. Furthermore, this refers to the orientation of the transistor channel length along which the reference current flows between the source / drain regions during operation, relative to the field-effect transistor's "extending elevationally," "elevationally-extending," "extending horizontally," "horizontally-extending," and similar terms. For a bipolar junction transistor, this refers to the orientation of the base length along which the reference current flows between the emitter and collector during operation, relative to the field-effect transistor's "extending elevationally," "elevationally-extending," "extending horizontally," "horizontally-extending," and similar terms. In some embodiments, any vertically extending component, feature, and / or region extends vertically or within a vertical 10° range.

[0038] Furthermore, the phrases "directly above," "directly below," and "directly under" require that the two stated areas / materials / components have at least some lateral (i.e., horizontal) overlap relative to each other. Moreover, the use of "above" without the preceding "directly" only requires that a portion of the stated area / material / component located above another stated area / material / component is vertically outside the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components). Similarly, the use of "below" and "under" without the preceding "directly" only requires that a portion of the stated area / material / component located below / under another stated area / material / component is vertically inside the other stated area / material / component (i.e., regardless of whether there is any lateral overlap between the two stated areas / materials / components).

[0039] Any of the materials, regions, and structures described herein may be homogeneous or heterogeneous, and in any event may be continuous or discontinuous on any material to which they are superimposed. Where one or more example components are provided for any material, that material may comprise, consist substantially of, or be composed of such one or more components. Furthermore, unless otherwise stated, each material may be formed using any suitable existing or future-developed technique, among which atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation are examples.

[0040] Furthermore, “thickness” itself (without a directional adjective preceding it) is defined as the average straight-line distance perpendicularly through a given material or region from the nearest surface of adjacent materials or regions of different compositions. Additionally, the various materials or regions described herein may have substantially constant thickness or variable thickness. If variable thickness is present, then unless otherwise indicated, the thickness refers to the average thickness, and due to the variable thickness, the material or region will have a minimum thickness and a maximum thickness. As used herein, “different compositions” requires only that the portions of two stated materials or regions that may be in direct contact with each other are chemically and / or physically different, for example, provided that such materials or regions are not homogeneous. If two stated materials or regions are not in direct contact with each other, then “different compositions” requires only that the portions of two stated materials or regions that are closest to each other are chemically and / or physically different, provided that such materials or regions are not homogeneous. In this document, a stated material, region, or structure is “in direct contact” with another material, region, or structure when there is at least some physical contact between them. Conversely, the words “on top of,” “on,” “near,” “along,” and “against” without the preceding “direct” encompass “direct abutment” and constructions in which (some) intermediate materials, (some) areas, or (some) structures result in the stated materials, areas, or structures not being in physical contact with each other.

[0041] In this document, if current can flow continuously from one zone-material-component to another during normal operation and, when sufficient subatomic positive and / or negative charges are generated, the flow is primarily through the movement of said subatomic positive and / or negative charges, then the zone-material-components are “electrically coupled” relative to each other. Another electronic component may be located between and electrically coupled to the zone-material-components. In contrast, when zone-material-components are referred to as “directly electrically coupled,” no intermediate electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) are located between the directly electrically coupled zone-material-components.

[0042] In this document, any use of the terms "row" and "column" is for the purpose of distinguishing a series or one orientation of features from another series or another orientation of features, and which have been or may form components along said "row" and "column". "Row" and "column" are used synonymously with any series of areas, components, and / or features, and are not related to function. In any case, rows may be straight and / or curved and / or parallel and / or non-parallel, and columns may be as well. Furthermore, rows and columns may intersect each other at 90° or one or more other angles (i.e., other than right angles).

[0043] The composition of any of the conductive / conductor / conductive materials mentioned herein may be conductive metallic materials and / or conductive doped semiconducting / semiconductor / semiconductive materials. "Metallic material" is any elemental metal, any mixture or alloy of two or more elemental metals, and any one or more metallic compounds or combinations thereof.

[0044] In this document, any use of “selective” regarding etching, etching, removing, removal, deposition, forming, and / or formation is an act in which a stated material acts relative to another stated material(s) at a volume ratio of at least 2:1. Furthermore, any use of selective deposition, selective growth, or selective formation is the deposition, growth, or formation of a material relative to another stated material(s) at a volume ratio of at least 2:1 for at least the first 75 angstroms of the deposition, growth, or formation.

[0045] Unless otherwise indicated, the use of "or" in this document covers either or both.

[0046] in conclusion

[0047] In some embodiments, a method for forming a memory circuit system includes forming pillars that project upward from a substrate and comprise conductive-doped single-crystal semiconducting material. Individual pillars comprise one source / drain region or another source / drain region of a transistor for an individual memory cell of the memory circuit system being formed. Conductive-doped single-crystal semiconductor material is epitaxially grown from the top and sidewalls of the individual pillars to form a conductive single-crystal cap, the conductive single-crystal cap being individually located directly above the top of the individual pillar and circumferentially surrounding the sidewalls of the individual pillar. Digital lines are formed, each digital line being individually located above a plurality of the individual pillars for the other source / drain region and directly electrically coupled to the plurality of individual pillars via the epitaxially grown conductive single-crystal cap located directly above the plurality of individual pillars. A memory element for the individual memory cell is formed. The memory element is individually located above the individual pillar for one source / drain region and electrically coupled to the individual pillar via the epitaxially grown conductive single-crystal cap located directly above the individual pillar.

[0048] In some embodiments, a memory circuit system includes a transistor, each transistor individually including a source / drain region and another source / drain region. Each of the one and other source / drain regions individually includes a pillar, the pillar comprising a conductive-doped single-crystal semiconducting material. The pillar includes a pillar top and pillar sidewalls. A channel region is located between the one and the other source / drain regions. A conductive gate is operatively proximate to the channel region. Conductive path configurations are individually located directly above and electrically coupled to the pillar of each of the other source / drain regions. Digital lines are individually located above and directly electrically coupled to a plurality of the conductive path configurations. Conductive path configurations are individually located directly above and electrically coupled to the pillar of each of the one source / drain regions. A memory element is individually electrically coupled to each of the conductive path configurations. Individual components of the conductive pathway structure include a conductive single-crystal capping material located directly above and abutting the top of the pillar, and circumferentially surrounding and abutting the sidewalls of the pillar. The conductive single-crystal capping material has the same crystallinity as the conductive doped single-crystal semiconducting material of the pillar. The conductive single-crystal capping material contains, at least primarily, a conductivity-enhancing dopant that is at least primarily present in the top of the pillar compared to its position in the pillar.

[0049] In some embodiments, a memory circuit system includes a transistor, each transistor individually including a source / drain region and another source / drain region. Each of the one and other source / drain regions individually includes a pillar, the pillar comprising a conductive-doped single-crystal semiconducting material. The pillar includes a pillar top and pillar sidewalls. A channel region is located between the one and the other source / drain regions. A conductive gate is operatively proximate to the channel region. Conductive path configurations are individually located directly above and electrically coupled to the pillar of each of the other source / drain regions. Digital lines are individually located above and directly electrically coupled to a plurality of the conductive path configurations. Conductive path configurations are individually located directly above and electrically coupled to the pillar of each of the one source / drain regions. A memory element is individually electrically coupled to each of the conductive path configurations. The individual conductive pathway structure includes a conductive single-crystal capping material located directly above and abutting the top of the pillar, and circumferentially surrounding and abutting the sidewall of the pillar. An intermediate region is located at the interface between the conductive single-crystal capping material and the top and sidewall of the pillar. The intermediate region includes areas individually located within a 1 x 10... 15 atoms / cm 3 Up to 5x 10 21 atoms / cm 3 Chlorine, fluorine and nitrogen.

[0050] In accordance with regulations, the subject matter disclosed herein has been described in language that is more or less specific to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include exemplary embodiments. Therefore, the claims should be given full scope in accordance with their literal wording and properly interpreted according to the doctrine of equivalents.

Claims

1. A method for forming memory circuitry, comprising: forming pillars that protrude upward from a substrate and comprise conductively-doped monocrystalline semiconductive material, individual ones of the pillars comprising one source / drain region or the other of a transistor of an individual memory cell of the memory circuitry being formed; epitaxially growing conductively-doped monocrystalline semiconductor material from tops and sidewalls of the individual pillars to form conductive monocrystalline caps that individually overlie the tops of the individual pillars and circumferentially surround the sidewalls of the individual pillars; forming digit lines that individually overlie a plurality of the individual pillars of the other source / drain region and are directly electrically coupled to a plurality of the individual pillars by the epitaxially grown conductive monocrystalline caps that overlie a plurality of the individual pillars; and forming storage elements of the individual memory cells that individually overlie the individual pillars of the one source / drain region and are electrically coupled to the individual pillars by the epitaxially grown conductive monocrystalline caps that overlie the individual pillars.

2. The method of claim 1 wherein the forming of the pillars comprises removing insulative material that surrounds the conductively-doped monocrystalline semiconductive material.

3. The method of claim 2 wherein the forming of the pillars comprises removing insulative material that overtops the conductively-doped monocrystalline semiconductive material.

4. The method of claim 3 wherein the removing each comprises etching.

5. The method of claim 4 wherein the insulative material comprises silicon nitride and silicon dioxide, the etching comprising using the same etching chemistry to simultaneously selectively etch the silicon nitride and the silicon dioxide relative to the conductively-doped monocrystalline semiconductive material.

6. The method of claim 4 wherein the insulative material comprises silicon nitride and silicon dioxide, the etching comprising first, second, and third etches; the first etch selectively removing some of the silicon nitride relative to the silicon dioxide and the conductively-doped monocrystalline semiconductive material; the second etch selectively removing some of the silicon dioxide relative to the silicon nitride and the conductively-doped monocrystalline semiconductive material; and the third etch selectively removing other of the silicon nitride relative to the silicon dioxide and the conductively-doped monocrystalline semiconductive material.

7. The method of claim 1 wherein the epitaxial growing forms the conductive monocrystalline caps to have at least a greater increase in conductivity therein than in the tops of the individual pillars.

8. The method of claim 7 wherein the greater increase in conductivity is at least 10 times.

9. The method of claim 7 wherein the conductively-doped monocrystalline semiconductor material and the conductively-doped monocrystalline semiconductive material have the same composition but different amounts of the increase in conductivity dopant.

10. The method of claim 9 wherein the same composition comprises at least predominantly elemental silicon.

11. The method of claim 1 wherein the epitaxial growth forms an intermediate region at the interface of individual ones of the conductive monocrystalline cap and the top of its pillar and the sidewall, the intermediate region comprising individually 1 x 10 15 atoms / cm 3 to 5 x 10 21 atoms / cm 3 of chlorine, fluorine, and nitrogen.

12. The method of claim 1 wherein said epitaxial growth forms said conductive single-crystal cap along a total vertical length of said sidewall of said pillar located above said substrate.

13. The method of claim 1 wherein said epitaxial growth forms said conductive single-crystal cap only along an uppermost portion of said sidewall of said pillar located above said substrate and thereby along a total height length of said sidewall of said pillar located above said substrate.

14. Memory circuitry comprising: a transistor individually comprising: one source / drain region and another source / drain region, said one and another source / drain region individually comprising a pillar, said pillar comprising a conductive doped single-crystalline semiconductive material, said pillar comprising a pillar top and a pillar sidewall; a channel region located between said one and said another source / drain region; and a conductive gate operatively proximate said channel region; a conductive access structure individually located directly above and directly electrically coupled to said pillar of an individual of said another source / drain region; a digit line individually located above and directly electrically coupled to a plurality of said conductive access structures; a conductive access structure individually located directly above and directly electrically coupled to said pillar of an individual of said one source / drain region; a storage element individually electrically coupled to an individual of said conductive access structures; and said individual of said conductive access structures and said individual conductive access structure comprising a conductive single-crystal cap located directly above and directly against said pillar top and circumferentially around and directly against said pillar sidewall, said conductive single-crystal cap having a same crystallinity as said conductive doped single-crystalline semiconductive material of said pillar, said conductive single-crystal cap having at least a predominantly greater conductivity increasing dopant therein than at least a predominantly in said pillar top.

15. The memory circuitry of claim 14 wherein said individual conductive access structure comprises a conductive material vertically located between one of said storage elements and its conductive single-crystal cap, said conductive material located directly above and directly electrically coupled to its conductive single-crystal cap, said conductive material having a different composition than a composition of its conductive single-crystal cap.

16. The memory circuitry of claim 14 wherein said greater conductivity increasing dopant is at least 10 times greater.

17. The memory circuitry of claim 14 wherein said conductive doped single-crystalline semiconductive material and said conductive doped single-crystalline semiconductive material have a same composition but a different amount of said conductivity increasing dopant.

18. The memory circuitry of claim 17 wherein said same composition comprises at least predominantly elemental silicon.

19. The memory circuitry of claim 14, comprising an intermediate region at an interface of the conductive monocrystalline cap with the pillar top and the pillar sidewall, the intermediate region comprising chlorine, fluorine, and nitrogen individually at 1 x 10 15 atoms / cm 3 to 5 x 10 21 atoms / cm 3 .

20. Memory circuitry comprising: a transistor individually comprising: one source / drain region and another source / drain region, said one and another source / drain region individually comprising a pillar, said pillar comprising a conductive doped single-crystalline semiconductive material, said pillar comprising a pillar top and a pillar sidewall; a channel region located between said one and said another source / drain region; and a conductive gate operatively proximate said channel region; a conductive access structure individually located directly above and directly electrically coupled to said pillar of an individual of said another source / drain region; a digit line individually located above and directly electrically coupled to a plurality of said conductive access structures; a conductive access structure individually located directly above and directly electrically coupled to said pillar of an individual of said one source / drain region; a storage element individually electrically coupled to an individual of said conductive access structures; and said individual of said conductive access structures and said individual conductive access structure comprising a conductive single-crystal cap located directly above and directly against said pillar top and circumferentially around and directly against said pillar sidewall, said conductive single-crystal cap having a same crystallinity as said conductive doped single-crystalline semiconductive material of said pillar, said conductive single-crystal cap having at least a predominantly greater conductivity increasing dopant therein than at least a predominantly in said pillar top. one source / drain region and another source / drain region, the one and another source / drain regions individually comprising a pillar, the pillar comprising an electrically conductive doped single crystalline semiconductive material, the pillar comprising a pillar top and a pillar sidewall; a channel region between the one and the another source / drain regions; and an electrically conductive gate operatively proximate the channel region; a conductive via structure individually located directly above and directly electrically coupled to the pillar of an individual of the another source / drain regions; a digit line individually located above and directly electrically coupled to a plurality of the conductive via structures; an electrically conductive via structure individually located directly above and directly electrically coupled to the pillar of an individual of the one source / drain regions; a storage element individually electrically coupled to an individual of the electrically conductive via structures; and an individual of the conductive via structures and the individual electrically conductive via structure comprising: an electrically conductive single crystalline cap located directly above and directly against the pillar top and circumferentially around and directly against the pillar sidewall; and an intermediate region at the interface of the conductive single-crystal cap and the pillar top and the pillar sidewall, the intermediate region comprising individually 1 x 10 15 atoms / cm 3 to 5 x 10 21 atoms / cm 3 of chlorine, fluorine, and nitrogen.

21. The memory circuitry of claim 20, wherein the intermediate region comprises individually 1 x 10 18 atoms / cm 3 to 5 x 10 19 atoms / cm 3 of chlorine, fluorine, and nitrogen.

22. The memory circuitry of claim 20, wherein the individual electrically conductive via structure comprises a conductive material vertically between one of the storage elements and the electrically conductive single crystalline cap, the conductive material located directly above and directly electrically coupled to the electrically conductive single crystalline cap, the conductive material having a different composition than a composition of the electrically conductive single crystalline cap.

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