Semiconductor memory device

Abstract

A semiconductor memory device includes: a bit line extending in a first direction on a substrate; a first active pattern and a second active pattern on the bit line and spaced apart from each other in a first direction; at least one conductive gate line between the first active pattern and the second active pattern and extending in the second direction; a gate shield pattern between the at least one conductive gate line and the bit line and including an insulating material doped with phosphorus (P); and a data storage pattern on the first active pattern and the second active pattern and electrically connected to the first active pattern and the second active pattern.

Description

Technical Field

[0001] This disclosure relates to a semiconductor memory device, and more specifically, to a semiconductor memory device including a vertical channel transistor (VCT). Background Technology

[0002] To meet consumer demand for superior performance and low cost, it is desirable to increase the integration density of semiconductor memory devices. Since the integration density of semiconductor memory devices is a factor determining product price, particularly high integration densities may be desired.

[0003] The integration density of two-dimensional (2D) or planar semiconductor memory devices can be determined by the area occupied by a unit memory cell and is therefore affected by the level of fine patterning technology. However, while the integration density of 2D semiconductor memory devices is increasing, it remains limited due to the use of ultra-high-cost equipment to miniaturize the patterns. Therefore, semiconductor memory devices including vertical channel transistors (VCTs) have been proposed, in which the channel extends vertically. Summary of the Invention

[0004] This disclosure provides a semiconductor memory device with improved integration density and electrical characteristics.

[0005] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon reference to the detailed description of the disclosure given below.

[0006] According to one aspect of this disclosure, a semiconductor memory device is provided, comprising: a bit line extending on a substrate in a first direction; a first active pattern and a second active pattern spaced apart from each other on the bit line and in the first direction; at least one conductive gate line extending between the first active pattern and the second active pattern in a second direction; a gate shielding pattern between the at least one conductive gate line and the bit line and comprising an insulating material doped with phosphorus (P); and a data storage pattern on the first active pattern and the second active pattern and electrically connected to the first active pattern and the second active pattern.

[0007] According to another aspect of this disclosure, a semiconductor memory device is provided, comprising: a bit line extending on a substrate in a first direction; an active pattern disposed on the bit line, the active pattern including first sidewalls and second sidewalls opposite to each other in the first direction, the active pattern including first surfaces and second surfaces opposite to each other in a vertical direction perpendicular to the substrate, wherein the first surface of the active pattern is electrically connected to the bit line; a word line on the first sidewall of the active pattern and extending in a second direction; a back gate electrode on the second sidewall of the active pattern and extending in the second direction; a first gate shielding pattern between the word line and the bit line; a second gate shielding pattern between the back gate electrode and the bit line; and a data storage pattern on the active pattern and electrically connected to the second surface of the active pattern, wherein at least one of the first gate shielding pattern and the second gate shielding pattern comprises phosphosilicate glass (PSG).

[0008] According to another aspect of this disclosure, a semiconductor memory device is provided, comprising: a peripheral gate structure on a substrate; a first bonding pad on the peripheral gate structure; a second bonding pad on and in contact with the first bonding pad; a bit line on the second bonding pad and extending in a first direction; a shielding conductive pattern on the second bonding pad, adjacent to the bit line and extending in the first direction, and including a plurality of shielding conductive line patterns; a first word line on the bit line and the shielding conductive pattern and extending in a second direction; a second word line on the bit line and the shielding conductive pattern, extending in the second direction, and spaced apart from the first word line in the first direction; a back gate electrode between the first word line and the second word line and extending in the second direction; a first active pattern on the bit line and between the first word line and the back gate electrode; a second active pattern on the bit line and between the second word line and the back gate electrode; a first gate shielding pattern between the first word line and the bit line, and between the second word line and the bit line, and including an insulating material doped with phosphorus (P); and a data storage pattern electrically connected to the first active pattern and the second active pattern.

[0009] It should be noted that the effects of this disclosure are not limited to those described above, and other effects of this disclosure will be apparent from the following description. Attached Figure Description

[0010] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0011] Figure 1 It is a layout diagram used to explain semiconductor memory devices according to some embodiments.

[0012] Figure 2 It is along Figure 1 A sectional view taken from lines AA and BB.

[0013] Figure 3 It is along Figure 1 A cross-sectional view taken from the CC and DD lines.

[0014] Figure 4 yes Figure 2 An enlarged sectional view of part P.

[0015] Figure 5 It is used for explanation Figure 4 Example diagram of the gate shielding pattern and the concentration of phosphorus (P) in the first impurity doped region.

[0016] Figure 6 This is a diagram used to explain semiconductor memory devices according to some embodiments.

[0017] Figures 7 to 9 This is a diagram used to explain semiconductor memory devices according to some embodiments.

[0018] Figure 10 and Figure 11 This is a diagram used to explain semiconductor memory devices according to some embodiments.

[0019] Figure 12 This is a diagram used to explain semiconductor memory devices according to some embodiments.

[0020] Figure 13 and Figure 14 This is a diagram used to explain semiconductor memory devices according to some embodiments.

[0021] Figure 15 and Figure 16 This is a diagram used to explain semiconductor memory devices according to some embodiments.

[0022] Figure 17 and Figure 18 This is a diagram used to explain semiconductor memory devices according to some embodiments.

[0023] Figure 19 and Figure 20 This is a diagram used to explain semiconductor memory devices according to some embodiments.

[0024] Figures 21 to 24 This is a diagram used to explain semiconductor memory devices according to some embodiments.

[0025] Figures 25 to 55 This is a diagram used to explain intermediate steps of a method for manufacturing a semiconductor memory device according to some embodiments. Detailed Implementation

[0026] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or section described below may be referred to as the second element, component, region, layer, or section.

[0027] To clarify this disclosure, the same elements or equivalents are designated by the same reference numerals throughout the specification. Furthermore, since the dimensions and thicknesses of the constituent components shown in the drawings are arbitrarily given for better understanding and ease of description, this disclosure is not limited to the dimensions and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are overstated for better understanding and ease of description.

[0028] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being “directly on” another element, there are no intermediate elements present. Furthermore, for ease of description, this document may use spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or feature and another element or feature as shown in the figures. It should be understood that, in addition to the orientations shown in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as being “below” or “under” another element or feature will be oriented “above” the other element or feature. Therefore, the term “below” can include both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0029] Furthermore, unless explicitly stated otherwise, the word “comprises” and variations thereof, such as “comprises” or “comprising,” shall be understood to imply inclusion of the stated elements but not exclusion of any other elements. As used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. The term “and / or” includes any and all combinations of one or more of the associated listed items. The term “connection” may be used herein to refer to physical and / or electrical connections, and may refer to direct or indirect physical and / or electrical connections. The term “exposed” may be used to define the relationship between a particular layer or surface, but it does not require that the layer or surface be free of other elements or layers in the finished device. When viewed along a line extending in a particular direction or in a plane perpendicular to a particular direction, components or layers described with reference to “overlapping” in a particular direction may at least partially obscure each other.

[0030] Figure 1 It is a layout diagram used to explain semiconductor memory devices according to some embodiments. Figure 2 It is along Figure 1 A sectional view taken from lines AA and BB. Figure 3 It is along Figure 1 A cross-sectional view taken from the CC and DD lines. Figure 4 yes Figure 2 An enlarged sectional view of part P. Figure 5 It is used for explanation Figure 4 Example diagram of the gate shielding pattern and the concentration of phosphorus (P) in the first impurity doped region.

[0031] According to some embodiments, a semiconductor memory device may include a memory cell that includes a vertical channel transistor (VCT).

[0032] refer to Figures 1 to 5 According to some embodiments, a semiconductor memory device may include a bit line BL, a first word line WL1, a second word line WL2, a back gate electrode BG, a shielding conductive pattern SL, a first active pattern AP1, a second active pattern AP2, and a data storage pattern DSP.

[0033] The substrate 100 may be a silicon (Si) substrate, or may include other materials such as silicon germanium (SiGe), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, but this disclosure is not limited thereto.

[0034] Although not shown, substrate 100 may include a cell array region in which a data storage pattern DSP is disposed and a peripheral circuit region defined around the cell array region.

[0035] A bonding insulating film 267 may be disposed on the substrate 100. The bonding insulating film 267 may be used to bond wafers. For example, the bonding insulating film 267 may comprise silicon carbonitride. In another example, the bonding insulating film 267 may comprise silicon oxide.

[0036] The shielding structures (171, SL and 175) may be disposed on the substrate 100. For example, the shielding structures (171, SL and 175) may be disposed on the bonding insulating film 267.

[0037] The shielding structure (171, SL, and 175) may include a shielding conductive pattern SL and shielding insulating films 171 and 175. For example, shielding insulating films 171 and 175 may include a shielding insulating pad 171 and a shielding insulating cover film 175.

[0038] The shielded conductive pattern SL may include a shielded conductive plate SLh and multiple shielded conductive line patterns SLp. The shielded conductive plate SLh may also have a flat plate shape.

[0039] Each shielded conductive wire pattern in the shielded conductive wire pattern SLp may extend in the second direction DR2. Each of the shielded conductive wire patterns SLp may be adjacent to each other in the first direction DR1. Each of the shielded conductive wire patterns SLp may protrude from or extend from the shielded conductive plate SLh in the third direction DR3. Each of the shielded conductive wire patterns SLp is directly connected to the shielded conductive plate SLh.

[0040] For example, the first direction DR1 and the second direction DR2 can be horizontal directions parallel to the substrate 100. The third direction DR3 can be vertical directions perpendicular to the substrate 100.

[0041] The shielding conductive plate SLh and the shielding conductive line pattern SLp can extend from the cell array region to the peripheral circuit region. A portion of the shielding conductive pattern SL can be disposed on the peripheral circuit region, but this disclosure is not limited thereto.

[0042] The shielding conductive pattern SL includes a conductive material. For example, the shielding conductive pattern SL may include at least one of conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, 2D material, or metal.

[0043] The shielding insulating cover film 175 can be disposed on the substrate 100. For example, the shielding insulating cover film 175 can be disposed between the substrate 100 and the shielding conductive pattern SL.

[0044] The shielding insulating cover film 175 may contact the shielding conductive pattern SL. In some embodiments, the shielding insulating cover film 175 may contact the shielding conductive plate SLh.

[0045] The shielding insulating pad 171 can be disposed on the shielding conductive pattern SL. The shielding insulating pad 171 can be disposed between the bit line BL and the substrate 100. The shielding insulating pad 171 can extend along the outline of the shielding conductive plate SLh and the shielding conductive line pattern SLp.

[0046] The shielding insulating pad 171 and the shielding insulating cover 175 may be formed of an insulating material. If the shielding insulating pad 171 and the shielding insulating cover 175 are formed of the same material, the boundary between the shielding insulating pad 171 and the shielding insulating cover 175 may be indistinguishable.

[0047] Because the shielding structures (171, SL and 175) are arranged between adjacent bit lines BL in the first direction DR1, the coupling noise between bit lines BL is reduced or suppressed.

[0048] Bit lines BL can be disposed on substrate 100. For example, bit lines BL can be disposed on bonding insulating film 267.

[0049] Bit lines BL can extend in the second direction DR2. Adjacent bit lines BL can be spaced apart in the first direction DR1. Bit lines BL include long sidewalls extending in the second direction DR2 and short sidewalls extending in the first direction DR1.

[0050] Bit line BL can be set on the shielded conductive pattern SL. Bit line BL can also be set on the shielded conductive plate SLh.

[0051] Bit line BL can be configured to be adjacent to shielded conductive line pattern SLp in the first direction DR1. That is, shielded conductive line pattern SLp can extend along the long sidewall of bit line BL in the second direction DR2.

[0052] Bit line BL can be disposed between adjacent shielded conductive line patterns SLp in the first direction DR1. Bit line BL can be disposed on shielding insulating pad 171. For example, shielding insulating pad 171 can contact bit line BL.

[0053] Although not shown, bit line BL can extend from the cell array region to the peripheral circuit region. A portion of bit line BL can be located on the peripheral circuit region.

[0054] Bit line BL may include an upper surface BL_US and a bottom surface BL_BS that are opposite each other on a third-direction DR3. The upper surface BL_US of bit line BL may face the first active pattern AP1 and the second active pattern AP2, which will be described later.

[0055] In some embodiments, a shielding conductive pattern SL may be disposed on the bottom surface BL_BS of the bit line BL. For example, a shielding conductive plate SLh may be disposed on the bottom surface BL_BS of the bit line BL.

[0056] Bit lines BL may include sequentially stacked semiconductor patterns 161, metal patterns 163, and bit line mask patterns 165. Alternatively, contrary to what is shown, bit lines BL may include either semiconductor patterns 161 or metal patterns 163. Or, each bit line BL may not include a bit line mask pattern 165.

[0057] Bit lines BL may include conductive bit lines. Conductive bit lines include films formed of conductive materials. Conductive bit lines may include semiconductor patterns 161 and metal patterns 163.

[0058] Semiconductor pattern 161 may include a conductive semiconductor material. The conductive semiconductor material may be, for example, a semiconductor material doped with impurities. Semiconductor pattern 161 may include at least one of polycrystalline silicon, polycrystalline SiGe, polycrystalline germanium (Ge), amorphous Si, amorphous SiGe, or amorphous Ge.

[0059] The metal pattern 163 may include a conductive material comprising a metal. For example, the metal pattern 163 may include at least one of a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a 2D material, or a metal. In some embodiments, the 2D material may be a metallic material and / or a semiconductor material. The 2D material may include a 2D allotrope or a 2D compound. For example, the 2D material may include at least one of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), or tungsten disulfide (WS2), but this disclosure is not limited thereto. In other words, the foregoing 2D materials are merely examples, and this disclosure is not limited thereto.

[0060] Bit line mask pattern 165 may include an insulating material. Bit line mask pattern 165 may include, for example, silicon nitride or silicon oxide nitride, but this disclosure is not limited thereto.

[0061] The first active pattern AP1 and the second active pattern AP2 can be set on the bit line BL. The first active pattern AP1 and the second active pattern AP2 can be arranged alternately along the second direction DR2.

[0062] The first active pattern AP1 can be spaced apart from each other in the first direction DR1. The first active pattern AP1 can be spaced apart at regular intervals. The second active pattern AP2 can be spaced apart from each other in the first direction DR1. The second active pattern AP2 can be spaced apart at regular intervals. The first active pattern AP1 can be spaced apart from the second active pattern AP2 in the second direction DR2. The first active pattern AP1 and the second active pattern AP2 can be arranged in two dimensions along the intersecting first direction DR1 and second direction DR2.

[0063] For example, the first active pattern AP1 and the second active pattern AP2 can be formed from a single-crystal semiconductor material. In one example, the first active pattern AP1 and the second active pattern AP2 can be formed from single-crystal Si. The first active pattern AP1 and the second active pattern AP2 can be Si active patterns.

[0064] The first active pattern AP1 and the second active pattern AP2 may have a length in the first direction DR1, a width in the second direction DR2, and a height in the third direction DR3. The first active pattern AP1 and the second active pattern AP2 may have substantially uniform widths. That is, the first active pattern AP1 and the second active pattern AP2 may have substantially the same width at their first surface S1 and second surface S2. Furthermore, the width of the first active pattern AP1 may be the same as the width of the second active pattern AP2.

[0065] The widths of the first active pattern AP1 and the second active pattern AP2 can range from a few nanometers to tens of nanometers. For example, the widths of the first active pattern AP1 and the second active pattern AP2 can range from 1 nm to 30 nm, such as about 1 nm to 10 nm, but this disclosure is not limited thereto. The lengths of the first active pattern AP1 and the second active pattern AP2 can be greater than the linewidth of the bit line BL. That is, the lengths of the first active pattern AP1 and the second active pattern AP2 can be greater than the width of the bit line BL in the first direction DR1.

[0066] exist Figure 4 In this configuration, the first active pattern AP1 and the second active pattern AP2 include a first surface S1 and a second surface S2 that are opposite to each other on a third-direction DR3. For example, the first surface S1 of the first active pattern AP1 and the second active pattern AP2 may face the bit line BL. The second surface S2 of the first active pattern AP1 and the second active pattern AP2 may face the contact pattern BC.

[0067] The first surface S1 of the first active pattern AP1 and the first surface S1 of the second active pattern AP2 are connected to the bit line BL. For example, the first surface S1 of the first active pattern AP1 and the first surface S1 of the second active pattern AP2 can be connected to the semiconductor pattern 161 of the bit line BL. Conversely, if the semiconductor pattern 161 is omitted, the first surface S1 of the first active pattern AP1 and the first surface S1 of the second active pattern AP2 can be connected to the metal pattern 163. The second surface S2 of the first active pattern AP1 and the second surface S2 of the second active pattern AP2 can be connected to the contact pattern BC.

[0068] The first active pattern AP1 and the second active pattern AP2 may include a first sidewall SS1 and a second sidewall SS2 that are opposite to each other in the second direction DR2. The second sidewall SS2 of the first active pattern AP1 may face the first sidewall SS1 of the second active pattern AP2.

[0069] The first sidewall SS1 of the first active pattern AP1 may be adjacent to the first letter line WL1. The second sidewall SS2 of the second active pattern AP2 may be adjacent to the second letter line WL2.

[0070] For example, the first active pattern AP1 and the second active pattern AP2 may include a first impurity-doped region AP_SDR. The first impurity-doped region AP_SDR may be adjacent to the bit line BL. The first impurity-doped region AP_SDR may include a first impurity element doped in it. The first impurity element doped in the first impurity-doped region AP_SDR may be an n-type impurity element. The first impurity element may include phosphorus (P). The first impurity element doped in the first impurity-doped region AP_SDR may be the same as the second impurity element doped in the gate shielding pattern 145, which will be described later.

[0071] Although not illustrated, in one example, the first active pattern AP1 and the second active pattern AP2 may include a second impurity-doped region adjacent to the corresponding contact pattern BC. The first active pattern AP1 and the second active pattern AP2 may include a channel region between the first impurity-doped region AP_SDR and the second impurity-doped region.

[0072] During operation of the semiconductor memory device, the channel regions of the first active pattern AP1 and the second active pattern AP2 can be controlled by the first word line WL1, the second word line WL2, and the back gate electrode BG. Since the first active pattern AP1 and the second active pattern AP2 are formed of single-crystal semiconductor material, the leakage current characteristics of the semiconductor memory device according to some embodiments can be improved.

[0073] The back gate electrode BG can be disposed on the bit line BL and the shielding conductive pattern SL. The back gate electrodes BG can be spaced apart from each other in the second direction DR2. The back gate electrodes BG can be spaced apart at regular intervals. Each of the back gate electrodes BG can extend across the bit line BL in the first direction DR1.

[0074] Each of the back gate electrodes BG can be disposed on the second direction DR2 between a pair of adjacent first active patterns AP1 and second active patterns AP2. In other words, the first active pattern AP1 can be disposed on a first side of each back gate electrode BG, and the second active pattern AP2 can be disposed on a second side of each back gate electrode BG. The height of the back gate electrode BG on the third direction DR3 can be less than the height of the first active pattern AP1 and the second active pattern AP2 on the third direction DR3.

[0075] Each of the back gate electrodes BG can be disposed between the second sidewall SS2 of the first active pattern AP1 and the first sidewall SS1 of the second active pattern AP2. Each of the back gate electrodes BG can be disposed on the second sidewall SS2 of the first active pattern AP1 and the first sidewall SS1 of the second active pattern AP2.

[0076] The first active pattern AP1 can be disposed between the first word line WL1 and the back gate electrode BG. The second active pattern AP2 can be disposed between the second word line WL2 and the back gate electrode BG. Each pair of adjacent first word lines WL1 and second word lines WL2 can be disposed between adjacent back gate electrodes BG in the second direction DR2.

[0077] The back gate electrode BG can be a first conductive gate line disposed between a pair of adjacent first active patterns AP1 and second active patterns AP2. A single back gate electrode BG can be disposed between a pair of adjacent first active patterns AP1 and second active patterns AP2.

[0078] The back gate electrode BG may include a first surface BG_S1 and a second surface BG_S2 opposite to each other on a third-direction DR3. The first surface BG_S1 of the back gate electrode BG may be closer to the bit line BL than the second surface BG_S2 of the back gate electrode BG. The first surface BG_S1 of the back gate electrode BG may face the bit line BL.

[0079] The back gate electrode (BG) may include a conductive material, such as at least one of a conductive semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a 2D material, or a metal.

[0080] During operation of a semiconductor memory device according to some embodiments, a voltage can be applied to the back gate electrode BG to adjust the threshold voltage of the leakage current transformer (VCT). By adjusting the threshold voltage of the VCT, degradation of leakage current characteristics can be prevented or suppressed.

[0081] The back gate separation pattern 111 can be disposed on the second direction DR2 between a pair of adjacent first active patterns AP1 and second active patterns AP2. The back gate separation pattern 111 can extend on the first direction DR1 parallel to the back gate electrode BG. The back gate separation pattern 111 can be disposed on the second surface BG_S2 of the back gate electrode BG.

[0082] The back gate separation pattern 111 may be formed of an insulating material. For example, the back gate separation pattern 111 may include silicon oxide, silicon oxide nitride, or silicon nitride, but this disclosure is not limited thereto.

[0083] The back gate insulating pattern 113 can be disposed between the back gate electrode BG and the first active pattern AP1, and between the back gate electrode BG and the second active pattern AP2. The back gate insulating pattern 113 can also be disposed between the back gate separating pattern 111 and the first active pattern AP1, and between the back gate separating pattern 111 and the second active pattern AP2.

[0084] The back gate insulating pattern 113 may be formed of an insulating material. For example, the back gate insulating pattern 113 may include silicon oxide, silicon nitride, a high-k dielectric material having a dielectric constant higher than that of silicon oxide, or a combination thereof.

[0085] A back gate shielding pattern 115 can be disposed between the bit line BL and the back gate electrode BG. The back gate shielding pattern 115 can be disposed on a second direction DR2 between a pair of adjacent first active patterns AP1 and second active patterns AP2. The back gate shielding pattern 115 can extend on a first direction DR1 parallel to the back gate electrode BG. The back gate shielding pattern 115 can be disposed on the first surface BG_S1 of the back gate electrode BG. The thickness of the back gate shielding pattern 115 between the bit lines BL can be different from the thickness of the back gate shielding pattern 115 on the upper surface BL_US of the bit line BL, but this disclosure is not limited thereto.

[0086] The back gate shielding pattern 115 may be formed of an insulating material. For example, the back gate shielding pattern 115 may include at least one of silicon oxide, silicon oxide nitride, or silicon nitride, but this disclosure is not limited thereto.

[0087] The first word line WL1 and the second word line WL2 can be disposed on the bit line BL and the shielding conductive pattern SL. The first word line WL1 and the second word line WL2 can extend in the first direction DR1. The first word line WL1 and the second word line WL2 can be arranged alternately in the second direction DR2.

[0088] The first character line WL1 can be positioned closer to the first active pattern AP1 than the second character line WL2. The first character line WL1 can be positioned on the first sidewall SS1 of the first active pattern AP1. The first character line WL1 can also be positioned outside the second sidewall SS2 of the first active pattern AP1.

[0089] The second character line WL2 can be positioned closer to the second active pattern AP2 than the first character line WL1. The second character line WL2 can be positioned on the second sidewall SS2 of the second active pattern AP2. The second character line WL2 may not be positioned on the first sidewall SS1 of the second active pattern AP2.

[0090] The first active pattern AP1 and the second active pattern AP2 can be disposed on the second direction DR2 between a pair of adjacent first word lines WL1 and second word lines WL2. In other words, the first word line WL1 and the second word line WL2 can be disposed on the second direction DR2 between a pair of adjacent first active patterns AP1 and second active patterns AP2. The first word line WL1 and the second word line WL2 can be second conductive gate lines disposed between a pair of adjacent first active patterns AP1 and second active patterns AP2.

[0091] The first word line WL1 and the second word line WL2 can be spaced apart from the bit line BL and the contact pattern BC on the third direction DR3. The first word line WL1 and the second word line WL2 can be located between the bit line BL and the contact pattern BC.

[0092] The first word line WL1 and the second word line WL2 can have widths in the second direction DR2. For example, the widths of the first word line WL1 and the second word line WL2 on the bit line BL can be different from the widths of the first word line WL1 and the second word line WL2 on the shielded conductive line SL.

[0093] For example, the first word line WL1 and the second word line WL2 may include a first portion WLa and a second portion WLb. The width of the first portion WLa in the second direction DR2 may be smaller than the width of the second portion WLb in the second direction DR2. For example, the first portion WLa may be disposed on the bit line BL, and the second portion WLb may be disposed on the shielded conductive pattern SL.

[0094] The first character line WL1 and the second character line WL2 may each include a first portion WLa and a second portion WLb arranged alternately along the first direction DR1. A first active pattern AP1 may be disposed on the first direction DR1 between adjacent second portions WLb of the first character line WL1. A second active pattern AP2 may be disposed on the first direction DR1 between adjacent second portions WLb of the second character line WL2.

[0095] Conversely, the width of the first portion WLa of the first word line WL1 and the second word line WL2 in the second direction DR2 can be the same as the width of the second portion WLb of the first word line WL1 and the second word line WL2 in the second direction DR2. In other words, the width of the first word line WL1 and the second word line WL2 on the bit line BL can be the same as the width of the first word line WL1 and the second word line WL2 on the shielded conductive line SL. The gate insulating pattern GOX, which will be described later, can at least partially fill the space between adjacent first active patterns AP1 in the first direction DR1, and the space between adjacent second active patterns AP2 in the first direction DR1.

[0096] The first word line WL1 and the second word line WL2 may include a first surface WL_S1 and a second surface WL_S2 opposite to each other on a third-party DR3. The first surface WL_S1 of the first word line WL1 and the second word line WL2 may be closer to the bit line BL than the second surface WL_S2 of the first word line WL1 and the second word line WL2. The first surface WL_S1 of the first word line WL1 and the second word line WL2 may face the bit line BL.

[0097] For example, the height of the first word line WL1 on the third-direction DR3 can be the same as the height of the back gate electrode BG on the third-direction DR3. In another example, the height of the first word line WL1 on the third-direction DR3 can be greater than the height of the back gate electrode BG on the third-direction DR3. In yet another example, the height of the first word line WL1 on the third-direction DR3 can be less than the height of the back gate electrode BG on the third-direction DR3.

[0098] Additionally, for example, the height of the first surface WL_S1 of the first word line WL1 can be the same as the height of the first surface BG_S1 of the back gate electrode BG on the third-party DR3 relative to the upper surface BL_US of the bit line BL. In another example, the first surface WL_S1 of the first word line WL1 can be higher than the first surface BG_S1 of the back gate electrode BG on the third-party DR3 relative to the upper surface BL_US of the bit line BL. In yet another example, the first surface WL_S1 of the first word line WL1 can be lower than the first surface BG_S1 of the back gate electrode BG on the third-party DR3 relative to the upper surface BL_US of the bit line BL.

[0099] Furthermore, for example, the height of the second surface WL_S2 of the first word line WL1 can be the same as the height of the upper surface BL_US of the bit line BL on the third-direction DR3 as the height of the second surface BG_S2 of the back gate electrode BG. In another example, the second surface WL_S2 of the first word line WL1 can be higher than the upper surface BL_US of the bit line BL on the third-direction DR3 than the second surface BG_S2 of the back gate electrode BG. In yet another example, the second surface WL_S2 of the first word line WL1 can be lower than the second surface BG_S2 of the back gate electrode BG on the third-direction DR3 relative to the upper surface BL_US of the bit line BL.

[0100] The first surface WL_S1 of the first word line WL1 and the second word line WL2 may be planar or coplanar, but this disclosure is not limited thereto. The second surface WL_S2 of the first word line WL1 and the second word line WL2 may also be planar or coplanar, but this disclosure is not limited thereto. The first surface BG_S1 and the second surface BG_S2 of the back gate electrode BG are illustrated as planar or coplanar, but this disclosure is not limited thereto.

[0101] The first word line WL1 and the second word line WL2 may include conductive materials. The first word line WL1 and the second word line WL2 may include at least one of the following: conductive semiconductor materials, conductive metal nitrides, conductive metal silicon nitrides, metal carbonitrides, conductive metal silicides, 2D materials, or metals.

[0102] A gate insulating pattern (GOX) may be disposed between the first word line WL1 and the first active pattern AP1, and between the second word line WL2 and the second active pattern AP2. The gate insulating pattern (GOX) may extend parallel to the first word line WL1 and the second word line WL2 in a first direction DR1.

[0103] The gate insulating pattern GOX may include silicon oxide, silicon oxide nitride, a high-k dielectric material having a dielectric constant higher than that of silicon oxide, or a combination thereof. The high-k dielectric material may include, for example, at least one of metal oxide, metal oxide nitride, metal silicon oxide, or metal silicon oxide nitride, but this disclosure is not limited thereto.

[0104] The gate insulating pattern GOX may extend along the first sidewall SS1 of the first active pattern AP1 and along the second sidewall SS2 of the second active pattern AP2. The gate insulating pattern GOX may be disposed between the first active pattern AP1 and the gate cap pattern 143, and between the second active pattern AP2 and the gate cap pattern 143.

[0105] In some embodiments, the gate insulating pattern GOX may not be disposed between the first active pattern AP1 and the gate shielding pattern 145, nor between the second active pattern AP2 and the gate shielding pattern 145.

[0106] From a cross-sectional perspective view or cross-sectional view, the gate insulating pattern GOX between the first active pattern AP1 and the first word line WL1 can be connected to the gate insulating pattern GOX between the second active pattern AP2 and the second word line WL2. Alternatively, contrary to the diagram, the gate insulating pattern GOX between the first active pattern AP1 and the first word line WL1 can be separated from the gate insulating pattern GOX between the second active pattern AP2 and the second word line WL2.

[0107] The gate shielding pattern 145 can be disposed between the first word line WL1 and the bit line BL, and between the second word line WL2 and the bit line BL. The gate shielding pattern 145 can be disposed on the first surface WL_S1 of the first word line WL1 and the second word line WL2.

[0108] The gate shielding pattern 145 may include an upper surface 145_S2 and a bottom surface 145_S1 opposite to each other on the third-direction DR3. The bottom surface 145_S1 of the gate shielding pattern 145 may face the bit line BL. The gate shielding pattern 145 may include a sidewall 145_SW connecting the bottom surface 145_S1 and the upper surface 145_S2.

[0109] The first word line WL1 and the second word line WL2 can be disposed on the upper surface 145_S2 of the gate shielding pattern 145. The gate insulating pattern GOX can extend along the upper surface 145_S2 of the gate shielding pattern 145.

[0110] In some embodiments, the gate shielding pattern 145 may contact the first active pattern AP1 and the second active pattern AP2. The sidewall 145_SW of the gate shielding pattern 145 may contact the first active pattern AP1 and the second active pattern AP2. In other words, the first sidewall SS1 of the first active pattern AP1 and the second sidewall SS2 of the second active pattern AP2 may contact the gate shielding pattern 145.

[0111] The first impurity-doped region AP_SDR of the first active pattern AP1 and the second active pattern AP2 may overlap with the gate shielding pattern 145 in the second direction DR2. The first impurity-doped region AP_SDR of the first active pattern AP1 and the second active pattern AP2 may contact the gate shielding pattern 145.

[0112] The gate shielding pattern 145 may include an insulating material doped with a second impurity element. The second impurity element may be an n-type impurity element. The second impurity element may include phosphorus (P), but this disclosure is not limited thereto. The gate shielding pattern 145 may include the doped second impurity element. The gate shielding pattern 145 may include a P-doped insulating material. For example, the gate shielding pattern 145 may include P-doped silicon oxide. In one example, the gate shielding pattern 145 may include phosphosilicate glass (PSG), but this disclosure is not limited thereto.

[0113] During manufacturing, phosphorus (P) doped in the gate shielding pattern 145 can diffuse into the first active pattern AP1 and the second active pattern AP2. As a result, a first impurity-doped region AP_SDR can be formed in the first active pattern AP1 and the second active pattern AP2. When the P doped in the gate shielding pattern 145 diffuses into the first active pattern AP1 and the second active pattern AP2, the resistance between the first active pattern AP1 and the bit line BL, and between the second active pattern AP2 and the bit line BL, can be reduced.

[0114] refer to Figure 5 The gate shielding pattern 145 and the first impurity doped region AP_SDR may include incorporated phosphorus (P). At the boundary between the gate shielding pattern 145 and the first impurity doped region AP_SDR, the concentration of P in the gate shielding pattern 145 ( / cm³) is... 3 The concentration of P in the first impurity doped region AP_SDR is illustrated as being lower than that in the first impurity doped region AP_SDR, but this disclosure is not limited thereto. The concentration of P in the first impurity doped region AP_SDR is illustrated as decreasing away from the gate shielding pattern 145, but this disclosure is not limited thereto.

[0115] In some embodiments, the back gate shielding pattern 115 may not include insulating material doped with n-type impurity elements. For example, the back gate shielding pattern 115 may not include PSG.

[0116] The gate separation pattern GSS can be set on the bit line BL. The gate separation pattern GSS can be set on the gate shield pattern 145.

[0117] A gate separation pattern GSS can be disposed on the second direction DR2 between the first word line WL1 and the second word line WL2. The first word line WL1 and the second word line WL2 can be separated by the gate separation pattern GSS. The gate separation pattern GSS can extend on the first direction DR1 between the first word line WL1 and the second word line WL2.

[0118] The first word line WL1 can be disposed between the gate separator pattern GSS and the first active pattern AP1. The gate separator pattern GSS can be disposed on the first sidewall SS1 of the first active pattern AP1. The second word line WL2 can be disposed between the gate separator pattern GSS and the second active pattern AP2. The gate separator pattern GSS can be disposed on the second sidewall SS2 of the second active pattern AP2.

[0119] The gate-separated pattern (GSS) can be formed of an insulating material. For example, the gate-separated pattern (GSS) may include one of silicon oxide, silicon oxide nitride, or silicon nitride, but this disclosure is not limited thereto. The gate-separated pattern (GSS) is illustrated as a single layer, but this disclosure is not limited thereto. Alternatively, contrary to what is illustrated, the gate-separated pattern (GSS) may include multiple insulating films.

[0120] The contact pattern BC can penetrate or extend into the contact interlayer insulating film 231 and the contact etch stop film 212. The contact pattern BC can be connected to the first active pattern AP1 and the second active pattern AP2, respectively. The contact pattern BC can be connected to the second surface S2 of the first active pattern AP1 and the second active pattern AP2. From a planar perspective, the contact pattern BC can have various shapes, such as circular, elliptical, rectangular, square, rhomboid, or hexagonal.

[0121] The contact pattern BC may include a conductive material. For example, the contact pattern BC may include at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, 2D material, or metal.

[0122] The contact etch stop film 212 can be disposed on the gate separation pattern GSS and the back gate separation pattern 111. The contact interlayer insulating film 231 and the contact etch stop film 212 can be formed of insulating material.

[0123] The landing pad LP can be set on the contact pattern BC. From a planar perspective, the landing pad LP can have various shapes, such as circular, elliptical, rectangular, square, rhomboid, or hexagonal.

[0124] The pad separation insulation pattern 235 can be disposed between the landing pads LP. From a planar perspective, the landing pads LP can be arranged in a matrix along a first direction DR1 and a second direction DR2. The upper surface of the landing pads LP can be substantially coplanar with the upper surface of the pad separation insulation pattern 235, but this disclosure is not limited thereto.

[0125] The landing pad LP may include a conductive material. For example, the landing pad LP may include at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, 2D material, or metal.

[0126] Contrary to what is shown, semiconductor memory devices according to some embodiments may not include landing pads LP.

[0127] The data storage pattern DSP can be separately set on the landing pad LP. The data storage pattern DSP can be electrically connected to the first active pattern AP1 and the second active pattern AP2. For example... Figure 1 As shown, the data storage pattern DSP can be arranged in a matrix along the first direction DR1 and the second direction DR2. The data storage pattern DSP can completely or partially overlap with the landing pad LP on the third direction DR3. The data storage pattern DSP can contact all or part of the upper surface of the landing pad LP.

[0128] For example, the data storage pattern DSP can be a capacitor. The data storage pattern DSP may include a capacitor dielectric film 253 interposed between the storage electrode 251 and the plate electrode 255. For example, the storage electrode 251 may contact the landing pad LP. From a planar perspective, the storage electrode 251 may have various shapes, such as circular, elliptical, rectangular, square, rhomboid, or hexagonal.

[0129] The data storage pattern DSP can contact all or part of the upper surface of the landing pad LP. The storage electrode 251 can penetrate or extend into the upper etch stop film 247. The upper etch stop film 247 can be formed of an insulating material. A portion of the storage electrode 251 is shown recessed into the landing pad LP, but this disclosure is not limited thereto.

[0130] The storage electrode 251 and the plate electrode 255 may include at least one of, for example, a conductive semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, or a metal. The capacitor dielectric film 253 may include at least one of a ferroelectric material, an antiferroelectric material, or a paraelectric material. For example, the capacitor dielectric film 253 may include at least one of a ferroelectric material, an antiferroelectric material, a paraelectric material, a combination of a ferroelectric material and an antiferroelectric material, a combination of a ferroelectric material and a paraelectric material, a combination of an antiferroelectric material and a paraelectric material, or a combination of a ferroelectric material, an antiferroelectric material and a paraelectric material.

[0131] Alternatively, the data storage pattern DSP can be a variable resistance pattern that switches between two resistance states in response to an electrical pulse applied to the memory element. For example, the data storage pattern DSP can include phase change materials, perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials, or antiferromagnetic materials whose crystallization state changes according to the amount of current.

[0132] Figure 6 This is a diagram used to explain semiconductor memory devices according to some embodiments. For convenience, it will be described below. Figure 6 The embodiments are mainly focused on the reference Figures 1 to 5 The differences in explanation. For reference, Figure 6 yes Figure 2 An enlarged sectional view of part P.

[0133] refer to Figure 6 In a semiconductor memory device according to some embodiments, the back gate shielding pattern 115 may contact the first active pattern AP1 and the second active pattern AP2.

[0134] The back gate shielding pattern 115 may include an upper surface 115_S2 and a bottom surface 115_S1 opposite to each other on a third-direction DR3. The bottom surface 115_S1 of the back gate shielding pattern 115 may face the bit line BL. The back gate shielding pattern 115 may include a sidewall 115_SW connecting the bottom surface 115_S1 and the upper surface 115_S2 of the back gate shielding pattern 115.

[0135] The sidewall 115_SW of the back gate shielding pattern 115 can contact the first active pattern AP1 and the second active pattern AP2. In other words, the second sidewall SS2 of the first active pattern AP1 and the first sidewall SS1 of the second active pattern AP2 can contact the back gate shielding pattern 115.

[0136] A back gate insulating pattern 113 may be disposed between the back gate electrode BG and the back gate shielding pattern 115. The back gate insulating pattern 113 may extend along the upper surface 115_S2 of the back gate shielding pattern 115. If the back gate insulating pattern 113 and the back gate shielding pattern 115 are formed of the same insulating material, the boundary between the back gate insulating pattern 113 and the back gate shielding pattern 115 may not be distinguishable.

[0137] Figures 7 to 9 This is a diagram used to explain semiconductor memory devices according to some embodiments. For convenience, it will be described below. Figures 7 to 9 The embodiments are mainly focused on the reference Figures 1 to 6 Differences in the explained embodiments.

[0138] For reference only. Figure 7It is along Figure 1 The sectional view taken by lines AA and BB. Figure 8 yes Figure 7 An enlarged sectional view of part P. Figure 9 It is used for explanation Figure 8 Example diagram of the back gate shielding pattern and the concentration of phosphorus (P) in the first impurity doped region.

[0139] refer to Figures 7 to 9 In a semiconductor memory device according to some embodiments, the back gate shielding pattern 115 may include an insulating material doped with a third impurity element, which is an n-type impurity element.

[0140] The third impurity element may include phosphorus (P), but this disclosure is not limited thereto. The back gate shielding pattern 115 may include a doped third impurity element. The back gate shielding pattern 115 may include a P-doped insulating material. For example, the back gate shielding pattern 115 may include P-doped silicon oxide. In one example, the back gate shielding pattern 115 may include PSG, but this disclosure is not limited thereto.

[0141] The first impurity-doped region AP_SDR of the first active pattern AP1 and the first impurity-doped region AP_SDR of the second active pattern AP2 can overlap with the phosphorus (P)-doped back gate shielding pattern 115 in the second direction DR2. The first impurity-doped region AP_SDR of the first active pattern AP1 and the second active pattern AP2 can contact the back gate shielding pattern 115.

[0142] During the manufacturing process, phosphorus (P) doped in the back gate shielding pattern 115 can diffuse into the first active pattern AP1 and the second active pattern AP2. As a result, the first impurity doped region AP_SDR of the first active pattern AP1 and the second active pattern AP2 can be formed.

[0143] refer to Figure 9 The back gate shielding pattern 115 and the first impurity-doped region AP_SDR may include incorporated phosphorus (P). At the boundary between the back gate shielding pattern 115 and the first impurity-doped region AP_SDR, the concentration of P in the back gate shielding pattern 115 is illustrated as lower than the concentration of P in the first impurity-doped region AP_SDR, but this disclosure is not limited thereto. The concentration of P in the first impurity-doped region AP_SDR is illustrated as decreasing away from the back gate shielding pattern 115, but this disclosure is not limited thereto.

[0144] Figure 10 and Figure 11 These are diagrams used to explain semiconductor memory devices according to some embodiments. For convenience, they will be described below. Figure 10 and Figure 11The embodiments are mainly focused on the reference Figures 1 to 9 The differences in the explained embodiments. For reference, Figure 10 It is along Figure 1 The sectional view taken by lines AA and BB. Figure 11 yes Figure 10 An enlarged sectional view of part P.

[0145] refer to Figure 10 and Figure 11 In some embodiments of a semiconductor memory device, the gate shielding pattern 145 may not include insulating material doped with n-type impurity elements.

[0146] For example, the gate shielding pattern 145 may not include phosphosilicate glass (PSG). The gate shielding pattern 145 may include at least one of silicon oxide, silicon oxide nitride, or silicon nitride, but this disclosure is not limited thereto.

[0147] Figure 12 These are diagrams used to explain semiconductor memory devices according to some embodiments. For convenience, they will be described below. Figure 10 and Figure 11 The embodiments are mainly focused on the reference Figure 10 and Figure 11 The differences in explanation. For reference, Figure 12 yes Figure 10 An enlarged sectional view of part P.

[0148] refer to Figure 12 According to some embodiments, semiconductor memory devices may not include a gate shielding pattern. Figure 10 (of "145").

[0149] The gate separation pattern GSS can be disposed on the first surface WL_S1 of the first word line WL1 and the first surface WL_S1 of the second word line WL2. The gate insulation pattern GOX may not extend along the first surface WL_S1 of the first word line WL1. The gate insulation pattern GOX may not extend along the first surface WL_S1 of the second word line WL2.

[0150] The gate insulating pattern GOX can be disposed between the first active pattern AP1 and the gate separation pattern GSS, and between the second active pattern AP2 and the gate separation pattern GSS.

[0151] Figure 13 and Figure 14 This is a diagram used to explain semiconductor memory devices according to some embodiments. Figure 15 and Figure 16 These are diagrams used to explain semiconductor memory devices according to some embodiments. For convenience, they will be described below. Figures 13 to 16The embodiments are mainly focused on the reference Figures 1 to 5 The differences in the explanations.

[0152] For reference only. Figure 14 yes Figure 13 An enlarged sectional view of part P.

[0153] refer to Figure 13 and Figure 14 According to some embodiments, the semiconductor memory device may also include a connection semiconductor pattern AP_EP.

[0154] The connecting semiconductor pattern AP_EP can be disposed on the first active pattern AP1 and the second active pattern AP2. The connecting semiconductor pattern AP_EP can contact the first active pattern AP1 and the second active pattern AP2. For example, the connecting semiconductor pattern AP_EP can contact the first surface S1 of the first active pattern AP1 and the second active pattern AP2.

[0155] The connecting semiconductor pattern AP_EP can be positioned between the first active pattern AP1 and the bit line BL, and between the second active pattern AP2 and the bit line BL. The bit line BL can cover or overlap the connecting semiconductor pattern AP_EP.

[0156] The interconnect semiconductor pattern AP_EP may include a semiconductor epitaxial pattern. The interconnect semiconductor pattern AP_EP may include, for example, elemental semiconductor materials such as Si or Ge. Alternatively, the interconnect semiconductor pattern AP_EP may include a binary or ternary compound containing at least two elements selected from carbon (C), Si, Ge, and tin (Sn), or a compound obtained by doping a binary or ternary compound with a group IV element.

[0157] Bit line BL is illustrated as including metal pattern 163 without semiconductor pattern 161, but this disclosure is not limited thereto. Contrary to what is shown, bit line BL may include both semiconductor pattern 161 and metal pattern 163.

[0158] refer to Figure 15 and Figure 16 In a semiconductor memory device according to some embodiments, the shielding conductive pattern SL may include multiple shielding conductive line patterns SLp without a shielding conductive plate SLh.

[0159] The shielding conductive pattern SL may not be provided on the bottom surface BL_BS of the bit line BL. For example, the shielding insulating cover film 175 may contact the shielding conductive pattern SLp.

[0160] The shielding insulating cover film 175 may have a linear shape extending along the shielding conductive line pattern SLp in the second direction DR2.

[0161] Alternatively, contrary to the illustration, the shielding insulating cover 175 may have a flat plate shape. In other words, the shielding insulating cover 175 may overlap with the shielding conductive line pattern SLp and bit line BL on the third-direction DR3.

[0162] Figure 17 and Figure 18 This is a diagram used to explain semiconductor memory devices according to some embodiments. Figure 19 and Figure 20 These are diagrams used to explain semiconductor memory devices according to some embodiments. For convenience, they will be described below. Figures 17 to 20 The embodiments are mainly focused on the reference Figures 1 to 5 The differences in the explanations.

[0163] For reference only. Figure 17 and 19 They are along Figure 1 The sectional view taken by lines AA and BB. Figure 18 and Figure 20 They are along Figure 1 A cross-sectional view taken from the CC and DD lines.

[0164] refer to Figures 17 to 20 According to some embodiments, the semiconductor memory device may also include a peripheral gate structure PG disposed between the substrate 100 and the bit line BL.

[0165] A peripheral gate structure PG can be disposed on the substrate 100. For example, the peripheral gate structure PG can be disposed on the upper surface 100US of the substrate 100. The peripheral gate structure PG can be disposed across both the cell array region and the peripheral circuit region of the substrate 100. In other words, a portion of the peripheral gate structure PG can be disposed in the cell array region, and another portion of the peripheral gate structure PG can be disposed in the peripheral circuit region.

[0166] The peripheral gate structure PG can be included in a sensing transistor, a transmission transistor, a driving transistor, etc. For example, a portion of the peripheral gate structure PG included in the sensing transistor can be disposed in the cell array region of the substrate 100, but this disclosure is not limited thereto. The type of transistor in the peripheral circuitry within the cell array region of the substrate 100 may vary depending on the design layout of the semiconductor memory device according to some embodiments.

[0167] The peripheral gate structure PG may include a peripheral gate insulating film 215, a lower peripheral conductive pattern 223, and an upper peripheral conductive pattern 225. The peripheral gate insulating film 215 may include a silicon oxide film, a silicon oxide nitride film, a high-k dielectric film having a dielectric constant higher than that of silicon oxide, or a combination thereof. The high-k dielectric film may include, for example, at least one of a metal oxide, a metal oxide nitride, a metal silicon oxide, or a metal silicon oxide nitride, but this disclosure is not limited thereto.

[0168] The lower peripheral conductive pattern 223 and the upper peripheral conductive pattern 225 may each include a conductive material. For example, the lower peripheral conductive pattern 223 and the upper peripheral conductive pattern 225 may each include at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a 2D material, or a metal. The peripheral gate structure PG is illustrated as including multiple conductive patterns, but this disclosure is not limited thereto.

[0169] Although not shown, the peripheral gate structure PG may also include a peripheral gate mask pattern disposed on the peripheral upper conductive pattern 225. The peripheral gate mask pattern may be formed of an insulating material.

[0170] The first lower peripheral insulating film 227 and the second lower peripheral insulating film 228 can be disposed on the upper surface 100US of the substrate 100. The first lower peripheral insulating film 227 and the second lower peripheral insulating film 228 may include insulating materials.

[0171] Peripheral contact plugs 241a and peripheral wiring lines 241b can be disposed within the first lower peripheral insulating film 227 and the second lower peripheral insulating film 228. Peripheral contact plugs 241a and peripheral wiring lines 241b can be connected to the conductive patterns (223 and 225) of the peripheral gate structure PG. Although not shown, peripheral contact plugs 241a and peripheral wiring lines 241b can be connected to the source / drain regions disposed on at least one side of the peripheral gate structure PG.

[0172] The peripheral contact plug 241a and the peripheral wiring line 241b are illustrated as different layers, but this disclosure is not limited thereto. The boundary between the peripheral contact plug 241a and the peripheral wiring line 241b may be indistinguishable. The peripheral contact plug 241a and the peripheral wiring line 241b may include conductive material.

[0173] The first upper peripheral insulating film 261 and the second upper peripheral insulating film 262 may be disposed on the peripheral contact plug 241a and the peripheral wiring line 241b. The first upper peripheral insulating film 261 and the second upper peripheral insulating film 262 may include insulating material. Alternatively, contrary to the illustration, a single insulating film may be disposed on the peripheral contact plug 241a and the peripheral wiring line 241b.

[0174] The first peripheral connection structures (242a and 242b) can be connected to the peripheral wiring line 241b. The first peripheral connection structures (242a and 242b) may include a first peripheral connection path 242a and a first peripheral connection conductor 242b. The first peripheral connection path 242a and the first peripheral connection conductor 242b may include a conductive material. The first peripheral connection path 242a and the first peripheral connection conductor 242b are illustrated as different layers, but this disclosure is not limited thereto.

[0175] The third and fourth peripheral upper insulating films 263 and 264 may be disposed on the first peripheral connection structures (242a and 242b). The third and fourth peripheral upper insulating films 263 and 264 may include insulating material. Alternatively, contrary to the illustration, a single insulating film may be disposed on the first peripheral connection structures (242a and 242b).

[0176] The second peripheral connection structures (243a and 243b) can be connected to the first peripheral connection wire 242b. The second peripheral connection structures (243a and 243b) may include a second peripheral connection path 243a and a second peripheral connection wire 243b. The second peripheral connection path 243a and the second peripheral connection wire 243b may include a conductive material. The second peripheral connection path 243a and the second peripheral connection wire 243b are illustrated as different layers, but this disclosure is not limited thereto.

[0177] The first peripheral connection structure (242a and 242b) and the second peripheral connection structure (243a and 243b) are illustrated as being disposed on the peripheral gate structure PG, but this disclosure is not limited thereto. Alternatively, contrary to the illustration, a single peripheral connection structure may be disposed only on the peripheral gate structure PG.

[0178] The fifth outer periphery upper insulating film 265 may be disposed on the second outer periphery connection structure (243a and 243b). The fifth outer periphery upper insulating film 265 may include insulating material.

[0179] The lower bonding pad BP1 can be disposed on the peripheral gate structure PG. The lower bonding pad BP1 can be connected to the second peripheral connection structure (243a and 243b).

[0180] For example, at least one of the lower bonding pads BP1 can be connected to the peripheral gate structure PG. At least another of the lower bonding pads BP1 can be connected to the source / drain region disposed on at least one side of the peripheral gate structure PG.

[0181] The lower pad plug 244 can connect to the lower bonding pad BP1 and the second peripheral connecting wire 243b. The lower bonding pad BP1 and the lower pad plug 244 can be disposed within the upper insulating film 265 of the fifth peripheral.

[0182] The lower insulating film 271 of the first unit, the lower insulating film 272 of the second unit, and the lower insulating film 273 of the third unit can be disposed on the upper insulating film 265 of the fifth periphery. The lower insulating film 271 of the first unit, the lower insulating film 272 of the second unit, and the lower insulating film 273 of the third unit can be disposed on the lower bonding pad BP1.

[0183] The lower insulating film 272 of the second unit can be disposed between the lower insulating film 271 of the first unit and the lower insulating film 273 of the third unit. The lower insulating film 273 of the third unit can be disposed between the lower insulating film 272 of the second unit and the upper insulating film 265 of the fifth periphery. The lower insulating film 271 of the first unit, the lower insulating film 272 of the second unit, and the lower insulating film 273 of the third unit can include insulating materials.

[0184] The upper bonding pad BP2 can be set on the lower bonding pad BP1. The upper bonding pad BP2 can be set on the fifth peripheral upper insulating film 265.

[0185] The upper bonding pad BP2 can be connected to the lower bonding pad BP1. The upper bonding pad BP2 can contact the lower bonding pad BP1.

[0186] Unit connection wire 281 can be disposed on the upper bonding pad BP2. Unit connection wire 281 can be disposed between the upper bonding pad BP2 and the bit line BL. Unit connection wire 281 can be disposed between the upper bonding pad BP2 and the shielding conductive pattern SL.

[0187] Although not shown, the unit connection wire 281 may be connected to at least one of the bit line BL or the shielded conductive pattern SL.

[0188] The unit connection trace 281 disposed on a single metal layer is illustrated as being disposed between the upper bonding pad BP2 and the bit line BL, but this disclosure is not limited thereto. Multiple unit connection traces 281 disposed on different metal layers may be disposed between the upper bonding pad BP2 and the bit line BL.

[0189] The upper pad plug 282 can connect the upper bonding pad BP2 and the unit connection wire 281. The upper bonding pad BP2 can be connected to the unit connection wire 281 through the upper pad plug 282.

[0190] The upper bonding pad BP2 and the upper pad plug 282 can be disposed within the lower insulating film 273 of the third unit. The unit connecting wire 281 can be disposed within the lower insulating film 272 of the second unit.

[0191] The upper pad plug 282 and the lower pad plug 244 may include a conductive material, which may include metal. The lower bonding pad BP1 and the upper bonding pad BP2 may each include a conductive material, which may include metal. The unit connection wire 281 may include a conductive material, which may include metal.

[0192] The lower bonding pad BP1 and the upper bonding pad BP2 are each illustrated as a single layer, but this disclosure is not limited thereto. The upper pad plug 282 and the lower pad plug 244 are each shown as a single layer, but this invention is not limited thereto. The unit connection wire 281 is shown as a single layer, but this disclosure is not limited thereto.

[0193] The shielding conductive pattern SL and bit line BL can be disposed on the peripheral gate structure PG. The shielding conductive pattern SL and bit line BL can be disposed on the upper bonding pad BP2. For example, the shielding conductive pattern SL and bit line BL can be disposed on the cell connection wire 281.

[0194] The lower insulating film 271 of the first unit can be disposed between the bit line BL and the unit connecting wire 281, and between the shielding conductive pattern SL and the unit connecting wire 281. The lower insulating film 271 of the first unit can be disposed between the shielding insulating pad 171 and the lower insulating film 272 of the second unit, and between the shielding insulating cover film 175 and the lower insulating film 272 of the second unit.

[0195] The upper insulating film 290 of the cell can be disposed on the data storage pattern DSP. The upper insulating film 290 of the cell may include insulating material.

[0196] exist Figure 17 and Figure 18 In this configuration, the bonding insulating film 267 can be disposed between the lower insulating film 273 of the third unit and the upper insulating film 265 of the fifth periphery. The bonding insulating film 267 can also be disposed between the peripheral gate structure PG and the shielding conductive pattern SL.

[0197] The bonding insulating film 267 can be provided along the extension line of the interface between the lower bonding pad BP1 and the upper bonding pad BP2. The interface between the lower bonding pad BP1 and the upper bonding pad BP2 can correspond to the boundary between the lower bonding pad BP1 and the upper bonding pad BP2.

[0198] exist Figure 19 and Figure 20 middle, Figure 17 and Figure 18 The bonding insulating film 267 may not be set along the extension line of the interface between the lower bonding pad BP1 and the upper bonding pad BP2. The lower insulating film 273 of the third unit may contact the upper insulating film 265 of the fifth periphery.

[0199] At the interface between the lower bonding pad BP1 and the upper bonding pad BP2, the width of the lower bonding pad BP1 can be the same as the width of the upper bonding pad BP2. Alternatively, contrary to the illustration, at the interface between the lower bonding pad BP1 and the upper bonding pad BP2, the width of the lower bonding pad BP1 can be different from the width of the upper bonding pad BP2.

[0200] At the interface between the lower bonding pad BP1 and the upper bonding pad BP2, the lower bonding pad BP1 can be aligned with the upper bonding pad BP2. Alternatively, contrary to the illustration, at the interface between the lower bonding pad BP1 and the upper bonding pad BP2, the lower bonding pad BP1 can be misaligned with the upper bonding pad BP2.

[0201] Figures 21 to 24 These are diagrams used to explain semiconductor memory devices according to some embodiments. For convenience, they will be described below. Figures 21 to 24 The embodiments are mainly focused on the reference Figures 1 to 20 The differences in the explanations.

[0202] refer to Figure 21 The first active pattern AP1 and the second active pattern AP2 can be arranged alternately in an inclined direction relative to the first direction DR1 and the second direction DR2. Here, the inclined direction can be parallel to the upper surface of the substrate 100.

[0203] From a planar perspective, the first active pattern AP1 and the second active pattern AP2 can have parallelogram or rhombus shapes. Since the first active pattern AP1 and the second active pattern AP2 are arranged along an inclined direction, the coupling between the first active pattern AP1 and the second active pattern AP2 facing the first active pattern AP1 on the second direction DR2 can be reduced.

[0204] refer to Figure 22From a planar perspective, the landing pads (LP) and data storage patterns (DSP) can be arranged in a zigzag or honeycomb pattern.

[0205] refer to Figure 23 From a planar perspective, the data storage pattern DSP can be arranged to be misaligned with the landing pad LP.

[0206] The data storage pattern DSP can contact the landing pad LP portion.

[0207] refer to Figure 24 From a planar perspective, the contact pattern BC set on the first active pattern AP1 and the second active pattern AP2 can have a semi-circular or semi-elliptical shape.

[0208] From a planar perspective, the contact pattern BC can be arranged symmetrically across the back gate electrode BG.

[0209] Figures 25 to 55 This diagram illustrates intermediate steps of a method for manufacturing a semiconductor memory device according to some embodiments. The method for manufacturing a semiconductor memory device according to some embodiments can produce the device referenced above. Figure 7 , Figure 8 , Figure 17 and Figure 18 Any of the semiconductor memory devices described.

[0210] refer to Figures 25 to 28 It can provide a sub-substrate structure including a first sub-substrate 200, a buried insulating layer 201 and an active layer 202.

[0211] A buried insulating layer 201 and an active layer 202 may be disposed on the first sub-substrate 200. The first sub-substrate 200, the buried insulating layer 201, and the active layer 202 may form a silicon-on-insulator (SOI) substrate. The first sub-substrate 200 may be a semiconductor substrate. For example, the first sub-substrate 200 may be a Si substrate, a Ge substrate, and / or a SiGe substrate. The first sub-substrate 200 will be described below as a Si substrate.

[0212] The buried insulating layer 201 may be a buried oxide (BOX) formed by an oxygen implantation separation (SIMOX) method or a bonding layer transfer method. Alternatively, the buried insulating layer 201 may be an insulating film formed by chemical vapor deposition (CVD). The buried insulating layer 201 may include, for example, silicon oxide, silicon nitride, silicon nitride, and / or a low-k dielectric film.

[0213] The active layer 202 may be a single-crystal semiconductor film. The active layer 202 may be, for example, a single-crystal Si substrate, a Ge substrate, and / or a SiGe substrate. The active layer 202 may have a first surface and a second surface opposite to each other on a third-direction DR3, and the second surface of the active layer 202 may be in contact with the buried insulating layer 201.

[0214] refer to Figures 28 to 30 A mask pattern MP1 can be formed on the active layer 202.

[0215] The mask pattern MP1 may have a linear opening extending in a first direction DR1. The mask pattern MP1 may include a first lower mask film 11 and a first upper mask film 12 stacked sequentially. The first upper mask film 12 may be formed of a material having etch selectivity relative to the first lower mask film 11. For example, the first lower mask film 11 may include silicon oxide, and the first upper mask film 12 may include silicon nitride. However, this disclosure is not limited to this example.

[0216] Subsequently, using mask pattern MP1 as an etching mask, the active layer 202 can be etched anisotropically. As a result, a back gate trench BG_T extending in the first direction DR1 can be formed in the active layer 202. The back gate trench BG_T can expose the buried insulating layer 201 and can be spaced apart from each other in the second direction DR2.

[0217] Alternatively, contrary to the illustration, at least a portion of the buried insulating layer 201 may be removed during the formation of the back gate trench BG_T.

[0218] refer to Figures 31 to 33 The back gate shielding pattern 115, the back gate insulating pattern 113, and the back gate electrode BG can be formed within the back gate trench BG_T.

[0219] Specifically, a back gate shielding pattern 115 may be formed within a back gate trench BG_T. The back gate shielding pattern 115 may fill a portion of the back gate trench BG_T. The back gate shielding pattern 115 may extend along the back gate trench BG_T in a first direction DR1. For example, the back gate shielding pattern 115 may contact a portion of the active layer 202 exposed by the back gate trench BG_T. For example, the back gate shielding pattern 115 may include an insulating material doped with phosphorus (P). Alternatively, the back gate shielding pattern 115 may include an insulating material that does not contain n-type impurity elements.

[0220] A back gate insulating pattern 113 can be formed along the sidewalls of the back gate trench BG_T, the upper surface of the back gate shielding pattern 115, and the upper surface of the mask pattern MP1. A back gate conductive film can be formed on the back gate insulating pattern 113. The back gate conductive film can fill at least a portion of the back gate trench BG_T. Subsequently, a back gate electrode BG extending in the first direction DR1 can be formed by isotropically etching the back gate conductive film. The back gate electrode BG can fill the remaining portion of the back gate trench BG_T. A thermal processing process can be performed during the formation of the back gate electrode BG. During the thermal processing process, phosphorus (P) contained in the back gate shielding pattern 115 can diffuse into the active layer 202.

[0221] Additionally, according to some embodiments, a gas phase doping (GPD) process or a plasma doping (PLAD) process can be performed prior to the formation of the back gate insulating pattern 113. This allows impurities to be doped into the portion of the active layer 202 exposed by the back gate trench BG_T.

[0222] Alternatively, contrary to the illustration, the back gate shielding pattern 115 may not be formed before the back gate insulating pattern 113 is formed. In this case, the back gate insulating pattern 113 may extend along the sidewalls and bottom surface of the back gate trench BG_T.

[0223] refer to Figures 34 to 36 A back gate separation pattern 111 can be formed on the back gate electrode BG.

[0224] The back gate separation pattern 111 can fill the remaining portion of the back gate trench BG_T. If the back gate separation pattern 111 and the back gate insulating pattern 113 are formed of the same material (e.g., silicon oxide), the back gate insulating pattern 113 on the upper surface of the mask pattern MP1 can be removed during the formation of the back gate separation pattern 111.

[0225] Simultaneously, a GPD process or a PLAD process can be performed before forming the back gate separation pattern 111. This allows impurities to be doped into the active layer 202 through the back gate trench BG_T, in which the back gate electrode BG is formed.

[0226] refer to Figures 37 to 39 After the back gate separation pattern 111 is formed, the first upper mask 12 can be removed.

[0227] The back gate separation pattern 111 may protrude or extend above the upper surface of the first lower mask film 11.

[0228] Subsequently, a spacer film 120 can be formed along the upper surface of the first lower mask film 11, the sidewalls of the back gate insulating pattern 113, and the upper surface of the back gate separation pattern 111. The spacer film 120 can be formed to have a uniform thickness. The width of the active pattern of the VCT can be determined based on the deposition thickness of the spacer film 120.

[0229] The spacer film 120 may be formed of an insulating material. For example, the spacer film 120 may include silicon oxide, silicon oxide nitride, silicon nitride, silicon carbide (SiC), silicon carbonitride (SiCN), or a combination thereof.

[0230] refer to Figures 40 to 42 An anisotropic etching process can be performed on the spacer film 120, and spacer pattern pairs 121 can be formed on the sidewalls of the back gate insulating pattern 113.

[0231] Using spacer pattern 121 as an etching mask, an anisotropic etching process can be performed on active layer 202. This allows the formation of pairs of initial active patterns PAPs that are separated from each other on both sides of back gate insulating pattern 113. As the initial active patterns PAPs are formed, buried insulating layer 201 can be exposed.

[0232] The initial active pattern PAP can extend in a first direction DR1 parallel to the back gate electrode BG. During the formation of the initial active pattern PAP, word line trenches WL_T can be formed in a second direction DR2 between adjacent initial active patterns PAP.

[0233] refer to Figures 40 to 45 A sacrificial film can be formed to fill at least a portion of the word line trench WL_T. A pattern mask can be formed on the sacrificial film. The pattern mask can have a linear shape extending in the second direction DR2. In another example, the pattern mask can have a linear shape extending obliquely relative to the first direction DR1 and the second direction DR2. Using the pattern mask as an etching mask, the sacrificial film can be etched to form sacrificial openings in the sacrificial film.

[0234] By etching the initial active pattern PAP exposed by the sacrificial opening, a first active pattern AP1 and a second active pattern AP2 can be formed on both sides of the back gate electrode BG. On the first sidewall of the back gate electrode BG, the first active pattern AP1 can be formed to be spaced apart from each other in the first direction DR1. On the second sidewall of the back gate electrode BG, the second active pattern AP2 can be formed to be spaced apart from each other in the first direction DR1. When the first active pattern AP1 and the second active pattern AP2 are formed, the sacrificial opening can expose a portion of the back gate insulating pattern 113.

[0235] Subsequently, the sacrificial film, pattern mask, and spacer pattern 121 can be removed. The first lower mask film 11 can remain on the first active pattern AP1 and the second active pattern AP2. The buried insulating layer 201 can be exposed.

[0236] refer to Figures 43 to 47 The gate shielding pattern 145 can be formed within the word line trench WL_T.

[0237] The gate shielding pattern 145 can fill a portion of the word line trench WL_T. The gate shielding pattern 145 can be formed on the buried insulating layer 201. The gate shielding pattern 145 can extend along the word line trench WL_T in the first direction DR1.

[0238] For example, gate shielding pattern 145 may contact the first active pattern AP1 and the second active pattern AP2. In one example, gate shielding pattern 145 may include an insulating material doped with phosphorus (P). In another example, gate shielding pattern 145 may include an insulating material that does not contain n-type impurity elements.

[0239] refer to Figure 48 and Figure 49 The gate insulating pattern GOX can be formed along the sidewall of the first active pattern AP1, the sidewall of the second active pattern AP2, and the upper surface of the back gate separation pattern 111.

[0240] The gate insulating pattern GOX can be formed along the upper surface of the gate shielding pattern 145. The gate insulating pattern GOX can be formed using at least one of physical vapor deposition (PVD), thermal CVD, low-pressure chemical vapor deposition (LP-CVD), plasma-enhanced chemical vapor deposition (PE-CVD), or atomic layer deposition (ALD), but this disclosure is not limited thereto.

[0241] Alternatively, contrary to what is shown, the gate shielding pattern 145 may not be formed before the gate insulating pattern GOX is formed.

[0242] Subsequently, the first word line WL1 and the second word line WL2 can be formed on the gate insulating pattern GOX.

[0243] In one example, a first initial word line film can be formed on a gate insulating pattern GOX. The first initial word line film can fill at least a portion of a word line trench WL_T. First word lines WL1 and second word lines WL2 can be formed by patterning the first initial word line film. In another example, a second initial word line film can be formed along the contour of the gate insulating pattern GOX. The second initial word line film can take the form of a pad. First word lines WL1 and second word lines WL2 can be formed by anisotropically etching the second initial word line film.

[0244] A heat treatment process can be performed during the formation of the first word line WL1 and the second word line WL2. During the heat treatment process, phosphorus (P) contained in the gate shielding pattern 145 can diffuse into the first active pattern AP1 and the second active pattern AP2.

[0245] As phosphorus (P) diffuses from the gate shielding pattern 145 and / or the back gate shielding pattern 115, a first impurity doped region can be formed. Figure 4 , Figure 8 and Figure 11 (in "AP_SDR").

[0246] refer to Figures 48 to 51 The gate separation pattern GSS can be formed on the first word line WL1 and the second word line WL2.

[0247] For example, the upper surface of the gate separation pattern GSS can be on the same plane as the upper surface of the back gate separation pattern 111.

[0248] refer to Figure 52 and Figure 53 Contact holes exposing the first active pattern AP1 and the second active pattern AP2 can be formed within the contact etch stop film 212 and the contact interlayer insulating film 231.

[0249] A contact pattern BC can be formed within a contact hole. The contact pattern BC can be formed on a first active pattern AP1 and a second active pattern AP2. The contact pattern BC can be connected to the first active pattern AP1 and the second active pattern AP2. A data storage pattern DSP can be formed on the contact pattern BC.

[0250] Subsequently, an upper insulating film 290 can be formed on the data storage pattern DSP.

[0251] If a high-temperature thermal processing step is performed after forming the data storage pattern DSP, thermal stress may occur within the data storage pattern DSP. This thermal stress can lead to cracks or other defects within the data storage pattern DSP, resulting in a decrease in the performance and reliability of the semiconductor memory device.

[0252] During the formation of the back gate electrode BG and / or word lines (WL1 and WL2), a first impurity doped region can be formed. Figure 4 , Figure 8 and Figure 11(The term "AP_SDR" is used here.) Since a junction is formed between the active patterns (AP1 and AP2) and the bit line BL through the first impurity doped region AP_SDR, the resistance between the active patterns (AP1 and AP2) and the bit line BL can be reduced. Because the first impurity doped region AP_SDR is formed before forming the data storage pattern DSP, a high-temperature thermal processing process is not required after forming the data storage pattern DSP. In other words, thermal stress that could be caused by a high-temperature thermal processing process is not generated in the data storage pattern DSP. Therefore, the performance and reliability of the semiconductor memory device can be improved.

[0253] refer to Figures 52 to 55 The first sub-substrate 200, which has a back gate electrode BG, word lines WL1 and WL2, active patterns AP1 and AP2, and a data storage pattern DSP, can be bonded to the second sub-substrate 300.

[0254] The back gate electrode (BG), word lines (WL1 and WL2), active patterns (AP1 and AP2), and data storage pattern (DSP) can be disposed between the first sub-substrate 200 and the second sub-substrate 300.

[0255] Although not shown, the first sub-substrate 200 and the second sub-substrate 300 can be joined using a bonding adhesive film.

[0256] In one example, the second sub-substrate 300 may be a semiconductor substrate. In another example, the second sub-substrate 300 may be an insulating substrate including an insulating material.

[0257] Afterwards, after bonding the first sub-substrate 200 and the second sub-substrate 300, a back-side lapping process can be performed to remove the first sub-substrate 200.

[0258] Removing the first sub-substrate 200 may involve sequentially performing a grinding process and a wet etching process to expose the buried insulating layer 201.

[0259] Subsequently, the first active pattern AP1 and the second active pattern AP2 can be exposed by removing the buried insulating layer 201. As the buried insulating layer 201 is exposed, the back gate shield pattern 115 and the gate shield pattern 145 can also be exposed.

[0260] Subsequently, a bit line BL extending in the second direction DR2 can be formed on the first active pattern AP1 and the second active pattern AP2. A shielding conductive pattern SL can be formed on the bit line BL. A shielding insulating cover film 175 can be formed on the shielding conductive pattern SL.

[0261] Subsequently, a first unit lower insulating film 271 can be formed on the shielding insulating cover film 175. A second unit lower insulating film 272 can be formed on the first unit lower insulating film 271. The unit connecting wire 281 can be formed within the second unit lower insulating film 272. A third unit lower insulating film 273 can be formed on the second unit lower insulating film 272. The upper pad plug 282 and the upper bonding pad BP2 can be formed within the third unit lower insulating film 273.

[0262] Subsequently, refer to Figure 7 , Figure 8 , Figure 17 and Figure 18 The substrate 100, which has a peripheral gate structure PG, a first peripheral connection structure (242a and 242b), a second peripheral connection structure (243a and 243b), a lower bonding pad BP1 and a lower bonding pad plug 244, can be bonded to the second sub-substrate 300.

[0263] The second sub-substrate 300 and the substrate 100 can be joined using the bonding adhesive film 267. Alternatively, contrary to the illustration, the second sub-substrate 300 and the substrate 100 can be joined without the bonding adhesive film 267.

[0264] After that, the second sub-substrate 300 can be removed.

[0265] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments without substantially departing from the principles of this disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for limiting purposes.

[0266] Cross-references to related applications

[0267] This application claims priority to Korean Patent Application No. 10-2024-0122381, filed on September 9, 2024, with the Korean Intellectual Property Office.

Claims

1. A semiconductor memory device, comprising: a bit line extending in a first direction on a substrate; a first active pattern and a second active pattern spaced apart from each other on the bit line and in the first direction; at least one conductive gate line extending between the first active pattern and the second active pattern and in a second direction; a gate shield pattern between the at least one conductive gate line and the bit line and including an insulating material doped with phosphorus (P); and a data storage pattern on and electrically connected with the first active pattern and the second active pattern.

2. The semiconductor memory device of claim 1, wherein: the at least one conductive gate line includes a first word line and a second word line, and the first word line and the second word line are spaced apart from each other in the first direction.

3. The semiconductor memory device of claim 2, wherein: the first word line is closer to the first active pattern than the second word line, the first active pattern includes a first sidewall and a second sidewall opposite each other in the first direction, and the conductive gate line is on the first sidewall of the first active pattern and is not disposed on the second sidewall of the first active pattern. the at least one conductive gate line includes a first conductive gate line between the first active pattern and the second active pattern.

4. The semiconductor memory device according to claim 1, wherein, the gate shield pattern includes a phosphosilicate glass (PSG).

5. The semiconductor memory device according to claim 1, wherein, 6. The semiconductor memory device of claim 1, wherein: the first active pattern and the second active pattern include an impurity doped region in contact with the gate shield pattern, and the impurity doped region includes P.

7. The semiconductor memory device of claim 1, further comprising: a connection semiconductor pattern in contact with the first active pattern and between the first active pattern and the bit line.

8. The semiconductor memory device of claim 1, further comprising a gate insulating pattern between the first active pattern and the conductive gate line, wherein: the gate shield pattern includes an upper surface and a bottom surface opposite each other in a third direction perpendicular to the first direction and the second direction, the bottom surface of the gate shield pattern faces the bit line, and the gate insulating pattern extends along the upper surface of the gate shield pattern.

9. The semiconductor memory device of claim 1, further comprising a shield conductive pattern disposed on the substrate, wherein: the shield conductive pattern includes a shield conductive plate and a plurality of shield conductive line patterns extending from the shield conductive plate, each of the plurality of shield conductive line patterns extends in the first direction, the bit line is between a first shield conductive line pattern and a second shield conductive line pattern of the plurality of shield conductive line patterns, and the first shield conductive line pattern and the second shield conductive line pattern are adjacent in the second direction.

10. The semiconductor memory device of claim 1, further comprising a shield conductive pattern disposed adjacent to the bit line in the second direction and extending in the first direction, wherein: ​ the bit line includes an upper surface and a bottom surface opposite to each other in a third direction perpendicular to the first direction and the second direction, the upper surface of the bit line faces the first active pattern and the second active pattern, and the shield conductive pattern is not disposed on the bottom surface of the bit line.

11. A semiconductor memory device, comprising: a bit line extending in a first direction on a substrate; an active pattern disposed on the bit line, the active pattern including first and second sidewalls opposite to each other in the first direction, the active pattern including first and second surfaces opposite to each other in a vertical direction perpendicular to the substrate, wherein the first surface of the active pattern is electrically connected to the bit line; a word line extending on the first sidewall of the active pattern and in a second direction; a back gate electrode extending on the second sidewall of the active pattern and in the second direction; a first gate shield pattern between the word line and the bit line; a second gate shield pattern between the back gate electrode and the bit line; and a data storage pattern on the active pattern and electrically connected to the second surface of the active pattern, wherein at least one of the first gate shield pattern and the second gate shield pattern includes a phosphosilicate glass (PSG).

12. The semiconductor memory device of claim 11, wherein each of the first gate shield pattern and the second gate shield pattern includes the PSG.

13. The semiconductor memory device of claim 11, wherein: the first gate shield pattern includes the PSG, and the second gate shield pattern does not include the PSG.

14. The semiconductor memory device of claim 11, wherein: the second gate shield pattern includes the PSG, and the first gate shield pattern does not include the PSG.

15. The semiconductor memory device of claim 11, further comprising: a connection semiconductor pattern contacting the first surface of the active pattern and between the active pattern and the bit line.

16. The semiconductor memory device of claim 11, further comprising a shield conductive pattern on the substrate, wherein: the shield conductive pattern includes a shield conductive plate and a plurality of shield conductive line patterns extending from the shield conductive plate, each of the plurality of shield conductive line patterns extends in the first direction, and the bit line is between a first shield conductive line pattern and a second shield conductive line pattern of the plurality of shield conductive line patterns in the second direction.

17. A semiconductor memory device, comprising: a peripheral gate structure on a substrate; a first bonding pad on the peripheral gate structure; a second bonding pad on and in contact with the first bonding pad; a bit line on the second bonding pad and extending in a first direction; a shield conductive pattern on the second bonding pad, adjacent to the bit line, extending in the first direction, and including a plurality of shield conductive line patterns. ​ a first word line over the bit line and the shield conductive pattern and extending in a second direction; a second word line over the bit line and the shield conductive pattern, extending in the second direction, and spaced apart from the first word line in the first direction; a back gate electrode between the first word line and the second word line and extending in the second direction; a first active pattern over the bit line and between the first word line and the back gate electrode; a second active pattern over the bit line and between the second word line and the back gate electrode; a first gate shield pattern between the first word line and the bit line, between the second word line and the bit line, and comprising an insulating material doped with phosphorus (P); and a data storage pattern electrically connected to the first active pattern and the second active pattern.

18. The semiconductor memory device of claim 17, further comprising: a second gate shield pattern between the back gate electrode and the bit line and comprising an insulating material doped with P. The first gate shield pattern comprises a phosphosilicate glass (PSG).

19. The semiconductor memory device of claim 17, wherein, 20. The semiconductor memory device of claim 17, wherein: the shield conductive pattern further comprises a shield conductive plate, the shield conductive line pattern extends from the shield conductive plate in a third direction perpendicular to the first direction and the second direction, and the bit line is over the shield conductive plate. ​

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