Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. The semiconductor device may include: a stack including electrode plates and insulating layers alternately stacked; an electrode post extending through the stack; the variable resistance layer surrounds the side wall of the electrode column; and first electrodes respectively located between the electrode plates and the variable resistance layer, each first electrode containing a metal oxide.

Description

Cross Reference to Related Applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0120273, filed September 4, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to electronic devices, and more particularly, to semiconductor devices and methods of manufacturing semiconductor devices. BACKGROUND

[0003] In recent years, with the development of trends such as miniaturization, low power consumption, performance improvement, and diversification of electronic devices, various electronic devices such as computers, portable communication devices, etc. require semiconductor devices capable of storing information. Accordingly, semiconductor devices capable of storing data using a characteristic of switching between different resistance states according to an applied voltage or current are being researched. Examples of such semiconductor devices include resistive random access memory (RRAM), phase change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), etc. SUMMARY

[0004] In one embodiment, a semiconductor device can include a stack including alternating electrode plates and insulating layers, an electrode pillar extending through the stack, a variable resistance layer provided over sidewalls of the electrode pillar and extending through the electrode plates and the insulating layers, and first electrodes between the electrode plates and the variable resistance layer, each first electrode including a metal oxide.

[0005] In one embodiment, a semiconductor device can include a stack including alternating electrode plates and insulating layers, an electrode pillar extending through the stack, a plurality of memory cells stacked along the electrode pillar, a variable resistance layer provided over the sidewalls of the electrode pillar and shared by the memory cells, and a first electrode provided over the variable resistance layer and shared by the memory cells, wherein the first electrode includes a metal oxide.

[0006] In one embodiment, a method of manufacturing a semiconductor device can include forming a stack including alternating electrode plates and insulating layers, forming a first opening extending through the stack to expose the electrode plates, forming first electrodes on or over the exposed electrode plates, each first electrode including a metal oxide, forming a variable resistance layer in the first opening, and forming an electrode pillar in the variable resistance layer.

[0007] In one embodiment, a method of manufacturing a semiconductor device may include: forming a stack comprising alternating stacked sacrificial layers and insulating layers; forming a first opening extending through the stack; forming a first electrode in the first opening, the first electrode comprising a metal oxide; forming a variable resistance layer along a surface of the first electrode; forming an electrode post along a surface of the variable resistance layer; and replacing the sacrificial layer with an electrode plate. Attached Figure Description

[0008] FIG. 1A and FIG. 1B It is a diagram used to describe the structure and operation of a semiconductor device according to one embodiment.

[0009] FIGS. 2A-2C This is a diagram used to describe the structure of a semiconductor device according to one embodiment.

[0010] FIG. 3A and FIG. 3B This is a diagram used to describe the structure of a semiconductor device according to one embodiment.

[0011] FIG. 4 It is a diagram used to describe the structure of a semiconductor device according to one embodiment.

[0012] FIGS. 5A-5G This is a diagram used to describe a method of manufacturing a semiconductor device according to one embodiment.

[0013] FIGS. 6A-6C This is a diagram used to describe a method of manufacturing a semiconductor device according to one embodiment.

[0014] FIGS. 7A-7G This is a diagram used to describe a method of manufacturing a semiconductor device according to one embodiment. Detailed Implementation

[0015] Various embodiments relate to semiconductor devices having stable structures and improved properties, as well as methods for manufacturing such semiconductor devices.

[0016] It can improve the integration, operating characteristics and reliability of semiconductor devices.

[0017] Embodiments in accordance with the technical spirit of this disclosure will now be described with reference to the accompanying drawings.

[0018] FIG. 1A and FIG. 1B It is a diagram used to describe the structure and operation of a semiconductor device according to one embodiment.

[0019] refer to FIG. 1A The semiconductor device may include a memory cell MC. The memory cell MC may include a first electrode 13, a variable resistance layer 14, and a second electrode 15. The semiconductor device may also include an electrode plate 11 and an insulating layer 12.

[0020] The electrode plate 11 can be located between the insulating layers 12. The electrode plate 11 can be an access line, a row line, or a column line. The electrode plate 11 can include a metal, such as tungsten.

[0021] The first electrode 13 can be located between the insulating layers 12. The first electrode 13 can be located on or above the electrode plate 11 and electrically connected with the electrode plate 11. The first electrode 13 and the electrode plate 11 can have substantially the same width W. The first electrode 13 can include a metal oxide. The metal oxide can be a switching material whose resistance is changed by formation and dissolution of a conductive filament. For example, the metal oxide can include one or more of tungsten oxide, titanium oxide, or hafnium oxide.

[0022] The variable resistance layer 14 can be located on or above the first electrode 13. The variable resistance layer 14 can extend to an upper surface of the insulating layer 12. The variable resistance layer 14 can have a characteristic of reversibly switching between different resistance states according to a voltage or a current applied to the memory cell MC. For example, when the variable resistance layer 14 is in a low resistance state, data "1" can be stored, and when the variable resistance layer 14 is in a high resistance state, data "0" can be stored.

[0023] For example, the variable resistance layer 14 can include a resistive material. An electrical path (or a conductive path) is formed or dissolved in the variable resistance layer 14 to control a resistance state thereof, so that data "1" or "0" can be stored. For example, the variable resistance layer 14 can include a transition metal oxide, or include a metal oxide such as a perovskite-based material.

[0024] For example, the variable resistance layer 14 can have a magnetic tunnel junction (MTJ) structure including a magnetization fixed layer, a tunnel barrier layer, and a magnetization free layer. Data can be stored according to a change in a magnetization direction of the magnetization free layer with respect to a magnetization direction of the magnetization fixed layer. For example, the magnetization fixed layer and the magnetization free layer can each include a magnetic material, and the tunnel barrier layer can include a metal oxide.

[0025] For example, the variable resistance layer 14 can include a phase change material or include a chalcogenide-based material. The variable resistance layer 14 can change a phase state thereof according to a programming operation. For example, the variable resistance layer 14 can have a low resistance crystalline state by a set operation. For example, the variable resistance layer 14 can have a high resistance amorphous state by a reset operation. Accordingly, data can be stored in the memory cell using a resistance difference depending on the phase state of the variable resistance layer 14.

[0026] For example, the variable resistance layer 14 can include a variable resistance material that changes resistance without accompanying phase change, or include a chalcogenide-based material. The variable resistance layer 14 can maintain its phase state after a programming operation. For example, the variable resistance layer 14 can have an amorphous state, and can maintain the amorphous state after a programming operation without transitioning to a crystalline state. The threshold voltage of the memory cell can vary according to a programming voltage applied to the memory cell, and the memory cell can be programmed to at least two states. For example, the memory cell can be programmed to a set state or a reset state using programming voltages having different polarities. Thus, data can be stored in the memory cell using a threshold voltage difference of the memory cell.

[0027] The second electrode 15 can be located on or above the variable resistance layer 14. The second electrode 15 can extend along a surface of the variable resistance layer 14. The second electrode 15 can include polysilicon, tungsten (W), tungsten nitride (WNx), tungsten silicide (WSix), titanium (Ti), titanium nitride (TiNx), titanium silicon nitride (TiSiN), aluminum titanium nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbon nitride (SiCN), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), platinum (Pt), molybdenum (Mo), ruthenium (Ru), etc., or a combination including the same.

[0028] Reference FIG. 1B The first electrode 13 can include conductive filaments F. During the manufacturing process of the semiconductor device, the first electrode 13 can be activated by a sintering operation, and the filaments F can be formed in the first electrode 13. The filaments F can provide an electrical path between the electrode plate 11 and the variable resistance layer 14. Thus, an electric field can be concentrated on the filaments F in the first electrode 13, thereby reducing the effective area of the first electrode 13.

[0029] The variable resistance layer 14 can include a first portion 14A and a second portion 14B. The first portion 14A is a region in which resistance change occurs when the memory cell MC is in operation, and can serve as an active region. The first portion 14A can have an area corresponding to the first electrode 13. The second portion 14B is a region in which substantially no resistance change occurs, and can serve as an inactive region. Since the filaments F reduce the effective area of the first electrode 13, the effective area of the variable resistance layer 14 can also be reduced.

[0030] According to the above-described structure, the first electrode 13 is located between the variable resistance layer 14 and the electrode plate 11. Thus, diffusion of the material of the electrode plate 11 into the variable resistance layer 14 can be reduced or prevented. In addition, the first electrode 13 can include a metal oxide, and the filaments F formed in the first electrode 13 can reduce the active area of the memory cell MC.

[0031] FIGS. 2A-2CFIG. 1 is a diagram for describing a structure of a semiconductor device according to an embodiment. Hereinafter, description overlapping with the foregoing will be omitted.

[0032] Referring to FIG. 2A , the semiconductor device can include a stack STA, first electrodes 23, a variable resistance layer 24, second electrodes 25, and an electrode pillar 26.

[0033] The stack STA can include electrode plates 21 and insulating layers 22 alternately stacked. The electrode plates 21 can be row lines or column lines, and each electrode plate 21 can include a metal, such as tungsten. The insulating layers 22 serve to insulate the stacked electrode plates 21 from each other, and each insulating layer can include an insulating material, such as an oxide, a nitride, or an air gap.

[0034] The electrode pillar 26 can extend through the stack STA. For example, the electrode pillar 26 can penetrate the stack STA in a stacking direction, and the stacking direction can be a vertical direction. The electrode pillar 26 can be electrically connected to a column line or a row line. For example, the electrode plates 21 can be row lines, and the electrode pillar 26 can be electrically connected to column lines. The electrode pillar 26 can include a conductive material, such as polysilicon or a metal.

[0035] The variable resistance layer 24 can surround sidewalls of the electrode pillar 26. The variable resistance layer 24 can extend along a surface of the electrode pillar 26. In an embodiment, the variable resistance layer 24 extends through the electrode plates 21 and the insulating layers 22. In an embodiment, the variable resistance layer 24 extends through a plurality of memory cells MC and is shared by the memory cells. The variable resistance layer 24 can include first portions 24P1 between the electrode plates 21 and the electrode pillar 26 and second portions 24P2 between the insulating layers 22 and the electrode pillar 26. The first portions 24P1 and the second portions 24P2 can be alternately arranged. The first portions 24P1 can be active regions in which resistance varies, and the second portions 24P2 can be passive regions in which resistance is substantially constant.

[0036] The first electrodes 23 can be respectively between the electrode plates 21 and the variable resistance layer 24. The first electrodes 23 can be between the stacked insulating layers 22 and separated from each other by the insulating layers 22. Each first electrode 23 can have substantially the same width W as the electrode plates 21.

[0037] The second electrodes 25 can be between the electrode pillar 26 and the variable resistance layer 24. The second electrodes 25 can surround sidewalls of the electrode pillar 26. The second electrodes 25 can include a material different from that of the first electrodes 23. For example, the material of the second electrodes 25 can include carbon.

[0038] Referring to FIG. 2B , the semiconductor device can include a stack STA, first electrodes 23A, a variable resistance layer 24A, second electrodes 25A, and an electrode pillar 26A.

[0039] Compared to the insulating layer 22, the first electrode 23A may protrude towards the electrode post 26A. The surface of the first electrode 23A that contacts (or approaches) the variable resistance layer 24A may include a curved surface. The variable resistance layer 24A may extend along the surface of the insulating layer 22 and the surface of the first electrode 23A, and may have an irregularly shaped cross-section. The second electrode 25A may extend along the surface of the variable resistance layer 24A, and may have an irregularly shaped cross-section.

[0040] Electrode post 26A may extend through the stacked STA and may penetrate the stacked STA in a vertical direction. A second electrode 25A may surround the sidewall of electrode post 26A. Electrode post 26A may include a through portion 26AA and at least one protruding portion 26AB. The through portion 26AA may extend through the stacked STA and may penetrate the stacked STA in a vertical direction. The protruding portion 26AB may protrude from the sidewall of the through portion 26AA toward insulating layer 22. The protruding portion 26AB may be located at a layer corresponding to the insulating layer.

[0041] refer to FIG. 2C The semiconductor device may include a stacked STA, a first electrode 23A, a variable resistance layer 24A, a second electrode 25A, and an electrode post 26B. The semiconductor device may also include at least one gap V. The gap V may be located between the electrode post 26B and the second electrode 25A. The gap V may be located at a level corresponding to the insulating layer 22.

[0042] According to the above structure, the memory cells MC can be located in the regions where the electrode plate 21 intersects with the electrode posts 26, 26A, or 26B. The memory cells MC can be resistive memory cells and can be stacked along the electrode posts 26, 26A, or 26B. Each memory cell MC may include a first electrode 23, a variable resistance layer 24 or 24A, and a second electrode 25 or 25A.

[0043] Memory cells MC adjacent to each other in the stacking direction may share a variable resistance layer 24 or 24A. Each memory cell MC adjacent to each other in the stacking direction may include a first electrode 23, and the first electrodes 23 may be separated from each other. Alternatively, memory cells MC adjacent to each other in the stacking direction may not share a first electrode 23. Even if memory cells MC share a variable resistance layer 24 or 24A, the active and passive regions are still defined within the variable resistance layer 24 or 24A by the separated first electrodes 23. Since passive regions exist between the active regions, element movement between the active regions can be reduced. For example, selenium (Se) movement between stacked memory cells MC can be reduced. Therefore, the phenomenon of threshold voltage fluctuations in memory cells MC caused by element movement within the variable resistance layer 24 or 24A can be improved.

[0044] FIG. 3A and FIG. 3B It is a diagram used to describe the structure of a semiconductor device according to one embodiment.

[0045] refer to FIG. 3A The semiconductor device may include a memory cell MC. The memory cell MC may include a first electrode 33, a variable resistance layer 34, and a second electrode 35. The semiconductor device may also include an electrode plate 31 and an insulating layer 32.

[0046] Electrode plates 31 may be located between insulating layers 32. A first electrode 33 may be located on or above electrode plates 31 and extend to the upper surface of insulating layers 32. The first electrode 33 may comprise a metal oxide. The metal oxide may be a switching material whose resistance is changed by the formation and dissolution of conductive filaments. For example, the metal oxide may comprise one or more of the following: tungsten oxide, titanium oxide, and hafnium oxide.

[0047] The variable resistance layer 34 may be located on the first electrode 33. The variable resistance layer 34 may extend along the surface of the first electrode 33. The second electrode 35 may be located on or above the variable resistance layer 34. The second electrode 35 may extend along the surface of the variable resistance layer 34.

[0048] refer to FIG. 3B The first electrode 33 may include a first portion 33A and a second portion 33B. The first portion 33A may be a portion overlapping the electrode plate 31 and may include conductive filaments F. The second portion 33B may be a portion not overlapping the electrode plate 31 and may not include conductive filaments F. The filaments F may be formed by a sintering operation in a semiconductor device manufacturing process. The filaments F may provide an electrical path between the electrode plate 31 and the variable resistance layer 34. The resistivity of the first portion 33A where the filaments F are formed may be lower than that of the second portion 33B where the filaments F are not formed. Therefore, the first portion 33A of the first electrode 33 where the filaments F are formed can be used as a physical electrode, and the electric field can be concentrated on the filaments F, thereby reducing the effective area of ​​the first electrode 33.

[0049] The variable resistance layer 34 includes a first portion 34A and a second portion 34B. The first portion 34A is the region where the resistance changes when the memory cell MC is working, and can be an active region. The first portion 34A may have an area corresponding to the first portion 33A of the first electrode 33. The second portion 34B may be a region where the resistance does not change, and can be a passive region. Because the effective area of ​​the first electrode 33 is reduced due to the filament F, the effective area of ​​the variable resistance layer 34 can also be reduced.

[0050] According to the above structure, the first electrode 33 may contain a metal oxide, and the filament F may be formed in a portion of the first electrode 33. Therefore, the working area of ​​the memory cell MC can be reduced.

[0051] FIG. 4This is a diagram illustrating the structure of a semiconductor device according to one embodiment. Content repeated in the following description will be omitted.

[0052] refer to FIG. 4 The semiconductor device may include a stacked ST, a first electrode 43, a variable resistance layer 44, a second electrode 45, and an electrode post 46.

[0053] The stacked ST may include alternating stacked electrode plates 41 and insulating layers 42. Electrode posts 46 may extend through the stacked ST. For example, the electrode plates 41 may be row lines, while the electrode posts 46 may be electrically connected to column lines.

[0054] A variable resistance layer 44 may be provided on the sidewall of the electrode post 46. The variable resistance layer 44 may surround the sidewall of the electrode post 46. The variable resistance layer 44 may extend along the surface of the electrode post 46. The variable resistance layer 44 may include a first portion 44A located between the electrode plate 41 and the electrode post 46, and a second portion 44B located between the insulating layer 42 and the electrode post 46. The first portion 44A and the second portion 44B may be arranged alternately. The first portion 44A may be an active region with varying resistance, while the second portion 44B may be a passive region with constant resistance.

[0055] A first electrode 43 may be provided on the variable resistive layer 44. The first electrode 43 may surround the variable resistive layer 44 and may extend along the outer wall of the variable resistive layer 44. The first electrode 43 may include a first portion 43A located between the variable resistive layer 44 and the electrode plate 41, and a second portion 43B located between the variable resistive layer 44 and the insulating layer 42. The first portion 43A and the second portion 43B may be arranged alternately. The position of the first portion 43A may correspond to the position of the first portion 44A, and the position of the second portion 43B may correspond to the position of the second portion 44B. The first portion 43A may be an active region containing filaments, and the second portion 43B may be a passive region without filaments. The resistivity of the first portion 43A may be lower than that of the second portion 43B.

[0056] The second electrode 45 may be located between the electrode post 46 and the variable resistance layer 44. The second electrode 45 may surround the sidewall of the electrode post 46. The second electrode 45 may contain carbon.

[0057] According to the above structure, the memory cells MC can be located in the regions where the electrode plate 41 and the electrode post 46 intersect each other. The memory cells MC can be stacked along the electrode post 46, and the electrode post 46 can extend through the memory cells MC. Each memory cell MC may include a first electrode 43, a variable resistance layer 44, and a second electrode 45.

[0058] Adjacent memory cells MC in the stacking direction can share the variable resistance layer 44 and the first electrode 43. Even though the memory cells MC share the variable resistance layer 44, the active and passive regions are still defined within the variable resistance layer 44. Since there are passive regions between the active regions, element movement between the active regions can be reduced. For example, selenium (Se) movement between stacked memory cells MC can be reduced. Therefore, the phenomenon of threshold voltage fluctuation of memory cells MC due to element movement within the variable resistance layer 44 can be improved.

[0059] Even though the memory cells MC share the first electrode 43, the active and passive regions are still confined within the first electrode 43. Since the active region forming the filament essentially acts as an electrode, and the electric field is concentrated on the filament, the effective area of ​​the first electrode 43 can be reduced.

[0060] FIGS. 5A-5G This is a diagram illustrating a method of manufacturing a semiconductor device according to one embodiment. Content repeated below will be omitted.

[0061] refer to FIG. 5A A stacked ST can be formed, comprising alternating stacked first sacrificial layers 51 and insulating layers 52. Each first sacrificial layer 51 may contain a material with high etch selectivity relative to the insulating layer 52. The first sacrificial layer 51 is used to ensure space for the electrode plate to be formed and may contain a sacrificial material such as a nitride. The insulating layer 52 may contain an insulating material such as an oxide.

[0062] Subsequently, a first opening OP1 extending through the stack ST can be formed. The first opening OP1 can extend through the stack ST in the stack direction. Subsequently, a second sacrificial layer 53 can be formed in the first opening OP1. The second sacrificial layer 53 extends through the first sacrificial layer 51 and the insulating layer 52. The second sacrificial layer 53 can extend through the first sacrificial layer 51 and the insulating layer 52 in the stack direction. The second sacrificial layer 53 may contain a material that has etch selectivity relative to the first sacrificial layer 51 and the insulating layer 52.

[0063] refer to FIG. 5B The second opening OP2 can be formed by removing the first sacrificial layer 51. For example, a slit SL can be formed through the stack ST, and the first sacrificial layer 51 can be selectively etched through the slit SL. This defines the second opening OP2 between the stacked insulating layers 52, and exposes the second sacrificial layer 53 through the second opening OP2. The remaining insulating layers 52 can be supported by the second sacrificial layer 53.

[0064] refer to FIG. 5C Electrode plates 54 can be formed in the second opening OP2. For example, electrode plates 54 can be formed by filling the second opening OP2 with metal (e.g., tungsten). Thus, a stacked STA including alternately stacked electrode plates 54 and insulating layer 52 can be formed.

[0065] refer to FIG. 5D The first opening OP1 can be formed by removing the second sacrificial layer 53. That is, the first opening OP1 can be reopened. Subsequently, the first electrode 55 can be formed by oxidizing the surface of the electrode plate 54 exposed by the first opening OP1. The surface of the electrode plate 54 can be selectively oxidized, and the first electrode 55 is formed in a self-aligned manner. The width W of each first electrode 55 can have a width W that is substantially the same as that of the electrode plate 54.

[0066] Depending on the oxidation conditions, the first electrode 55 may protrude into the first opening OP1, or the sidewall of the first electrode 55 may be aligned with the sidewall of the insulating layer 52.

[0067] The first electrode 55 may be formed by an oxide metal layer, and each first electrode 55 may contain a metal oxide. The resistivity of the first electrode 55 may be determined according to the degree of oxidation of the metal layer. The metal oxide may be a resistive switching material. For example, the metal oxide may include one or more of the following: tungsten oxide, titanium oxide, and hafnium oxide.

[0068] refer to FIG. 5E A variable resistance material layer 56 can be formed in the first opening OP1. The variable resistance material layer 56 can be formed along the inner wall of the first opening OP1 and can extend along the upper surface of the stacked STA. The variable resistance material layer 56 can contact the first electrode 55. Subsequently, a second electrode layer 57 can be formed along the surface of the variable resistance material layer 56. The second electrode layer 57 can contact the variable resistance material layer 56.

[0069] refer to FIG. 5F The second electrode 57A and the variable resistance layer 56A can be formed by etching the second electrode layer 57 and the variable resistance material layer 56. For example, portions of the second electrode layer 57 and the variable resistance material layer 56 formed on the upper surface of the stacked STA can be etched by performing an etch-back process. Thus, the variable resistance layer 56A and the second electrode 57A can be formed on the inner wall of the first opening OP1. The second electrode 57A may contain carbon.

[0070] refer to FIG. 5G Electrode posts 58 can be formed in the first opening OP1. For example, a conductive layer can be formed to fill the first opening OP1. The conductive layer can also be formed on the upper surface of the stacked STA and may contain a metal (e.g., tungsten). Subsequently, the electrode posts 58 can be formed by planarizing the conductive layer until the upper surface of the stacked STA is exposed. The planarization process can employ a chemical mechanical polishing (CMP) process.

[0071] For reference, the process of planarizing the conductive layer can also be combined with the etching process described above. For example, the reference can be omitted. FIG. 5FThe etching process described. In this case, a conductive layer may be formed on the second electrode layer 57. Subsequently, the electrode pillar 58, the second electrode 57A, and the variable resistance layer 56A may be formed by etching the conductive layer, the second electrode layer 57, and the variable resistance material layer 56 until the surface of the stacked STA is exposed.

[0072] Therefore, memory cells MC can be formed in the regions where the electrode plate 54 and the electrode post 58 intersect. Each memory cell MC may include a first electrode 55 and may share a variable resistance layer 56A.

[0073] Subsequently, the first electrode 55 can be activated. For example, the first electrode 55 can be activated by performing an ignition operation to apply strong electrical stimulation to the memory cell MC. During the ignition operation, an ignition current with a large current quantity can be applied to the memory cell MC. The ignition current can cause the relatively thin first electrode 55 to break down or be damaged, and a filament can be formed in the first electrode 55. Regardless of whether the memory cell MC is in a set operation or a reset operation, the filament formed by the ignition operation can remain in the first electrode 55.

[0074] According to the manufacturing method described above, the first electrode 55 can be formed by selectively oxidizing the surface of the electrode plate 54 through the first opening OP1. Thus, the first electrodes 55, separated from each other, can be formed in a self-aligning manner.

[0075] FIGS. 6A-6C This is a diagram illustrating a method of manufacturing a semiconductor device according to one embodiment. Content repeated below will be omitted.

[0076] refer to FIG. 6A A stacked STA can be formed, comprising alternately stacked electrode plates 61 and an insulating layer 62. The stacked STA may include an opening OP, and the opening OP may extend through the stacked STA. A method for forming a stacked STA including an opening OP is similar to that described above. FIGS. 5A-5C The described embodiments are similar.

[0077] Subsequently, a first electrode 63 can be formed by oxidizing the surface of the electrode plate 61 exposed by the opening OP. During the oxidation process, the first electrode 63 may expand and protrude into the opening OP. The sidewalls of the first electrode 63 may be closer to the center of the opening OP than the sidewalls of the insulating layer 62. The inner wall of the opening OP may be irregular.

[0078] refer to FIG. 6BA variable resistance layer 64 can be formed in the opening OP. For example, the variable resistance layer 64 can be formed by a deposition method with good step coverage, and can be deposited by atomic layer deposition (ALD). The variable resistance layer 64 can be formed along the contour of the protruding first electrode 63, and due to the irregular shape of the protruding first electrode 63, it can be transferred onto the variable resistance layer 64. Therefore, the surface of the variable resistance layer 64 can be irregular.

[0079] Subsequently, a second electrode 65 can be formed along the surface of the variable resistance layer 64. The second electrode 65 can be formed by a deposition method with good step coverage, and can be deposited by atomic layer deposition (ALD). The second electrode 65 can be formed along the contour of the variable resistance layer 64, and the irregular shape of the variable resistance layer 64 can be transferred to the second electrode 65. Therefore, the surface of the second electrode 65 can be irregular.

[0080] refer to FIG. 6C Electrode pillars 66 can be formed within the opening OP. The electrode pillars 66 can be formed to fill the opening OP. For example, conductive material can be deposited along the contour of the second electrode 65 using a deposition method with relatively good step coverage. For example, conductive material can be deposited using a chemical vapor deposition (CVD) method to fill irregular portions of the second electrode 65. In this case, electrode pillars 66 including through portions and protrusions can be formed. Alternatively, conductive material can be deposited using a deposition method with relatively poor step coverage. For example, conductive material can be deposited using a physical vapor deposition (PVD) method, and it may not be possible to completely fill the irregular portions. In this case, a void V can be formed between the second electrode 65 and the electrode pillar 66. The void can be located at a layer corresponding to the insulating layer 62.

[0081] Subsequently, a sintering operation can be performed. A filament can be formed in the first electrode 63 through the sintering operation. For example, the filament can be formed in a metal oxide layer. The formed filament can be maintained regardless of the operation of the memory cell MC.

[0082] According to the manufacturing method described above, the first electrode 63 can be formed by selectively oxidizing the surface of the electrode plate 61 through the opening OP. Therefore, the first electrodes 63, which are separated from each other, can be formed in a self-aligning manner.

[0083] FIGS. 7A-7G This is a diagram illustrating a method of manufacturing a semiconductor device according to one embodiment. Content repeated below will be omitted.

[0084] refer to FIG. 7AA stacked ST comprising alternating sacrificial layers 71 and insulating layers 72 can be formed. Each sacrificial layer 71 may contain a material with high etch selectivity relative to the insulating layer 72. The sacrificial layers 71 are used to ensure space for forming the electrode plate, and each sacrificial layer may contain a sacrificial material such as a nitride. Each insulating layer 72 may contain an insulating material such as an oxide.

[0085] Subsequently, a first opening OP1 extending through the stack ST can be formed. The first opening OP1 can penetrate the stack ST in the stacking direction. Subsequently, a seed layer 73 can be formed in the first opening OP1. The seed layer 73 can be formed along the inner wall of the first opening OP1 and can extend along the upper surface of the stack ST. The seed layer 73 is used to form the first electrode and can contain a metal such as tungsten, titanium, or hafnium.

[0086] refer to FIG. 7B A first electrode layer 73A can be formed by oxidizing a seed layer 73. The first electrode layer 73A can be formed along the inner wall of the first opening OP1 and can extend along the upper surface of the stack ST. The first electrode layer 73A may contain a metal oxide and may be a resistive switching material. For example, the metal oxide may include one or more of the following: tungsten oxide, titanium oxide, or hafnium oxide.

[0087] For reference, the first electrode layer 73A can also be deposited directly without forming a seed layer 73. The first electrode layer 73A can be deposited along the inner wall of the first opening OP1 and the upper surface of the stacked ST. For example, a metal oxide layer can be deposited directly.

[0088] refer to FIG. 7C A variable resistance layer 74 may be formed in the first electrode layer 73A. For example, a variable resistance material layer may be formed along the surface of the first electrode layer 73A. The variable resistance material layer may be formed not only in the first opening OP1 but also on the upper surface of the stacked ST. Subsequently, a portion of the variable resistance material layer formed on the upper surface of the stacked ST may be etched by performing an etch-back process. Thus, the variable resistance layer 74 located in the first opening OP1 may be formed. During the etch-back process, the first electrode layer 73A formed on the upper surface of the stacked ST may also be etched at least partially.

[0089] refer to FIG. 7D A second electrode layer 75 may be formed along the surface of the variable resistance layer 74. The second electrode layer 75 may be formed in the first opening OP1 and may extend to the upper surface of the stack ST. The second electrode layer 75 may contain carbon.

[0090] Subsequently, a conductive layer 76 may be formed in the second electrode layer 75. The conductive layer 76 is used to form the electrode post and may contain a metal such as tungsten. The conductive layer 76 may fill the first opening OP1 or may be formed on the upper surface of the stack ST.

[0091] refer toFIG. 7E Electrode pillars 76A can be formed in the first opening OP1. For example, electrode pillars 76A, second electrode 75A, and first electrode 73B can be formed by planarizing the conductive layer 76, the second electrode layer 75, and the first electrode layer 73A until the upper surface of the stacked ST is exposed. The planarization process can be a CMP process.

[0092] For reference, the process of planarizing the conductive layer 76 can also be combined with the above-described etching process. For example, in FIG. 7C In this configuration, a variable resistance material layer can be formed along the inner wall of the first opening OP1 and the upper surface of the stacked ST. In this case, electrode pillars 76A, second electrode 75A, variable resistance layer 74, and first electrode 73B can be formed by etching the conductive layer 76, second electrode layer 75, variable resistance material layer, and first electrode layer 73A until the surface of the stacked ST is exposed.

[0093] refer to FIG. 7F The second opening OP2 can be formed by removing the sacrificial layer 71. For example, a slit SL can be formed through the stack ST, through which the sacrificial layer 71 can be selectively etched. Thus, the second opening OP2 can be defined between the stacked insulating layers 72, through which the first electrode 73B can be exposed. The remaining insulating layers 72 can be supported by electrode posts 76A.

[0094] refer to FIG. 7G Electrode plates 77 can be formed in the second opening OP2. For example, electrode plates 77 can be formed by filling the second opening OP2 with metal (e.g., tungsten). Thus, a stacked STA including alternately stacked electrode plates 77 and insulating layer 72 can be formed.

[0095] Subsequently, a sintering operation can be performed. Through the sintering operation, the first electrode 73B can be locally activated. The filament can be formed only in the region where the electrode plate 77 and the electrode post 76A of the first electrode 73B intersect. The filament can be locally formed in the metal oxide layer, and the corresponding portion can be used as an electrode.

[0096] According to the manufacturing method described above, a first electrode 73B containing a metal oxide can be formed in the first opening OP1. When the memory cell is in operation, the portion of the first electrode 73B located between the variable resistance layer 74 and the electrode plate 77 can serve as a physical electrode, while the remaining portion of the first electrode 73B can serve as a passive region.

[0097] Although embodiments based on the technical concept of this disclosure have been described above with reference to the accompanying drawings, this is only for explaining embodiments based on the concept of this disclosure, and this disclosure is not limited to the above embodiments. Those skilled in the art can make various types of substitutions, modifications, alterations, and combinations to the embodiments without departing from the technical concept defined by the appended claims, and such substitutions, modifications, alterations, and combinations should be understood to fall within the scope of this disclosure.

Claims

1. A semiconductor device comprising: a stack including electrode plates and insulating layers alternately stacked; an electrode pillar extending through the stack; a variable resistance layer provided over sidewalls of the electrode pillar and extending through the electrode plates and the insulating layers; and first electrodes between the electrode plates and the variable resistance layer, respectively, each of the first electrodes including a metal oxide. Each of the first electrodes includes a conductive filament.

2. The semiconductor device of claim 1, wherein, The conductive filament provides a conductive path between the electrode plate and the variable resistance layer.

3. The semiconductor device of claim 2, wherein, The metal oxide includes one or more of tungsten oxide, titanium oxide, or hafnium oxide.

4. The semiconductor device of claim 1, wherein, 5. The semiconductor device according to claim 1, further comprising second electrodes between the electrode pillar and the variable resistance layer. The second electrodes include carbon.

6. The semiconductor device of claim 5, wherein, Each of the first electrodes has a width substantially the same as a width of a corresponding electrode plate.

7. The semiconductor device of claim 1, wherein, The first electrodes project more toward the electrode pillar than the insulating layers.

8. The semiconductor device of claim 1, wherein, A cross section of the variable resistance layer has an irregular shape.

9. The semiconductor device of claim 8, wherein, 10. The semiconductor device according to claim 8, further comprising second electrodes between the electrode pillar and the variable resistance layer, a cross section of the second electrodes having an irregular shape.

11. The semiconductor device according to claim 8, further comprising: second electrodes between the electrode pillar and the variable resistance layer; and at least one void between the electrode pillar and the second electrodes. The electrode pillar includes: a through portion extending through the stack; and 12. The semiconductor device of claim 8, wherein, at least one protruding portion protruding from a sidewall of the through portion.

13. The semiconductor device according to claim 1, further comprising: a plurality of memory cells sharing the variable resistance layer, each of the memory cells being defined in an area where one of the electrode plates and the electrode pillar cross each other. The memory cells respectively include the first electrodes, and the first electrodes are separated from each other.

15. A semiconductor device comprising:

14. The semiconductor device of claim 13, wherein, a stack including electrode plates and insulating layers alternately stacked; an electrode pillar extending through the stack; a plurality of memory cells stacked along the electrode pillar; a variable resistance layer provided over sidewalls of the electrode pillar and shared by the memory cells; and first electrodes provided over the variable resistance layer and shared by the memory cells, wherein the first electrodes include a metal oxide. The first electrodes include a conductive filament. The conductive filament provides a conductive path between the electrode plate and the variable resistance layer. The conductive filament is located in an area where the electrode plate and the electrode pillar cross each other.

16. The semiconductor device of claim 15, wherein, The metal oxide includes one or more of tungsten oxide, titanium oxide, or hafnium oxide.

17. The semiconductor device of claim 16, wherein, 20. The semiconductor device according to claim 15, further comprising second electrodes between the electrode pillar and the variable resistance layer.

18. The semiconductor device of claim 16, wherein, The second electrodes include carbon.

19. The semiconductor device of claim 15, wherein, The variable resistance layer extends between the first electrodes and the second electrodes. The memory cells are respectively located in areas where the electrode plates and the electrode pillar cross each other.

21. The semiconductor device of claim 20, wherein, 24. A method of manufacturing a semiconductor device, the method comprising:

22. The semiconductor device of claim 20, wherein, ​ 23. The semiconductor device of claim 15, wherein, ​ ​ forming a stack comprising alternately stacked electrode plates and insulating layers; forming a first opening extending through the stack to expose the electrode plates; forming first electrodes on or over the exposed electrode plates, each of the first electrodes comprising a metal oxide; forming a variable resistance layer in the first opening; and forming electrode pillars in the variable resistance layer. The first electrodes are formed by oxidizing the exposed electrode plates.

25. The method of claim 24, wherein, 26. The method of claim 24, forming the stack comprises: wherein alternately stacking first sacrificial layers and the insulating layers; forming second sacrificial layers extending through the first sacrificial layers and the insulating layers; removing the first sacrificial layers to form second openings; and forming the electrode plates in the second openings, respectively. The first openings are formed by removing the second sacrificial layers.

27. The method of claim 26, wherein, The first electrodes protrude into the first openings, and the variable resistance layer is formed along a profile of the protruding first electrodes.

28. The method of claim 24, wherein, 29. The method of claim 24, further comprising forming second electrodes along a surface of the variable resistance layer. The variable resistance layer has an irregular shape, and the second electrodes are formed along a profile of the variable resistance layer.

30. The method of claim 29, wherein, The second electrodes comprise carbon.

31. The method of claim 29, wherein, The electrode pillars comprise at least one protruding portion corresponding to the insulating layers by depositing an electrically conductive material to fill irregular portions of the second electrodes.

32. The method of claim 30, wherein, 33. The method of claim 24, further comprising forming at least one void between the electrode pillars and the second electrodes at a level corresponding to each of the insulating layers.

34. The method of claim 24, further comprising forming electrically conductive filaments in the first electrodes by performing a sintering operation. The metal oxide comprises one or more of tungsten oxide, titanium oxide, or hafnium oxide.

35. The method of claim 24, wherein, 36. A method of manufacturing a semiconductor device, the method comprising: forming a stack comprising alternately stacked sacrificial layers and insulating layers; forming a first opening extending through the stack; forming first electrodes in the first opening, the first electrodes comprising a metal oxide; forming a variable resistance layer along a surface of the first electrodes; forming electrode pillars along a surface of the variable resistance layer; and replacing the sacrificial layers with electrode plates. forming the first electrodes comprises: forming a seed layer in the first opening; and 37. The method of claim 36, wherein, oxidizing the seed layer to form the first electrodes. A metal oxide layer is deposited in the first opening during forming the first electrodes. replacing the sacrificial layers with the electrode plates comprises:

38. The method of claim 36, wherein, forming second openings by removing the sacrificial layers; and 39. The method of claim 36, wherein, forming the electrode plates in the second openings, respectively.

40. The method of claim 36, further comprising forming second electrodes along the surface of the variable resistance layer. The second electrodes comprise carbon. Electrically conductive filaments are formed in areas of the first electrodes where the electrode plates and the electrode pillars intersect each other by performing a sintering operation.

41. The method of claim 40, wherein, The metal oxide comprises one or more of tungsten oxide, titanium oxide, or hafnium oxide.

42. The method of claim 36, further comprising: ​ 43. The method of claim 36, wherein, ​

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