Method of forming semiconductor stack on substrate including semimetal liner

Abstract

Semi-metal gaskets and metal-insulator-metal (MIM) capacitors (MIMCAP) and methods of manufacture or fabrication are described. The MIM capacitor structure includes a liner formed of a thin layer or film of semimetal that is a few nanometers thick, for example in a range of about 0.5 nm to about 5 nm or greater. A semi-metal liner is sandwiched between the electrode layer and a dielectric layer (e.g., a high or ultra-high k material layer), providing a cap for the electrode to limit leakage current in the structure.

Description

Technical Field

[0001] This invention generally relates to the design and manufacture of capacitors for use in electronic devices, including memory devices such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), etc., and more specifically, to the manufacture of pads for electronic devices and the manufacture of metal-insulator-metal (MIM) capacitors (generally marked "MIMCAP") with enhanced leakage current characteristics for use in memory and other electronic or computer devices. Background Technology

[0002] DRAM and other memory devices can utilize capacitors to store information bits within integrated circuits. Such capacitors are formed by placing a dielectric material between two electrodes made of conductive material. As device size and spacing decrease, DRAM devices typically use MIM capacitors, where the electrode material is metal. These electrode materials generally have higher conductivity than other electrode materials, such as semiconductors, and also possess various work functions, resulting in improved stability and reduced depletion effects.

[0003] Electrode materials with high conductivity are typically chosen to ensure fast device speeds, and MIMs often utilize insulating materials with dielectric constants or k values ​​much higher than those of SiO2, where such dielectric materials are classified as high-k or ultra-high-k materials. Unfortunately, increasing the k value can reduce the conduction band offset relative to the metal electrode, which can lead to undesirable leakage currents in MIM devices, especially at elevated temperatures.

[0004] There remains a need for MIM capacitor designs used in DRAM and other devices with reduced leakage current. For this purpose, electrodes have a strong influence on leakage conduction in MIM capacitors. For example, electrodes can affect leakage current by: (a) directly injecting electrons into the conduction band of the dielectric material if the energy difference between the conduction band and the work function of the metal is too small; (b) allowing electrons to tunnel through the dielectric material; and (c) removing oxygen from the dielectric material, which creates oxygen vacancies and thus increases trap density. Therefore, innovative manufacturing technologies are needed that can mass-produce advanced MIM capacitors while maintaining high-quality electrical characteristics, meeting tight thermal budgets, and remaining cost-effective for large-scale production. Summary of the Invention

[0005] This summary is provided to present the chosen concepts in a simplified form. These concepts are further described in detail in the following description of exemplary embodiments of this disclosure. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0006] Various embodiments provide a method for forming a semiconductor stack on a substrate for use in a metal-insulator-metal (MIM) capacitor, the method comprising: forming a first electrode layer comprising a conductive material on the substrate; forming a first half-metal layer on the first electrode layer; and forming a dielectric layer on the first half-metal layer; wherein the first half-metal layer forms a first pad between the first electrode layer and the dielectric layer.

[0007] In some embodiments, the first half-metal layer is an elemental half-metal layer.

[0008] In some embodiments, the first electrode layer, the first half-metal layer, and the dielectric layer are formed by an atomic layer deposition process.

[0009] In some embodiments, the atomic layer deposition of the first electrode layer, the first half-metal layer, and the dielectric layer is performed within the same semiconductor processing apparatus.

[0010] In some embodiments, atomic layer deposition of the first electrode layer, the first half-metal layer, and the dielectric layer is carried out in the first reaction chamber without disrupting the vacuum.

[0011] In some embodiments, the first half-metal layer comprises antimony, bismuth, or tellurium.

[0012] In some embodiments, forming the first half-metal layer includes: depositing a first metal oxide layer on a first electrode layer by an atomic layer deposition process; and performing a post-deposition heat treatment on the first metal oxide layer in a reducing atmosphere to convert the first metal oxide layer into a first half-metal layer.

[0013] In some embodiments, atomic layer deposition of the first electrode layer, the first metal oxide layer, and the dielectric layer, as well as post-deposition heat treatment of the first metal oxide layer, are performed in the first reaction chamber without disrupting the vacuum.

[0014] In some embodiments, the first half-metal layer comprises α-tin (α-Sn).

[0015] In some embodiments, the method further includes: forming a second half-metal layer on the dielectric layer; and forming a second electrode layer on the second half-metal layer; wherein the second half-metal layer forms a second pad between the dielectric layer and the second electrode layer.

[0016] In some embodiments, the first electrode layer, the first half-metal layer, the dielectric layer, the second half-metal layer, and the second electrode layer are formed in the first reaction chamber by an atomic layer deposition process without breaking the vacuum.

[0017] In some embodiments, the second half-metal layer comprises an elemental half-metal layer.

[0018] In some embodiments, the second half-metal layer comprises antimony, bismuth, or tellurium.

[0019] In some embodiments, forming the second half-metal layer further includes: depositing a second metal oxide layer on the dielectric layer by an atomic layer deposition process; and performing a post-deposition heat treatment on the second metal oxide layer in a reducing atmosphere to convert the second metal oxide layer into a second half-metal layer.

[0020] In some embodiments, the dielectric layer includes a hafnium zirconium oxide (HfZrO) dielectric layer.

[0021] In some embodiments, a hafnium zirconium oxide (HfZrO) dielectric layer is formed by performing one or more supercycles of an atomic layer deposition process, each supercycle comprising: performing one or more repetitions of a hafnium oxide subcycle; and performing one or more repetitions of a zirconium oxide subcycle; wherein the hafnium zirconium oxide (HfZrO) dielectric layer has a stoichiometry (Hf:Zr) between 1:1 and 1:5.

[0022] Various embodiments provide a method for forming a semiconductor stack on a substrate for use in a metal-insulator-metal (MIM) capacitor, the method comprising: depositing a first electrode layer comprising a conductive material on the substrate; forming a first half-metal layer directly on the first electrode layer; depositing a hafnium zirconium oxide (HfZrO) dielectric layer directly on the first half-metal layer; forming a second half-metal layer directly on the hafnium zirconium oxide (HfZrO) dielectric layer; and depositing a second electrode layer directly on the second half-metal layer; wherein the first half-metal layer forms a first pad between the first electrode layer and the hafnium zirconium oxide dielectric layer, and the second half-metal layer forms a second pad between the hafnium zirconium oxide (HfZrO) dielectric layer and the second electrode layer.

[0023] In some embodiments, the first half-metal layer and the second half-metal layer comprise a material selected from antimony, bismuth, tellurium and α-tin (α-Sn).

[0024] In some embodiments, the semiconductor stack is formed in the first reaction chamber without breaking the vacuum through an atomic layer deposition process.

[0025] In some embodiments, the first half-metal layer and the second half-metal layer are α-tin (α-Sn) and are formed by: depositing a first tin oxide layer on a first electrode layer by an atomic layer deposition process; depositing a second tin oxide layer on a hafnium zirconium dielectric layer; and subjecting the first tin oxide layer and the second tin oxide layer to a post-deposition heat treatment in a reducing atmosphere to convert the first tin oxide layer into a first α-tin (first α-Sn) half-metal layer and the second tin oxide layer into a second α-tin (second α-Sn) half-metal layer.

[0026] For the purpose of outlining this disclosure and its advantages relative to prior art implementations, certain objects and advantages of this disclosure have been described above. It should be understood, of course, that not all such objects or advantages may be achieved according to any particular embodiment of this disclosure. Therefore, for example, those skilled in the art will recognize that the embodiments disclosed herein may be performed in a manner that achieves or optimizes one or more advantages taught or suggested herein, without necessarily achieving other objects or advantages that may be taught or suggested herein.

[0027] All these embodiments are intended to fall within the scope of this disclosure. These and other embodiments will become apparent to those skilled in the art from the following detailed description of certain embodiments with reference to the accompanying drawings, and this disclosure is not limited to any particular embodiment discussed. Attached Figure Description

[0028] Although this specification concludes with claims that are specifically pointed out and clearly claimed as embodiments of this disclosure, the advantages of embodiments of this disclosure can be more readily determined from the description of certain examples of embodiments when read in conjunction with the accompanying drawings. Elements having the same element numbers in all the drawings are intended to be identical.

[0029] Figure 1 A method for forming a semiconductor stack on a substrate for use in a metal-insulator-metal (MIM) capacitor is illustrated according to one or more embodiments of the present disclosure.

[0030] Figure 2 A simplified cross-sectional view of a substrate on which a semiconductor stack can be formed, according to one or more embodiments of the present disclosure, is shown.

[0031] Figures 3 to 7 A simplified cross-sectional view of the structure and semiconductor stack formed by one or more embodiments of the present disclosure is shown. Detailed Implementation

[0032] Although certain embodiments and examples are disclosed below, those skilled in the art will understand that this disclosure extends beyond the specific disclosed embodiments and / or the uses of this disclosure and their obvious modifications and equivalents. Therefore, it is intended that the scope of this disclosure should not be limited to the specific embodiments described herein.

[0033] The illustrations presented herein are not intended to be actual views of any particular material, device, structure, or equipment, but are merely representations for illustrating embodiments of this disclosure.

[0034] As used herein, the term "substrate" can refer to any one or more underlying materials that can be used to form or on which devices, circuits, or films can be formed using methods according to embodiments of the invention. A substrate may comprise a bulk material, such as silicon (e.g., single-crystal silicon), other group IV materials (e.g., germanium), or other semiconductor materials (e.g., group II-VI or III-V semiconductor materials), and may comprise one or more layers overlying or underlying the bulk material. A substrate may include various topologies, such as gaps, including recesses, lines, trenches, or spaces between protrusions (e.g., fins) formed within or on at least a portion of the layers of the substrate. For example, a substrate may comprise a bulk semiconductor material and an insulating or dielectric material layer covering at least a portion of the bulk semiconductor material. Furthermore, the term "substrate" can refer to any one or more underlying materials that can be used or on which devices, circuits, or films can be formed. A "substrate" can be continuous or discontinuous; rigid or flexible; solid or porous. A "substrate" can be any form, such as powder, plate, or workpiece. Plate-type substrates can include wafers of various shapes and sizes. The substrate can be made of materials such as silicon, silicon germanium, silicon oxide, gallium arsenide, gallium nitride, and silicon carbide. The continuous substrate can extend beyond the boundary of the processing chamber, where the deposition process takes place, and the continuous substrate can move through the processing chamber such that the process continues until the end of the substrate is reached. The continuous substrate can be supplied from a continuous substrate feed system, allowing the continuous substrate to be manufactured and output in any suitable form. Non-limiting examples of continuous substrates may include sheets, nonwoven films, rolls, foils, meshes, flexible materials, bundles of continuous filaments or fibers (i.e., ceramic fibers or polymer fibers). The continuous substrate may also include a carrier or sheet on which a non-continuous substrate is mounted.

[0035] As used herein, the terms “layer” and / or “film” are used interchangeably and can refer to any continuous or discontinuous structure and material, such as materials deposited by the methods disclosed herein. For example, a layer can include two-dimensional materials, three-dimensional materials, nanoparticles, partially or entirely molecular layers, partially or entirely atomic layers, or clusters of atoms and / or molecules. A layer can consist partially or entirely of a plurality of dispersed atoms on a substrate surface and / or embedded in the substrate and / or embedded in devices fabricated on the substrate. A layer can include a material or layer having pinholes and / or isolation islands. A layer can be at least partially continuous. A layer can be patterned, e.g., subdivided, and can include multiple semiconductor devices.

[0036] As used herein, the term "cyclic deposition process" or "cyclic deposition process" can refer to the sequential introduction of precursors (and / or reactants) into a reaction chamber to deposit a layer on a substrate, and includes processing techniques such as atomic layer deposition (ALD), cyclic chemical vapor deposition (cyclic CVD), and hybrid cyclic deposition processes that include ALD and cyclic CVD components. In some cases, a cyclic deposition process may include a continuous flow of one or more precursors, reactants, or inert gases, and pulses of other precursors or reactants.

[0037] As used herein, the term "atomic layer deposition" can refer to a vapor phase deposition process in which deposition cycles, typically multiple consecutive, are performed in a processing chamber. As used herein, the term atomic layer deposition is also intended to include processes specified by related terms, such as chemical vapor phase atomic layer deposition when performed with alternating pulses of precursor / reactive gases and purge gases (e.g., inert carrier gases). Typically, for an ALD process, during each cycle, a precursor is introduced into the reaction chamber and chemisorbed onto the deposition surface (e.g., a substrate surface that may include previously deposited material from a previous ALD cycle or other material), forming a monolayer or sub-monolayer of material that is not readily reactive with additional precursors (i.e., self-limiting reaction). Subsequently, in some cases, a reactant (e.g., another precursor or reactive gas) may be subsequently introduced into the processing chamber to convert the chemisorbed precursor into the desired material on the deposition surface. The reactant may be able to react further with the precursor. During one or more cycles, such as during each step of each cycle, a purge step may be used to remove any excess precursor from the processing chamber and / or any excess reactant and / or reaction byproducts from the reaction chamber.

[0038] As used herein, the term “chemical vapor deposition” can refer to any process in which a substrate is exposed to one or more volatile precursors that react and / or decompose on the substrate surface to produce the desired deposition.

[0039] As described in more detail below, the various details and embodiments of this disclosure can be used in conjunction with reaction chambers configured for a variety of deposition processes, including but not limited to ALD, CVD, metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), and plasma etching. Embodiments of this disclosure can also be used in semiconductor processing systems configured for depositing (providing or forming) layers or thin films of MIM capacitors, semiconductor processing systems known to (or yet to be developed) by those skilled in the art.

[0040] As used herein, the terms "semi-metal" and "semi-metal layer" can refer to materials having band dispersions different from those of elemental metallic layers. For example, as used herein, the terms "semi-metal" and "semi-metal layer" can refer to materials where the density of states at the Fermi level decreases to zero. As a further example, as used herein, the terms "semi-metal" and "semi-metal layer" can refer to materials where the band dispersion near the Fermi level is linear. As used herein, the terms "semi-metal" and "semi-metal layer" do not refer to materials and layers comprising or composed of silicon and germanium.

[0041] The inventors recognized that the electrodes of a MIM capacitor can have a strong influence on leakage conduction. Instead of replacing the entire MIM capacitor electrode with a half-metal to control leakage conduction, the inventors created a method for manufacturing an MIM capacitor having a half-metallic pad sandwiched between the electrodes and an insulator or dielectric. The half-metallic pad can be formed using PVD, ALD, or other deposition processes.

[0042] Half-metals exhibit band dispersion that differs from more common metallic layers. Unbound by any theory—at the Fermi level, the density of states in the half-metal band decreases to zero. This indicates that there are no charge carrier states at the Fermi level from which carriers can tunnel or cross the Schottky barrier to cause leakage. This reduction in the density of states at the Fermi level can suppress leakage in MIM capacitors. Unlike elemental metallic layers, the half-metal band dispersion near the Fermi level is also linear, thus reducing the availability of carriers to tunnel through the dielectric layer and cause leakage. Furthermore, since the provided pads are half-metallic layers, they do not add additional effective oxide thickness to the entire layer stack of the MIM capacitor, thereby not significantly reducing the high dielectric constant of the dielectric layer. Therefore, due to the unique band structure of half-metals, half-metallic pads can reduce leakage due to carrier tunneling without increasing the additional equivalent oxide thickness (EOT).

[0043] The new MIM capacitor is unique, partly due to the introduction or use of a semi-metallic pad instead of replacing the entire electrode with a precious metal. This innovative design offers several advantages. First, precious metals can be expensive. By using thin (e.g., 0.5 to 5 nm) pads, the cost of using semi-metals in MIM capacitors is significantly reduced compared to using precious metals for bulk electrodes that can be 20 nm or thicker. Second, using pads requires only minor process modifications, unlike the larger downstream and upstream process modifications required for replacing the entire electrode. For example, in the case of etching the electrode, the electrode metal can be etched as usual, and the pad can act as an etch stop layer. The pad can then be penetrated using short, and in some cases, different, etch cycles. Third, the use of semi-metallic pads allows the capacitor to be designed to provide work function regulation with less leakage through direct carrier injection. Fourth, the pads provide a capacitor with less oxygen removal, resulting in less leakage through reduced trap density. Fifth, the use of semi-metallic pads prevents oxidation of the bottom electrode, a root cause of increased equivalent oxide thickness (EOT).

[0044] Figure 1 An exemplary method 100 is shown for forming a semiconductor stack on a substrate for use in a metal-insulator-metal (MIM) capacitor or capacitor stack (e.g., a DRAM capacitor stack). Those skilled in the art will understand that each layer discussed herein and used in a MIM capacitor or capacitor stack can be formed using any common formation technique available for depositing thin films or layers of the materials described herein, such as ALD (or ALD-like processes or other cyclic deposition processes), PVD, or CVD. Therefore, method 100 is intended to include methods for depositing... Figures 3 to 7 Any useful process for the MIM capacitor or the layer or film of the capacitor stack shown.

[0045] Now turn to the attached image. Figure 1 A method 100 for forming a semiconductor stack on a substrate for use in a metal-insulator-metal (MIM) capacitor or capacitor stack is illustrated. In brief, method 100 includes placing a substrate in a reaction chamber and forming a first electrode layer on the substrate (step 102), forming a first half-metal layer on the first electrode layer (step 104), and forming a dielectric layer on the first half-metal layer (step 106). In another aspect, method 100 includes forming a second half-metal layer on the dielectric layer (step 108) and forming a second electrode layer on the second half-metal layer (step 110).

[0046] More specifically, the substrate on which the semiconductor stack is formed may include the substrate described above, and may also include a portion of a device structure, such as a partially fabricated device structure. For example, Figure 2A substrate 202 on which a semiconductor stack can be formed is shown. The substrate 202 may include partially fabricated logic devices, memory devices, integrated circuits, etc. The substrate is disposed in a reaction chamber configured for depositing the semiconductor stack. In such an example, the reaction chamber may include a component or assembly of a single-wafer ALD reactor or a batch ALD reactor, wherein deposition on multiple substrates occurs simultaneously. In some embodiments, the reaction chamber may form part of a cluster of tools in which various different processes for fabricating devices and / or integrated circuits are performed. In some embodiments, a flow reactor and associated reaction chamber may be used. In some embodiments, a single-wafer ALD reactor and associated reaction chamber capable of high-volume fabrication may be used. In other embodiments, a batch reactor comprising multiple substrates may be used. For embodiments using a batch ALD reactor, the number of substrates may range from 10 to 300, from 50 to 150, or from 300 to 130. Furthermore, in some embodiments, the substrate may be disposed in other forms of reaction chambers associated with various reactors, such as, but not limited to, CVD reactors, PVD reactors, PECVD reactors, PEALD reactors, etc.

[0047] Before forming a stack on a substrate (e.g., substrate 202), the substrate is heated to a desired temperature, and the pressure in the reaction chamber can also be adjusted to achieve the deposition of the semiconductor stack.

[0048] Turn to Figure 1 Method 100, step 102 includes forming a first electrode layer on a substrate. In some embodiments, the first electrode layer (or bottom electrode layer) may be formed on the upper surface of the substrate or directly thereon. For example, Figure 3 A structure 300 is shown, including a substrate 202 and a first electrode layer 302 directly disposed on the upper surface of the substrate 202. The first electrode layer 302 is formed by depositing a thin layer of conductive material on the substrate. In some embodiments, the first electrode layer 302 comprises titanium nitride (TiN). The conductive first electrode layer may be formed of other metals, conductive metal oxides, conductive metal silicides, conductive metal nitrides, and combinations thereof. The purpose of the first or bottom electrode in a MIM capacitor or other device is typically to serve as a primary conductor. The first electrode layer may be formed by a deposition process, such as, but not limited to, PVD, CVD, etc. In a particular embodiment, the first electrode layer is deposited by an atomic layer deposition process.

[0049] According to an example of this disclosure, step 104 of method 100 includes forming a first half-metal layer on the first electrode layer 302. This may involve depositing the half-metal layer or film onto the upper or exposed surface of the electrode formed in step 102, or directly thereon, using PVD, ALD, or another useful deposition technique. For example, Figure 4Structure 400 is shown, which includes a substrate 202 and a first electrode layer 302 as described above, and a first half-metal layer 402 disposed on the upper surface of the first electrode layer 302.

[0050] In some embodiments of method 100, step 104 of forming the first half-metal layer includes performing a cyclic deposition process (e.g., ALD, ALD-like process, etc.) comprising multiple deposition cycles. Each deposition cycle may include a precursor pulse and a reactant pulse, wherein the precursor pulse includes exposing a substrate (e.g., for the first electrode layer of step 104) to a precursor, and the reactant pulse includes exposing the same substrate to a reactant.

[0051] According to examples of this disclosure, the first half-metal layer 402 may include an elemental half-metal layer. In one aspect, the first half-metal layer is formed by directly depositing an elemental half-metal layer. In another aspect, the first half-metal layer is formed by depositing a metal oxide layer and subsequently employing a post-deposition heat treatment to convert the metal oxide layer into an elemental half-metal layer.

[0052] In examples where the first half-metal layer is directly deposited as an elemental half-metal layer, the first half-metal layer may contain antimony, bismuth, or tellurium. In such examples, the first half-metal layer is antimony, bismuth, tellurium, or an alloy thereof, or is composed of or substantially composed of them. Direct deposition of the elemental first half-metal layer can be achieved through an atomic layer deposition process, but other suitable deposition processes can be used.

[0053] An ALD process for depositing a first half-metal layer comprising antimony, bismuth, or tellurium may include performing one or more deposition cycles, wherein each deposition cycle may include the following process steps: (a) introducing a metal precursor (e.g., an Sb precursor, a Bi precursor, or a Te precursor) into a reaction chamber, and (b) introducing a reduction reactant into the reaction chamber to react with the absorbed metal precursor to form the first half-metal layer. A purge cycle may be performed after step (a) and / or step (b) to remove any excess precursor / reactant and / or reactant byproducts. Steps (a) and (b) of the ALD process may be repeated as needed to deposit a first half-metal layer of sufficient thickness. Furthermore, steps (a) and (b) may be started and / or terminated in any order. Additionally, an ALD process for directly depositing an elemental first half-metal layer may include one or more (e.g., 1-10 or 1-5) steps (a) and / or (b) before proceeding to another step (b) or (a). It should also be understood that the ALD process for directly depositing the first half-metal layer may include additional process steps not described herein, such as, but not limited to, cleaning steps, surface preparation steps, etc.

[0054] Suitable metal precursors for directly depositing the first half-metal layer via the ALD process may include metal-containing precursors. In some embodiments, the metal precursor (e.g., an Sb precursor, a Bi precursor, or a Te precursor) may include one or more of a metal halide precursor and a metal-organic precursor.

[0055] In various embodiments, the antimony precursor may include antimony chloride (SbCl3). Other antimony precursors may be used instead of antimony chloride or in addition to antimony chloride. Other antimony precursors may comprise other antimony halides. Other antimony precursors may comprise compounds in the form of SbX3, where X represents a halide. Other antimony precursors may comprise SbF3, SbBr3, or SbI3. Other volatile antimony-containing compounds may be used as antimony precursors for ALD. Antimony precursors may comprise Sb(OCH2CF3)3 and its derivatives, Sb(NR2)3 (where R represents a generalized organic group), etc. Sb(NMe2)3 is an example of a specific molecule that can be used as an antimony precursor.

[0056] In various embodiments, the bismuth precursor may include bismuth chloride (BiCl3), bismuth amino complexes such as Bi(NMe2)3, other bismuth halides, or other bismuth precursors. Additionally, the bismuth precursor may include BiF3, BiBr3, or Bib. The bismuth precursor may include triphenylbismuth. The bismuth precursor may include aryl and alkyl derivatives of BiPh3, such as tris(4-methylphenyl)bismuth, tris(4-fluorophenyl)bismuth, etc. The bismuth precursor may include Bi(OCH2CF3)3. The bismuth precursor may include related alkoxides of Bi(OCH2CF3)3.

[0057] In various embodiments, the reducing reactants may include one or more of the following: syngas (H2+N2), ammonia (NH3), hydrazine (N2H4), alkyl hydrazine (e.g., tert-butylhydrazine (C4H4)). 12 N2), molecular hydrogen (H2), hydrogen atom (H), hydrogen plasma, hydrogen free radical, hydrogen excitation substance, (e.g., C1-C4) alcohol, (e.g., C1-C4) aldehyde, (e.g., C1-C4) carboxylic acid, (e.g., B1-B12) borane or amine.

[0058] On the other hand, a first half-metal layer is formed by depositing a metal oxide layer and subsequently performing a post-deposition heat treatment to convert the metal oxide layer into an elemental half-metal layer. As a non-limiting example, step 104 of method 100 may include depositing a first metal oxide layer on or directly on a first electrode layer via an atomic layer deposition process, and performing a post-deposition heat treatment on the first metal oxide layer in a reducing atmosphere to convert the first metal oxide layer into a first half-metal layer. In at least one example, the first metal oxide layer may comprise a tin oxide layer (or a first tin oxide layer) deposited via an atomic layer deposition process. The ALD process for depositing the tin oxide layer may be the same as or similar to those described above. For example, the ALD process for depositing the tin oxide layer may include (a) introducing a tin precursor into a reaction chamber, and (b) introducing an oxygen reactant into the reaction chamber to react with the absorbed tin precursor to form a tin oxide layer. A purging cycle may be performed after steps (a) and / or (b) to remove any excess precursor / reactant and / or reactant byproducts. Steps (a) and (b) of the ALD process may be repeated as needed to deposit the tin oxide layer to a sufficient thickness. Furthermore, steps (a) and (b) can be started and / or terminated in any order. Additionally, the ALD method for depositing the first tin oxide layer may include one or more (e.g., 1-10 or 1-5) steps (a) and / or (b) before proceeding to another step (b) or (a). It should also be recognized that the ALD process for directly depositing the tin oxide layer (i.e., the first tin oxide layer) may include additional process steps not described herein, such as, but not limited to, cleaning steps, surface preparation steps, etc.

[0059] In various embodiments, suitable tin precursors for depositing tin oxide layers via the ALD process may include metal-containing precursors. In some embodiments, the tin precursor may include one or more of metal halide precursors and organometallic precursors. For example, the tin precursor may include one or more of the following: SnCl 4, Sn(dmamb)2, Sn(edpa)2, Sn( i Pr2fAMD)2,Sn(N(SiMe3)2)2, Sn(Ot-Amyl)2, Sn(η2 -((N t Bu)CMe2CH2(N t Bu))), Sn(acac)2, Sn(NMe2)4 and Sn(tbba).

[0060] In various embodiments, suitable oxygen reactants for depositing the first metal oxide layer (e.g., a tin oxide layer or a first tin oxide layer) may include one or more of the following: water vapor (H2O), ozone (O3), molecular oxygen O2, hydrogen peroxide vapor (H2O2), and oxygen-based plasma (including oxygen-excited material generated by a plasma generation device supplied with oxygen-containing gas).

[0061] When depositing a first metal oxide layer (e.g., a first tin oxide layer), the first metal oxide layer is treated in a reducing atmosphere for post-deposition heat treatment to transform the first metal oxide layer into a first half-metal layer. In various embodiments, the first metal oxide layer is heated in a reaction chamber in an atmosphere containing a reducing agent. In such embodiments, the reducing agent may contain hydrogen (H2) or a carbon-containing gas (e.g., CO2 and CH4). In such examples, the first metal oxide layer may be heated to a temperature of 500°C to 1000°C in a reducing atmosphere. As a non-limiting example, the first metal oxide layer may include a tin oxide layer, and post-deposition heat treatment in a reducing atmosphere transforms the tin oxide layer into a half-metallic form of tin, commonly referred to as α-tin (α-Sn), which may also be called gray tin. In contrast to metallic tin, α-tin (α-Sn) is an allotrope having a diamond cubic structure and is a half-metallic material. In an alternative embodiment, a layer of metallic tin can be deposited via an ALD process, and the metallic tin can be cooled to a temperature below 13.2°C, at which temperature the metallic tin is transformed into the semi-metallic form α-tin (α-Sn).

[0062] The first half-metal layer 402 is "thin" because it has a thickness of less than or equal to 5 nm, with some embodiments of method 100 depositing half-metal layers in the range of 1 to 5 nm. Various half-metals can be deposited in step 104 to form the first pad, with antimony, bismuth, tellurium, and α-tin being desirable in some exemplary applications, having work functions between 4 eV and 5 eV, and their low oxygen scavenging potentials acting to provide a scavenging barrier layer. In other cases, a first half-metal layer with a work function greater than about 5 eV can be selected.

[0063] Turn to Figure 1Method 100 includes step 106 of forming a dielectric layer on or directly thereon the exposed upper surface of the first half-metal layer (e.g., a first pad) formed in step 104. Again, any useful and well-known deposition technique may be used in step 106. Suitably, step 106 may include forming a metal oxide-containing layer by an ALD process. Suitable ALD processes include the sequence of exposing the substrate to a metal precursor, exposing the substrate to a purge gas, exposing the substrate to an oxygen reactant, and exposing the substrate to a purge gas. Suitable metal precursors include organometallic precursors and halides, and are known in the art. Suitable oxygen reactants include oxygen-containing gases, such as O2, O3, H2O, and H2O2. The dielectric layer may be formed by a process including depositing a high-k or ultra-high-k dielectric material (e.g., hafnium oxide (HfO2), doped HfO2, hafnium zirconium oxide (HfZrO), doped HfZrO, etc.). In some cases, the dielectric layer comprises a high-k metal oxide material, such as titanium oxide, zirconium oxide, aluminum oxide, barium strontium titanate, erbium oxide, hafnium silicate, lanthanum oxide, niobium oxide, lead zirconium titanate, strontium titanate, tantalum oxide, titanium oxide, zirconium oxide, or other high-k or ultra-high-k metal oxides (e.g., having a k value greater than about 40). For example, Figure 5 Structure 500 is shown, which includes a substrate 202, a first electrode layer 302, a first half-metal layer 402, and a dielectric layer 502 disposed on or directly disposed thereon the first half-metal layer 402. Figure 5 As shown, the first half-metal layer 402 forms a first pad between the first electrode layer 302 and the dielectric layer 502.

[0064] In various embodiments, the dielectric layer comprises a hafnium zirconium oxide (HfZrO) dielectric layer. In such embodiments, the hafnium zirconium oxide (HfZrO) layer may be doped or undoped. The hafnium zirconium oxide (HfZrO) dielectric layer can be formed by performing one or more supercycles of an atomic layer deposition process. In some examples, each supercycle may include: performing one or more repetitions of a hafnium oxide subcycle (e.g., to deposit an HfO metal oxide component); and performing one or more repetitions of a zirconium oxide subcycle (e.g., to deposit a ZrO metal oxide component). Each of the hafnium oxide subcycles may be similar to the ALD process described above, such as (a) introducing a hafnium precursor into the reaction chamber, and (b) introducing an oxygen reactant into the reaction chamber to react with the absorbed hafnium precursor. Similarly, each of the zirconium oxide subcycles may be similar to the ALD process described above, such as (a) introducing a zirconium precursor into the reaction chamber, and (b) introducing an oxygen reactant into the reaction chamber to react with the absorbed zirconium precursor.

[0065] In some embodiments, the stoichiometry of the hafnium zirconium oxide dielectric layer can be tuned by adjusting the ratio of the individual metal oxides (e.g., HfO and ZrO) in the HfZrO dielectric layer. In some embodiments, the desired stoichiometry of the hafnium zirconium oxide dielectric layer can be achieved by selecting the number of times each sub-cycle (e.g., hafnium oxide and zirconium oxide sub-cycles) is repeated within a deposition supercycle, for example, to provide a desired Hf:Zr stoichiometry. In some embodiments, the deposited hafnium zirconium oxide dielectric layer may have the following stoichiometry or elemental ratio (Hf:Zr): 1:1, or 1:2 to 1:3, or 1:4, or 1:5, or 1:6, 1:7, or 1:8, or 1:9, or 1:10, or between 1:1 and 1:10. In other aspects, the dielectric layer is a hafnium oxide layer deposited by one or more repeated hafnium oxide sub-cycles. In still other aspects, the dielectric layer is a zirconium oxide layer deposited by one or more repeated zirconium oxide sub-cycles.

[0066] like Figure 5 As shown, the semiconductor stack 504 formed by steps 102, 104 and 106 of method 100 includes a first electrode layer 302 disposed on a substrate 202, a first half-metal layer 402 disposed on the first electrode layer 302 and a dielectric layer 502 (e.g., HfZrO) disposed on the first half-metal layer 402, wherein the first half-metal layer 402 forms a first pad sandwiched between the first electrode layer 302 and the dielectric layer 502.

[0067] According to examples of this disclosure, the first electrode layer 302, the first half-metal layer 402, and the dielectric layer 502 can be formed by an atomic layer deposition process. In some embodiments, the atomic layer deposition of the first electrode layer 302, the first half-metal layer 402, and the dielectric layer 502 can be performed within the same semiconductor processing apparatus.

[0068] In one aspect, the semiconductor processing system for performing method 100 may include a clustering tool comprising two or more reaction chambers, such as a first reaction chamber, a second reaction chamber, a third reaction chamber, etc., and at least one of steps 102, 104, 106 may be performed in the first reaction chamber, and / or at least one of steps 102, 104, 106 may be performed in the second reaction chamber, and / or at least one of steps 102, 104, and 106 may be performed in the third reaction chamber. When one step of method 100 is performed in the first reaction chamber and subsequent steps of method 100 are performed in the second reaction chamber, a transfer chamber with a controlled environment may be used to transfer the substrate 202 between the first and second reaction chambers to prevent contamination of layers formed on the substrate.

[0069] On the other hand, atomic layer deposition of the first electrode layer 302, the first half-metal layer 402, and the dielectric layer 502 can be performed in the first reaction chamber. In some aspects, the formation of the semiconductor stack 504 can be completed without disrupting the vacuum in the reaction chamber, i.e., steps 102, 104, and 106 can be performed sequentially one after another without transferring the substrate to the second reaction chamber.

[0070] On the other hand, atomic layer deposition of the first electrode layer, the first metal oxide layer, and the dielectric layer, as well as post-deposition heat treatment of the first metal oxide layer, are carried out in the first reaction chamber without disrupting the vacuum.

[0071] Turn to Figure 1 The method 100 is shown. In various embodiments, method 100 includes forming a second half-metal layer on the dielectric layer. In such embodiments, the second half-metal layer may comprise all of the materials described above formed by one or more processes referred to in step 104. For example, Figure 6 Structure 600 is shown, which includes Figure 5 The semiconductor stack 504 has a second half-metal layer 602 added on the dielectric layer 502.

[0072] In some embodiments, the second half-metal layer comprises an elemental half-metal layer. In such embodiments, the second half-metal layer may comprise antimony, bismuth, or tellurium. In such embodiments, the second half-metal layer may be deposited using the atomic layer deposition method described above.

[0073] In some embodiments, forming the second half-metal layer may include depositing a second metal oxide layer on a dielectric layer via an atomic layer deposition process, and performing a post-deposition heat treatment on the second metal oxide layer in a reducing atmosphere to transform the second metal oxide layer into a second half-metal layer. In such embodiments, the second metal oxide layer may comprise a second tin oxide layer, and the second tin oxide layer is transformed into a second α-tin half-metal layer by reducing the second tin oxide layer through a post-deposition heat treatment in a reducing atmosphere; that is, the second half-metal layer comprises a second α-tin half-metal layer.

[0074] In various embodiments, method 100 includes forming a second electrode layer on the second half-metal layer (step 110). In such embodiments, the second half-metal layer forms a second pad between the dielectric layer and the second electrode layer. For example, Figure 7 Structure 700 is shown, which includes Figure 6 The structure 600 includes a second electrode layer 702 added on the dielectric layer 502, thereby forming a semiconductor stack 704. (Example) Figure 7As shown, the semiconductor stack includes a first half-metal layer 402 and a second half-metal layer 602. The first half-metal layer 402 forms a first pad between the first electrode layer 302 and the dielectric layer 502, and the second half-metal layer 602 forms a second pad between the dielectric layer 502 and the second electrode layer 702.

[0075] In some embodiments, the second electrode layer (or top electrode layer) may be formed on the upper surface of the second half-metal layer or directly thereon. The second electrode layer is formed by depositing a thin layer of conductive material on the substrate. In some embodiments, the second electrode layer 702 comprises titanium nitride (TiN). The conductive second electrode layer may be formed of other metals, conductive metal oxides, conductive metal silicides, conductive metal nitrides, and combinations thereof. In some embodiments, the second electrode layer may be formed by a deposition process, such as, but not limited to, PVD, CVD, etc. In a particular embodiment, the second electrode layer is deposited by an atomic layer deposition process.

[0076] In one aspect, the semiconductor processing system for performing method 100 may include a clustering tool comprising two or more reaction chambers, such as a first reaction chamber, a second reaction chamber, a third reaction chamber, a fourth reaction chamber, a fifth reaction chamber, etc., and at least one of steps 102, 104, 106, 108, and 110 may be performed in the first reaction chamber, and / or at least one of steps 102, 104, 106, 108, and 110 may be performed in the second reaction chamber, and / or at least one of steps 102, 104, 106, 108, and 110 may be performed in the third reaction chamber, and / or at least one of steps 102, 104, 106, 108, and 110 may be performed in the fourth reaction chamber, and / or at least one of steps 102, 104, 106, 108, and 110 may be performed in the fifth reaction chamber.

[0077] On the other hand, atomic layer deposition of the first electrode layer 302, the first half-metal layer 402, the dielectric layer 502, the second half-metal layer 602, and the second electrode layer 702 can be performed within the first reaction chamber. In some aspects, the semiconductor stack 704 ( Figure 7 The formation of the substrate can be completed without disrupting the vacuum in the reaction chamber, that is, steps 102, 104, 106, 108 and 110 can be performed sequentially one after another without transferring the substrate to the second reaction chamber.

[0078] On the other hand, atomic layer deposition of the first electrode layer, the first metal oxide layer, and the dielectric layer, as well as post-deposition heat treatment of the first metal oxide layer and the second metal oxide layer, are carried out in the first reaction chamber without disrupting the vacuum.

[0079] Turn to Figure 7The first half-metal layer 402 forming the first pad, along with the semiconductor stack 704, may have an average layer thickness of less than or equal to 5 nm (e.g., in the range of 0.5 to 5 nm). Furthermore, the second half-metal layer 602 forming the second pad may have an average layer thickness of less than or equal to 5 nm (e.g., in the range of 0.5 to 5 nm). Additionally, the dielectric layer 502 (e.g., HfO, ZrO, or HfZrO) may have an average layer thickness of less than or equal to 5 nm (e.g., in the range of 0.5 to 5 nm), wherein the dielectric constant is greater than 30, or greater than 40, or greater than 50. In some embodiments, the dielectric layer 502 comprises a hafnium zirconium oxide dielectric layer having an average layer thickness of less than or equal to 5 nm (e.g., in the range of 0.5 to 5 nm), a dielectric constant greater than 30, or greater than 40, or greater than 50, and a stoichiometry (Hf:Zr) between 1:1 and 1:5, or between 1:1 and 1:4, or between 1:3, or between 1:2.

[0080] Benefits, other advantages, and solutions to problems have been described herein with reference to specific embodiments. However, these benefits, advantages, solutions to problems, and any elements that may lead to or make more significant any benefit, advantage, or solution should not be construed as key, essential, or necessary features or elements of this disclosure.

[0081] References to features, advantages, or similar language throughout this specification do not imply that all features and advantages achievable with this disclosure should be included in any single embodiment of the invention. Rather, language relating to features and advantages is to be understood as indicating that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the subject matter disclosed herein. Therefore, the discussion of features and advantages throughout this specification, as well as similar language, may refer to, but do not necessarily refer to the same embodiment.

[0082] Furthermore, the features, advantages, and characteristics described in this disclosure may be combined in one or more embodiments in any suitable manner. Those skilled in the art will recognize that the subject matter of this application may be practiced without one or more specific features or advantages of a particular embodiment. In other instances, additional features and advantages that may not be present in all embodiments of this disclosure may be recognized in certain embodiments. No claim element is intended to invoke 35 USC 112(f) unless such element is explicitly stated using the phrase “for means”.

[0083] The scope of this disclosure is limited only by the appended claims, wherein, unless expressly stated, the singular form of an element does not mean "one and only one," but rather "one or more." It should be understood that, unless specifically stated, references to "a," "an," and / or "the" can include one or more, and references to singular items can also include plural items. Furthermore, the term "a plurality of" can be defined as "at least two." As used herein, when used with a list of items, the phrase "at least one" means that different combinations of one or more of the listed items may be used, and that only one item from the list may be required. The item can be a particular object, thing, or category. Furthermore, when phrases like "at least one of A, B, and C" are used in the claims, the phrase is intended to be interpreted as meaning that A may exist alone in one embodiment, B may exist alone in one embodiment, C may exist alone in one embodiment, or any combination of elements A, B, and C may exist in a single embodiment; for example, A and B, A and C, B and C, or A, B, and C. In some cases, "at least one of project A, project B and project C" can mean, for example, but not limited to, two projects A, one project B and ten projects C; four projects B and seven projects C; or some other suitable combination.

[0084] All scopes and ratio limits disclosed herein can be combined. Unless otherwise stated, the terms “first,” “second,” etc., are used herein only as labels and are not intended to impose any order, position, or rank requirement on the items referred to by these terms. Furthermore, references to items such as “second” do not require or exclude the existence of items such as “first” or lower numbered, and / or items such as “third” or higher numbered.

[0085] Any references to attachment, fixation, connection, etc., may include permanent, removable, temporary, partial, complete, and / or any other possible attachment options. Furthermore, any reference to non-contact (or similar phrases) may also include reduced contact or minimal contact. Certain terms such as “upper,” “lower,” “upper part,” “lower part,” “horizontal,” “vertical,” “left,” “right,” etc., may be used in the above description. These terms are used where applicable to provide some clarity when dealing with relative relationships. However, these terms do not imply absolute relationships, positions, and / or orientations. For example, for an object, the “upper” surface can simply become the “lower” surface by flipping the object. Nevertheless, it remains the same object.

[0086] Furthermore, instances of one element being "connected" to another element in this specification can include direct and indirect connections. A direct connection can be defined as one element being connected to another element and having some contact with the other element. An indirect connection can be defined as a connection between two elements that are not in direct contact with each other, but have one or more additional elements between the connected elements. Additionally, as used herein, securing one element to another element can include direct and indirect securing. Furthermore, as used herein, "adjacent" does not necessarily mean contact. For example, one element may be adjacent to another element without contacting it.

[0087] While exemplary embodiments of this disclosure are set forth herein, it should be understood that this disclosure is not limited thereto. For example, although reactor systems are described in conjunction with various specific configurations, this disclosure is not necessarily limited to these examples. Various modifications, variations, and enhancements may be made to the systems and methods set forth herein without departing from the spirit and scope of this disclosure.

[0088] The subject matter of this disclosure includes all novel and non-obvious combinations and sub-combinations of various systems, components and configurations, as well as other features, functions, actions and / or properties disclosed herein, and any and all equivalents thereof.

Claims

1. A method of forming a semiconductor stack on a substrate for use in a metal- insulator-metal (MIM) capacitor, the method comprising: forming a first electrode layer comprising a conductive material on a substrate; forming a first semimetal layer on the first electrode layer; and forming a dielectric layer on the first semimetal layer; wherein the first semimetal layer forms a first liner between the first electrode layer and the dielectric layer. The first semimetal layer is an elemental semimetal layer.

2. The method of claim 1, wherein, The first electrode layer, the first semimetal layer, and the dielectric layer are formed by an atomic layer deposition process.

3. The method of claim 2, wherein, Atomic layer deposition of the first electrode layer, the first semimetal layer, and the dielectric layer are performed within the same semiconductor processing equipment.

4. The method of claim 3, wherein, Atomic layer deposition of the first electrode layer, the first semimetal layer, and the dielectric layer are performed within a first reaction chamber without breaking vacuum.

5. The method of claim 4, wherein, The first semimetal layer comprises antimony, bismuth, or tellurium.

6. The method of claim 5, wherein, Forming the first semimetal layer comprises:

7. The method of claim 1, wherein, depositing a first metal oxide layer on the first electrode layer by an atomic layer deposition process; and post-deposition heat treating the first metal oxide layer in a reducing atmosphere to convert the first metal oxide layer to the first semimetal layer. Atomic layer deposition of the first electrode layer, the first metal oxide layer, and the dielectric layer and post-deposition heat treating of the first metal oxide layer are performed within the first reaction chamber without breaking vacuum.

8. The method of claim 7, wherein, The first semimetal layer comprises alpha-tin (a-Sn).

9. The method of claim 8, wherein, 10. The method of claim 1, further comprising: forming a second semimetal layer on the dielectric layer; and forming a second electrode layer on the second semimetal layer; wherein the second semimetal layer forms a second liner between the dielectric layer and the second electrode layer. The first electrode layer, the first semimetal layer, the dielectric layer, the second semimetal layer, and the second electrode layer are formed by an atomic layer deposition process in the first reaction chamber without breaking vacuum. The second semimetal layer comprises an elemental semimetal layer.

11. The method of claim 10, wherein, The second semimetal layer comprises antimony, bismuth, or tellurium.

12. The method of claim 11, wherein, Forming the second semimetal layer further comprises:

13. The method of claim 12, wherein, depositing a second metal oxide layer on the dielectric layer by an atomic layer deposition process; and 14. The method of claim 13, wherein, post-deposition heat treating the second metal oxide layer in a reducing atmosphere to convert the second metal oxide layer to the second semimetal layer. The dielectric layer comprises a hafnium zirconium oxide (HfZrO) dielectric layer. The hafnium zirconium oxide (HfZrO) dielectric layer is formed by performing one or more supercycles of an atomic layer deposition process, each supercycle comprising:

15. The method of claim 1, wherein, performing one or more repetitions of a hafnium oxide subcycle; and 16. The method of claim 15, wherein, performing one or more repetitions of a zirconium oxide subcycle; wherein the hafnium zirconium oxide (HfZrO) dielectric layer has a stoichiometry (Hf:Zr) between 1:1 and 1:

5.

17. A method of forming a semiconductor stack on a substrate for use in a metal- insulator-metal (MIM) capacitor, the method comprising: depositing a first electrode layer comprising a conductive material on a substrate; forming a first semimetal layer directly on the first electrode layer; depositing a hafnium zirconium oxide (HfZrO) dielectric layer directly on the first semimetal layer; ​ ​ forming a second semi-metal layer directly on the hafnium zirconium oxide (HfZrO) dielectric layer; and depositing a second electrode layer directly on the second semi-metal layer; wherein the first semi-metal layer forms a first liner between the first electrode layer and the hafnium zirconium oxide dielectric layer, and the second semi-metal layer forms a second liner between the hafnium zirconium oxide (HfZrO) dielectric layer and the second electrode layer.

18. The method of claim 17, wherein, The first semi-metal layer and the second semi-metal layer comprise a material selected from the group consisting of antimony, bismuth, tellurium, and alpha-tin (a-Sn).

19. The method of claim 18, wherein, The semiconductor stack is formed within the first reaction chamber by an atomic layer deposition process without breaking vacuum.

20. The method of claim 19, wherein, The first semi-metal layer and the second semi-metal layer are alpha-tin (a-Sn), formed by: depositing a first tin oxide layer on the first electrode layer by an atomic layer deposition process; depositing a second tin oxide layer on the hafnium zirconium dielectric layer; and post-deposition heat treating the first tin oxide layer and the second tin oxide layer in a reducing atmosphere to convert the first tin oxide layer to a first alpha-tin (first a-Sn) semi-metal layer and the second tin oxide layer to a second alpha-tin (second a-Sn) semi-metal layer.

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