Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. There is provided a method of manufacturing a semiconductor device, the method including: forming an insulating film on a semiconductor substrate; selectively removing the insulating film; forming a metal film on the semiconductor substrate by leaving a damaged layer on the surface of the semiconductor substrate, the damaged layer being generated when the insulating film is selectively removed; forming an electrode by selectively removing the metal film; and forming a polyimide on the electrode. A damaged layer of the surface of the semiconductor substrate generated when the insulating film is selectively removed may be selectively removed.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Japanese Patent Application No. 2024-145046, filed on August 27, 2024, the contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductors, and more specifically, to a semiconductor device and a method of manufacturing the same. Background Technology

[0004] The following is a publicly available technology.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2024-54039

[0006] Patent Document 1 discloses a method for manufacturing a semiconductor device, which includes performing wet etching in a contact step connecting a semiconductor substrate and one or more metal wirings to reduce damage to the surface of the semiconductor substrate due to dry etching. Summary of the Invention

[0007] However, if etching is performed to reduce damage to the surface of the semiconductor substrate, there is a problem of generating silicon pits in one or more subsequent steps. Therefore, the object of this disclosure is to provide a method for manufacturing a semiconductor device, etc., that forms a metal film by leaving a damage layer on the surface of the semiconductor substrate to suppress the formation of silicon pits.

[0008] Other issues and novel features will become clear from this specification and the accompanying drawings.

[0009] According to one embodiment, a method of manufacturing a semiconductor device forms a metal layer on a semiconductor substrate by leaving a damage layer on the surface of the semiconductor substrate, the damage layer being generated when an interlayer insulating film is selectively removed.

[0010] According to this embodiment, a method for manufacturing a semiconductor device can be provided, which forms a metal film by leaving a damage layer on the surface of a semiconductor substrate. Attached Figure Description

[0011] Figure 1 This is a top view of the first semiconductor device according to the present disclosure;

[0012] Figure 2 yes Figure 1 VIB-VIB cross-sectional view of a semiconductor device;

[0013] Figure 3This is a first cross-sectional view of a semiconductor device, which illustrates the manufacturing method of the relevant semiconductor device;

[0014] Figure 4 This is a second cross-sectional view of a semiconductor device, which illustrates the manufacturing method of the relevant semiconductor device;

[0015] Figure 5 This is a third cross-sectional view of a semiconductor device, which illustrates the manufacturing method of the relevant semiconductor device;

[0016] Figure 6 This is the fourth cross-sectional view of the semiconductor device, which illustrates the manufacturing method of the relevant semiconductor device;

[0017] Figure 7 This is the fifth cross-sectional view of the semiconductor device, which illustrates the manufacturing method of the relevant semiconductor device;

[0018] Figure 8 The VI characteristics of a semiconductor device when silicon pits are generated and the VI characteristics of a semiconductor device when silicon pits are not generated are shown.

[0019] Figure 9 This is a schematic diagram of silicon pits formed in semiconductor devices;

[0020] Figure 10 It is a flowchart of the manufacturing method of the relevant semiconductor device;

[0021] Figure 11 It is a cross-sectional view of the manufacturing method of the relevant semiconductor device;

[0022] Figure 12 This is a view showing the relationship between photoetching time and VF characteristics;

[0023] Figure 13 This is a flowchart of a method for manufacturing a semiconductor device according to the present disclosure;

[0024] Figure 14 This is a cross-sectional view of the first manufacturing step of the semiconductor device according to the present disclosure;

[0025] Figure 15 This is a cross-sectional view of the second manufacturing step of the semiconductor device according to the present disclosure;

[0026] Figure 16 This is a cross-sectional view illustrating the formation principle of silicon pits;

[0027] Figure 17 This is a view showing the relationship between the width and depth of a silicon pit;

[0028] Figure 18This is a view showing the path of the current when a probe is applied to the location where a silicon pit is formed;

[0029] Figure 19 This is a view showing the path of the current when the bonding wire is applied to the location where the silicon pit is formed;

[0030] Figure 20 This is a view showing the spacing of silicon pits;

[0031] Figure 21 This is a view showing the simulation results illustrating the relationship between the spacing of silicon pits and VR characteristics;

[0032] Figure 22 This is a top view of the second semiconductor device according to the present disclosure; and

[0033] Figure 23 yes Figure 22 XXI-XXI cross-sectional view of a semiconductor device. Detailed Implementation

[0034] Example

[0035] In the following description, embodiments of the invention will be illustrated with reference to the accompanying drawings. However, the invention according to the claims is not limited to the embodiments described below. Furthermore, all configurations described in the embodiments are not necessarily necessary means to solve the problem. For clarity, the descriptions and drawings mentioned below will be appropriately omitted and simplified. In each drawing, the same reference numerals denote the same components, and repeated descriptions will be omitted where necessary.

[0036] Description of the semiconductor device disclosed herein

[0037] Figure 1 This is a top view of the first semiconductor device according to the present disclosure. Figure 2 yes Figure 1 A VIB-VIB cross-sectional view of a semiconductor device. (Refer to...) Figure 1 and Figure 2 This describes a first semiconductor device according to the present disclosure.

[0038] like Figure 1 As shown, when viewed from the upper surface of the semiconductor substrate, the semiconductor device according to this disclosure is formed in a rectangular shape. In this example, although it is formed in a rectangular shape, the semiconductor device can be formed as a rectangle without corners, a circle, an integral shape, etc., to occupy a specific area of ​​the semiconductor substrate. The semiconductor device 100 has an anode pad 101 at the center, and polyimide 102 surrounding the anode pad when viewed from the upper surface.

[0039] like Figure 2As shown, the semiconductor device according to this disclosure has a cathode electrode 24 and an N electrode sequentially arranged from the bottom. + Type semiconductor region 201, N - Type drift region 11, P-type body region 14, interlayer insulating film 21, metal layer 23, anode electrode AE, anode pad 101 and polyimide 102.

[0040] The semiconductor device according to this disclosure is formed by P + Type semiconductor region and N - A diode with a PN junction in the N-type drift region. Semiconductor devices may not have an N-type drift region. + Type semiconductor region 201.

[0041] Description of manufacturing methods for related semiconductor devices

[0042] Figure 3 This is a first cross-sectional view of a semiconductor device, which illustrates the manufacturing method of the relevant semiconductor device. Figure 4 This is a second cross-sectional view of a semiconductor device, which illustrates the manufacturing method of the relevant semiconductor device. Figure 5 This is a third cross-sectional view of a semiconductor device, which illustrates the manufacturing method of the relevant semiconductor device. Figure 6 This is the fourth cross-sectional view of the semiconductor device, which illustrates the manufacturing method of the relevant semiconductor device. Figure 7 This is the fifth cross-sectional view of the semiconductor device, illustrating the manufacturing process of the device. (Refer to...) Figures 3 to 7 This describes a method for manufacturing a semiconductor device according to the present disclosure. Figures 3 to 7 A cross-sectional view is shown, which illustrates... Figure 2 The manufacturing steps of the semiconductor device are shown.

[0043] First, such as Figure 3 As shown, a semiconductor wafer is fabricated from a silicon single-crystal semiconductor substrate 1a in which N-type impurities such as phosphorus are introduced. The semiconductor wafer has an upper surface 1a and a rear surface 1b opposite to the upper surface 1a.

[0044] The concentration of N-type impurities in a semiconductor wafer can be set, for example, to approximately 2 × 10⁻⁶. 14 cm -3 The thickness of a semiconductor wafer can be set, for example, from about 450 micrometers to 1000 micrometers.

[0045] Next, a silicon nitride film (Si3N4) is formed on the upper surface of the semiconductor wafer, and a Si3N4 film mask is formed by patterning the Si3N4 film. Device isolation region 12 is formed by oxidizing the upper surface of the semiconductor wafer in the area outside the Si3N4 film mask region under an oxidizing atmosphere.

[0046] Next, using ion implantation with a resist pattern as a mask, P-type impurities are introduced into the semiconductor substrate 1s on the upper surface 1a side of the semiconductor wafer, thereby forming a P-type field region 13. As suitable ion implantation conditions at this time, the following ion implantation conditions can be used, for example, where the ion type is set to boron (B) and the dose is set to approximately 3.5 × 10⁻⁶. 13 cm -2 Furthermore, the ion implantation energy was set to approximately 75 keV.

[0047] Next, after removing the resist, annealing is performed for about 30 minutes in a nitrogen (N2) atmosphere as an inert gas at, for example, about 1200 degrees Celsius, and crystal defects in the P-type field region 13 are repaired and pulled diffusion is performed.

[0048] Next, as Figure 4 As shown, P-type impurities are introduced into necessary portions of cell region 2a and scribe region 3 by ion implantation using a resist pattern as a mask, thereby forming P-type body region 14.

[0049] Specifically, the P-type body region 14 is formed in the P-type field region 13 and N formed in the unit region 2a. - On the drift region 11 (1s). Furthermore, the P-type body region 14 is formed in the N-type region 3. - Drift zone 11 (1s) on.

[0050] As suitable ion implantation conditions at this time, the following ion implantation conditions can be used, where, for example, the ion type is set to B and the dose is set to approximately 1 × 10⁻⁶. 13 cm -2 The injection energy was set to approximately 75 keV. After removing the resist, annealing was performed for approximately 100 minutes in an N2 atmosphere at, for example, approximately 1000 degrees Celsius.

[0051] Next, as Figure 5 As shown, N is implanted using an ion implantation method that employs a resist pattern as a mask. - Type I impurities introduce N into peripheral region 2b - On the drift region 11 (1s) and the P-type body region 14 in the scribing region 3, N is formed. + Type semiconductor region 15.

[0052] As suitable ion implantation conditions at this time, the following ion implantation conditions can be used, where, for example, the ion type is set to arsenic (As) and the dose is set to approximately 5 × 10⁻⁶. 15 cm -2The injection energy was set to approximately 80 keV. After removing the resist, annealing was performed for approximately 100 minutes in an N2 atmosphere at, for example, approximately 1000 degrees Celsius.

[0053] Next, as Figure 6 As shown, an interlayer insulating film 21, made of, for example, phosphosilicate glass (PSG) film, is formed on the upper surface 1a of a semiconductor wafer by, for example, CVD. The interlayer insulating film 21 is formed to cover, for example, N... - Type 11 drift region (1s), P-type field region 13, P-type body region 14 and N-type drift region 15 + Semiconductor region 15. The thickness of the interlayer insulating film 21 is, for example, about 0.6 micrometers. As the material for the interlayer insulating film 21, borosilicate glass (BPSG) film, undoped silicate glass (NSG) film, spin-coated glass (SOG) film, silicon oxide (SiO2) film, and composite films made from these can be used as suitable materials.

[0054] Next, contact holes (openings) 22 are formed in the interlayer insulating film 21 using an anisotropic dry etching method with a resist pattern as a mask. Suitable gases for this anisotropic dry etching include, for example, a mixture of argon (Ar), trifluoromethane (CHF3), and tetrafluoromethane (CF4).

[0055] Subsequently, to reduce damage to the upper surface of the semiconductor substrate caused by dry etching, after removing the resist, the contact hole 22 and the semiconductor substrate 1s are etched using the SEZ wet etching method, with the interlayer insulating film 21 as a mask. For example, a suitable etchant for SEZ dry etching is a mixture of nitric acid (HNO3):hydrogen fluoride (HF) = 200:1. Alternatively, the contact hole 22 and the semiconductor substrate 1s can be etched by dry etching instead of SEZ wet etching. For example, a mixture of oxygen (O2) and tetrafluoromethane (CF4) can be used as the gas for this dry etching.

[0056] Next, as Figure 7 As shown, a metal layer 23, such as an anode electrode AE, is formed. Specifically, for example, the following process is performed. First, an aluminum-based metal film (e.g., a certain percentage of silicon addition and the remainder aluminum) is formed on the entire upper surface 1a of the semiconductor wafer by, for example, sputtering, to embed contact holes 22. The thickness of the aluminum-based metal film is, for example, about 5 micrometers.

[0057] Next, a metal layer 23 made of an aluminum-based metal film is formed by a dry etching method using a resist pattern as a mask. Suitable gases for this dry etching process include, for example, chlorine (Cl2) gas / boron trichloride (BCl3) gas.

[0058] Therefore, in unit region 2a, the anode electrode AE ​​is formed in the contact hole 22 and on the interlayer insulating film 21. In scribe region 3, electrode pads 42 and 43 are formed in the contact hole 22 and on the interlayer insulating film 21. Here, the metal layer 23 in the contact hole 22 is referred to as the contact portion.

[0059] The anode electrode AE ​​is electrically connected to the P-type body region 14 formed in unit region 2a. Electrode pad 42 is electrically connected to the P-type body region 14 formed in scribing region 3, and electrode pad 43 is electrically connected to the N-type body region formed in scribing region 3. + Type semiconductor region 15.

[0060] Next, an insulating film, which serves as a passivation film, is formed on the anode electrode. This film is made of an organic film containing polyimide as the main component. The thickness of the insulating film is, for example, about 2.5 micrometers to 10 micrometers.

[0061] Next, the insulating film is patterned using a dry etching method with a resist pattern as a mask, forming an opening that penetrates the insulating film and reaches the anode electrode AE. Then, an anode pad formed by the anode electrode AE ​​is formed in the portion exposed from the opening.

[0062] Next, the back surface 1b of the semiconductor wafer is back-polished, for example,

[0063] If necessary, the thickness of approximately 800 micrometers can be reduced to approximately 30 to 200 micrometers. For example, with a breakdown voltage of approximately 600V, the final thickness is approximately 70 micrometers. Furthermore, if necessary, chemical etching or similar processes can be performed to remove damage to the back surface 1b.

[0064] Next, for example by sputtering, an electrical connection to N is formed on the back surface 11b of the semiconductor wafer. - The cathode electrode 24 of the drift region 11 (1s). Then, by cutting or the like, the semiconductor substrate 1s is divided into one or more semiconductor chip regions 2, and if necessary, by sealing it at the package, the semiconductor chip as a semiconductor device is almost completed.

[0065] Formation of silicon pits in semiconductor devices

[0066] Figure 8 The VI characteristics of a semiconductor device when silicon pits are generated and the VI characteristics of a semiconductor device when silicon pits are not generated are shown. Figure 9This is a schematic diagram of silicon pits formed on semiconductor devices. Figure 10 It is a flowchart of the manufacturing method of the relevant semiconductor device. Figure 11 It is a cross-sectional view of the manufacturing method of the relevant semiconductor device.

[0067] like Figure 8 As shown, in the relevant semiconductor devices, when measuring the V1 characteristic, diodes have been manufactured as good products, in which the current rises sharply at a certain voltage, such as C; and as defective products, in which the current leaks and gradually rises, such as A and B. In the defective product diodes, silicon pits, which are openings in the silicon, have been formed. Therefore, A and B, where silicon pits are formed, are defective products, while C is a good product.

[0068] like Figure 9 As shown, silicon pits are also formed in the good products, but the silicon pits have not yet reached the depletion layer. For example, when the depletion layer is 0.5 micrometers, the depth of the silicon pits in the good products is about 0.5 micrometers or less, such as in the center or on the right side, while the silicon pits in the defective products exceed 0.5 micrometers and reach 1 micrometer.

[0069] like Figure 10 and Figure 11 As shown, the formation of silicon pits can be imagined as follows. First, an opening is made in the anode contact area by dry etching (step S1001). The opening is formed by selectively removing insulating films (such as interlayer insulating films) on the semiconductor substrate. By doing so, as... Figure 11 As shown in the upper figure, a damage layer 1101 is formed on the P-type body region 14 in the opening. The damage layer 1101 is an unterminated layer, such as a low-valence oxide of silicon.

[0070] Next, the damaged layer is removed by photolithography (step S1002). For example... Figure 11 As shown in the second figure, the damaged layer 1101 is removed. Next, an AlSi electrode is formed (step S1003). Figure 11 As shown in the third figure, the anode electrode AE ​​is formed from AlSi. At this time, a trench 1102 reaching the silicon can be formed.

[0071] Finally, after anode formation, a silicon pit is formed by injecting an alkaline liquid into trench 1102 using a polyimide formation step. In a subsequent heat treatment step, the injected chemical liquid is vaporized. Additionally, the electrode is reflowed and embedded into the silicon pit portion (step S1004). Figure 11 As shown in the last figure, silicon pits reach N - Type 11 drift region is formed.

[0072] It is conceivable that this situation is a factor contributing to leakage current. Therefore, there is a need for manufacturing methods of semiconductor devices that suppress silicon pit formation.

[0073] Description of the first manufacturing method of the semiconductor device disclosed herein

[0074] Figure 12 This is a view showing the relationship between photoetching time and VF characteristics. Figure 13 This is a flowchart of a method for manufacturing a semiconductor device according to the present disclosure. Figure 14 This is a cross-sectional view of the first manufacturing step of the semiconductor device according to this disclosure. (Refer to...) Figure 13 and Figure 14 A first method for manufacturing a semiconductor device according to the present disclosure is described.

[0075] The inventors have discovered that in the manufacturing method of related semiconductor devices, silicon pits are generated when the damaged layer is removed in step S1002. Furthermore, the inventors have discovered that, as Figure 12 As shown, for example, by performing photo-etching for 10 to 20 seconds, the VF characteristic as a resistor will decrease, and unless photo-etching is performed, the VF characteristic will decrease further.

[0076] Therefore, as Figure 13 As shown, according to the first manufacturing method of the semiconductor device of this disclosure, an opening is made in the anode contact portion by dry etching (step S1301). Figure 14 As shown in the upper figure, a damage layer 1101 is formed through the anode opening. Next, the photolithography used to remove the damage layer (step S1302) is skipped. Figure 14 As shown in the second figure, a damaged layer 1101 is left. Next, an AlSi electrode is formed (step S1303). Figure 4 As shown in the third figure, the anode electrode AE ​​is formed.

[0077] Finally, an alkaline liquid is injected via a polyimide formation step, but the injected chemical liquid is vaporized via a subsequent heat treatment step (step S1304). Figure 14 As shown in the last figure, no silicon pits are formed in the semiconductor device.

[0078] In this way, in order to suppress the formation of silicon pits when polyimide is formed after the metal film is formed, a method for manufacturing a semiconductor device can be provided in which a damage layer is left and a metal film is formed on the upper surface of a semiconductor substrate.

[0079] Furthermore, the semiconductor device manufactured in this manner has an insulating film selectively disposed on a semiconductor substrate, electrodes formed from metal films selectively disposed on the semiconductor substrate, and polyimide on the electrodes. Additionally, when the insulating film is selectively removed, the semiconductor device has a damage layer beneath the electrodes.

[0080] Description of the second manufacturing method of the semiconductor device according to this disclosure

[0081] Figure 15 This is a cross-sectional view of the second manufacturing step of the semiconductor device according to the present disclosure. Figure 16 This is a cross-sectional view illustrating the formation principle of silicon pits. Figure 17 This is a view showing the relationship between the width and depth of a silicon pit. Figure 18 This is a view showing the path of the current when a probe is applied to the location where a silicon pit is formed. Figure 19 This is a view showing the path of current when a bonding wire is applied to the location where a silicon pit is formed. Figure 20 This is a view showing the spacing of silicon pits. Figure 21 This is a view showing the simulation results illustrating the relationship between the spacing of silicon pits and VR characteristics. (Refer to...) Figures 15 to 21 A second manufacturing method for a semiconductor device according to this disclosure is described.

[0082] The second manufacturing method for the semiconductor device according to this disclosure involves controlling the formation of silicon pits. For example... Figure 15 As shown in the upper figure, the damaged layer 1101 is formed in the opening of the anode electrode contact. Next, as... Figure 15 As shown in the second figure, the damaged layer 1101 is selectively removed by forming a mask 1103. The photoetching time is preferably 10 to 20 seconds.

[0083] Next, as Figure 15 As shown in the third figure, the anode electrode AE ​​is formed. At this point, a trench 1102 reaching the silicon is formed in the anode electrode AE. Next, as... Figure 15 As shown in the last figure, silicon pits are formed by reflowing the anode electrode AE ​​after the polyimide is formed. However, silicon pits are not formed in the portions where the damaged layer is not removed, and silicon pits are also selectively formed at certain locations.

[0084] By selectively removing the damaged layer in this manner, a method for manufacturing a semiconductor device and the resulting semiconductor device are obtained, in which the formation of silicon pits can be controlled.

[0085] Figure 16 The etching of silicon due to the injection of an alkaline liquid is shown. (As shown) Figure 16As shown, when an opening exists in the damaged layer, the P-type body region 14 is etched to form a tandem shape with the upper surface. -1 √2 = 54.7 degrees (tan -1 (2) 1 / 2 =54.7 degrees). This is because, if we assume the upper surface is oriented in a {100} plane, then its side surface is oriented in a {111} plane. If we assume its depth is D, then D is represented by D = (size of the opening X) multiplied by tan(54.7 degrees) / 2, as... Figure 17 As shown. If the size X of the damaged layer to be removed is 2 times (the thickness to the depletion layer) / tan(54.7 degrees), then the silicon pit will never reach the depletion layer.

[0086] Therefore, the region in which the damaged layer is removed is preferably smaller than (the thickness of the depletion layer of the semiconductor device) multiplied by 2 / tan(54.7 degrees). For example, if the depletion layer is generated from 500 nm, the region in which the damaged layer is removed preferably has a width of 708 nm. In this way, the depth of the silicon pit can be controlled by controlling the width used to remove the damaged layer.

[0087] like Figure 18 As shown, the probe 1801 used for wafer testing can be placed in the area where silicon pits are formed. Figure 12 As shown, due to the VF characteristic, current flows more easily when the etching time is 0, while it becomes difficult for current to flow if photolithography is performed. Therefore, by placing the probe 1801 in the region where the selectively formed silicon pit is created, current concentration caused by the probe 1801 can be prevented. Therefore, the region where the damaged layer is selectively removed is preferably suited to be combined with the region where the probe 1801 is placed.

[0088] like Figure 19 As shown, bonding wire 1901 can be placed in the region where the silicon pit is formed. By placing bonding wire 1901 in the region where the selectively formed silicon pit is formed, current concentration caused by bonding wire 1901 can be prevented, similar to probe 1801. Therefore, the region where the damaged layer 1101 is selectively removed is preferably suited to be combined with the region where bonding wire 1901 is placed.

[0089] Reference Figure 20 and Figure 21 Consider the pit spacing. For example... Figure 20 and Figure 21 As shown, when simulations are performed by changing the pit spacing, the pit spacing becomes an avalanche point due to the electric field concentration at the tips of the silicon pits, and the breakdown voltage decreases according to the pit shape. Figure 21As shown in the simulation, it can be understood that when the pit spacing is 10 micrometers or smaller, such as 5 micrometers, the VR characteristic, which is a breakdown voltage characteristic, increases. Reducing the pit spacing can bring about the field plate effect, alleviate the electric field at the pit tip, and improve the breakdown voltage characteristics. Therefore, as Figure 20 As shown, by selectively removing the damaged layer, the pit spacing is 10 micrometers or less, preferably 5 micrometers or less.

[0090] Description of the second semiconductor device according to this disclosure

[0091] Figure 22 This is a top view of the second semiconductor device according to the present disclosure. Figure 23 yes Figure 22 XXI-XXI cross-sectional view of the semiconductor device. (Refer to...) Figure 22 and Figure 23 A second semiconductor device according to this disclosure is described.

[0092] like Figure 22 and Figure 23 As shown, near the end of the anode electrode AE, current is carried over from the periphery during the recovery operation, making current concentration more likely to occur near the anode electrode AE. Therefore, to prevent current concentration, photolithography is performed near the end of the anode electrode AE. That is, the end of the anode electrode AE ​​is combined with the area where the damage layer 1101 is removed. By doing so, damage during the recovery operation is suppressed. For example, "near the end" is a range of approximately 5 to 100 micrometers from the end.

[0093] For example, the semiconductor device according to the above embodiments may have a configuration in which the conductivity type (p-type or n-type) of the semiconductor substrate, semiconductor layer, diffusion layer (diffusion region), etc., is reversed. Therefore, when one of the n-type and p-type conductivity types is the first conductivity type and the other conductivity type is the second conductivity type, it is possible to set the first conductivity type to p-type and the second conductivity type to n-type, and vice versa, and it is also possible to set the first conductivity type to n-type and the second conductivity type to p-type.

[0094] As described above, the inventors’ invention has been specifically described based on the embodiments, but the invention is not limited to the above embodiments, and needless to say, variations can be made without departing from its spirit.

Claims

1. A method of manufacturing a semiconductor device, the method comprising: forming an insulating film on a semiconductor substrate; selectively removing the insulating film; forming a metal film on the semiconductor substrate by leaving a damage layer of a surface of the semiconductor substrate generated when the insulating film is selectively removed; forming an electrode by selectively removing the metal film; and forming a polyimide on the electrode.

2. The method according to claim 1, wherein the damage layer of the surface of the semiconductor substrate generated when the insulating film is selectively removed is selectively removed.

3. The method according to claim 2, wherein an area in which the damage layer is removed is less than a thickness of a depletion layer of the semiconductor device multiplied by 2 / tan 54.7 degrees.

4. The method according to claim 2, wherein the removal of the damage layer is performed by performing a wet etching during 10 seconds to 20 seconds.

5. The method according to claim 2, wherein a probe or a wire for wafer testing is placed in an area in which the damage layer is removed.

6. The method according to claim 2, wherein a pitch of an area in which the damage layer is removed is 5 micrometers or less.

7. The method according to claim 2, wherein an area in which the damage layer is removed is close to an end of the electrode.

8. A semiconductor device comprising: an insulating film selectively disposed on a semiconductor substrate; an electrode formed from a metal film selectively disposed on the semiconductor substrate; and a polyimide on the electrode, wherein the semiconductor device has a damage layer under the electrode when the insulating film is selectively removed.

9. The semiconductor device according to claim 8, wherein the damage layer is selectively removed.

10. The semiconductor device according to claim 9, wherein an area in which the damage layer is removed is less than a thickness of a depletion layer of the semiconductor device multiplied by 2 / tan 54.7 degrees.

11. The semiconductor device according to claim 9, wherein a probe or a wire for wafer testing is placed in an area in which the damage layer is removed.

12. The semiconductor device according to claim 9, wherein a pitch of an area in which the damage layer is removed is 5 micrometers or less.

13. The semiconductor device according to claim 9, wherein an area in which the damage layer is removed is close to an end of the electrode. ​ ​

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