Semiconductor device

Abstract

The invention relates to a semiconductor device. A semiconductor device includes a semiconductor layer, a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third electrode, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type, and a fifth semiconductor region of the second conductivity type. The first electrode and the second electrode are provided on the first main surface and the second main surface of the semiconductor layer, respectively. The first semiconductor region is disposed in the semiconductor layer. The second semiconductor region is over the first semiconductor region. The third electrode faces the second semiconductor region with the insulating region interposed therebetween. The third semiconductor region is located on the second semiconductor region. The fourth semiconductor region is located between the first electrode and the first semiconductor region. The fifth semiconductor region is provided so as to be surrounded by the fourth semiconductor region, and has a lower impurity concentration than the fourth semiconductor region.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2024-1533840 (filed on September 5, 2024). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention generally relate to semiconductor devices. Background Technology

[0004] In semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), it is preferable to enable high-speed switching. Summary of the Invention

[0005] The semiconductor device of the embodiment includes a semiconductor layer, a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third electrode, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type, and a fifth semiconductor region of the second conductivity type. The semiconductor layer has a first main surface and a second main surface. The first electrode is disposed on the first main surface. The second electrode is disposed on the second main surface. The first semiconductor region is disposed within the semiconductor layer. The second semiconductor region is disposed within the semiconductor layer and located above the first semiconductor region. The third electrode is opposite to the second semiconductor region via an insulating region. The third semiconductor region is disposed within the semiconductor layer, located above the second semiconductor region, and electrically connected to the second electrode. The fourth semiconductor region is disposed within the semiconductor layer, located between the first electrode and the first semiconductor region, and electrically connected to the first electrode. The fifth semiconductor region is disposed within the semiconductor layer and surrounded by the fourth semiconductor region, and electrically connected to the first electrode. The impurity concentration of the fifth semiconductor region is lower than the impurity concentration of the fourth semiconductor region.

[0006] According to this embodiment, a semiconductor device capable of high-speed switching can be provided. Attached Figure Description

[0007] Figure 1 This is a top view of the semiconductor device according to the first embodiment.

[0008] Figure 2 This is a bottom view of the semiconductor device according to the first embodiment.

[0009] Figure 3 This is a cross-sectional view of the semiconductor device according to the first embodiment, along... Figure 1 andFigure 2 A cross-sectional view along line AA.

[0010] Figure 4 This is a bottom view of a semiconductor device according to a variation of the first embodiment.

[0011] Figure 5 This is a graph showing the evaluation results of the short-circuit withstand capability in the semiconductor devices of the first embodiment and the comparative example.

[0012] Figure 6A This is a cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0013] Figure 6B It continues Figure 6A A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0014] Figure 6C It continues Figure 6B A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0015] Figure 6D It continues Figure 6C A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0016] Figure 6E It continues Figure 6D A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0017] Figure 6F It continues Figure 6E A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0018] Figure 7 This is a bottom view of the semiconductor device according to the second embodiment.

[0019] Figure 8 This is a bottom view of a semiconductor device according to a variation of the second embodiment. Detailed Implementation

[0020] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the present invention. The drawings are schematic or conceptual, and the proportions of the parts may not be the same as in reality. In the specification and drawings, the same reference numerals are used for elements that have been described above with respect to the accompanying drawings, and detailed descriptions are omitted where appropriate.

[0021] In addition, for ease of explanation, such as Figures 1-3As shown, an orthogonal XYZ coordinate system is used. The Z-axis direction is the stacking direction (thickness direction) of the semiconductor device. Additionally, the emitter electrode side in the Z-axis direction is referred to as "upper," and the collector electrode side as "lower." However, this representation is for convenience and is independent of the direction of gravity.

[0022] Additionally, in the following explanation, to indicate the relative levels of impurity concentration in each conductivity type, n is sometimes used. + n, n - and p + p, p - The expression. That is, n + This indicates that the concentration of n-type impurities is relatively higher than that of n, n - This indicates that the concentration of n-type impurities is relatively lower than that of n. Additionally, p... + This indicates that the concentration of p-type impurities is relatively higher than that of p-type impurities. - This indicates that the concentration of p-type impurities is relatively lower than that of n-type impurities. These statements, when both p-type and n-type impurities are present in various regions, represent the relative levels of the actual impurity concentrations after these impurities have compensated for each other. n-type, n... + type and n - p-type is an example of the first conductivity type in the claims. + Type and p - The n-type is an example of the second conductivity type in the claims. Furthermore, in the following description, the n-type and p-type can also be reversed. That is, the first conductivity type can also be p-type.

[0023] Furthermore, the impurity concentration in the semiconductor region can be determined, for example, by secondary ion mass spectrometry (SIMS). Additionally, the relative level of impurity concentration can be determined, for example, by the carrier concentration obtained through scanning capacitance microscopy (SCM).

[0024] In addition, dimensions such as the width of semiconductor regions can be determined, for example, by surface and cross-sectional analysis using Transmission Electron Microscope (TEM), Energy Dispersive X-ray spectroscopy (EDX), and Scanning Electron Microscope (SEM).

[0025] (First Implementation)

[0026] Reference Figures 1-3The semiconductor device 1 of the first embodiment will be described. Figure 1 is a plan view of the semiconductor device 1 of the first embodiment. Figure 2 is a bottom view of the semiconductor device 1 of the first embodiment. Figure 3 is a sectional view of the semiconductor device 1 of the first embodiment, taken along Figure 1 and Figure 2 A-A line. In addition, the emitter electrode 12 is omitted in Figure 1 , and the collector electrode 11 is omitted in Figure 2 .

[0027] The semiconductor device 1 is, for example, an IGBT. In the present embodiment, a case where the semiconductor device 1 is a vertical type IGBT having a trench gate structure will be described. Note that the semiconductor device 1 can also be a vertical type IGBT having a planar gate structure, or the like.

[0028] As shown in Figure 3 , the semiconductor device 1 of the present embodiment includes a semiconductor layer 2, a collector electrode 11, an emitter electrode 12, a gate electrode 13, and an insulating region 30.

[0029] The semiconductor layer 2 has a lower surface 2a, an upper surface 2b on the opposite side of the lower surface 2a, and a side portion 2c. The lower surface 2a and the upper surface 2b are each an example of the first main surface and the second main surface in the claims.

[0030] In addition, the semiconductor layer 2 has an outer peripheral region OA extending from the side portion 2c of the semiconductor layer 2 toward the inner side of the semiconductor layer 2, and an inner side region IA inward of the outer peripheral region OA. The inner side region IA is a region that becomes a main path of current at the time of operation of the semiconductor device 1, and is also referred to as a cell region. In Figures 1-3 , reference sign B1 indicates the boundary between the outer peripheral region OA and the inner side region IA. As shown in Figure 1 and Figure 2 , the outer peripheral region OA located outward of the boundary B1 surrounds the inner side region IA located inward of the boundary B1.

[0031] As shown in Figure 3 , an n-base region 21, a buffer region 22, a p-base region 23, an emitter region 24, a collector region 25, a low concentration region 26, a low concentration region 27, and a guard ring region 28 are provided, for example, within the semiconductor layer 2. Details of these regions are described later.

[0032] Semiconductor layer 2 can be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate and an epitaxial layer disposed thereon. In this embodiment, semiconductor layer 2 is silicon (Si). In this case, arsenic (As), phosphorus (P), or antimony (Sb) is used as an n-type impurity, and boron (B) is used as a p-type impurity.

[0033] The collector electrode 11 functions as the collector of the IGBT. The collector electrode 11 is disposed on the lower surface 2a of the semiconductor layer 2, and is in contact with the collector region 25, the low-concentration region 26, and the low-concentration region 27. The collector electrode 11 is an example of the first electrode in the claims. The collector electrode 11 is, for example, made of a material comprising at least one of aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), etc.

[0034] The emitter electrode 12 functions as the emitter electrode of the IGBT. The emitter electrode 12 is disposed on the upper surface 2b of the semiconductor layer 2, and is in contact with the p-base region 23, the emitter region 24, and the protective region. The emitter electrode 12 is an example of the second electrode described in the claims. The emitter electrode 12 is, for example, made of a material comprising at least one of aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), etc.

[0035] The gate electrode 13 functions as the gate electrode of the IGBT. The gate electrode 13 is positioned opposite the p-base region 23 via an insulating region 30. In this embodiment, the gate electrode 13 is disposed within the p-base region 23 via the insulating region 30, and is electrically insulated from the emitter electrode 12 and the semiconductor layer 2 by the insulating region 30. The gate electrode 13 is an example of the third electrode in the claims. The gate electrode 13 is, for example, made of polysilicon containing p-type or n-type impurities. When a voltage is applied to the gate electrode 13, a channel is formed in the p-base region 23, and charge carriers flow between the n-base region 21 and the emitter region 24. Thus, the IGBT becomes in the on state.

[0036] The insulating region 30 is provided in such a way that it covers the upper surface of the gate electrode 13 and the sidewalls of a plurality of trenches disposed on the upper surface 2b of the semiconductor layer 2. The insulating region 30 is, for example, an insulating film comprising silicon oxide or silicon nitride.

[0037] Next, a detailed description of each region located within semiconductor layer 2 will be provided.

[0038] like Figure 3 As shown, the n-base region 21 functions as the n-base region (drift region) of the IGBT. Figure 3 As shown, the n-base region 21 is located above the buffer region 22 (above the collector electrode 11). The n-base region 21 is, for example, n... -The n-type semiconductor region. The n-type impurity concentration of the n-base region 21 is, for example, 1 × 10⁻⁶. 12 cm -3 Above and 1×10 15 cm -3 the following.

[0039] Buffer region 22 functions as a buffer region for the IGBT. Buffer region 22 is located between the n-base region 21 and the collector region 25. Buffer region 22 is, for example, n... + The buffer region 22 is a type of semiconductor region. Specifically, the n-type impurity concentration in the buffer region 22 is higher than that in the n-base region 21. The effective n-type impurity concentration in the buffer region 22 is, for example, 1 × 10⁻⁶. 15 cm -3 Above and 1×10 17 cm -3 the following.

[0040] An example of the first semiconductor region in the claims being formed by the n-base region 21 and the buffer region 22. Alternatively, the buffer region 22 may not be provided. In this case, for example, the n-base region 21 is also provided at the location of the buffer region 22. Or, the n-base region 21 may not be provided. In this case, for example, the buffer region 22 is also provided at the location of the n-base region 21.

[0041] The p-base region 23 functions as the p-base region of the IGBT. The p-base region 23 is located above the n-base region 21. The p-base region 23 is an example of the second semiconductor region described in the claims. The p-base region 23 is, for example, a p-type semiconductor region. The p-type impurity concentration of the p-base region 23 is, for example, 1 × 10⁻⁶. 17 cm -3 Above and 1×10 19 cm -3 The following. (e.g.) Figure 1 As shown, the p-base region 23 extends along the Y-axis. Furthermore, in Figure 3 In this example, the p-base region 23 has a first portion located below the emitter region 24 and a second portion extending from the first portion toward the upper surface 2b of the semiconductor layer 2 and penetrating the emitter region 24. The second portion is connected to and electrically connected to the emitter electrode 12. Furthermore, the p-type impurity concentration in the second portion may be higher than that in the first portion.

[0042] Emitter region 24 functions as the emitter region of the IGBT. Emitter region 24 is located above p-base region 23. Emitter region 24 is connected to and electrically connected to emitter electrode 12. Emitter region 24 is an example of the third semiconductor region described in the claims. Figure 1As shown, emitter region 24 extends along the Y-axis. Emitter region 24 is, for example, n + The emitter region 24 is a semiconductor region of type n. The n-type impurity concentration in the emitter region 24 is, for example, 1 × 10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 the following.

[0043] Collector region 25 functions as the collector region of the IGBT. For example... Figure 3 As shown, collector region 25 is located between collector electrode 11 and n-base region 21, and more specifically, between collector electrode 11 and buffer region 22. Collector region 25 is connected to and electrically connected to collector electrode 11. Collector region 25 is an example of the fourth semiconductor region in the claims. Collector region 25 is, for example, a p-type semiconductor region. The p-type impurity concentration of collector region 25 is, for example, 5 × 10⁻⁶. 17 cm -3 about.

[0044] The low-concentration region 26 is provided such that it is surrounded by the collector region 25 within the semiconductor layer 2. Specifically, the collector regions 25 are provided on both sides of the low-concentration region 26 along the X-axis and on both sides of the low-concentration region 26 along the Y-axis. Furthermore, the low-concentration region 26 is isolated from the low-concentration region 27 by the collector regions 25. The low-concentration region 26 is connected to and electrically connected to the collector electrode 11. The low-concentration region 26 is an example of the fifth semiconductor region in the claim. The low-concentration region 26 is, for example, p... - The low-concentration region 26 is a semiconductor region where the p-type impurity concentration is lower than that of the collector region 25. For example, the p-type impurity concentration in the low-concentration region 26 is 1 × 10⁻⁶. 16 cm -3 Above and less than 5×10 17 cm -3 .

[0045] like Figure 1 and Figure 2 As shown, in this embodiment, the low concentration region 26 is located at the center of the inner region IA, that is, the center of the collector region 25.

[0046] Alternatively, the low-concentration region 26 may also be located outside the center of the inner region IA. Figure 4 This is a bottom view of the semiconductor device 1A, a variation of the first embodiment. Figure 4 In the attached drawing, reference numeral B2 indicates a position located one-quarter of the width d of the inner region IA, away from the boundary B1 between the outer peripheral region OA and the inner region IA. Figure 4In the example, the low-concentration region 26 is not located at the center of the inner region IA. However, the low-concentration region 26 is located in a region that is further inside the boundary B2 (hereinafter also referred to as the "cell center"). In other words, the low-concentration region 26 is located more than one-quarter of the width d of the inner region IA from the boundary B1. More specifically, the low-concentration region 26 is located more than one-quarter of the length of the inner region IA in the X-axis direction from the boundary B1, and more than one-quarter of the length of the inner region IA in the Y-axis direction from the boundary B1.

[0047] In addition, Figure 4 In the example, the planar shape of the inner region IA is square. However, it is not limited to this; the planar shape of the inner region IA can also be rectangular. In this case, the low-concentration region 26 is also set to extend at least one-quarter of its length from the boundary B1 along the X-axis direction away from the inner region IA, and at least one-quarter of its length from the boundary B1 along the Y-axis direction away from the inner region IA.

[0048] exist Figure 2 and Figure 4 In the example, the width of the low-concentration region 26 is more than 1 / 60th of the width of the semiconductor layer 2. More specifically, the length of the low-concentration region 26 in both the X-axis and Y-axis directions is more than 1 / 60th of the larger of the lengths in the X-axis and Y-axis directions of the semiconductor layer 2.

[0049] In addition, Figure 2 and Figure 4 In the example, the planar shape of the low-concentration region 26 is circular. Furthermore, the planar shape of the low-concentration region 26 can be arbitrary, and can also be rectangular, polygonal, etc.

[0050] The low-concentration region 27 is located within the outer peripheral region OA of the semiconductor layer 2. For example... Figure 2 As shown, the low-concentration region 27 is arranged to surround the collector region 25. Figure 3 As shown, the low-concentration region 27 is connected to and electrically connected to the collector electrode 11. The low-concentration region 27 is an example of the sixth semiconductor region in the claims. The low-concentration region 27 is, for example, p... - The low-concentration region 27 is a semiconductor region where the p-type impurity concentration is lower than that of the collector region 25. For example, the p-type impurity concentration in the low-concentration region 27 is 1 × 10⁻⁶. 17 cm -3 about.

[0051] By setting up collector region 25, low concentration region 26, and low concentration region 27, the concentration of p-type impurities along the X-axis and Y-axis directions increases from low concentration region 26 to collector region 25, and then decreases from collector region 25 to low concentration region 27.

[0052] In this embodiment, the p-type impurity concentration in low-concentration region 27 is equal to the p-type impurity concentration in low-concentration region 26. Alternatively, the p-type impurity concentration in low-concentration region 27 may be lower than the p-type impurity concentration in low-concentration region 26.

[0053] Furthermore, the p-type impurity concentrations in the collector region 25, low-concentration region 26, and low-concentration region 27 described above are one example, and in other embodiments, they can vary by about one to two orders of magnitude.

[0054] In this embodiment, such as Figure 1 as well as Figure 3 As shown, a guard ring region 28 is provided. The guard ring region 28 is disposed within the outer peripheral region OA of the semiconductor layer 2. The guard ring region 28 is connected to and electrically connected to the emitter electrode 12. Additionally, as... Figure 1 As shown, the guard ring region 28 is connected to the end of the p-base region 23 in the Y-axis direction. The guard ring region 28 is, for example, a p-type semiconductor region. The p-type impurity concentration of the guard ring region 28 is, for example, 1 × 10⁻⁶. 17 cm -3 Above and 1×10 19 cm -3 The following applies. By setting the protection ring region 28, the withstand voltage of the semiconductor device 1 can be improved.

[0055] exist Figure 3 In this example, both the low-concentration region 27 and the protective ring region 28 are located within the outer peripheral region OA. On the other hand, neither the low-concentration region 27 nor the protective ring region 28 is located within the inner region IA. In other words, the inner ends of the low-concentration region 27 and the protective ring region 28 are aligned and located on the boundary B1. Furthermore, the inner ends of the low-concentration region 27 and the protective ring region 28 may not be aligned. That is, the inner end of the low-concentration region 27 may be located further inward or outward than the inner end of the protective ring region 28.

[0056] Furthermore, although not shown, the semiconductor device 1 may also include a field plate electrode (FP electrode) disposed within the semiconductor layer 2 through an insulating region. The FP electrode is electrically insulated from the semiconductor layer 2 by the insulating region and electrically connected to the emitter electrode 12. By providing such an FP electrode, when the IGBT is in the off state, the depletion layer extends from the FP electrode to the surrounding n-base region 21 by applying a voltage between the collector electrode 11 and the emitter electrode 12. By connecting this depletion layer to the depletion layers of adjacent FP electrodes, the withstand voltage of the semiconductor device 1 can be improved.

[0057] in addition, Figures 1-3The structure of the semiconductor device 1 shown is an example, and this embodiment is not limited to it. For example, in Figure 1 and Figure 3 In this example, the low-concentration region 26 is located below the gate electrode 13. However, it is not limited to this; it can also be located outside of both the low-concentration region 26 and the gate electrode 13. That is, the positional relationship between the low-concentration region 26 and the gate electrode 13 is arbitrary. Furthermore, the number of gate electrodes 13 extending along the Y-axis, i.e., the number of insulating regions 30, can be greater than... Figure 1 There can be many examples, or few. Alternatively, a gate pad can be provided on the upper surface 2b of semiconductor layer 2.

[0058] As described above, the semiconductor device 1 of the first embodiment includes a semiconductor layer 2, a collector electrode 11, an emitter electrode 12, an n-base region 21 of a first conductivity type and a buffer region 22, a p-base region 23 of a second conductivity type, a gate electrode 13, an emitter region 24 of a first conductivity type, a collector region 25 of a second conductivity type, and a low-concentration region 26 of a second conductivity type. The semiconductor layer 2 has a lower surface 2a and an upper surface 2b. The collector electrode 11 is disposed on the lower surface 2a of the semiconductor layer 2. The emitter electrode 12 is disposed on the upper surface 2b of the semiconductor layer 2. The n-base region 21 and the buffer region 22 are disposed within the semiconductor layer 2. The p-base region 23 is disposed within the semiconductor layer 2 and is located above the n-base region 21. The gate electrode 13 is opposite to the p-base region 23 across an insulating region 30. The emitter region 24 is disposed within the semiconductor layer 2, is located above the p-base region 23, and is electrically connected to the emitter electrode 12. Collector region 25 is disposed within semiconductor layer 2, located between collector electrode 11 and buffer region 22, and electrically connected to collector electrode 11. Low-concentration region 26 is disposed within semiconductor layer 2 such that it is surrounded by collector region 25, and electrically connected to collector electrode 11. The p-type impurity concentration in low-concentration region 26 is lower than the p-type impurity concentration in collector region 25.

[0059] In this embodiment, the low-concentration region 26 is arranged to be surrounded by the collector region 25. This suppresses the amount of hole injection from the collector region 25 to the n-base region 21, reducing the switching losses of the semiconductor device 1. Here, switching losses refer to the power losses generated when the semiconductor device 1 is turned on and off. According to this embodiment, the low-concentration region 26 is surrounded by the collector region 25, thereby more effectively suppressing the amount of hole injection compared to the case where it is arranged around the collector region 25. Therefore, according to this embodiment, the switching speed of the semiconductor device 1 can be increased.

[0060] Furthermore, the semiconductor device 1 of this embodiment also includes a low-concentration region 27 of a second conductivity type. This low-concentration region 27 is disposed within the outer peripheral region OA of the semiconductor layer 2, electrically connected to the collector electrode 11, and has a lower p-type impurity concentration than the collector region 25. This improves the avalanche tolerance of the semiconductor device 1.

[0061] Furthermore, in this embodiment, the p-type impurity concentration in low-concentration region 27 is equal to the p-type impurity concentration in low-concentration region 26. Therefore, as described later, low-concentration region 26 and low-concentration region 27 can be formed simultaneously. Additionally, the p-type impurity concentration in low-concentration region 27 can be lower than the p-type impurity concentration in low-concentration region 26. This further improves the avalanche tolerance of semiconductor device 1.

[0062] Furthermore, in this embodiment, the low-concentration region 26 is disposed at the center of the inner region IA on the lower surface 2a of the semiconductor layer 2. This reduces switching losses at the center of the inner region IA, where the current density is high, and enables efficient high-speed switching of the semiconductor device 1.

[0063] Furthermore, the low-concentration region 26 extends beyond the boundary B1 between the outer peripheral region OA and the inner region IA by more than one-quarter of the width d of the inner region IA. This improves the short-circuit withstand capability of the semiconductor device 1. Referring hereafter... Figure 5 This effect will be explained in detail. Figure 5 This is a graph showing the evaluation results of the short-circuit withstand capability in the semiconductor devices of the first embodiment and the comparative example.

[0064] Figure 5 The horizontal axis represents the diameter and location of the low-concentration region 26 in each semiconductor device used in the short-circuit withstand capability evaluation. "None" indicates that no low-concentration region 26 is provided. "Small," "Medium," and "Large" indicate that the diameter of the low-concentration region 26 is 1 / 300, 1 / 100, and 1 / 60 of the width of the semiconductor layer 2, respectively. "Center of cell" indicates that the low-concentration region 26 is located in... Figure 4 The case of the region inside boundary B2 (cell center) refers to the case where the low-concentration region 26 is more than one-quarter of the width d of the inner region IA, which is located at the boundary B1 between the outer peripheral region OA and the inner region IA. "Cell end" refers to the case where the low-concentration region 26 is located in the region between boundary B1 and boundary B2 (cell end), that is, the case where the low-concentration region 26 is not more than one-quarter of the width d of the inner region IA, which is located at the boundary B1. Both the semiconductor device 1 of the first embodiment and the semiconductor device 1A of the modified example of the first embodiment are equivalent to... Figure 5 The case where the "unit is in the center" and is "large". Figure 5The vertical axis represents the gate-emitter voltage applied to each semiconductor device. The cross (×) in the chart indicates the gate-emitter voltage at which the semiconductor device is damaged, and the circle (○) indicates the gate-emitter voltage at which the semiconductor device is not damaged.

[0065] like Figure 5 As shown, when the low-concentration region 26 is located at the "cell center," the short-circuit withstand capability of the semiconductor device is higher than that at the "cell end," regardless of the size of the low-concentration region 26. More specifically, the short-circuit withstand capability is higher when the region is at the "cell center" and "small" compared to the "cell end" and "small" case; higher when the region is at the "cell center" and "medium" compared to the "cell end" and "medium" case; and higher when the region is at the "cell center" and "large" compared to the "cell end" and "large" case. Therefore, the low-concentration region 26 is located more than one-quarter of the width d of the inner region IA from the boundary B1 between the outer peripheral region OA and the inner region IA, thereby improving the short-circuit withstand capability of the semiconductor device 1.

[0066] In addition, such as Figure 5 As shown, in the case of "center of cell" and "large", compared with the cases of "center of cell" and "small" or "center of cell" and "medium", the short-circuit withstand capability of the semiconductor device is observed to decrease. However, although not shown, in the case of "center of cell" and "large", the failure mode of the semiconductor device changes. More specifically, in the cases of "center of cell" and "small" or "center of cell" and "medium", the failure mode of the semiconductor device is failure upon disconnection. On the other hand, in the case of "center of cell" and "large", the failure mode of the semiconductor device is thermal failure after disconnection, i.e., BT (Bias Temperature) failure. Therefore, when the low-concentration region 26 is located in the center of the cell, by further increasing the width of the low-concentration region 26 to more than 1 / 60th of the width of the semiconductor layer 2, the short-circuit withstand capability of the semiconductor device 1 can be further improved.

[0067] Next, refer to Figures 6A-6F An example of the manufacturing method of the semiconductor device 1 of this embodiment will be described. Figures 6A-6F This is a cross-sectional view illustrating an example of the manufacturing process of the semiconductor device 1 according to the first embodiment. Furthermore, in Figures 6A-6F In the text, the portion of the through-emitter region 24 in the p-base region 23 is omitted (the second part).

[0068] First, such as Figure 6AAs shown, a semiconductor layer 2 is prepared having a lower surface 2a and an upper surface 2b opposite to the lower surface 2a. The semiconductor layer 2 includes a gate electrode 13, an n-base region 21, a p-base region 23, an emitter region 24, a guard ring region 28, and an insulating region 30.

[0069] Next, as Figure 6B As shown, a buffer region 22 is formed below the n-base region 21 by ion implantation of n-type impurities into the lower surface 2a of the semiconductor layer 2. The n-type impurities used here are, for example, at least one of phosphorus (P) and arsenic (As). The concentration of n-type impurities in the buffer region 22 is higher than that in the n-base region 21.

[0070] Next, as Figure 6C As shown, a p-region 250 is formed by ion implantation of a p-type impurity into the lower surface 2a of semiconductor layer 2. The p-type impurity used here is, for example, boron (B). The p-region 250 is, for example, p... - Type of semiconductor region.

[0071] Next, as Figure 6D As shown, resist 41 and resist 42 are formed on a portion of the lower surface 2a of semiconductor layer 2. More specifically, resist 41 is formed on a portion of the lower surface 2a of semiconductor layer 2 in the inner region IA, and resist 42 is formed on the lower surface 2a of semiconductor layer 2 in the outer peripheral region OA.

[0072] Next, as Figure 6E As shown, a collector region 25 is formed by ion implantation of a p-type impurity into the lower surface 2a of the semiconductor layer 2. The p-type impurity used is, for example, boron (B). The p-type impurity concentration in the collector region 25 is higher than that in the p-region 250. Furthermore, through this process, the portion of the p-region 250 covered by the photoresist 41 becomes a low-concentration region 26, and the portion covered by the photoresist 42 becomes a low-concentration region 27.

[0073] Next, as Figure 6F As shown, resist 41 and resist 42 are removed.

[0074] Subsequently, although not shown in the figure, a collector electrode 11 and an emitter electrode 12 are formed on the lower surface 2a and upper surface 2b of the semiconductor layer 2, respectively.

[0075] Semiconductor device 1 is manufactured through the above processes.

[0076] According to the manufacturing method of the semiconductor device 1 of this embodiment, low-concentration region 26 and low-concentration region 27 can be formed simultaneously. In this case, the p-type impurity concentration of low-concentration region 27 is equal to the p-type impurity concentration of low-concentration region 26.

[0077] Alternatively, for example, the p-region 250 can be formed with a lower p-type impurity concentration. After forming the collector region 25, with the resist 41 removed and the resist 42 remaining, p-type impurities can be ion-implanted again onto the lower surface 2a of the semiconductor layer 2. This maintains the p-type impurity concentration in the low-concentration region 26 and further reduces the p-type impurity concentration in the low-concentration region 27. In this case, the p-type impurity concentration in the low-concentration region 27 is lower than that in the low-concentration region 26.

[0078] (Second Implementation)

[0079] Reference Figure 7 The semiconductor device 1B of the first embodiment will be described. Figure 7 This is a bottom view of the semiconductor device 1B according to the second embodiment. One difference between this embodiment and the first embodiment is the number of low-concentration regions 26. Hereinafter, this embodiment will be described focusing on the differences from the first embodiment.

[0080] like Figure 7 As shown, the semiconductor device 1B of this embodiment includes multiple low-concentration regions 26. Specifically, in Figure 7 In the example, semiconductor device 1B has five low-concentration regions 26. Furthermore, the number of low-concentration regions 26 can be four or fewer, or six or more.

[0081] Each low-concentration region 26 is arranged and separated from the other in such a way that it is surrounded by the collector region 25 within the semiconductor layer 2. Each low-concentration region 26 is connected to and electrically connected to the collector electrode 11.

[0082] The p-type impurity concentration in each low-concentration region 26 is lower than that in the collector region 25. Furthermore, the p-type impurity concentration in each low-concentration region 26 can be all equal, or at least one low-concentration region 26 may have a different p-type impurity concentration than the other low-concentration regions 26.

[0083] exist Figure 7 In the example, each low-concentration region 26 is located inside the boundary B2 (in the center of the cell). In addition, one of the multiple low-concentration regions 26 is located at the center of the lower surface 2a of the semiconductor layer 2.

[0084] In addition, Figure 7In this example, multiple low-concentration regions 26 are symmetrically arranged on the lower surface 2a of the semiconductor layer 2. More specifically, the multiple low-concentration regions 26 are symmetrically arranged about a straight line passing through the center of the lower surface 2a of the semiconductor layer 2 and parallel to the X-axis, and about a straight line passing through the center and parallel to the Y-axis. This allows for efficient high-speed switching of the semiconductor device 1B. Alternatively, the multiple low-concentration regions 26 may also be symmetrically arranged about at least one straight line passing through the center of the lower surface 2a of the semiconductor layer 2 and parallel to the XY plane. Or, the multiple low-concentration regions 26 may also be symmetrically arranged about the center of the lower surface 2a of the semiconductor layer 2.

[0085] According to this embodiment, by providing multiple low-concentration regions 26, the switching speed of the semiconductor device 1B can be increased.

[0086] Furthermore, multiple low-concentration regions 26 can also be configured such that the density increases as the distance approaches the center of the lower surface 2a of the semiconductor layer 2. Figure 8 This is a bottom view of a semiconductor device 1C, a modified example of the second embodiment.

[0087] exist Figure 8 In the example, the low-concentration region near the center of the lower surface 2a of the semiconductor layer 2 is closer to other low-concentration regions 26 than the low-concentration region near the boundary B2. Therefore, in the semiconductor device 1C, the density of the low-concentration region 26 near the center of the lower surface 2a of the semiconductor layer 2 is higher than that near the boundary B2. That is, in Figure 8 In this example, multiple low-concentration regions 26 are configured such that their density increases as they approach the center of the lower surface 2a of the semiconductor layer 2. This enables efficient high-speed switching of the semiconductor device 1C.

[0088] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device comprising: a semiconductor layer including a first main surface and a second main surface; a first electrode provided on the first main surface; a second electrode provided on the second main surface; a first semiconductor region of a first conductivity type provided in the semiconductor layer; a second semiconductor region of a second conductivity type provided in the semiconductor layer above the first semiconductor region; a third electrode opposing the second semiconductor region through an insulating region; a third semiconductor region of the first conductivity type provided in the semiconductor layer above the second semiconductor region and electrically connected to the second electrode; a fourth semiconductor region of the second conductivity type provided in the semiconductor layer between the first electrode and the first semiconductor region and electrically connected to the first electrode; and a fifth semiconductor region of the second conductivity type provided in a manner surrounded by the fourth semiconductor region in the semiconductor layer, electrically connected to the first electrode, and having a lower impurity concentration than the fourth semiconductor region. Further comprising: a sixth semiconductor region of the second conductivity type provided in an outer peripheral region extending from a side portion of the semiconductor layer to an inner side of the semiconductor layer, electrically connected to the first electrode, and having a lower impurity concentration than the fourth semiconductor region.

3. The semiconductor device according to claim 2, wherein the semiconductor layer further includes an inner side region inside the outer peripheral region, and the fifth semiconductor region is separated from the inner side region by more than 1 / 4 of a width of the inner side region from a boundary between the outer peripheral region and the inner side region.

4. The semiconductor device according to claim 3, wherein a width of the fifth semiconductor region is more than 1 / 60 of a width of the semiconductor layer.

5. The semiconductor device according to claim 2, wherein an impurity concentration of the sixth semiconductor region is equal to an impurity concentration of the fifth semiconductor region.

6. The semiconductor device according to claim 5, wherein the semiconductor layer further includes an inner side region inside the outer peripheral region, and the fifth semiconductor region is separated from the inner side region by more than 1 / 4 of a width of the inner side region from a boundary between the outer peripheral region and the inner side region.

7. The semiconductor device according to claim 6, wherein a width of the fifth semiconductor region is more than 1 / 60 of a width of the semiconductor layer.

8. The semiconductor device according to claim 2, wherein an impurity concentration of the sixth semiconductor region is lower than an impurity concentration of the fifth semiconductor region.

9. The semiconductor device according to claim 8, wherein the semiconductor layer further includes an inner side region inside the outer peripheral region, and the fifth semiconductor region is separated from the inner side region by more than 1 / 4 of a width of the inner side region from a boundary between the outer peripheral region and the inner side region.

10. The semiconductor device according to claim 9, wherein a width of the fifth semiconductor region is more than 1 / 60 of a width of the semiconductor layer.

11. The semiconductor device according to claim 1, wherein the semiconductor device includes a plurality of the fifth semiconductor regions.

2. The semiconductor device according to claim 1, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 12. The semiconductor device according to claim 11, wherein the semiconductor layer has a peripheral region extending from a side portion of the semiconductor layer toward an inner side of the semiconductor layer and an inner side region inside the peripheral region, the fifth semiconductor region is separated from the inner side region by more than 1 / 4 of a width of the inner side region from a boundary between the peripheral region and the inner side region.

13. The semiconductor device according to claim 8, wherein a width of the fifth semiconductor region is more than 1 / 60 of a width of the semiconductor layer.

14. The semiconductor device according to claim 11, wherein the plurality of fifth semiconductor regions are symmetrically arranged on the first main surface of the semiconductor layer.

15. The semiconductor device according to claim 14, wherein the semiconductor layer has a peripheral region extending from a side portion of the semiconductor layer toward an inner side of the semiconductor layer and an inner side region inside the peripheral region, the fifth semiconductor region is separated from the inner side region by more than 1 / 4 of a width of the inner side region from a boundary between the peripheral region and the inner side region.

16. The semiconductor device according to claim 11, wherein the plurality of fifth semiconductor regions are arranged in a manner that a density thereof increases as approaching a center of the first main surface of the semiconductor layer.

17. The semiconductor device according to claim 16, wherein the semiconductor layer has a peripheral region extending from a side portion of the semiconductor layer toward an inner side of the semiconductor layer and an inner side region inside the peripheral region, the fifth semiconductor region is separated from the inner side region by more than 1 / 4 of a width of the inner side region from a boundary between the peripheral region and the inner side region.

18. The semiconductor device according to claim 1, wherein the semiconductor layer has a peripheral region extending from a side portion of the semiconductor layer toward an inner side of the semiconductor layer and an inner side region inside the peripheral region, the fifth semiconductor region is separated from the inner side region by more than 1 / 4 of a width of the inner side region from a boundary between the peripheral region and the inner side region.

19. The semiconductor device according to claim 18, wherein the fifth semiconductor region is arranged in the first main surface of the semiconductor layer at a center of the inner side region.

20. The semiconductor device according to claim 18, wherein a width of the fifth semiconductor region is more than 1 / 60 of a width of the semiconductor layer.

Images