Semiconductor device and method of manufacturing semiconductor device

Abstract

The embodiment of the invention relates to a semiconductor device and a manufacturing method of the semiconductor device. A semiconductor device includes a semiconductor substrate having an upper surface and a lower surface, an element region including a semiconductor element, and a peripheral region surrounding the element region in plan view. The semiconductor substrate in the peripheral region includes an N-type drift layer, an N + + type channel stop layer provided on an upper surface side with respect to the N-type drift layer, the channel stop layer being at least one ring-shaped N + + type channel stop layer surrounding the element region, and an N-type guard ring layer provided on the upper surface side with respect to the N-type drift layer.

Description

[0001] Cross Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2024-151987 filed on September 4, 2024, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. BACKGROUND

[0004] One disclosed technology is listed below.

[0005] [Patent Literature 1] Japanese Unexamined Patent Application Publication No. 2024-003808

[0006] Patent Literature 1 describes a semiconductor device having an IGBT (Insulated Gate Bipolar Transistor). SUMMARY

[0007] It is desirable to reduce the size of a semiconductor device. For example, it is desirable to reduce the size of a semiconductor device without increasing the processing cost of an IGBT and without impairing the negative charge tolerance of the IGBT. In the present specification, the term “negative charge tolerance” refers to the limit of the amount of negative charge that can reach the surface of a semiconductor device during use without rendering the device unable to maintain a predetermined breakdown voltage.

[0008] Other challenges and novel features will become apparent from the description and drawings of this specification.

[0009] According to one embodiment, a semiconductor device includes a semiconductor substrate having a first main surface and a second main surface opposite the first main surface. In a plan view from the first main surface side, the semiconductor substrate includes an element region including a semiconductor element, and a peripheral region surrounding the element region. The semiconductor substrate in the peripheral region includes a drift layer of a first conductivity type, at least one annular channel stop layer of the first conductivity type arranged on the first main surface side with respect to the drift layer, the annular channel stop layer surrounding the element region, and at least one annular guard ring layer of the first conductivity type arranged on the first main surface side with respect to the drift layer, the annular guard ring layer being arranged in the plan view between a most peripheral structure within an inner portion surrounded by the channel stop layer and the channel stop layer. The most peripheral structure includes at least one of an annular semiconductor layer of a second conductivity type arranged on the first main surface side with respect to the drift layer in the semiconductor substrate, and an annular field plate including a conductive material arranged on the first main surface side with respect to the semiconductor substrate. A concentration of impurities of the first conductivity type in the guard ring layer is greater than a concentration of impurities of the first conductivity type in the drift layer, and is less than a concentration of impurities of the first conductivity type in the channel stop layer.

[0010] According to one embodiment, a method of manufacturing a semiconductor device includes: providing, in a plan view from a first main surface side, an element region including a semiconductor element and a peripheral region surrounding the element region in a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; forming, in the peripheral region of the semiconductor substrate, a drift layer of a first conductivity type and at least one annular channel stop layer of the first conductivity type arranged on the first main surface side with respect to the drift layer, the annular channel stop layer surrounding the element region; and forming at least one annular guard ring layer of the first conductivity type arranged on the first main surface side with respect to the drift layer, the annular guard ring layer being arranged between a most peripheral structure within an inner portion surrounded by the channel stop layer and the channel stop layer. In forming the guard ring layer: the most peripheral structure is caused to include at least one of an annular semiconductor layer of a second conductivity type arranged on the first main surface side with respect to the drift layer in the semiconductor substrate, and an annular field plate including a conductive material arranged on the first main surface side with respect to the semiconductor substrate; and a concentration of impurities of the first conductivity type in the guard ring layer is caused to be greater than a concentration of impurities of the first conductivity type in the drift layer and less than a concentration of impurities of the first conductivity type in the channel stop layer.

[0011] According to embodiments, it is possible to provide a semiconductor device and a method for manufacturing a semiconductor device that can reduce a size. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1is a plan view illustrating a semiconductor device according to Embodiment 1.

[0013] Figure 2 is a cross-sectional view illustrating a peripheral region in the semiconductor device according to Embodiment 1, the cross-sectional view showing a cross section along Figure 1 line II-II in FIG. 1.

[0014] Figure 3 is an enlarged cross-sectional view illustrating the peripheral region in the semiconductor device according to Embodiment 1, the enlarged cross-sectional view showing a cross section along Figure 2 plane III in FIG. 1.

[0015] Figure 4 is a cross-sectional view illustrating an element region in the semiconductor device according to Embodiment 1, the cross-sectional view showing a cross section along Figure 1 line IV-IV in FIG. 1.

[0016] Figure 5 is a cross-sectional view illustrating a manufacturing process of the peripheral region in the method for manufacturing a semiconductor device according to Embodiment 1.

[0017] Figure 6 is a cross-sectional view illustrating a manufacturing process of the element region in the method for manufacturing a semiconductor device according to Embodiment 1.

[0018] Figure 7 is a cross-sectional view illustrating a manufacturing process of the element region in the method for manufacturing a semiconductor device according to Embodiment 1.

[0019] Figure 8 is a cross-sectional view illustrating a manufacturing process of the element region in the method for manufacturing a semiconductor device according to Embodiment 1.

[0020] Figure 9 is a cross-sectional view illustrating a manufacturing process of the element region in the method for manufacturing a semiconductor device according to Embodiment 1.

[0021] Figure 10 is a cross-sectional view illustrating a manufacturing process of the element region in the method for manufacturing a semiconductor device according to Embodiment 1.

[0022] Figure 11 is a cross-sectional view illustrating a peripheral region in a semiconductor device according to Comparative Example 1.

[0023] Figure 12 is a cross-sectional view illustrating a peripheral region in a semiconductor device according to Comparative Example 2.

[0024] Figure 13is a cross-sectional view illustrating a peripheral region in a semiconductor device according to Comparative Example 3. DETAILED DESCRIPTION

[0025] For the sake of clear explanation, the following description and drawings are appropriately omitted and simplified. In the drawings, hatching can be omitted even in the case of cross-sectional views if the hatching becomes complicated or if the distinction from voids is obvious. In each drawing, the same elements are denoted by the same reference numerals, and the repeated description is omitted as necessary. Furthermore, the reference numerals are appropriately omitted so as to prevent the drawings from becoming confusing.

[0026] In this specification, when the conduction type of a semiconductor is N-type, this means that electrons are the only charge carriers, or both electrons and holes are charge carriers, but the concentration of electrons is higher than that of holes, making electrons the dominant charge carriers. Similarly, when the conduction type of a semiconductor is P-type, this means that holes are the only charge carriers, or both electrons and holes are charge carriers, but the concentration of holes is higher than that of electrons, making holes the dominant charge carriers.

[0027] Note that N++-type and P++-type indicate low-resistance N-type and P-type conduction, respectively. N+-type and P+-type have higher resistance than N++-type and P++-type conduction, but have lower resistance than N-type and P-type conduction. P- type and N-type indicate high-resistance N-type and P-type conduction, respectively, than N-type and P-type conduction. Thus, N-type and P-type indicate N-type and P-type conduction having resistance between N+-type and P+-type and N-type and P-type. N+-type and P+-type indicate N-type and P-type conduction having resistance between N++-type and P++-type and N-type and P-type, respectively. The meanings are the same unless otherwise specified.

[0028] The N-type conduction type can be referred to as a first conduction type, and the P-type conduction type can be referred to as a second conduction type. Conversely, the N-type conduction type can be referred to as a second conduction type, and the P-type conduction type can be referred to as a first conduction type. Furthermore, a semiconductor device of each configuration having an opposite conduction type in this disclosure is also within the scope of the technical concept of this disclosure. In addition, the resistance of each semiconductor layer of N++-type, N+-type, N-type, and N-type is exemplary. Unless specifically mentioned, the resistance can be larger or smaller than that shown in this disclosure. In some cases, the resistance relationship of each semiconductor layer of N++-type, N+-type, N-type, and N-type can be reversed. Similarly, the resistance of each semiconductor layer of P++-type, P+-type, P-type, and P-type is exemplary. Unless specifically mentioned, the resistance can be larger or smaller than that shown in this disclosure. In some cases, the resistance relationship of each semiconductor layer of P++-type, P+-type, P-type, and P-type can be reversed.

[0029] <Example 1>

[0030] A semiconductor device according to Example 1 will be described. Figure 1 is a plan view illustrating a semiconductor device 1 according to Example 1. As Figure 1 indicated, the semiconductor device 1 includes a semiconductor substrate 100. The semiconductor substrate 100 is, for example, a rectangular plate. Two plate surfaces of the semiconductor substrate 100 are referred to as a first main surface and a second main surface. The second main surface is a surface opposite to the first main surface. Thus, the semiconductor substrate 100 has the first main surface and the second main surface opposite to the first main surface. For convenience of explanation, the first main surface can be referred to as an upper surface 101, and the second main surface is referred to as a lower surface 102.

[0031] Here, for convenience of explanation of the semiconductor device 1 and the like, an XYZ orthogonal coordinate system is introduced. A direction perpendicular to the upper surface 101 is a Z-axis direction, and two directions perpendicular to the Z-axis direction are an X-axis direction and a Y-axis direction. A direction from the lower surface 102 to the upper surface 101 is a +Z-axis direction. The first main surface side is the +Z-axis direction side, that is, the upper surface 101 side. The second main surface side is the -Z-axis direction side, that is, the lower surface 102 side. For convenience, the +Z-axis direction is referred to as upward, and the -Z-axis direction is referred to as downward. Note that upward and downward are directions for convenience of explanation, and do not indicate directions when the semiconductor device 1 is actually used.

[0032] In this specification, "in a plan view" means when viewed from a direction perpendicular to the upper surface 101 of the semiconductor substrate 100. In other words, "in a plan view" means when the semiconductor substrate 100 is viewed from the +Z-axis direction in the -Z-axis direction.

[0033] In a plan view, the semiconductor device 1 and the semiconductor substrate 100 include an element region A10 and a peripheral region B10. The element region A10 includes a semiconductor element. The peripheral region B10 is arranged to surround the element region A10. The peripheral region B10 can include a first peripheral region B11, a second peripheral region B12, and a third peripheral region B13. The third peripheral region B13 is arranged to surround the element region A10. The second peripheral region B12 is arranged to surround the element region A10 and the third peripheral region B13. Thus, the third peripheral region B13 is provided between the element region A10 and the second peripheral region B12. The first peripheral region B11 is arranged to surround the element region A10, the third peripheral region B13, and the second peripheral region B12. Thus, the second peripheral region B12 is provided between the third peripheral region B13 and the first peripheral region B11.

[0034] A direction from the element region A10 toward the third peripheral region B13 is referred to as outward, and a direction from the third peripheral region B13 toward the element region A10 is referred to as inward. The peripheral region B10 is arranged outside the element region A10. The element region A10 is arranged inside the peripheral region B10. Hereinafter, a <peripheral region> and an <element region> are described, respectively.

[0035] <Peripheral region>

[0036] Figure 2 is a cross-sectional view illustrating the peripheral region B10 in the semiconductor device 1 according to the first embodiment, which shows a cross section along Figure 1 line II-II thereof. Figure 3 is an enlarged cross-sectional view illustrating the peripheral region B10 in the semiconductor device 1 according to the first embodiment, which shows a cross section of Figure 2 plane III thereof. As Figure 2 and Figure 3 illustrated in the peripheral region B10, the first peripheral region B11, the second peripheral region B12, and the third peripheral region B13 are arranged in one direction from the element region A10 toward the third peripheral region B13. In Figure 2 and Figure 3 , as an example, the first peripheral region B11, the second peripheral region B12, and the third peripheral region B13 are arranged in the X-axis direction. Note that the first peripheral region B11, the second peripheral region B12, and the third peripheral region B13 can be arranged in the Y-axis direction or in a direction inclined from the X-axis and Y-axis directions.

[0037] The semiconductor substrate 100 of the peripheral region B10 includes an N-type drift layer 10, an N++-type channel stop layer 11, and an N-type guard ring layer 12. Note that the semiconductor substrate 100 of the peripheral region B10 can include a P-type semiconductor layer 13. Further, the semiconductor substrate 100 of the peripheral region B10 can further include other semiconductor layers not illustrated.

[0038] The N-type drift layer 10 is included in the semiconductor substrate 100 of the peripheral region B10. That is, the N-type drift layer 10 is formed across the first peripheral region B11, the second peripheral region B12, and the third peripheral region B13. Note that the N-type drift layer 10 is also formed in the element region A10.

[0039] <First peripheral region>

[0040] In the first peripheral region B11, the semiconductor device 1 includes the semiconductor substrate 100 including the N-type drift layer 10. The N++-type channel stop layer 11 is arranged on the +Z-axis side with respect to the N-type drift layer 10 in the semiconductor substrate 100 of the first peripheral region B11. The N++-type channel stop layer 11 has at least one annular shape that surrounds the element region A10. Therefore, in a plan view, the element region A10 is arranged inside a region surrounded by the N++-type channel stop layer 11. In other words, in a plan view, the element region A10 is arranged inside the N++-type channel stop layer 11.

[0041] In the first peripheral region B11, the semiconductor device 1 can include the first interlayer insulating film 21 and the equipotential ring 31 in addition to the semiconductor substrate 100. The first interlayer insulating film 21 is provided on the +Z-axis side with respect to the semiconductor substrate 100 in which the N++-type channel stop layer 11 is arranged. The equipotential ring 31 is provided on the +Z-axis side with respect to the first interlayer insulating film 21. The equipotential ring 31 includes an electrically conductive material. For example, the equipotential ring 31 contains aluminum. The equipotential ring 31 is connected to the N++-type channel stop layer 11 via the contact groove 26 formed in the first interlayer insulating film 21. The equipotential ring 31 can have a portion that protrudes inward with respect to the N++-type channel stop layer 11. In the direction shown in the figure, the equipotential ring 31 can have a portion that protrudes in the -X-axis direction with respect to the N++-type channel stop layer 11.

[0042] <Second peripheral region>

[0043] In the second peripheral region B12, the semiconductor device 1 includes the semiconductor substrate 100 including the N-type drift layer 10. The N-type guard ring layer 12 is arranged on the +Z-axis side with respect to the N-type drift layer 10 in the semiconductor substrate 100 of the second peripheral region B12. The N-type guard ring layer 12 is arranged inside a region surrounded by the N++-type channel stop layer 11. In other words, in a plan view, the N-type guard ring layer 12 is arranged inside the N++-type channel stop layer 11. The N-type guard ring layer 12 has at least one annular shape that surrounds the element region A10.

[0044] The semiconductor substrate 100 in the peripheral region B12 can include a plurality of N-type guard ring layers 12. The plurality of N-type guard ring layers 12 is arranged inside a region surrounded by the N++-type channel stop layer 11. In other words, in a plan view, the plurality of N-type guard ring layers 12 is arranged inside the N++-type channel stop layer 11. The plurality of N-type guard ring layers 12 is arranged annularly to surround the element region A10. The plurality of N-type guard ring layers 12 is spaced apart from each other. Further, the N-type guard ring layer 12 is spaced apart from the N++-type channel stop layer 11. Further, in a plan view, the N-type guard ring layer 12 can be spaced apart from the equipotential ring 31. The N-type guard ring layer 12 can be spaced apart from the P-type semiconductor layer 13.

[0045] The concentration of the N-type impurity in the N-type guard ring layer 12 is greater than the concentration of the N-type impurity in the N-type drift layer 10, and is less than the concentration of the N-type impurity in the N++-type channel stop layer 11. In addition, if the semiconductor device 1 includes an IGBT as the semiconductor element in the element region A10, the N-type guard ring layer 12 can contain the same type of impurity as an N-type barrier layer in the IGBT. Further, the N-type guard ring layer 12 can contain the same concentration of impurity as the N-type barrier layer. As will be described later, the N-type barrier layer is a portion arranged below (collector side) a P-type body layer (P-type channel layer) adjacent to a trench gate electrode.

[0046] In the second peripheral region B12, the semiconductor device 1 can include a second interlayer insulating film 22 in addition to the semiconductor substrate 100. The second interlayer insulating film 22 is provided on the +Z-axis side with respect to the semiconductor substrate 100 in which the N-type guard ring layer 12 is arranged. The thickness of the second interlayer insulating film 22 is greater than the thickness of the first interlayer insulating film 21. For example, the second interlayer insulating film 22 can include an insulating material such as LOCOS (local oxidation of silicon). The N-type guard ring layer 12 can be covered by the LOCOS. In contrast, the first interlayer insulating film 21 can be formed by a different process from the second interlayer insulating film 22.

[0047] <Third peripheral region>

[0048] In the third peripheral region B13, the semiconductor device 1 includes the semiconductor substrate 100 including the N-type drift layer 10. In the third peripheral region B13, the semiconductor substrate 100 can include at least one P-type semiconductor layer 13. In the semiconductor substrate 100 of the third peripheral region B13, the P-type semiconductor layer 13 is arranged on the +Z-axis side with respect to the N-type drift layer 10. In a plan view, the P-type semiconductor layer 13 is arranged inside a region surrounded by the N++-type channel stop layer 11. In other words, in a plan view, the P-type semiconductor layer 13 is arranged inside the N++-type channel stop layer 11. The P-type semiconductor layer 13 can be arranged annularly to surround the element region A10.

[0049] In the third peripheral region B13, in addition to the semiconductor substrate 100, the semiconductor device 1 may also include a third interlayer insulating film 23 and at least one field plate 33. The third interlayer insulating film 23 is disposed on the +Z axis side relative to the semiconductor substrate 100 in which the P-type semiconductor layer 13 is disposed. The thickness of the third interlayer insulating film 23 may be greater than the thickness of the first interlayer insulating film 21.

[0050] Field plate 33 is disposed on the +Z axis side relative to the third interlayer insulating film 23. Field plate 33 comprises a conductive material. For example, the conductive material comprises aluminum. In a plan view, field plate 33 is disposed within the region surrounded by the N++ type channel stop layer 11. In other words, in a plan view, field plate 33 is disposed inside the N++ type channel stop layer 11. Field plate 33 is arranged annularly to surround element region A10. Field plate 33 can be connected to P-type semiconductor layer 13 via contact grooves 26 formed in the third interlayer insulating film 23. Field plate 33 may have a portion protruding outward relative to P-type semiconductor layer 13. In the direction shown in the figure, field plate 33 may have a portion protruding relative to P-type semiconductor layer 13 in the +X axis direction.

[0051] Semiconductor device 1 may include an outermost structure. The outermost structure includes at least one of a P-type semiconductor layer 13 and a field plate 33, which, in a plan view, are arranged at the outermost position within the region surrounded by the N++ type channel stop layer 11. In this case, in the plan view, an N-type guard ring layer 12 is disposed between the outermost structure within the region surrounded by the N++ type channel stop layer 11 and the N++ type channel stop layer 11.

[0052] Semiconductor substrate 100 may include a P-type semiconductor layer 13, which may include a plurality of field confinement ring layers 13a. The plurality of field confinement ring layers 13a are positioned on the +Z-axis side relative to the N-type drift layer 10. In plan view, the plurality of field confinement ring layers 13a are located inside an N++-type channel stop layer 11. That is, in plan view, the plurality of field confinement ring layers 13a are positioned inside the N++-type channel stop layer 11. The plurality of field confinement ring layers 13a are arranged in a ring to surround the device region A10. The plurality of field confinement ring layers 13a are spaced apart from each other.

[0053] Semiconductor device 1 may be equipped with a plurality of field plates 33 corresponding to a plurality of field confinement ring layers 13a. The plurality of field plates 33 may be connected to the plurality of field confinement ring layers 13a via a plurality of contact grooves 26 formed in a third interlayer insulating film 23. In this case, the outermost structure includes either the field confinement ring layer 13a or any of the field plates 33 located at the outermost perimeter among the plurality of field confinement ring layers 13a and the plurality of field plates 33. Therefore, in plan view, an N-type guard ring layer 12 is disposed within the interior surrounded by an N++ type channel stop layer 11 and an N++ type channel stop layer 11 between any of the field confinement ring layers 13a or field plates 33 located at the outermost perimeter.

[0054] When the semiconductor element in element region A10 includes a P-type semiconductor layer 13 (e.g., a P-type floating layer) positioned on the +Z axis side relative to the N-type drift layer 10, the P-type semiconductor layer 13 can be used as the outermost structure. In this case, the semiconductor substrate 100 in the peripheral region B10, including the third peripheral region B13, does not necessarily have a P-type semiconductor layer 13. An N-type guard ring layer 12 is disposed between the P-type semiconductor layer 13 and the N++ type channel stop layer 11 in element region A10.

[0055] Furthermore, for example, in a structure such as a JTE (junction termination extension), the semiconductor substrate 100 in the peripheral region B10 may include a P-type semiconductor layer 13 serving as a termination structure positioned on the +Z axis side relative to the N-type drift layer 10. In a plan view, the P-type semiconductor layer 13 may be positioned within the interior surrounded by the N++ type channel stop layer 11. In this case, the outermost structure includes the P-type semiconductor layer 13.

[0056] In the peripheral region B10, an interlayer insulating film comprising a first interlayer insulating film 21, a second interlayer insulating film 22, and a third interlayer insulating film 23 is disposed on the +Z axis side of the peripheral region B10 relative to the semiconductor substrate 100. At least one of the first interlayer insulating film 21, the second interlayer insulating film 22, and the third interlayer insulating film 23 may have a fixed positive charge. Therefore, the interlayer insulating film in the peripheral region B10 may have a fixed positive charge. For example, at least one of the first interlayer insulating film 21, the second interlayer insulating film 22, and the third interlayer insulating film 23 may be formed using P-TEOS deposited by a plasma CVD method using TEOS (tetraethoxysilane) as the main raw material. During this process, the charge generated within the P-TEOS may be fixed by RTA (rapid thermal annealing).

[0057] <Component Area>

[0058] Figure 4This is a cross-sectional view of element region A10 in semiconductor device 1 according to a first embodiment, showing the cross-sectional view along... Figure 1 The cross-section of line IV-IV in the diagram. For example... Figure 4 As shown, in the element region A10, in addition to the semiconductor substrate 100, the semiconductor device 1 may also include an insulating film 24a, an interlayer insulating film 25, an emitter wiring 34, and a collector wiring 35. Multiple semiconductor elements may be formed in the element region A10. The semiconductor elements may include, for example, an IGBT. The semiconductor elements may also include at least one of a MOSFET and a diode.

[0059] As part of the IGBT configuration, the semiconductor substrate 100 in the device region A10 includes an N-type drift layer 10, an N-type barrier layer 14, P-type body layers 15a and 15i, an N+ type emitter layer 16, a P+ type latch-up prevention layer 17, and a P+ type body contact layer 18. Additionally, the semiconductor substrate 100 in the device region A10 includes a trench gate electrode 41, a trench emitter electrode 42, a P-type floating layer 43, a P+ type collector layer 44, an N-type field stop layer 45, a trench insulating film 46, and a trench insulating film 47. Emitter wiring 34 is connected to the N+ type emitter layer 16, the P-type body layer 15a, the P+ type body contact layer 18, and the trench emitter electrode 42 via contact trenches 26 formed in the insulating film 24a and the interlayer insulating film 25. Collector wiring 35 is connected to the P+ type collector layer 44.

[0060] An N-type drift layer 10 is continuously disposed between the device region A10 and the peripheral region B10. In the device region A10, the N-type drift layer 10 is positioned on the +Z axis side relative to the N-type field stop layer 45 in the semiconductor substrate 100.

[0061] The N-type barrier layer 14 is positioned on the +Z axis side relative to the N-type drift layer 10. In a plan view, the N-type barrier layer 14 extends, for example, in the Y-axis direction. The N-type barrier layer 14 is sandwiched between the trench gate electrode 41 and the trench emitter electrode 42 from both sides in the X-axis direction. That is, the N-type barrier layer 14 is positioned inside the trench gate electrode 41 and the trench emitter electrode 42.

[0062] A portion of the P-type body layer 15a present in the active cell region 40a is positioned on the +Z axis side relative to the N-type barrier layer 14. The P-type body layer 15a is sandwiched between the trench gate electrode 41 and the trench emitter electrode 42 from both sides in the X-axis direction. The P-type body layer 15a is connected to the emitter wiring 34 filled in the contact trench 26 that penetrates the interlayer insulating film 25, the insulating film 24a, and the N+ type emitter layer 16.

[0063] The N+ type emitter layer 16 is positioned on the +Z axis side relative to the P type body layer 15a. The N+ type emitter layer 16 is positioned within the interior sandwiched between the trench gate electrode 41 and the trench emitter electrode 42. The N+ type emitter layer 16 is connected to the emitter wiring 34 filled in the contact groove 26 that penetrates the insulating film 24a and the interlayer insulating film 25.

[0064] The trench gate electrode 41 and trench emitter electrode 42 are configured to sandwich the N-type barrier layer 14, the P-type body layer 15a, and the N+ type emitter layer 16 from both sides in the X-axis direction. In a plan view, the trench gate electrode 41 and trench emitter electrode 42 include portions extending, for example, in the Y-axis direction. For example, the trench gate electrode 41 is positioned on the +X-axis side relative to the trench emitter electrode 42. The trench emitter electrode 42 is positioned on the -X-axis side relative to the trench gate electrode 41.

[0065] For example, the trench gate electrode 41 is connected to the gate wiring. The trench emitter electrode 42 is connected to the emitter wiring 34, which is filled in the contact trench 26 that penetrates the insulating film 24a and the interlayer insulating film 25. Therefore, the N+ type emitter layer 16, the P type body layer 15a, and the trench gate electrode 41 are connected to the emitter wiring 34. The structure between the trench gate electrode 41 and the trench emitter electrode 42 is called the inter-trench structure. For example, the inter-trench structure of an IGBT includes an N-type barrier layer 14, a P-type body layer 15a, and an N+ type emitter layer 16. The inter-trench structure of an IGBT may also include a P+ type latch-up prevention layer 17 and a P+ type body contact layer 18. For example,

[0066] A P-type floating layer 43 is disposed between adjacent IGBTs in a plurality of IGBTs. For example, the P-type floating layer 43 is disposed between the trench gate electrode 41 of the IGBT on the -X-axis side and the trench emitter electrode 42 of the IGBT on the +X-axis side in adjacent IGBTs. The P-type floating layer 43 is disposed on the opposite side of the N-type barrier layer 14, the P-type body layer 15a and the N+ type emitter layer 16, clamping the trench gate electrode 41 or the trench emitter electrode 42.

[0067] The P-type floating layer 43 is positioned on the +Z axis side relative to the N-type drift layer 10. The P-type body layer 15i is positioned on the +Z axis side relative to the P-type floating layer 43. Therefore, on the +Z axis side of the N-type drift layer 10, along the X-axis direction from the -X axis side, a stack of the P-type floating layer 43 and the P-type body layer 15i, a trench emitter electrode 42 (covered by a trench insulating film 47), an inter-trench structure, a trench gate electrode 41 (covered by a trench insulating film 46), and a stack of the P-type floating layer 43 and the P-type body layer 15i are arranged. In the device region A10, this configuration is arranged to repeat in the X-axis direction.

[0068] Multiple IGBTs are formed in the component region A10. Except for the IGBTs at the +X-axis end and the -X-axis end of the component region A10, the P-type floating layer 43 contacts the trench gate electrode 41 and the trench emitter electrode 42. In other words, the P-type floating layer 43 is formed between adjacent IGBTs except at the X-axis end of the component region A10.

[0069] If the third peripheral region B13 in the peripheral region B10 does not have a P-type semiconductor layer 13 such as a field-confining ring layer 13a, then the P-type floating layer 43 of the device region A10 can be used as the P-type semiconductor layer 13 of the outermost structure. That is, the outermost structure includes the P-type floating layer 43. Therefore, the P-type floating layer 43 of the IGBT disposed at the outermost edge of the device region A10 can be an annular P-type semiconductor layer 13 disposed on the +Z axis side of the N-type drift layer 10 within the N++ type channel stop layer 11. Therefore, the N-type guard ring layer 12 can be disposed between the outermost annular P-type floating layer 43 and the N++ type channel stop layer 11. In this way, the P-type semiconductor layer 13 can include the P-type floating layer 43.

[0070] A trench insulating film 46 is disposed between the trench emitter electrode 42 and the semiconductor substrate 100. Specifically, the trench insulating film 46 is disposed between the trench emitter electrode 42 and the N-type drift layer 10, the N-type barrier layer 14, the P-type body layer 15a, the N+ type emitter layer 16, the P-type body layer 15i, and the P-type floating layer 43. A trench insulating film 47 is disposed between the trench gate electrode 41 and the semiconductor substrate 100. Specifically, the trench insulating film 47 is disposed between the trench gate electrode 41 and the N-type drift layer 10, the N-type barrier layer 14, the P-type body layer 15a, the P-type body layer 15i, and the P-type floating layer 43.

[0071] An N-type field stop layer 45 is disposed on the -Z axis side of the N-type drift layer 10. A P+ type collector layer 44 is disposed on the -Z axis side of the N-type field stop layer 45. The P+ type collector layer 44 is connected to the collector wiring 35.

[0072] Component region A10 may include multiple active cell regions 40a and multiple passive cell regions 40i. The multiple active cell regions 40a extend in the Y-axis direction in a plan view and are periodically arranged in the X-axis direction. In other words, the active cell regions 40a are formed as vertical strips.

[0073] Furthermore, multiple passive cell regions 40i extend along the Y-axis in the plan view and are periodically arranged along the X-axis. Active cell regions 40a and passive cell regions 40i are alternately arranged along the X-axis. A unit cell region 40 is composed of an active cell region 40a, a half of the passive cell regions 40i adjacent to the +X-axis side of the active cell region 40a, and a half of the passive cell regions 40i adjacent to the -X-axis side of the active cell region 40a. Therefore, the element region A10 includes multiple unit cell regions 40. The unit cell regions 40 include, for example, IGBTs as semiconductor elements. Therefore, the element region A10 may include multiple IGBTs.

[0074] In the active cell region 40a, on the N-type drift layer 10, starting from the bottom, in addition to the N-type barrier layer 14, the P-type body layer 15a, and the N+ type emitter layer 16, a P+ type latch-up prevention layer 17 and a P+ type body contact layer 18 may also be arranged. The N+ type emitter layer 16 may be disposed only on the trench gate electrode 41 side. An insulating film 24a and an interlayer insulating film 25 are formed on the +Z axis side of the trench gate electrode 41, the trench emitter electrode 42, the P-type body layer 15a, and the N+ type emitter layer 16. In the active cell region 40a, a contact trench 26 reaching the trench emitter electrode 42 and the interior of the semiconductor substrate 100 is formed in portions of the insulating film 24a and the interlayer insulating film 25. At the bottom of the contact trench 26, a P+ type body contact layer 18 and a P+ type latch-up prevention layer 17 are disposed. Through the contact groove 26, the P-type body layer 15a and the N+ type emitter layer 16 are connected to the emitter wiring 34 disposed on the insulating film 24a and the interlayer insulating film 25.

[0075] Here, the N-type barrier layer 14 is a blocking region that prevents holes from flowing into the channel from the N-type drift layer 10 to the N+ type emitter layer 16. The impurity concentration in the N-type barrier layer 14 is lower than that in the N+ type emitter layer 16, but higher than that in the N-type drift layer 10. The presence of this N-type barrier layer 14 effectively prevents holes accumulated in the N-type drift layer 10 from entering the emitter channel of the active cell region 40a (the channel from the N-type drift layer 10 to the P+ type body contact layer 18).

[0076] In contrast, in the passive cell region 40i, the P-type floating layer 43 and the P-type body layer 15i are arranged sequentially on the N-type drift layer 10, starting from the bottom. The depth of the P-type floating layer 43 is greater than the depth of the trench gate electrode 41 and the trench emitter electrode 42. Furthermore, the P-type floating layer 43 is distributed to cover the lower ends of the trench gate electrode 41 and the trench emitter electrode 42.

[0077] <Semiconductor Device Manufacturing Methods>

[0078] Next, a method for manufacturing the semiconductor device 1 of this embodiment will be described. First, a semiconductor substrate 100 comprising a silicon single crystal is prepared, wherein an N-type impurity such as phosphorus is introduced into the silicon single crystal. The semiconductor substrate 100 has an upper surface 101 as a first main surface and a lower surface 102 as a second main surface opposite to the upper surface 101. Then, in a plan view, a component region A10 and a peripheral region B10 surrounding the component region A10 are disposed on the semiconductor substrate 100. In the step of disposing of the component region A10 and the peripheral region B10, the peripheral region B10 may include a third peripheral region B13 surrounding the component region A10, a second peripheral region B12 surrounding the component region A10 and the third peripheral region B13, and a first peripheral region B11 surrounding the component region A10, the third peripheral region B13, and the second peripheral region B12.

[0079] Component isolation members such as LOCOS can be formed on the semiconductor substrate 100. For example, LOCOS can be formed as a second interlayer insulating film 22 or a portion thereof on the +Z axis side of the semiconductor substrate 100 in the second peripheral region B12. The methods for manufacturing the peripheral region and the component region will be described below.

[0080] <Manufacturing Method for the Peripheral Area>

[0081] Figure 5 This is a cross-sectional view illustrating the manufacturing process of the peripheral region B10 in the manufacturing method of the semiconductor device 1 according to the first embodiment. (See diagram below.) Figure 5 As shown, an N-type drift layer 10 and an N++-type channel stop layer 11 disposed on the +Z axis side of the N-type drift layer 10 are formed on the semiconductor substrate 100 in the first peripheral region B11. The N++-type channel stop layer 11 is formed in an annular shape to surround the device region A10. For example, the N++-type channel stop layer 11 is formed on the N-type drift layer 10 by introducing N-type impurities with a higher concentration than that of the N-type drift layer 10 into the semiconductor substrate 100.

[0082] Furthermore, an N-type drift layer 10 and an N-type guard ring layer 12 disposed on the +Z axis side of the N-type drift layer 10 are formed on the semiconductor substrate 100 in the second peripheral region B12. The N-type guard ring layer 12 is formed to have at least one annular shape between the outermost structure disposed inside the N++ type channel stop layer 11 and the N++ type channel stop layer 11. For example, the N-type guard ring layer 12 is formed on the N-type drift layer 10 by introducing N-type impurities with a concentration higher than that of the N-type drift layer 10 into the semiconductor substrate 100.

[0083] In the step of forming the N-type guard ring layer 12, the concentration of N-type impurities in the N-type guard ring layer 12 is made greater than the concentration of N-type impurities in the N-type drift layer 10. Furthermore, the concentration of N-type impurities in the N-type guard ring layer 12 is made less than the concentration of N-type impurities in the N++ type channel stop layer 11. Note that the step of forming the N-type guard ring layer 12 can introduce N-type impurities into the semiconductor substrate 100 through the second interlayer insulating film 22 or a portion thereof (such as LOCOS). For example, N-type impurities can be introduced into the semiconductor substrate 100 by ion implantation.

[0084] Furthermore, the outermost structure can be formed in the third outermost region B13. The outermost structure includes at least one of the following: a field plate 33 containing conductive material disposed on the +Z axis side of the semiconductor substrate 100 and a P-type semiconductor layer 13 disposed on the +Z axis side of the N-type drift layer 10 in the semiconductor substrate 100.

[0085] A first interlayer insulating film 21 is formed on the +Z axis side of the semiconductor substrate 100 in the first peripheral region B11. As described above, a second interlayer insulating film 22 is formed on the +Z axis side of the semiconductor substrate 100 in the second peripheral region B12. In the process of forming the first interlayer insulating film 21 or the second interlayer insulating film 22, the thickness of the second interlayer insulating film 22 is made greater than the thickness of the first interlayer insulating film 21. For example, a portion of the second interlayer insulating film 22 is formed on the semiconductor substrate 100 side using LOCOS, and after performing ion implantation to form the N-type guard ring layer 12 and the N++ type channel stop layer 11, the remaining portion of the second interlayer insulating film 22 and the first interlayer insulating film 21 are formed using P-TEOS in the same process. A third interlayer insulating film 23 is formed on the +Z axis side of the semiconductor substrate 100 in the third peripheral region B13. The portion of the third interlayer insulating film 23 on the semiconductor substrate 100 side can be formed using LOCOS in the same process as a similar portion of the second interlayer insulating film 22. The remaining portion of the third interlayer insulating film 23 can be formed using P-TEOS in the same process as the first interlayer insulating film 21. Alternatively, the entire third interlayer insulating film 23 can be formed using P-TEOS in the same process as the first interlayer insulating film 21. Contact grooves 26 are formed in both the first interlayer insulating film 21 and the third interlayer insulating film 23.

[0086] Then, as Figure 2 and Figure 3 As shown, contact grooves 26 are filled in the first peripheral region B11, and an equipotential ring 31 is formed on the first interlayer insulating film 21 in the first peripheral region B11. Furthermore, contact grooves 26 are filled in the third peripheral region B12, and a field plate 33 is formed on the third interlayer insulating film 23 in the third peripheral region B13. In this way, the peripheral region B10 of the semiconductor device 1 can be formed.

[0087] <Manufacturing Method of Component Area>

[0088] Next, a method for manufacturing the component region A10 will be described. The method for manufacturing the component region A10 includes the step of forming an IGBT, which serves as a semiconductor component, within the component region A10. The method for manufacturing the component region A10 and the method for manufacturing the peripheral region B10 may include simultaneous manufacturing processes. Figures 6 to 10 This is a cross-sectional view illustrating the manufacturing process of the element region A10 in the manufacturing method of the semiconductor device 1 according to the first embodiment.

[0089] like Figure 6 As shown, for example, an N-type barrier layer 14 is formed by introducing N-type impurities into the upper surface 101 side of the semiconductor substrate 100 using an ion implantation method with a resist pattern as a mask. The N-type barrier layer 14 is formed in the active cell region 40a. As described above, the element region A10 has a plurality of active regions 40a and a plurality of passive regions 40i. In the step of forming the N-type guard ring layer 12 in the above-described method for manufacturing the peripheral region B10, the N-type guard ring layer 12 can be formed simultaneously with the N-type barrier layer 14 in the process of forming the IGBT.

[0090] Next, for example, a P-type impurity is introduced into the upper surface 101 side of the semiconductor substrate 100 using an ion implantation method with a resist pattern as a mask, forming a P-type floating layer 43. The P-type floating layer 43 is formed in the passive cell region 40i. In the step of forming the P-type semiconductor layer 13 in the above-described method for manufacturing the peripheral region B10, the P-type semiconductor layer 13 can be formed simultaneously with the P-type floating layer 43 in the process of forming the IGBT.

[0091] Next, as Figure 7 As shown, for example, a plurality of trenches 27 and a plurality of trenches 28 are formed on the upper surface 101 of the semiconductor substrate 100 by anisotropic dry etching using a hard mask made of silicon oxide film.

[0092] Next, as Figure 8 As shown, lateral diffusion is performed on the P-type floating layer 43 and the N-type barrier layer 14. During this lateral diffusion, the -Z-axis side of the P-type floating layer 43 is positioned in the Z-axis direction at the -Z-axis side of the plurality of trenches 27 and the plurality of trenches 28. Next, for example, an insulating film 24 made of silicon oxide is formed on the upper surface 101 of the semiconductor substrate 100 by thermal oxidation or other methods. Furthermore, a trench insulating film 46 made of silicon oxide is formed on the inner wall of the trenches 27. Furthermore, a trench insulating film 47 made of silicon oxide is formed on the inner wall of the trenches 28. The insulating film 24, the trench insulating film 46, and the trench insulating film 47 can be formed simultaneously.

[0093] Through the aforementioned lateral diffusion, a P-type floating layer 43 is formed on the +X-axis side of trench 27 and the -X-axis side of trench 28. Preferably, the P-type floating layer 43 contacts the trench insulating film 46 formed on the inner wall of trench 27 and the trench insulating film 47 formed on the inner wall of trench 28. Furthermore, an N-type barrier layer 14 is formed between the -X-axis side of trench 27 and the +X-axis side of trench 28. Preferably, the N-type barrier layer 14 contacts the trench insulating film 46 formed on the inner wall of trench 27 and the trench insulating film 47 formed on the inner wall of trench 28. During lateral diffusion, the regions in the N-type semiconductor substrate 100 where the P-type floating layer 43 and the N-type barrier layer 14 are not formed become N-type drift layers 10.

[0094] Next, a conductive film 29, consisting of a phosphorus-doped polycrystalline silicon film, is formed on the upper surface 101 of the semiconductor substrate 100 and inside the trenches 27 and 28, for example by CVD (chemical vapor deposition) or other methods.

[0095] Next, as Figure 9 As shown, for example, the conductive film 29 is etched back using a dry etching process. This forms a trench gate electrode 41 composed of the conductive film 29, which is embedded inside the trench 27 via a trench insulating film 46. Furthermore, a trench emitter electrode 42 composed of the conductive film 29 is formed, which is embedded inside the trench 28 via a trench insulating film 47.

[0096] Next, for example, the insulating film 24 outside trenches 27 and 28 is removed by dry etching. Next, for example, an insulating film 24a consisting of a relatively thin silicon oxide film is formed on the upper surface 101 of the semiconductor substrate 100 by thermal oxidation or CVD for subsequent ion implantation. The insulating film 24a is also referred to as an ion implantation penetrating insulating film because it is used as a penetrating film for ion implantation. Next, P-type impurities are introduced into the entire surface and other necessary portions of the device region A10 using an ion implantation method with a resist pattern as a mask, forming P-type body layers 15a and 15i.

[0097] Specifically, in the active cell region 40a, a P-type body layer 15a is formed between trenches 27 and 28. This P-type body layer is in contact with the trench insulating film 46 formed on the inner wall of trench 27 and the trench insulating film 47 formed on the inner wall of trench 28. The P-type body layer 15a is formed on the N-type barrier layer 14. Furthermore, in the passive cell region 40i, the P-type body layer 15i is formed on the P-type floating layer 43.

[0098] Furthermore, for example, an N+ type emitter layer 16 is formed by introducing N-type impurities into the upper layer of the P-type body layer 15a in the active cell region 40a using an ion implantation method with a resist pattern as a mask. In the step of forming the N++ type channel stop layer 11 in the manufacturing method of the peripheral region B10 described above, the N++ type channel stop layer 11 can be formed simultaneously with the N+ type emitter layer 16 in the process of forming the IGBT. Next, an interlayer insulating film 25, including, for example, a PSG (phosphosilicate glass) film, is formed on the upper surface 101 of the semiconductor substrate 100, for example, by CVD or other methods. The interlayer insulating film 25 is formed to cover the P-type body layers 15a and 15i in each of the active cell region 40a and the passive cell region 40i via an insulating film 24a. As materials for the interlayer insulating film 25, in addition to PSG films, BPSG (borophosphosilicate glass), NSG (undoped silicate glass), SOG (spin-coated glass), P-TEOS films, or composite films thereof can be suitably exemplified. In the step of forming the first interlayer insulating film 21 in the manufacturing method of the aforementioned peripheral region B10, the first interlayer insulating film 21 can be formed simultaneously with the interlayer insulating film 25 during the IGBT formation process.

[0099] Next, as Figure 10 As shown, contact trenches 26 are formed in the interlayer insulating film 25 and the insulating film 24a by anisotropic dry etching using a resist pattern as a mask. Subsequently, the contact trenches 26 are extended into the semiconductor substrate 100 by anisotropic dry etching. This forms contact trenches 26 as openings that penetrate the interlayer insulating film 25, the insulating film 24a, and the N+ type emitter layer 16 to reach the P-type bulk layer 15a and pass through trenches 28 in the active cell region 40a. In the active cell region 40a, the contact trenches 26 are continuously formed along the Y-axis direction in a plan view.

[0100] Next, for example, P-type impurities are ion implanted through contact trench 26 to form a P+ type body contact layer 18. Next, for example, P-type impurities are ion implanted through contact trench 26 to form a P+ type latch-up prevention layer 17. The concentration of P-type impurities in the P+ type body contact layer 18 is higher than the concentration in the P+ type latch-up prevention layer 17.

[0101] Therefore, in the active cell region 40a, the P+ type body contact layer 18 and the P+ type latch-up prevention layer 17 are formed in the portion of the P-type body layer 15a exposed through the contact groove 26. In the active cell region 40a, in plan view, the P+ type body contact layer 18 and the P+ type latch-up prevention layer 17 are continuously formed along the Y-axis direction. That is, the P+ type body contact layer 18 and the P+ type latch-up prevention layer 17 are formed in the portion located between the groove 27 and the groove 28, and are in contact with the P-type body layer 15a. In the active cell region 40a, the concentration of P-type impurities in the P+ type body contact layer 18 and the P+ type latch-up prevention layer 17 is higher than the concentration in the P-type body layer 15a.

[0102] Next, as Figure 4 As shown, emitter wiring 34 is formed. Specifically, for example, a titanium-tungsten film is formed on the upper surface 101 of the semiconductor substrate 100 as a barrier metal film by sputtering. Then, an aluminum metal film is formed on the entire surface of the barrier metal film by sputtering to embed the contact trench 26. As a result, emitter wiring 34 is formed inside the contact trench 26 and on the interlayer insulating film 25 in the active cell region 40a. Emitter wiring 34 electrically connects a plurality of N+ type emitter layers 16, a plurality of P+ type body contact layers 18 and a plurality of P+ type latch-up prevention layers 17 formed in the active cell region 40a.

[0103] Next, back-side grinding is performed on the lower surface 102 of the semiconductor substrate 100. This thins the semiconductor substrate 100. Next, N-type impurities are introduced into the lower surface 102 of the semiconductor substrate 100 by ion implantation to form an N-type field stop layer 45. Then, P-type impurities are introduced into the lower surface 102 of the semiconductor substrate 100 by ion implantation to form a P+ type collector layer 44. Next, for example, collector wiring 35 electrically connected to the P+ type collector layer 44 is formed on the lower surface 102 of the semiconductor substrate 100 by sputtering. In this way, the device region A10 can be formed.

[0104] Subsequently, the semiconductor substrate 100 is divided into chip regions by cutting, etc., and the semiconductor device 1 is nearly completed by sealing it in a package as needed.

[0105] Next, the effects of this embodiment will be explained. The semiconductor device 1 of this embodiment includes at least one annular N-type guard ring layer 12, which is located between the outermost structure and the N++ type channel stop layer 11 within the interior surrounded by the N++ type channel stop layer 11. This allows for a reduction in the size of the peripheral breakdown voltage structure in the semiconductor device 1 without compromising negative charge tolerance.

[0106] For example, when using semiconductor device 1, a large amount of negative charge can reach the upper surface 101 side of semiconductor substrate 100. In such cases, the area near the upper surface 101 directly below the second interlayer insulating film 22 in the second peripheral region B12 can become inverted or nearly inverted, making it difficult to maintain the breakdown voltage. However, in this embodiment, semiconductor device 1 has an N-type protective ring layer 12 directly below the upper surface 101 of the second interlayer insulating film 22. Therefore, it is possible to suppress the inversion near the upper surface 101 directly below the second interlayer insulating film 22.

[0107] Therefore, increasing the donor density of the upper surface 101 of the semiconductor substrate 100 is effective in suppressing reversal caused by negative charges on the upper surface 101 of the semiconductor substrate 100. One reason is that the negative charges on the upper surface 101 of the semiconductor substrate 100 can be neutralized by the positive charges of ionized donors. Here, the concentration of N-type impurities in the N-type guard ring layer 12 is greater than the concentration of N-type impurities in the N-type drift layer 10, but less than the concentration of N-type impurities in the N++ type channel stop layer 11. Importantly, the N-type guard ring layer 12 has this concentration of N-type impurities to increase the donor density of the upper surface 101 of the semiconductor substrate 100 in the second peripheral region B12. Therefore, it is possible to suppress reversal near the upper surface 101.

[0108] Figure 11 This is a cross-sectional view of the peripheral region B10 in the semiconductor device 1a according to Comparative Example 1. Figure 12 This is a cross-sectional view of the peripheral region B10 in the semiconductor device 1b according to Comparative Example 2. Figure 13 This is a cross-sectional view of the peripheral region B10 in the semiconductor device 1c according to Comparative Example 3.

[0109] like Figure 11 As shown, the semiconductor device 1a of Comparative Example 1 does not have an N-type guard ring layer 12 on the N-type drift layer 10 in the second peripheral region B12. In this case, when a large amount of negative charge reaches the upper surface 101 side of the semiconductor substrate 100 during the use of the semiconductor device 1a, the vicinity of the upper surface 101 directly below the second interlayer insulating film 22 may become inverted or nearly inverted, making it difficult to maintain the breakdown voltage.

[0110] like Figure 12As shown, in Comparative Example 2, the semiconductor device 1b has a semiconductor layer 12b containing the same concentration of N++ type impurities as the N++ type channel stop layer 11 on the N-type drift layer 10 in the second peripheral region B12. In this case, the donor density is not continuously depleted from the semiconductor layer 12b to the N++ type channel stop layer 11. Therefore, the end of the semiconductor layer 12b on the -X-axis side becomes the same potential as the equipotential ring 31. In other words, it is simply equivalent to extending the N++ type channel stop layer 11 to the -X-axis side. Therefore, it is impossible to increase the breakdown voltage of the peripheral region B10.

[0111] like Figure 13 As shown, the semiconductor device 1c of Comparative Example 3 has a semiconductor layer 12c containing the same concentration of N-type impurities as the N-type drift layer 10 on the N-type drift layer 10 in the second peripheral region B12. In this case, a portion of the semiconductor layer 12c also has a donor density that undergoes depletion. In other words, it is essentially the same structure as Comparative Example 1. Therefore, the ionized donors included in the depletion layer (such as the field confinement ring layer 13a) extending from the P-type semiconductor layer 13 side will cancel out the ionized acceptors of the P-type semiconductor layer 13, making it impossible to suppress the inversion on the upper surface 101 side of the semiconductor substrate 100.

[0112] Unlike comparative examples 1 to 3, this embodiment has an N-type guard ring layer 12, which may have a different potential than the N++ type channel stop layer 11 and the N-type drift layer 10, preventing complete depletion on the upper surface 101 side of the semiconductor substrate 100. Therefore, it is possible to suppress the inversion of the upper surface 101 of the semiconductor substrate 100 and increase the breakdown voltage.

[0113] Furthermore, the N-type guard ring layer 12 is arranged to be spaced apart from the N++ type channel stop layer 11. This results in a configuration where the space between the separated N-type guard ring layer 12 and the N++ type channel stop layer 11 is partially exhausted. When multiple N-type guard ring layers 12 are arranged, each N-type guard ring layer 12 can have a different potential. This configuration allows for increased breakdown voltage.

[0114] Specifically, the depletion layer surrounds the N-type protective ring layer 12 and depletes to the upper surface 101 of the spacer portion (excluding the reverse channel). However, this configuration prevents avalanche breakdown at the end of the N-type protective ring layer 12 on the -X-axis side or the entire N-type protective ring layer 12 from becoming depleted. Therefore, it is desirable to adjust the N-type protective ring layer 12 to have an appropriate width in the X-axis direction.

[0115] For example, the lower limit of the width of the N-type guard ring layer 12 is that not all of the multiple N-type guard ring layers 12 become depleted. In other words, if the width of the multiple N-type guard ring layers 12 is narrow, then all N-type guard ring layers 12 become depleted. Therefore, the width should be greater than the lower limit.

[0116] On the other hand, as the depletion layer expands beneath the N-type guard ring layer 12, the electric field at the end of the N-type guard ring layer 12 on the -X-axis side continues to rise. Therefore, the upper limit of the width of the N-type guard ring layer 12 is such that it does not experience avalanche breakdown. In other words, if the widths of multiple N-type guard ring layers 12 are wide, avalanche breakdown occurs at the end on the -X-axis side before the depletion layer reaches the end on the +X-axis side. Therefore, the width should be less than the upper limit.

[0117] The N-type guard ring layer 12 can function with only one ring, but it is preferable to arrange multiple N-type guard ring layers 12 according to the breakdown voltage that should be borne outside the outermost structure when a negative charge reaches the upper surface 101. With only one N-type guard ring layer 12, it is only possible to increase the breakdown voltage by applying a voltage of +α to the upper surface 101 (excluding the reverse channel) of the separated portion outside the N-type guard ring layer 12 until the required voltage is exhausted. It is possible to increase the breakdown voltage to some extent by widening the width of an N-type guard ring layer 12 in the X-axis direction. However, if the width is too wide, the electric field at the inner corners of the N-type guard ring layer 12 becomes too high, causing avalanche breakdown, which in turn reduces the breakdown voltage. Therefore, there is a limitation on the width of the N-type guard ring layer 12.

[0118] By providing an equipotential ring 31 in the first peripheral region B11, it is possible to increase the breakdown voltage of the semiconductor device 1. However, when the N-type protective ring layer 12 is present, the equipotential ring 31 can be considered unnecessary from the perspective of negative charge tolerance.

[0119] Without the N-type guard ring layer 12, from the perspective of negative charge tolerance, the equipotential ring 31 extends inward from the N++ type channel stop layer 11 on the semiconductor substrate 100 to operate as a reverse field plate. On the other hand, with the N-type guard ring layer 12 present, if a negative charge reaches the upper surface 101, the breakdown voltage is supported in the portion below the extension of the equipotential ring 31 where the negative charge does not reach. Therefore, the electric field becomes higher at the end of the extension of the equipotential ring 31. For example, the equipotential ring 31 is placed directly above the N++ type channel stop layer 11, and the equipotential ring 31 is arranged not to extend inward from the N++ type channel stop layer 11. In other words, the inner end of the equipotential ring 31 is aligned with the inner end of the N++ type channel stop layer 11. Alternatively, the inner end of the equipotential ring 31 can be placed outside the inner end of the N++ type channel stop layer 11. With this configuration, it is possible to support a voltage when a negative charge reaches the upper surface 101 with the N-type protective ring layer 12. Therefore, it is possible to suppress the application of a large electric field to the inner end of the equipotential ring 31.

[0120] When a positive charge reaches the upper surface 101, the depletion layer does not extend in the direction of the first peripheral region B11 or the second peripheral region B12, therefore it is not necessary to first share the withstand voltage in the first peripheral region B11 or the second peripheral region B12. As its name suggests, the equipotential ring 31 is originally intended to prevent the potential of the periphery of the element region A10 from becoming uneven along the periphery. Therefore, it is not a problem to reduce the width of the equipotential ring 31 to a degree that does not impair its function. Furthermore, if the effect of the potential becoming uneven at the periphery of the element region A10 is small, the equipotential ring 31 may not be necessary in extreme cases.

[0121] The semiconductor device in component region A10 is an IGBT with an N-type barrier layer 14, and if the ion implantation energy used to form the N-type barrier layer 14 is high enough to penetrate the second interlayer insulating film 22 or a portion thereof (e.g., LOCOS) already present during the manufacturing process, the N-type guard ring layer 12 can be formed in the same manufacturing process as the N-type barrier layer 14. This can reduce manufacturing costs.

[0122] The N++ channel stop layer 11 requires high-dose ion implantation, making it difficult to introduce N-type impurities through thick interlayer insulating films such as LOCOS. On the other hand, when forming the first interlayer insulating film 21, providing a step to remove the material used to form the first interlayer insulating film 21 in the portion where the second interlayer insulating film 22 already exists is particularly expensive. Therefore, the thickness of the first interlayer insulating film 21 is made smaller than the thickness of the second interlayer insulating film 22. For example, after forming a portion of the second interlayer insulating film 22 present on the semiconductor substrate 100 side, the remaining portion of the second interlayer insulating film 22 and the first interlayer insulating film 21 are formed in the same process, making the thickness of the first interlayer insulating film 21 smaller than the thickness of the second interlayer insulating film 22.

[0123] The interlayer insulating film in the peripheral region B10 can have a fixed positive charge. The fixed positive charge in the interlayer insulating film suppresses the extension of the depletion layer, allowing the distance between the outermost structure and the N++ type channel stop layer 11 to be narrowed, thereby reducing the size of the semiconductor device 1. For example, the interlayer insulating film can be formed using P-TEOS, and the positive charge generated in the P-TEOS can be fixed by RTA.

[0124] Although the disclosure made by the inventors has been specifically described based on embodiments, it should be understood that this disclosure is not limited to the embodiments and modified examples, and various modifications can be made without departing from its spirit. For example, appropriate combinations of the configurations of the first embodiment are also within the scope of the technical concept of this embodiment. In addition, the following configurations are also within the scope of the technical concept of the embodiments.

[0125] (Additional Statement 1)

[0126] A method for manufacturing a semiconductor device, the method comprising:

[0127] In a plan view from the first main surface side, an element region comprising a semiconductor element and a peripheral region surrounding the element region is disposed in a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;

[0128] A drift layer of a first conductivity type and at least one annular channel stop layer of the first conductivity type are formed in a peripheral region of a semiconductor substrate. The annular channel stop layer is disposed on a first main surface side relative to the drift layer and surrounds a device region.

[0129] At least one annular protective ring layer of a first conductivity type is formed, the annular protective ring layer being disposed on the first main surface side relative to the drift layer, and the annular protective ring layer being disposed between the outermost outermost structure within the interior surrounded by the channel stop layer and the channel stop layer.

[0130] During the formation of the protective ring layer:

[0131] The outermost structure includes at least one of the following: a ring-shaped semiconductor layer of a second conductivity type disposed on the first main surface side relative to a drift layer in the semiconductor substrate, and a ring-shaped field plate containing a conductive material disposed on the first main surface side relative to the semiconductor substrate; and

[0132] The concentration of impurities of the first conductivity type in the guard ring layer is greater than that in the drift layer, but less than that in the channel stop layer.

[0133] (Additional Statement 2)

[0134] According to the method of manufacturing a semiconductor device according to Additional Statement 1, in which the guard ring layer is formed to be spaced apart from the channel stop layer during the formation of the guard ring layer.

[0135] (Additional Statement 3)

[0136] According to the method of manufacturing a semiconductor device according to Additional Statement 1, in forming a guard ring layer, the semiconductor substrate in the peripheral region is configured to include a plurality of guard ring layers, and the plurality of guard ring layers are formed to be spaced apart from each other.

[0137] (Additional Statement 4)

[0138] The method for manufacturing a semiconductor device according to Appendix 1 further includes:

[0139] A first interlayer insulating film is formed on the first main surface side of the semiconductor substrate in the peripheral region;

[0140] A contact groove is formed in the first interlayer insulating film; and

[0141] An equipotential ring is formed on the first main surface side relative to the first interlayer insulating film comprising a conductive material;

[0142] In the process of forming the equipotential ring, the equipotential ring is formed to be connected to the channel stop layer via a contact groove.

[0143] (Additional Statement 5)

[0144] According to the method of manufacturing a semiconductor device according to Additional Statement 4, in forming an equipotential ring, a guard ring layer is formed to be spaced apart from the equipotential ring in a plan view.

[0145] (Additional Statement 6)

[0146] According to the method for manufacturing a semiconductor device as described in Appendix 1, when setting up an element region comprising a semiconductor element and a peripheral region surrounding the element region...

[0147] The outer area is constructed to include:

[0148] The third outer region surrounds the component area;

[0149] The second outer region surrounds the component region and the third outer region; and

[0150] The first outer region surrounds the component region, the third outer region, and the second outer region.

[0151] This method also includes:

[0152] A first interlayer insulating film is formed in the first peripheral region on the first main surface side relative to the semiconductor substrate; and

[0153] A second interlayer insulating film is formed in the second peripheral region on the side of the first main surface of the semiconductor substrate, and

[0154] When forming the second interlayer insulating film, the thickness of the second interlayer insulating film is made to be greater than the thickness of the first interlayer insulating film.

[0155] (Additional Statement 7)

[0156] According to the method of manufacturing a semiconductor device according to Additional Statement 6, in forming a second interlayer insulating film, the second interlayer insulating film is configured to include LOCOS, and a protective ring layer is covered by LOCOS.

[0157] (Additional Statement 8)

[0158] The method for manufacturing a semiconductor device according to Appendix 1 further includes:

[0159] In the semiconductor substrate in the peripheral region, on the first main surface side relative to the drift layer, multiple field confinement ring layers are formed inside the region surrounded by the channel stop layer.

[0160] A third interlayer insulating film is formed on the first main surface side relative to the semiconductor substrate;

[0161] Multiple contact grooves are formed in the third interlayer insulating film; and

[0162] Multiple field plates are formed on the first main surface side relative to the third interlayer insulating film.

[0163] During the formation of the field plate

[0164] Multiple field plates are connected to multiple field confinement ring layers via multiple contact grooves, and;

[0165] The outermost structure includes at least one of the following: a field confinement ring layer and a field plate arranged on the outermost layer among a plurality of field confinement ring layers and a plurality of field plates.

[0166] (Additional Statement 9)

[0167] The method for manufacturing a semiconductor device according to Appendix 1 further includes:

[0168] In the semiconductor substrate of the peripheral region, on the first main surface side relative to the drift layer, inside the region surrounded by the channel stop layer, a second conductivity type semiconductor layer is formed as a termination structure.

[0169] When forming a semiconductor layer, the outermost structure includes a semiconductor layer.

[0170] (Additional Statement 10)

[0171] The method for manufacturing a semiconductor device according to Appendix 1 further includes: forming a semiconductor element, wherein the semiconductor element includes a drift layer and a floating layer of a second conductivity type disposed on a first main surface side relative to the drift layer.

[0172] In the formation of semiconductor devices, the outermost structure includes a floating layer.

[0173] (Additional Statement 11)

[0174] The method for manufacturing a semiconductor device according to Additional Statement 1 further includes: forming an interlayer insulating film in a peripheral region on a first main surface side relative to the semiconductor substrate.

[0175] In the step of forming the interlayer insulating film, the interlayer insulating film is designed to fix positive charges.

[0176] (Additional Statement 12)

[0177] The method of manufacturing a semiconductor device according to Additional Statement 1 further includes: wherein, when setting a component region containing a semiconductor element and a peripheral region surrounding the component region, the peripheral region includes:

[0178] The third outer region surrounds the component area;

[0179] The second outer region surrounds the component region and the third outer region; and

[0180] The first outer region surrounds the component region, the third outer region, and the second outer region.

[0181] This method also includes:

[0182] Formed in the third peripheral region:

[0183] Drift layer;

[0184] A field confinement ring layer of the second conductivity type is disposed on the first main surface side relative to the drift layer;

[0185] A third interlayer insulating film is disposed on the first main surface side relative to a semiconductor substrate in which a field confinement ring layer is disposed; and

[0186] The field plate is disposed on the first main surface side relative to the third interlayer insulating film;

[0187] Formed in the second peripheral region:

[0188] Drift layer;

[0189] Protective ring layer; and

[0190] A second interlayer insulating film is disposed on the first main surface side relative to a semiconductor substrate in which a protective ring layer is disposed; and

[0191] Formed in the first peripheral region:

[0192] Drift layer;

[0193] Channel stopping layer;

[0194] A first interlayer insulating film is disposed on a first main surface side relative to a semiconductor substrate in which a channel stop layer is disposed; and

[0195] An equipotential ring is disposed on the first main surface side relative to the first interlayer insulating film, and the equipotential ring comprises a conductive material.

[0196] (Additional Statement 13)

[0197] The method of manufacturing a semiconductor device according to Additional Statement 1 further includes: forming a semiconductor element as an IGBT in an element region, wherein the IGBT comprises:

[0198] Drift layer;

[0199] A first conductive barrier layer is disposed on the first main surface side relative to the drift layer;

[0200] A body layer of the second conductivity type is disposed on the side of the first main surface relative to the barrier layer;

[0201] An emitter layer of a first conductivity type is disposed on the first main surface side relative to the bulk layer;

[0202] The trench gate electrode and the trench emitter electrode are configured to sandwich the barrier layer, the body layer and the emitter layer from both sides in one direction in a plane parallel to the first main surface.

[0203] A trench insulating film is disposed between the trench gate electrode and the semiconductor substrate, and between the trench emitter electrode and the semiconductor substrate; and

[0204] A floating layer of the second conductivity type is disposed on the opposite sides of the barrier layer, body layer, and emitter layer across the trench gate electrode, and on the opposite sides of the barrier layer, body layer, and emitter layer across the trench emitter electrode.

[0205] In particular, the protective ring layer is formed simultaneously with the barrier layer formed during the formation of the IGBT.

[0206] (Additional Statement 14)

[0207] According to the method of manufacturing a semiconductor device according to Additional Statement 13, in which the guard ring layer is designed to include impurities of the same type as those in the barrier layer when forming the guard ring layer.

[0208] (Additional Statement 15)

[0209] According to the method of manufacturing a semiconductor device according to Additional Statement 13, in forming a guard ring layer, the guard ring layer is designed to include the same concentration of impurities as the impurities in the barrier layer.

[0210] (Additional Statement 16)

[0211] The method of manufacturing a semiconductor device according to Additional Statement 1, wherein the semiconductor element is designed to include at least one of a MOSFET and a diode.

[0212] (Additional Statement 17)

[0213] The method for manufacturing a semiconductor device according to Appendix 1 further includes: forming a second interlayer insulating film on a first main surface side relative to the semiconductor substrate.

[0214] The formation of the protective ring layer involves introducing impurities of a first conductivity type into the semiconductor substrate through a second interlayer insulating film.

Claims

1. A semiconductor device comprising a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, wherein the semiconductor substrate comprises, in a plan view from the first main surface side: an element region including a semiconductor element; and a peripheral region surrounding the element region, wherein the semiconductor substrate in the peripheral region comprises: a drift layer of a first conductivity type; at least one annular channel stop layer of the first conductivity type arranged on the first main surface side with respect to the drift layer and surrounding the element region; and at least one annular guard ring layer of the first conductivity type arranged on the first main surface side with respect to the drift layer and between, in a plan view, an outermost structure within an interior surrounded by the channel stop layer and the channel stop layer, wherein the outermost structure comprises at least one of an annular semiconductor layer of a second conductivity type arranged on the first main surface side with respect to the drift layer and in the semiconductor substrate, and an annular field plate including a conductive material arranged on the first main surface side with respect to the semiconductor substrate; and wherein a concentration of impurities of the first conductivity type in the guard ring layer is greater than a concentration of impurities of the first conductivity type in the drift layer and less than a concentration of impurities of the first conductivity type in the channel stop layer.

2. The semiconductor device according to claim 1, wherein the guard ring layer is spaced apart from the channel stop layer.

3. The semiconductor device according to claim 1, wherein the semiconductor substrate in the peripheral region comprises a plurality of guard ring layers, and the plurality of guard ring layers are spaced apart from each other.

4. The semiconductor device according to claim 1, further comprising: a first interlayer insulating film provided on the first main surface side with respect to the semiconductor substrate in which the channel stop layer is arranged, and an equipotential ring provided on the first main surface side with respect to the first interlayer insulating film and including the conductive material, wherein the equipotential ring is connected to the channel stop layer through a contact groove formed in the first interlayer insulating film.

5. The semiconductor device according to claim 4, wherein the guard ring layer is spaced apart from the equipotential ring in a plan view.

6. The semiconductor device according to claim 1, further comprising: a first interlayer insulating film provided on the first main surface side with respect to the semiconductor substrate in which the channel stop layer is arranged, and a second interlayer insulating film provided on the first main surface side with respect to the semiconductor substrate in which the guard ring layer is arranged, wherein a thickness of the second interlayer insulating film is greater than a thickness of the first interlayer insulating film.

7. The semiconductor device according to claim 6, wherein the second interlayer insulating film includes LOCOS, and the guard ring layer is covered by the LOCOS.

8. The semiconductor device according to claim 1, ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ wherein the semiconductor substrate in the peripheral region includes a plurality of annular field limiting ring layers of the second conductivity type, which are arranged on the first main surface side with respect to the drift layer and are arranged within the inner portion surrounded by the channel stop layer, wherein the semiconductor device further includes a third interlayer insulating film provided on the first main surface side with respect to the semiconductor substrate in which the field limiting ring layers are arranged, wherein a plurality of field plates are connected to the plurality of field limiting ring layers through a plurality of contact grooves formed in the third interlayer insulating film, respectively, and wherein the outermost peripheral structure includes one of the field limiting ring layers and the field plates among the plurality of field limiting ring layers and the plurality of field plates arranged on the outermost periphery.

9. The semiconductor device according to claim 1, wherein the semiconductor substrate in the peripheral region includes a semiconductor layer of the second conductivity type, which is arranged on the first main surface side with respect to the drift layer, serves as a termination structure, and is arranged within the inner portion surrounded by the channel stop layer, and wherein the outermost peripheral structure includes the semiconductor layer.

10. The semiconductor device according to claim 1, wherein the semiconductor element includes: a drift layer; and a floating layer of the second conductivity type, which is arranged on the first main surface side with respect to the drift layer, and wherein the outermost peripheral structure includes the floating layer.

11. The semiconductor device according to claim 1, further comprising an interlayer insulating film provided on the first main surface side with respect to the semiconductor substrate in the peripheral region, wherein the interlayer insulating film is designed to fix a positive charge.

12. The semiconductor device according to claim 1, wherein the peripheral region includes: a third peripheral region surrounding the element region; a second peripheral region surrounding the element region and the third peripheral region; and a first peripheral region surrounding the element region, the third peripheral region, and the second peripheral region, wherein the third peripheral region includes: the drift layer; a field limiting ring layer of the second conductivity type arranged on the first main surface side with respect to the drift layer, a third interlayer insulating film provided on the first main surface side with respect to the semiconductor substrate in which the field limiting ring layer is arranged; and the field plate provided on the first main surface side with respect to the third interlayer insulating film, wherein the second peripheral region includes: the drift layer; the guard ring layer; and the second interlayer insulating film provided on the first main surface side with respect to the semiconductor substrate in which the guard ring layer is arranged, wherein the first peripheral region includes: the drift layer; the channel stop layer; a first interlayer insulating film provided on the first main surface side with respect to the semiconductor substrate in which the channel stop layer is arranged; and an equipotential ring provided on the first main surface side with respect to the first interlayer insulating film and including a conductive material.

13. The semiconductor device according to claim 1, wherein the semiconductor element includes an IGBT, wherein the IGBT includes: the drift layer; the barrier layer of the first conductivity type arranged on the first main surface side with respect to the drift layer; the body layer of the second conductivity type arranged on the first main surface side with respect to the barrier layer; and the emitter layer of the first conductivity type arranged on the first main surface side with respect to the body layer; a trench gate electrode and a trench emitter electrode disposed to sandwich the barrier layer, the body layer, and the emitter layer from both sides in a direction in a plane parallel to the first main surface; a trench insulating film disposed between the trench gate electrode and the semiconductor substrate, and between the trench emitter electrode and the semiconductor substrate; and the floating layer of the second conductivity type disposed on the opposite sides of the barrier layer, the body layer, and the emitter layer across the trench gate electrode, and on the opposite sides of the barrier layer, the body layer, and the emitter layer across the trench emitter electrode.

14. The semiconductor device according to claim 13, wherein the guard ring layer contains the same type of impurity as in the barrier layer.

15. The semiconductor device according to claim 13, wherein the guard ring layer contains the same concentration of impurity as in the barrier layer.

16. The semiconductor device according to claim 1, wherein the semiconductor element includes at least one of a MOSFET and a diode.

17. A method of manufacturing a semiconductor device, the method comprising: disposing, in a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, an element region including a semiconductor element and a peripheral region surrounding the element region, in a plan view from the first main surface side; forming, in the semiconductor substrate in the peripheral region, a drift layer of a first conductivity type and at least one annular channel stop layer of the first conductivity type arranged on the first main surface side with respect to the drift layer and surrounding the element region; and forming at least one annular guard ring layer of the first conductivity type arranged on the first main surface side with respect to the drift layer and between an outermost structure inside an interior surrounded by the channel stop layer and the channel stop layer, wherein, in forming the guard ring layer, the outermost structure is caused to include at least one of an annular semiconductor layer of a second conductivity type arranged on the first main surface side with respect to the drift layer in the semiconductor substrate, and an annular field plate containing a conductive material arranged on the first main surface side with respect to the semiconductor substrate; and wherein a concentration of an impurity of the first conductivity type in the guard ring layer is caused to be greater than a concentration of the impurity of the first conductivity type in the drift layer, and less than a concentration of the impurity of the first conductivity type in the channel stop layer. ​ 18. The method of claim 17, further comprising: forming an IGBT as the semiconductor element in the element region, wherein the IGBT is produced to include: the drift layer; the barrier layer of the first conductivity type arranged on the first main surface side with respect to the drift layer; the body layer of the second conductivity type arranged on the first main surface side with respect to the barrier layer; the emitter layer of the first conductivity type arranged on the first main surface side with respect to the body layer; the trench gate electrode and the trench emitter electrode provided to sandwich the barrier layer, the body layer, and the emitter layer from both sides in a direction in a plane parallel to the first main surface; the trench insulating film provided between the trench gate electrode and the semiconductor substrate, and between the trench emitter electrode and the semiconductor substrate; and the floating layer of the second conductivity type provided on the opposite sides of the barrier layer, the body layer, and the emitter layer across the trench gate electrode, and on the opposite sides of the barrier layer, the body layer, and the emitter layer across the trench emitter electrode, and wherein the guard ring layer is formed at the same time as the barrier layer at the time of forming the IGBT when forming the guard ring layer.

19. The method according to claim 17, wherein the peripheral region is caused to include: a third peripheral region surrounding the element region; a second peripheral region surrounding the element region and the third peripheral region; and a first peripheral region surrounding the element region, the third peripheral region, and the second peripheral region, wherein the method further includes: forming a first interlayer insulating film on the first main surface side of the semiconductor substrate in the first peripheral region; and forming a second interlayer insulating film on the first main surface side of the semiconductor substrate in the second peripheral region, wherein the thickness of the second interlayer insulating film is caused to be greater than the thickness of the first interlayer insulating film when forming the second interlayer insulating film.

20. The method according to claim 17, further including: forming a second interlayer insulating film on the first main surface side of the semiconductor substrate, wherein forming the guard ring layer includes introducing impurities of the first conductivity type into the semiconductor substrate through the second interlayer insulating film. ​

Images