Method for manufacturing semiconductor device, and semiconductor device

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A method for manufacturing a semiconductor device includes: preparing a semiconductor layer including a first main surface and a second main surface; the semiconductor layer includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type located on the first semiconductor region, and a control electrode provided so as to face the second semiconductor region across an insulating region. And a third semiconductor region of the first conductivity type located between the second main surface and the second semiconductor region. Forming a fourth semiconductor region in which the second conductivity type impurity concentration is the first concentration by ion implantation of the second conductivity type impurity into the first main surface; the first conductivity type impurity is ion-implanted into the first main surface in the outer peripheral region of the semiconductor layer to form a fifth semiconductor region in which the concentration of the second conductivity type impurity is substantially a second concentration lower than the first concentration after the first conductivity type impurity and the second conductivity type impurity are mutually compensated.

Description

[0001] [Related Applications]

[0002] This application enjoys priority based on Japanese Patent Application No. 2024-153418 (filed on September 5, 2024). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention generally relate to methods for manufacturing semiconductor devices and semiconductor devices. Background Technology

[0004] In semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), high avalanche tolerance is preferred. Summary of the Invention

[0005] A method for manufacturing a semiconductor device according to an embodiment includes preparing a semiconductor layer having a first main surface and a second main surface. The semiconductor layer includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type located above the first semiconductor region, a control electrode disposed opposite to the second semiconductor region with an insulating region between it and the second semiconductor region, and a third semiconductor region of the first conductivity type located between the second main surface and the second semiconductor region. The method further includes ion implanting a second conductivity type impurity into the first main surface of the semiconductor layer to form a fourth semiconductor region with a second conductivity type impurity concentration of a first concentration; and ion implanting a first conductivity type impurity into the first main surface of the semiconductor layer in an outer peripheral region extending from the side of the semiconductor layer toward the inner side of the semiconductor layer to form a fifth semiconductor region. The fifth semiconductor region has a substantial second conductivity type impurity concentration that is lower than the first concentration after mutual compensation between the first conductivity type impurity and the second conductivity type impurity.

[0006] According to this embodiment, a method for manufacturing a semiconductor device capable of producing a semiconductor device with improved avalanche tolerance can be provided. Attached Figure Description

[0007] Figure 1 This is a top view of the semiconductor device according to the first embodiment.

[0008] Figure 2 This is a bottom view of the semiconductor device according to the first embodiment.

[0009] Figure 3 This is a cross-sectional view of the semiconductor device according to the first embodiment, along... Figure 1 and Figure 2 A cross-sectional view along line AA.

[0010] Figure 4A This is a cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0011] Figure 4B It continues Figure 4A A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0012] Figure 4C It continues Figure 4B A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0013] Figure 4D It continues Figure 4C A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0014] Figure 4E It continues Figure 4D A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0015] Figure 4F It continues Figure 4E A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0016] Figure 5 This is a top view of the semiconductor device according to the second embodiment.

[0017] Figure 6 This is a bottom view of the semiconductor device according to the second embodiment.

[0018] Figure 7 This is a cross-sectional view of the semiconductor device according to the second embodiment, along... Figure 5 and Figure 6 A cross-sectional view of the BB line.

[0019] Figure 8 This is a bottom view of the semiconductor device of Modified Example 1 of the second embodiment.

[0020] Figure 9 It is a graph showing the evaluation results of short-circuit withstand capability in the semiconductor devices of the first embodiment, the second embodiment, and the comparative example.

[0021] Figure 10A This is a cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the second embodiment.

[0022] Figure 10B It continues Figure 10A A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the second embodiment.

[0023] Figure 10C It continues Figure 10B A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the second embodiment.

[0024] Figure 11 This is a bottom view of the semiconductor device of the second embodiment, variant 2.

[0025] Figure 12 This is a bottom view of the semiconductor device of Modified Example 3 of the second embodiment. Detailed Implementation

[0026] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the present invention. The drawings are schematic or conceptual, and the proportions of the parts may not be the same as in reality. In the specification and drawings, for elements already described in the drawings, the same reference numerals are used, and detailed descriptions are omitted where appropriate.

[0027] In addition, for ease of explanation, such as Figures 1-3 As shown, an orthogonal XYZ coordinate system is used. The Z-axis direction is the stacking direction (thickness direction) of the semiconductor device. Additionally, the emitter electrode side in the Z-axis direction is referred to as "upper," and the collector electrode side as "lower." However, this representation is for convenience and is independent of the direction of gravity.

[0028] Additionally, in the following explanation, to indicate the relative levels of impurity concentration in each conductivity type, n is sometimes used. + n, n - and p + p, p - The expression. That is, n + This indicates that the effective concentration of n-type impurities is relatively higher than that of n, n - This indicates that the effective concentration of n-type impurities is relatively lower than that of n. Additionally, p... + This indicates that the effective concentration of p-type impurities is relatively higher than that of p, p - This indicates that the effective p-type impurity concentration is relatively lower than p. Furthermore, in this application, the term "effective p-type (n-type) impurity concentration" refers to the actual p-type (n-type) impurity concentration after mutual compensation when both p-type and n-type impurities are present in each region. On the other hand, in this application, the simple term "p-type (n-type) impurity concentration" means that even when both p-type and n-type impurities are present in each region, these impurities mutually compensate for the previous p-type (n-type) impurity concentration. n-type, n + type and n - p-type is an example of the first conductivity type in the claims. + Type and p -The n-type is an example of the second conductivity type in the claims. Furthermore, in the following description, the n-type and p-type can also be reversed. That is, the first conductivity type can also be p-type.

[0029] Furthermore, the impurity concentration in the semiconductor region can be determined, for example, by secondary ion mass spectrometry (SIMS). Additionally, the relative level of impurity concentration can be determined, for example, by the carrier concentration obtained through scanning capacitance microscopy (SCM).

[0030] In addition, dimensions such as the width of semiconductor regions can be determined, for example, by surface and cross-sectional analysis using Transmission Electron Microscope (TEM), Energy Dispersive X-ray spectroscopy (EDX), and Scanning Electron Microscope (SEM).

[0031] (First Implementation)

[0032] Reference Figures 1-3 The semiconductor device 1 of the first embodiment will be described. Figure 1 This is a top view of the semiconductor device 1 according to the first embodiment. Figure 2 This is a bottom view of the semiconductor device 1 according to the first embodiment. Figure 3 This is a cross-sectional view of the semiconductor device 1 according to the first embodiment, along... Figure 1 and Figure 2 A cross-sectional view along line AA. Additionally, in Figure 1 The emitter electrode 12 is omitted in the text. Figure 2 Collector electrode 11 is omitted.

[0033] Semiconductor device 1 is, for example, an IGBT. In this embodiment, the case where semiconductor device 1 is a vertical IGBT with a trench gate structure will be described as an example. However, semiconductor device 1 may also be a vertical IGBT with a planar gate structure, etc.

[0034] like Figure 3 As shown, the semiconductor device 1 of this embodiment includes a semiconductor layer 2, a collector electrode 11, an emitter electrode 12, a gate electrode 13, and an insulating region 30.

[0035] Semiconductor layer 2 has a lower surface 2a, an upper surface 2b opposite to the lower surface 2a, and a side portion 2c. The lower surface 2a and the upper surface 2b are examples of the first main surface and the second main surface as stated in the claims, respectively.

[0036] Furthermore, semiconductor layer 2 has an outer peripheral region OA extending from side portion 2c of semiconductor layer 2 towards the inner side of semiconductor layer 2, and an inner region IA located further inward than the outer peripheral region OA. The inner region IA is the region that becomes the main path for current during the operation of semiconductor device 1, and is also referred to as a cell region. Figures 1-3 In the attached diagram, reference numeral B1 indicates the boundary between the outer peripheral region OA and the inner region IA. For example... Figure 1 as well as Figure 2 As shown, the outer peripheral region OA, located outside the boundary B1, surrounds the inner region IA, located inside the boundary B1.

[0037] like Figure 3 As shown, within semiconductor layer 2, for example, an n-base region 21, a buffer region 22, a p-base region 23, an emitter region 24, a collector region 25, a low-concentration region 27, and a guard ring region 28 are provided. Details of these regions will be described later.

[0038] Semiconductor layer 2 can be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate and an epitaxial layer disposed thereon. In this embodiment, semiconductor layer 2 is silicon (Si). In this case, arsenic (As), phosphorus (P), or antimony (Sb) is used as an n-type impurity, and boron (B) is used as a p-type impurity.

[0039] The collector electrode 11 functions as the collector of the IGBT. The collector electrode 11 is disposed on the lower surface 2a of the semiconductor layer 2, and is in contact with the collector region 25 and the low-concentration region 27. The collector electrode 11 is an example of the first electrode in the claims. The collector electrode 11 is, for example, made of a material comprising at least one of aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), etc.

[0040] The emitter electrode 12 functions as the emitter electrode of the IGBT. The emitter electrode 12 is disposed on the upper surface 2b of the semiconductor layer 2, and is in contact with the p-base region 23, the emitter region 24, and the protective region. The emitter electrode 12 is an example of the second electrode described in the claims. The emitter electrode 12 is, for example, made of a material comprising at least one of aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), etc.

[0041] The gate electrode 13 functions as the gate electrode of the IGBT. The gate electrode 13 is disposed opposite the p-base region 23, separated by an insulating region 30. In this embodiment, the gate electrode 13 is disposed within the p-base region 23, separated by the insulating region 30, and is electrically insulated from the emitter electrode 12 and the semiconductor layer 2 by the insulating region 30. The gate electrode 13 is an example of the control electrode described in the claims. The gate electrode 13 is, for example, made of polysilicon containing p-type or n-type impurities. When a voltage is applied to the gate electrode 13, a channel is formed in the p-base region 23, and charge carriers flow between the n-base region 21 and the emitter region 24. Thus, the IGBT becomes in the on state.

[0042] The insulating region 30 is provided in such a way that it covers the upper surface of the gate electrode 13 and the sidewalls of a plurality of trenches disposed on the upper surface 2b of the semiconductor layer 2. The insulating region 30 is, for example, an insulating film comprising silicon oxide or silicon nitride.

[0043] Next, a detailed description of each region located within semiconductor layer 2 will be provided.

[0044] like Figure 3 As shown, the n-base region 21 functions as the n-base region (drift region) of the IGBT. The n-base region 21 is located above the buffer region 22 (above the collector electrode 11). The n-base region 21 is an example of the first semiconductor region in the claims. For example, the n-base region 21 is an n... - The n-type semiconductor region. The effective n-type impurity concentration of the n-base region 21 is, for example, 1 × 10⁻⁶. 12 cm -3 Above and 1×10 15 cm -3 the following.

[0045] Buffer region 22 functions as a buffer region for the IGBT. Buffer region 22 is located between the n-base region 21 and the collector region 25. Buffer region 22 is an example of the sixth semiconductor region in the claims. Buffer region 22 is, for example, an n-base region. + The buffer region 22 has a higher n-type impurity concentration than the n-base region 21. Furthermore, the effective n-type impurity concentration of the buffer region 22 is higher than that of the n-base region 21. For example, the effective n-type impurity concentration of the buffer region 22 is 1 × 10⁻⁶. 15 cm -3 Above and 1×10 17 cm -3 the following.

[0046] like Figure 3As shown, the buffer region 22 includes a first portion 22a located within the outer peripheral region OA and a second portion 22b located within the inner region IA. The first portion 22a is located above the low concentration region 27, and the second portion 22b is located above the collector region 25.

[0047] In this embodiment, the concentration of n-type impurities in the first portion 22a is equal to the concentration of n-type impurities in the second portion 22b. That is, the effective concentration of n-type impurities in the first portion 22a is equal to the effective concentration of n-type impurities in the second portion 22b. Alternatively, the concentration of n-type impurities in the first portion 22a may be higher than the concentration of n-type impurities in the second portion 22b. In this case, the effective concentration of n-type impurities in the first portion 22a is higher than the effective concentration of n-type impurities in the second portion 22b.

[0048] Alternatively, the buffer region 22 may not be provided. In this case, for example, the n-base region 21 is also provided at the location of the buffer region 22. Alternatively, the n-base region 21 may not be provided. In this case, for example, the buffer region 22 is also provided at the location of the n-base region 21. Furthermore, in this case, the buffer region 22 is an example of the first semiconductor region in the claims.

[0049] The p-base region 23 functions as the p-base region of the IGBT. The p-base region 23 is located above the n-base region 21. The p-base region 23 is an example of the second semiconductor region described in the claims. The p-base region 23 is, for example, a p-type semiconductor region. The effective p-type impurity concentration of the p-base region 23 is, for example, 1 × 10⁻⁶. 17 cm -3 Above and 1×10 19 cm -3 The following. (e.g.) Figure 1 As shown, the p-base region 23 extends along the Y-axis. Furthermore, in Figure 3 In this example, the p-base region 23 has a third portion located below the emitter region 24 and a fourth portion extending from the third portion toward the upper surface 2b of the semiconductor layer 2 and penetrating the emitter region 24. The fourth portion contacts and is electrically connected to the emitter electrode 12. Furthermore, the effective p-type impurity concentration of the fourth portion can also be higher than the effective p-type impurity concentration of the third portion.

[0050] Emitter region 24 functions as the emitter region of the IGBT. Emitter region 24 is located above p-base region 23. Emitter region 24 is in contact with and electrically connected to emitter electrode 12. Emitter region 24 is an example of the third semiconductor region described in the claims. Figure 1 As shown, emitter region 24 extends along the Y-axis. Emitter region 24 is, for example, n +The emitter region 24 is a semiconductor region of type n. The effective n-type impurity concentration is, for example, 1 × 10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 the following.

[0051] Collector region 25 functions as the collector region of the IGBT. For example... Figure 3 As shown, collector region 25 is located between collector electrode 11 and n-base region 21, and more specifically, between collector electrode 11 and buffer region 22. Collector region 25 is in contact with and electrically connected to collector electrode 11. Collector region 25 is an example of the fourth semiconductor region in the claims. Collector region 25 is, for example, a p-type semiconductor region. The p-type impurity concentration of collector region 25 is a first concentration. Furthermore, the effective p-type impurity concentration of collector region 25 is, for example, 5 × 10⁻⁶. 17 cm -3 about.

[0052] The low-concentration region 27 is located within the outer peripheral region OA of the semiconductor layer 2. For example... Figure 2 As shown, the low-concentration region 27 is arranged to surround the collector region 25. Figure 3 As shown, the low-concentration region 27 is in contact with and electrically connected to the collector electrode 11. The low-concentration region 27 is an example of the fifth semiconductor region in the claims. The low-concentration region 27 contains both n-type and p-type impurities. The p-type impurity concentration in the low-concentration region 27 is, for example, a first concentration that is the same as the p-type impurity concentration in the collector region 25. On the other hand, the low-concentration region 27 may be, for example, a p-type impurity region. - The semiconductor region is a low-concentration region 27. Specifically, the effective p-type impurity concentration in this low-concentration region 27 is a second concentration lower than the first concentration. The second concentration is, for example, 1 × 10⁻⁶. 17 cm -3 about.

[0053] Furthermore, the values ​​of the first and second concentrations mentioned above are just one example; in other embodiments, they may vary by about one to two orders of magnitude.

[0054] Furthermore, as described later, the collector region 25 and the low-concentration region 27 are formed by forming a p-type semiconductor region (p-region 250) on the lower surface 2a of the semiconductor layer 2, and then anti-doping an n-type impurity on the lower surface 2a of the semiconductor layer 2 in the outer peripheral region OA. Therefore, the n-type impurity concentration in the low-concentration region 27 is higher than that in the collector region 25.

[0055] In this embodiment, such as Figure 1 as well as Figure 3As shown, a guard ring region 28 is provided. The guard ring region 28 is disposed within the outer peripheral region OA of the semiconductor layer 2. The guard ring region 28 is in contact with and electrically connected to the emitter electrode 12. Additionally, as... Figure 1 As shown, the guard ring region 28 contacts the end of the p-base region 23 in the Y-axis direction. The guard ring region 28 is, for example, a p-type semiconductor region. The effective p-type impurity concentration of the guard ring region 28 is, for example, 1 × 10⁻⁶. 17 cm -3 And 1×10 19 cm -3 The following applies. By setting the protection ring region 28, the withstand voltage of the semiconductor device 1 can be improved.

[0056] exist Figure 3 In this example, both the low-concentration region 27 and the protective ring region 28 are located within the outer peripheral region OA. On the other hand, neither the low-concentration region 27 nor the protective ring region 28 is located within the inner region IA. In other words, the inner ends of the low-concentration region 27 and the protective ring region 28 are aligned and located on the boundary B1. Furthermore, the inner ends of the low-concentration region 27 and the protective ring region 28 may not be aligned. That is, the inner end of the low-concentration region 27 may be located further inside or outside than the inner end of the protective ring region 28.

[0057] Furthermore, although not shown, the semiconductor device 1 may also include a field plate electrode (FP electrode) disposed within the semiconductor layer 2 through an insulating region. The FP electrode is electrically insulated from the semiconductor layer 2 by the insulating region and electrically connected to the emitter electrode 12. By providing such an FP electrode, when the IGBT is in the off state, the depletion layer extends from the FP electrode to the surrounding n-base region 21 by applying a voltage between the collector electrode 11 and the emitter electrode 12. By connecting this depletion layer to the depletion layers of adjacent FP electrodes, the withstand voltage of the semiconductor device 1 can be improved.

[0058] in addition, Figures 1-3 The structure of the semiconductor device 1 shown is an example, and this embodiment is not limited to it. For example, the number of gate electrodes 13 extending in the Y-axis direction, i.e., the number of insulating regions 30, can be greater than... Figure 1 There can be many examples, or few. Alternatively, a gate pad can be provided on the upper surface 2b of semiconductor layer 2.

[0059] As described above, the semiconductor device 1 of the first embodiment includes a semiconductor layer 2, a collector electrode 11, an emitter electrode 12, an n-base region 21 of a first conductivity type, a p-base region 23 of a second conductivity type, a gate electrode 13, an emitter region 24 of a first conductivity type, a collector region 25 of a second conductivity type, and a low-concentration region 27 of a second conductivity type. The semiconductor layer 2 has a lower surface 2a and an upper surface 2b. The collector electrode 11 is disposed on the lower surface 2a of the semiconductor layer 2. The emitter electrode 12 is disposed on the upper surface 2b of the semiconductor layer 2. The n-base region 21 is disposed within the semiconductor layer 2. The p-base region 23 is disposed within the semiconductor layer 2 and is located above the n-base region 21. The gate electrode 13 is disposed opposite to the p-base region 23 with an insulating region 30 between them. The emitter region 24 is disposed within the semiconductor layer 2, is located above the p-base region 23, and is electrically connected to the emitter electrode 12. The collector region 25 is disposed within the semiconductor layer 2, located between the collector electrode 11 and the n-base region 21, and electrically connected to the collector electrode 11. The p-type impurity concentration is a first concentration. The low-concentration region 27 is disposed within the outer peripheral region OA extending from the side portion 2c of the semiconductor layer 2 towards the inner side of the semiconductor layer 2, and is electrically connected to the collector electrode 11. The low-concentration region 27 contains both n-type and p-type impurities, and is a second concentration where the p-type impurity concentration is the first concentration, but the n-type and p-type impurities have been mutually compensated, resulting in a p-type impurity concentration that is actually lower than the first concentration.

[0060] In this embodiment, by setting a low-concentration region 27, the avalanche tolerance of the semiconductor device 1 can be improved.

[0061] <Manufacturing Method of Semiconductor Device 1>

[0062] Next, refer to Figures 4A-4F An example of the manufacturing method of the semiconductor device 1 of this embodiment will be described. Figures 4A-4F This is a cross-sectional view illustrating an example of the manufacturing process of the semiconductor device 1 according to the first embodiment. Furthermore, in Figures 4A-4F In the text, the portion of the through-emitter region 24 in the p-base region 23 is omitted (Part Four).

[0063] First, such as Figure 4A As shown, a semiconductor layer 2 is prepared having a lower surface 2a and an upper surface 2b opposite to the lower surface 2a. The semiconductor layer 2 includes a gate electrode 13, an n-base region 21, a p-base region 23, an emitter region 24, a guard ring region 28, and an insulating region 30.

[0064] Next, as Figure 4BAs shown, a buffer region 22 is formed below the n-base region 21 by ion implantation of n-type impurities into the lower surface 2a of the semiconductor layer 2. The n-type impurities used here are, for example, at least one of phosphorus (P) and arsenic (As). The concentration of n-type impurities in the buffer region 22 is higher than that in the n-base region 21.

[0065] Next, as Figure 4C As shown, a p-region 250 is formed by ion implantation of a p-type impurity into the lower surface 2a of the semiconductor layer 2. The p-type impurity used is, for example, boron (B). The p-region 250 is an example of the fourth semiconductor region described in the claims. The p-region 250 is, for example, a p-type semiconductor region. Furthermore, the concentration of the p-type impurity in the formed p-region 250 is a first concentration.

[0066] Next, as Figure 4D As shown, a photoresist 41 is formed on a portion of the lower surface 2a of the semiconductor layer 2. More specifically, after the photoresist is formed on the entire lower surface 2a of the semiconductor layer 2, the portion of the photoresist located in the outer peripheral region OA is removed by photolithography or the like. Thus, the photoresist 41 is formed on the lower surface 2a of the semiconductor layer 2 outside the outer peripheral region OA, i.e., in the inner region IA.

[0067] Next, as Figure 4E As shown, a low-concentration region 27 is formed by ion implantation (anti-doping) of n-type impurities into the lower surface 2a of semiconductor layer 2. More specifically, the low-concentration region 27 is formed by ion implantation of n-type impurities into the peripheral region OA of the lower surface 2a of semiconductor layer 2, which is not covered by resist 41. The n-type impurity used here is, for example, at least one of phosphorus (P) and arsenic (As). The p-type impurity concentration of the low-concentration region 27 is a first concentration. On the other hand, the effective p-type impurity concentration of the low-concentration region 27 is a second concentration, which is lower than the first concentration. Through this process, a collector region 25 is formed in the portion of p-region 250 covered by resist 41. Furthermore, the n-type impurity concentration of the low-concentration region 27 is higher than the n-type impurity concentration of the collector region 25.

[0068] Furthermore, during the process of forming the low-concentration region 27, some n-type impurities sometimes diffuse into the buffer region 22. Therefore, when the buffer region 22 is divided into a first part 22a located in the outer peripheral region OA and a second part 22b located in the inner region IA, the concentration of n-type impurities in the first part 22a can be higher than the concentration of n-type impurities in the second part 22b.

[0069] Next, as Figure 4F As shown, remove resist 41.

[0070] Subsequently, although not shown in the figure, a collector electrode 11 and an emitter electrode 12 are formed on the lower surface 2a and upper surface 2b of the semiconductor layer 2, respectively.

[0071] Semiconductor device 1 is manufactured through the above processes.

[0072] As explained above, in the manufacturing method of the semiconductor device 1 in the first embodiment, a semiconductor layer 2 having a lower surface 2a and an upper surface 2b is prepared. The semiconductor layer 2 includes an n-type base region 21 of a first conductivity type, a p-type base region 23 of a second conductivity type located above the n-type base region 21, a gate electrode 13 disposed opposite to the p-type base region 23 with an insulating region 30 between it, and an emitter region 24 of a first conductivity type located between the upper surface 2b of the semiconductor layer 2 and the p-type base region 23. P-type impurities are ion-implanted into the lower surface 2a of the semiconductor layer 2 to form a p-region 250 with a p-type impurity concentration of a first concentration. N-type impurities are ion-implanted into the lower surface 2a of the semiconductor layer 2 in the outer peripheral region OA of the semiconductor layer 2 to form a low-concentration region 27 where the actual p-type impurity concentration is a second concentration lower than the first concentration after mutual compensation of n-type and p-type impurities.

[0073] According to the manufacturing method of the semiconductor device 1 of this embodiment, a low-concentration region 27 with an effective p-type impurity concentration lower than that of the collector region 25 can be formed in the peripheral region OA. Therefore, it is possible to manufacture a semiconductor device 1 with improved avalanche tolerance.

[0074] Furthermore, in the manufacturing method of this embodiment, after forming the p-region 250, a low-concentration region 27 is formed by ion implantation of n-type impurities (anti-doping) into the peripheral region OA. Forming the low-concentration region 27 includes: forming a photoresist on the lower surface 2a of the semiconductor layer 2, removing the portion of the photoresist located in the peripheral region OA; ion implanting an n-type impurity into the lower surface 2a of the semiconductor layer 2; and removing the remaining portion of the photoresist (photoresist 41). This avoids photolithography in the inner region IA, preventing the formation of regions with lower p-type impurity concentrations (pattern defects) in the collector region 25 at undesirable locations due to dust adhesion or photoresist residue in the inner region IA. As a result, the reduction in short-circuit withstand capability of the semiconductor device 1 due to pattern defects in the collector region 25 can be suppressed.

[0075] Furthermore, by intentionally forming a region with an effective low concentration of p-type impurities in the collector region 25, it is possible to suppress the decrease in short-circuit withstand capability and to accelerate the switching speed of the semiconductor device 1. Hereinafter, this will be described as a second embodiment.

[0076] (Second Implementation)

[0077] Reference Figures 5-7 The semiconductor device 1A of the second embodiment will be described. Figure 5 This is a top view of the semiconductor device 1A according to the second embodiment. Figure 6 This is a bottom view of the semiconductor device 1A according to the second embodiment. Figure 7 This is a cross-sectional view of the semiconductor device 1A according to the second embodiment, along... Figure 5 and Figure 6 A cross-sectional view along the BB line. Additionally, in Figure 5 The emitter electrode 12 is omitted in the text. Figure 6 The current collector electrode 11 is omitted. One difference between this embodiment and the first embodiment is the presence of the low concentration region 26. Hereinafter, this embodiment will be described focusing on the differences from the first embodiment.

[0078] like Figures 5-7 As shown, the semiconductor device 1A further includes a low-concentration region 26. The low-concentration region 26 is provided such that it is surrounded by a collector region 25 within the semiconductor layer 2. That is, the collector regions 25 are provided on both sides of the low-concentration region 26 along the X-axis direction and on both sides of the low-concentration region 26 along the Y-axis direction. Furthermore, the low-concentration region 26 is isolated from the low-concentration region 27 by the collector regions 25. The low-concentration region 26 is in contact with and electrically connected to the collector electrode 11. The low-concentration region 26 is an example of the seventh semiconductor region in the claims. The low-concentration region 27 contains n-type impurities and p-type impurities. The p-type impurity concentration of the low-concentration region 27 is, for example, a first concentration that is the same as the p-type impurity concentration of the collector region 25. On the other hand, the low-concentration region 26 is, for example, a p-type impurity concentration. - The semiconductor region is a type of low-concentration region. Specifically, the effective p-type impurity concentration in low-concentration region 26 is a third concentration, lower than the first concentration. The third concentration is, for example, 1 × 10⁻⁶. 16 cm -3 Above and less than 5×10 17 cm -3 .

[0079] Furthermore, as described later, the low-concentration region 26 is formed by reverse-doping the p-region 250 with n-type impurities. Therefore, the n-type impurity concentration in the low-concentration region 26 is higher than the n-type impurity concentration in the collector region 25.

[0080] like Figure 7 As shown, in this embodiment, the buffer region 22 includes a first portion 22a located within the outer peripheral region OA and a second portion 22b and a fifth portion 22c located within the inner region IA. The first portion 22a is located above the low concentration region 27, the second portion 22b is located above the collector region 25, and the fifth portion 22c is located above the low concentration region 26.

[0081] In this embodiment, the concentration of n-type impurities in the fifth part 22c is equal to the concentration of n-type impurities in the second part 22b. That is, the effective concentration of n-type impurities in the fifth part 22c is equal to the effective concentration of n-type impurities in the second part 22b. Alternatively, the concentration of n-type impurities in the fifth part 22c may be higher than the concentration of n-type impurities in the second part 22b. In this case, the effective concentration of n-type impurities in the fifth part 22c is higher than the effective concentration of n-type impurities in the second part 22b.

[0082] like Figure 5 and Figure 6 As shown, in this embodiment, the low concentration region 26 is located at the center of the inner region IA, that is, the center of the collector region 25.

[0083] Alternatively, the low-concentration region 26 may also be located outside the center of the inner region IA. Figure 8 This is a bottom view of the semiconductor device 1B of Modified Example 1 of the second embodiment. Figure 8 In the attached drawing, reference numeral B2 indicates a position one-quarter of the width d of the inner region IA, located away from the boundary B1 between the outer peripheral region OA and the inner region IA. Figure 8 In the example, the low-concentration region 26 is not located at the center of the inner region IA. However, the low-concentration region 26 is located in a region that is further inside the boundary B2 (hereinafter also referred to as the "cell center"). In other words, the low-concentration region 26 is located more than one-quarter of the width d of the inner region IA from the boundary B1. More specifically, the low-concentration region 26 is located more than one-quarter of the length of the inner region IA in the X-axis direction from the boundary B1, and more than one-quarter of the length of the inner region IA in the Y-axis direction from the boundary B1.

[0084] In addition, Figure 8 In the example, the planar shape of the inner region IA is square. However, it is not limited to this; the planar shape of the inner region IA can also be rectangular. In this case, the low-concentration region 26 is also set to extend more than one-quarter of its length from the boundary B1 along the X-axis direction of the inner region IA, and more than one-quarter of its length from the boundary B1 along the Y-axis direction of the inner region IA.

[0085] exist Figure 6 and Figure 8 In the example, the width of the low-concentration region 26 is more than 1 / 60th of the width of the semiconductor layer 2. More specifically, the length of the low-concentration region 26 in both the X-axis and Y-axis directions is more than 1 / 60th of the larger of the lengths in the X-axis and Y-axis directions of the semiconductor layer 2.

[0086] In addition, Figure 6 andFigure 8 In the example, the planar shape of the low-concentration region 26 is circular. Furthermore, the planar shape of the low-concentration region 26 can be arbitrary, and can also be rectangular, polygonal, etc.

[0087] By setting up collector region 25, low concentration region 26, and low concentration region 27, the effective p-type impurity concentration along the X-axis and Y-axis directions increases from low concentration region 26 to collector region 25, and then decreases from collector region 25 to low concentration region 27.

[0088] In this embodiment, the effective p-type impurity concentration, i.e., the second concentration, in the low-concentration region 27 is equal to the effective p-type impurity concentration, i.e., the third concentration, in the low-concentration region 26. Alternatively, the second concentration may be lower than the third concentration.

[0089] Furthermore, the aforementioned third concentration value is one example, and in other embodiments it can vary by about one to two orders of magnitude.

[0090] in addition, Figures 6-8 The structure of the semiconductor device 1A shown is an example, and this embodiment is not limited to it. For example, in Figure 6 and Figure 8 In this example, the low-concentration region 26 is located below the gate electrode 13. However, it is not limited to this; it can also be located outside of both the low-concentration region 26 and the gate electrode 13. That is, the positional relationship between the low-concentration region 26 and the gate electrode 13 is arbitrary.

[0091] In this embodiment, the low-concentration region 26 is arranged to be surrounded by the collector region 25. This suppresses the amount of hole injection from the collector region 25 to the n-base region 21, reducing the switching losses of the semiconductor device 1A. Here, switching losses refer to the power losses generated when the semiconductor device 1A is turned on and off. According to this embodiment, the low-concentration region 26 is surrounded by the collector region 25, thereby more effectively suppressing the amount of hole injection compared to the case where it is arranged around the collector region 25. Therefore, according to this embodiment, the switching speed of the semiconductor device 1A can be increased.

[0092] Furthermore, in this embodiment, the p-type impurity concentration in low-concentration region 27 is equal to the p-type impurity concentration in low-concentration region 26. Therefore, as described later, low-concentration region 26 and low-concentration region 27 can be formed simultaneously. Additionally, the p-type impurity concentration in low-concentration region 27 can be lower than the p-type impurity concentration in low-concentration region 26. This further improves the avalanche tolerance of semiconductor device 1A.

[0093] Furthermore, in this embodiment, the low-concentration region 26 is disposed at the center of the inner region IA on the lower surface 2a of the semiconductor layer 2. This reduces switching losses at the center of the inner region IA, where the current density is high, and enables efficient high-speed switching of the semiconductor device 1A.

[0094] Furthermore, the low-concentration region 26 extends from the boundary B1 between the outer peripheral region OA and the inner region IA by more than one-quarter of the width d of the inner region IA. This improves the short-circuit withstand capability of the semiconductor device 1A. Referring hereafter... Figure 9 This effect will be explained in detail. Figure 9 It is a graph showing the evaluation results of short-circuit withstand capability in the semiconductor devices of the first embodiment, the second embodiment, and the comparative example.

[0095] Figure 9 The horizontal axis represents the diameter and location of the low-concentration region 26 in each semiconductor device used in the short-circuit withstand capability evaluation. "None" indicates that no low-concentration region 26 is provided. "Small," "Medium," and "Large" indicate that the diameter of the low-concentration region 26 is 1 / 300, 1 / 100, and 1 / 60 of the width of the semiconductor layer 2, respectively. "Center of cell" indicates that the low-concentration region 26 is located in... Figure 8 The case where the low-concentration region 26 is located inside boundary B2 (cell center) refers to the case where the low-concentration region 26 has moved more than one-quarter of the width d of the inner region IA from the boundary B1 between the outer peripheral region OA and the inner region IA. "Cell end" refers to the case where the low-concentration region 26 is located in the region between boundary B1 and boundary B2 (cell end), that is, the case where the low-concentration region 26 has not moved more than one-quarter of the width d of the inner region IA from boundary B1. The semiconductor device 1 of the first embodiment corresponds to... Figure 9 The case of "none" in the text. Furthermore, both the semiconductor device 1A of the second embodiment and the semiconductor device 1B of the modified example 1 of the second embodiment are equivalent to... Figure 9 The case where the "unit is in the center" and is "large". Figure 9 The vertical axis represents the gate-emitter voltage applied to each semiconductor device. The cross (×) in the chart indicates the gate-emitter voltage at which the semiconductor device is damaged, and the circle (○) indicates the gate-emitter voltage at which the semiconductor device is not damaged.

[0096] like Figure 9As shown, when the low-concentration region 26 is located at the "cell center," the short-circuit withstand capability of the semiconductor device is higher than that at the "cell end," regardless of the size of the low-concentration region 26. More specifically, the short-circuit withstand capability is higher when the region is at the "cell center" and "small" compared to the "cell end" and "small" case; higher when the region is at the "cell center" and "medium" compared to the "cell end" and "medium" case; and higher when the region is at the "cell center" and "large" compared to the "cell end" and "large" case. Therefore, the low-concentration region 26 is located more than one-quarter of the width d of the inner region IA from the boundary B1 between the outer peripheral region OA and the inner region IA, thereby improving the short-circuit withstand capability of the semiconductor device 1A.

[0097] In addition, such as Figure 9 As shown, in the case of "center of cell" and "large", compared with the cases of "center of cell" and "small" or "center of cell" and "medium", the short-circuit withstand capability of the semiconductor device is observed to decrease. However, although not shown, in the case of "center of cell" and "large", the failure mode of the semiconductor device changes. More specifically, in the cases of "center of cell" and "small" or "center of cell" and "medium", the failure mode of the semiconductor device is failure upon disconnection. On the other hand, in the case of "center of cell" and "large", the failure mode of the semiconductor device is thermal failure after disconnection, i.e., BT (Bias Temperature) failure. Therefore, when the low-concentration region 26 is located in the center of the cell, by further increasing the width of the low-concentration region 26 to more than 1 / 60th of the width of the semiconductor layer 2, the short-circuit withstand capability of the semiconductor device 1A can be further improved.

[0098] <Manufacturing Method of Semiconductor Device 1A>

[0099] Next, refer to Figures 10A-10C An example of the manufacturing method of the semiconductor device 1A of this embodiment will be described, focusing on the differences from the first embodiment. Figures 10A-10C This is a cross-sectional view illustrating an example of the manufacturing process of the semiconductor device 1A according to the second embodiment. Furthermore, in Figures 10A-10C The portion of the p-base region 23 that contacts the emitter electrode 12 is omitted (Part Four).

[0100] In reference Figure 4C After the process of forming region p250 as described above, such as Figure 10A As shown, a photoresist 41A is formed on a portion of the lower surface 2a of the semiconductor layer 2. More specifically, after the photoresist is formed on the lower surface 2a of the semiconductor layer 2, the portion of the photoresist located in the peripheral region OA and the opening H portion that subsequently forms the low-concentration region 26 are removed by photolithography or the like. Thus, a... Figure 10AThe resist shown is 41A.

[0101] Next, as Figure 10B As shown, low-concentration regions 26 and 27 are formed by ion implantation (anti-doping) of n-type impurities on the lower surface 2a of semiconductor layer 2. More specifically, low-concentration regions 26 and 27 are formed by ion implantation of n-type impurities into the peripheral region OA and opening H of the lower surface 2a of semiconductor layer 2 that are not covered by resist 41A. The n-type impurities used here are, for example, at least one of phosphorus (P) and arsenic (As). The p-type impurity concentrations of low-concentration regions 26 and 27 are both at a first concentration. On the other hand, the effective p-type impurity concentration of low-concentration region 26 is a third concentration lower than the first concentration, and the effective p-type impurity concentration of low-concentration region 27 is a second concentration lower than the first concentration. Through this process, a collector region 25 is formed in the portion of p-region 250 covered by resist 41A. Furthermore, the n-type impurity concentrations of low-concentration regions 26 and 27 are both higher than the n-type impurity concentration of collector region 25.

[0102] Furthermore, during the process of forming low-concentration regions 26 and 27, some n-type impurities sometimes diffuse into the buffer region 22. Therefore, when the buffer region 22 is divided into a first part 22a located within the outer peripheral region OA, a second part 22b located within the inner region IA, and a fifth part 22c located above the low-concentration region 26, the concentration of n-type impurities in the first part 22a can be higher than the concentration of n-type impurities in both the second part 22b and the fifth part 22c.

[0103] The subsequent procedures are the same as in the first implementation method.

[0104] As explained above, in the manufacturing method of the semiconductor device 1A in the second embodiment, after the p region 250 is formed, a portion of the lower surface 2a of the semiconductor layer 2 in the inner region IA is ion-implanted with n-type impurities to form a low-concentration region 26 surrounded by the collector region 25, where the n-type impurities and p-type impurities are mutually compensated, and the actual p-type impurity concentration is a third concentration lower than the first concentration.

[0105] Thus, it is possible to manufacture a semiconductor device 1A with high-speed switching.

[0106] Furthermore, according to the manufacturing method of the semiconductor device 1A of this embodiment, the low-concentration region 26 and the low-concentration region 27 can be formed together. In this case, the second concentration is equal to the third concentration.

[0107] Furthermore, the low-concentration region 26 can be formed before or after the formation of the low-concentration region 27. This allows the second concentration to be different from the third concentration. For example, by making the second concentration lower than the third concentration, it is possible to manufacture a semiconductor device 1A with further improved avalanche tolerance.

[0108] Alternatively, multiple low-concentration zones can be set. See below for reference. Figure 11 The semiconductor device 1C of the second embodiment, variant 2, will be described. Figure 11 This is a bottom view of the semiconductor device 1C of Modified Example 2 of the second embodiment. Hereinafter, this embodiment will be described focusing on the differences from the second embodiment.

[0109] like Figure 11 As shown, the semiconductor device 1C of this modified example has multiple low-concentration regions 26. Specifically, in Figure 11 In the example, the semiconductor device 1C has five low-concentration regions 26. Furthermore, the number of low-concentration regions 26 can be four or fewer, or six or more.

[0110] Each low-concentration region 26 is arranged within the semiconductor layer 2 and surrounded by the collector region 25, and is separated from each other. Each low-concentration region 26 is in contact with the collector electrode 11 and is electrically connected to the collector electrode 11.

[0111] The effective p-type impurity concentration in each low-concentration region 26 is lower than that in the collector region 25. Furthermore, the effective p-type impurity concentration in each low-concentration region 26 may be equal, or at least one low-concentration region 26 may have a different effective p-type impurity concentration than the other low-concentration regions 26.

[0112] exist Figure 11 In the example, each low-concentration region 26 is located inside the boundary B2 (in the center of the cell). In addition, one of the multiple low-concentration regions 26 is located at the center of the lower surface 2a of the semiconductor layer 2.

[0113] In addition, Figure 11In this example, multiple low-concentration regions 26 are symmetrically arranged on the lower surface 2a of the semiconductor layer 2. More specifically, the multiple low-concentration regions 26 are symmetrically arranged about a straight line passing through the center of the lower surface 2a of the semiconductor layer 2 and parallel to the X-axis, and about a straight line passing through the center and parallel to the Y-axis. This allows for efficient high-speed switching of the semiconductor device 1C. Furthermore, the multiple low-concentration regions 26 may also be symmetrically arranged about at least one straight line passing through the center of the lower surface 2a of the semiconductor layer 2 and parallel to the XY plane. Alternatively, the multiple low-concentration regions 26 may also be symmetrically arranged about the center of the lower surface 2a of the semiconductor layer 2.

[0114] According to this embodiment, by providing multiple low-concentration regions 26, the switching speed of the semiconductor device 1C can be increased.

[0115] Furthermore, multiple low-concentration regions 26 can also be configured such that the density increases as the distance approaches the center of the lower surface 2a of the semiconductor layer 2. Figure 12 This is a bottom view of the semiconductor device 1D of the modified example 3 of the second embodiment.

[0116] exist Figure 12 In the example, the low-concentration region near the center of the lower surface 2a of the semiconductor layer 2 is closer to other low-concentration regions 26 than the low-concentration region near the boundary B2. Therefore, in the semiconductor device 1C, the density of the low-concentration region 26 near the center of the lower surface 2a of the semiconductor layer 2 is higher than that near the boundary B2. That is, in Figure 12 In the example, multiple low-concentration regions 26 are configured such that the density increases as the distance approaches the center of the lower surface 2a of the semiconductor layer 2. This enables efficient high-speed switching of the semiconductor device 1D.

[0117] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A method for manufacturing a semiconductor device, preparing a semiconductor layer having a first main surface and a second main surface, the semiconductor layer including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type located above the first semiconductor region, a control electrode provided so as to face the second semiconductor region with an insulating region interposed therebetween, and a third semiconductor region of the first conductivity type located between the second main surface and the second semiconductor region; ion-implanting impurities of the second conductivity type into the first main surface of the semiconductor layer to form a fourth semiconductor region in which a concentration of impurities of the second conductivity type is a first concentration; ion-implanting impurities of the first conductivity type into the first main surface of the semiconductor layer in a peripheral region extending from a side portion of the semiconductor layer toward an inner side of the semiconductor layer to form a fifth semiconductor region in which a concentration of impurities of the first conductivity type and a concentration of impurities of the second conductivity type after mutual compensation therebetween are substantially a second conductivity type concentration lower than the first concentration.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the concentration of impurities of the first conductivity type in the fifth semiconductor region is higher than the concentration of impurities of the first conductivity type in the fourth semiconductor region.

3. The method for manufacturing a semiconductor device according to claim 2, wherein after the fourth semiconductor region is formed, impurities of the first conductivity type are ion-implanted into a portion of the first main surface of the semiconductor layer in an inner side region inside the peripheral region to form a seventh semiconductor region surrounded by the fourth semiconductor region and having a concentration of impurities of the second conductivity type after mutual compensation between impurities of the first conductivity type and impurities of the second conductivity type, which is a third concentration lower than the first concentration.

4. The method for manufacturing a semiconductor device according to claim 1, wherein after the semiconductor layer is prepared, before the fourth semiconductor region is formed, impurities of the first conductivity type are ion-implanted into the first main surface of the semiconductor layer to form a sixth semiconductor region having a higher concentration of impurities of the first conductivity type than the first semiconductor region.

5. The method for manufacturing a semiconductor device according to claim 4, wherein after the fourth semiconductor region is formed, impurities of the first conductivity type are ion-implanted into a portion of the first main surface of the semiconductor layer in an inner side region inside the peripheral region to form a seventh semiconductor region surrounded by the fourth semiconductor region and having a concentration of impurities of the second conductivity type after mutual compensation between impurities of the first conductivity type and impurities of the second conductivity type, which is a third concentration lower than the first concentration.

6. The method for manufacturing a semiconductor device according to claim 4, wherein the sixth semiconductor region has a first portion located in the peripheral region and a second portion located in an inner side region inside the peripheral region, the concentration of impurities of the first conductivity type in the first portion is higher than the concentration of impurities of the first conductivity type in the second portion.

7. The method according to claim 6, wherein after the fourth semiconductor region is formed, a portion of the first main face of the semiconductor layer in an inner region inside the outer region is ion-implanted with impurities of the first conductivity type to form a seventh semiconductor region surrounded by the fourth semiconductor region and having a substantially second-conductivity-type impurity concentration after mutual compensation between the first-conductivity-type impurities and the second-conductivity-type impurities of a third concentration lower than the first concentration.

8. The method according to claim 1, wherein forming the fifth semiconductor region includes: after the resist is formed on the first main face of the semiconductor layer, removing a portion of the resist located in the outer region; ion-implanting the first main face of the semiconductor layer with impurities of the first conductivity type; and removing the remaining portion of the resist.

9. The method according to claim 8, wherein after the fourth semiconductor region is formed, a portion of the first main face of the semiconductor layer in an inner region inside the outer region is ion-implanted with impurities of the first conductivity type to form a seventh semiconductor region surrounded by the fourth semiconductor region and having a substantially second-conductivity-type impurity concentration after mutual compensation between the first-conductivity-type impurities and the second-conductivity-type impurities of a third concentration lower than the first concentration.

10. The method according to claim 1, wherein the first conductivity type is n-type, the impurities of the first conductivity type used when forming the fifth semiconductor region are at least one of phosphorus and arsenic.

11. The method according to claim 10, wherein after the fourth semiconductor region is formed, a portion of the first main face of the semiconductor layer in an inner region inside the outer region is ion-implanted with impurities of the first conductivity type to form a seventh semiconductor region surrounded by the fourth semiconductor region and having a substantially second-conductivity-type impurity concentration after mutual compensation between the first-conductivity-type impurities and the second-conductivity-type impurities of a third concentration lower than the first concentration.

12. The method according to claim 1, wherein the second conductivity type is p-type, the impurities of the second conductivity type used when forming the fourth semiconductor region are boron.

13. The method according to claim 12, wherein after the fourth semiconductor region is formed, a portion of the first main face of the semiconductor layer in an inner region inside the outer region is ion-implanted with impurities of the first conductivity type to form a seventh semiconductor region surrounded by the fourth semiconductor region and having a substantially second-conductivity-type impurity concentration after mutual compensation between the first-conductivity-type impurities and the second-conductivity-type impurities of a third concentration lower than the first concentration.

14. The method according to claim 1, wherein After the fourth semiconductor region is formed, a portion of the first main face of the semiconductor layer in an inner region that is inside the outer region is ion-implanted with impurities of the first conductivity type to form a seventh semiconductor region that is surrounded by the fourth semiconductor region and has a third concentration of impurities of the second conductivity type that is substantially the second conductivity type after impurities of the first conductivity type and impurities of the second conductivity type have been mutually compensated for, the third concentration being lower than the first concentration.

15. A semiconductor device comprising: a semiconductor layer including a first main face and a second main face; a first electrode provided on the first main face; a second electrode provided on the second main face; a first semiconductor region of a first conductivity type provided in the semiconductor layer; a second semiconductor region of a second conductivity type provided in the semiconductor layer, above the first semiconductor region; a control electrode provided so as to face the second semiconductor region with an insulating region interposed therebetween; a third semiconductor region of the first conductivity type provided in the semiconductor layer, above the second semiconductor region, and electrically connected to the second electrode; a fourth semiconductor region of the second conductivity type provided in the semiconductor layer, between the first electrode and the first semiconductor region, and electrically connected to the first electrode, the fourth semiconductor region having a first concentration of impurities of the second conductivity type; and a fifth semiconductor region of the second conductivity type provided in an outer region extending from a side portion of the semiconductor layer toward an inner portion of the semiconductor layer, and electrically connected to the first electrode, the fifth semiconductor region containing impurities of the first conductivity type and impurities of the second conductivity type, the fifth semiconductor region having a first concentration of impurities of the second conductivity type, and a substantially second concentration of impurities of the second conductivity type after impurities of the first conductivity type and impurities of the second conductivity type have been mutually compensated for, the second concentration being lower than the first concentration.

16. The semiconductor device according to claim 15, wherein the fifth semiconductor region has a higher concentration of impurities of the first conductivity type than the fourth semiconductor region.

17. The semiconductor device according to claim 16, wherein the semiconductor device further comprises a seventh semiconductor region of the second conductivity type provided in the semiconductor layer so as to be surrounded by the fourth semiconductor region, and electrically connected to the first electrode, the seventh semiconductor region containing impurities of the first conductivity type and impurities of the second conductivity type, the seventh semiconductor region having a first concentration of impurities of the second conductivity type, and a substantially third concentration of impurities of the second conductivity type after impurities of the first conductivity type and impurities of the second conductivity type have been mutually compensated for, the third concentration being lower than the first concentration.

18. The semiconductor device according to claim 15, wherein the semiconductor device further comprises a sixth semiconductor region of the first conductivity type provided in the semiconductor layer, between the first semiconductor region and the fourth semiconductor region, the sixth semiconductor region having a higher concentration of impurities of the first conductivity type than the first semiconductor region, ​ The sixth semiconductor region includes a first portion in the outer peripheral region and a second portion in an inner region that is more inward than the outer peripheral region, The impurity concentration of the first conductive type in the first portion is higher than the impurity concentration of the first conductive type in the second portion.

19. The semiconductor device according to claim 18, wherein The semiconductor device further includes a seventh semiconductor region of the second conductive type that is provided in the semiconductor layer so as to be surrounded by the fourth semiconductor region, that is electrically connected to the first electrode, that includes an impurity of the first conductive type and an impurity of the second conductive type, that has the second concentration of the impurity of the second conductive type, and that has a third concentration of the impurity of the second conductive type that is substantially the second concentration after the impurity of the first conductive type and the impurity of the second conductive type have been mutually compensated for, the third concentration being lower than the first concentration.

20. The semiconductor device according to claim 15, wherein The semiconductor device further includes a seventh semiconductor region of the second conductive type that is provided in the semiconductor layer so as to be surrounded by the fourth semiconductor region, that is electrically connected to the first electrode, that includes an impurity of the first conductive type and an impurity of the second conductive type, that has the second concentration of the impurity of the second conductive type, and that has a third concentration of the impurity of the second conductive type that is substantially the second concentration after the impurity of the first conductive type and the impurity of the second conductive type have been mutually compensated for, the third concentration being lower than the first concentration.

Images