High electron mobility transistor, manufacturing method thereof and electronic equipment

Abstract

The invention provides a high-electron-mobility transistor, a manufacturing method thereof and electronic equipment, relates to the field of semiconductor devices, and can solve electric leakage and parasitic effects caused by impurities on a GaN substrate interface. The high electron mobility transistor comprises a GaN substrate, and a barrier function layer, a source electrode, a drain electrode and a grid electrode which are arranged on the GaN substrate. Wherein the source electrode, the drain electrode and the grid electrode are arranged on one side, far away from the GaN substrate, of the barrier function layer. The distance between the barrier function layer and the GaN substrate is smaller than or equal to 50 nm. In this way, the distance between the grid electrode and the GaN substrate is very small, so that when the grid electrode is in a reverse bias state, the depletion region can cover a two-dimensional electron gas channel (2DEG) and a substrate interface, a parasitic channel can be depleted, and then off-state electric leakage and a parasitic effect can be reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, and more particularly to a high electron mobility transistor, a method for fabricating the same, and an electronic device. Background Technology

[0002] Gallium nitride high electron mobility transistors (GaN HEMTs) are representative of wide-bandgap power semiconductor devices and have great potential in applications such as high-frequency power.

[0003] GaN HEMTs are typically obtained through epitaxial growth on sapphire, silicon (Si), or silicon carbide (SiC) substrates. Epitaxial growth on these heterogeneous substrates is accompanied by lattice mismatch, resulting in numerous dislocation defects. Furthermore, nucleation layers and buffer layers need to be grown before heteroepitaxial growth to obtain better material quality and improve channel electron transport characteristics. However, interface defects can form at the interfaces of these layers (nucleation layers, buffer layers, etc.), becoming potential electron traps. Material defects in RF devices can lead to stress-induced electron trapping and decreased current density, thereby degrading device performance.

[0004] With the development of materials technology, GaN self-supporting substrate technology has gradually matured. Using GaN homogeneous substrates for epitaxial growth can effectively solve the problems of dislocations and interface defects caused by lattice mismatch. However, due to the large number of dangling bonds on the surface of GaN substrates, a large number of impurities are adsorbed during substrate processing. Among them, Si impurities, as donor impurities, will form a layer of conductive parasitic channels in the subsequent epitaxial structure. This parasitic channel will cause a sharp increase in device leakage current and deteriorate reliability. At the same time, the presence of parasitic channels will also increase RF loss and impair RF performance. Summary of the Invention

[0005] This application provides a high electron mobility transistor and its fabrication method, as well as an electronic device, which can solve the leakage current and parasitic effects caused by interface impurities in gallium nitride (GaN) substrates.

[0006] This application provides a high electron mobility transistor (HEMT), which includes a GaN substrate and a barrier functional layer, a source, a drain, and a gate disposed on the GaN substrate. The source, drain, and gate are disposed on the side of the barrier functional layer away from the GaN substrate. In this HEMT, the distance between the barrier functional layer and the GaN substrate is less than or equal to 50 nm. This allows for a very small distance between the gate and the impurity channel, so that when the gate is in reverse bias, the depletion region can cover the 2DEG (2-dimensional electron gas) and the substrate interface, thereby depleting the parasitic channel, reducing off-state leakage current, and improving radio frequency performance.

[0007] In some possible implementations, the barrier functional layer is in contact with the GaN substrate, which ensures that the distance between the gate and the impurity channel is very small. Thus, when the gate is in reverse bias, the depletion region can cover the 2DEG channel and the substrate interface, thereby depleting the parasitic channel, reducing off-state leakage current and improving RF performance.

[0008] In some possible implementations, the aforementioned HEMT also includes a channel layer located between the barrier functional layer and the GaN substrate. The channel layer comprises GaN, and its thickness is less than or equal to 50 nm. In this case, on the one hand, the homoepitaxial GaN (channel layer) on the GaN substrate exhibits excellent crystal quality and lower defect density, resulting in higher channel electron mobility, greater output current density, and better device performance. On the other hand, the thin channel layer ensures a small distance between the gate and the impurity channel. Consequently, when the gate is in reverse bias, the depletion region can cover the 2DEG channel and the substrate interface, thereby depleting the parasitic channel and reducing off-state leakage current, thus improving RF performance.

[0009] In some possible implementations, the barrier functional layer includes a barrier layer comprising at least one of AlGaN (aluminum gallium nitride), AlInN (aluminum indium nitride), AlScN (aluminum scandium nitride), or AlN (aluminum nitride). By using such materials and controlling the Al composition to be above 10%, a higher polarization effect can be achieved, increasing the density of the two-dimensional electron gas (2DEG) and improving the output current density of the device.

[0010] In some possible implementations, the barrier functional layer also includes a cap layer, which is disposed on the side of the barrier layer away from the GaN substrate and contains GaN. The cap layer can protect the barrier layer.

[0011] In some possible implementations, the barrier functional layer also includes an insertion layer disposed on the side of the barrier layer close to the GaN substrate, and the insertion layer includes AlN. The insertion layer reduces alloy disorder scattering at the heterojunction interface, further improving the electron mobility of the device.

[0012] In some possible implementations, the thickness of the barrier functional layer is in the range of 1 nm to 50 nm. The main function of this barrier functional layer is to form a barrier layer. Under this band structure, electrons from the barrier layer and the surface donor levels will fall into the heterojunction quantum well, forming an extremely high electron surface density, thereby forming a 2DEG channel.

[0013] In some possible implementations, the distance between the gate and the GaN substrate is in the range of 1nm to 200nm, which can ensure that there is a small distance between the gate and the GaN substrate, and that the depletion region can cover the 2DEG channel and the substrate interface when the gate is in reverse bias.

[0014] This application also provides a method for fabricating a high electron mobility transistor (HEMT), the method comprising: providing a GaN substrate; fabricating a barrier functional layer on the GaN substrate; and fabricating a source, drain, and gate on the barrier functional layer. Using this method, by directly fabricating the barrier functional layer on the surface of the GaN substrate, a smaller distance is achieved between the gate and the GaN substrate. This distance primarily depends on the thickness of the barrier functional layer. Consequently, when the gate is in reverse bias, the depletion region can cover the 2DEG channel and the substrate interface, thereby depleting the parasitic channel, reducing off-state leakage current, avoiding RF losses, and improving RF performance.

[0015] This application also provides a method for fabricating a high electron mobility transistor (HEMT), which includes: providing a GaN substrate; fabricating a GaN layer with a thickness of less than 50 nm as a channel layer on the GaN substrate; and fabricating a barrier functional layer on the channel layer; fabricating the source, drain, and gate on the barrier functional layer. Using this fabrication method, the homoepitaxial GaN (channel layer) on the GaN substrate exhibits excellent crystal quality and lower defect density, thereby enabling higher channel electron mobility, greater output current density, and better device performance. Furthermore, due to the thinness of the channel layer, when the gate is in reverse bias, the depletion region can cover the 2DEG channel and substrate interface, thereby depleting parasitic channels, reducing off-state leakage current, avoiding RF losses, and improving RF performance.

[0016] This application also provides an electronic device comprising a circuit board and a high electron mobility transistor (HEMT) as provided in any of the aforementioned possible implementations, wherein the circuit board is electrically connected to the HEMT. Attached Figure Description

[0017] Figure 1 A schematic diagram of a GaN HEMT provided in an embodiment of this application;

[0018] Figure 2 A schematic diagram of a GaN HEMT provided in an embodiment of this application;

[0019] Figure 3 A schematic diagram of the barrier functional layer in a GaN HEMT provided in this application embodiment;

[0020] Figure 4 A flowchart illustrating a method for fabricating a GaN HEMT, as provided in an embodiment of this application;

[0021] Figure 5 This application provides a schematic diagram of the structure of a GaN HEMT during its fabrication process.

[0022] Figure 6 A flowchart illustrating a method for fabricating a GaN HEMT, as provided in an embodiment of this application;

[0023] Figure 7 This is a schematic diagram of the structure of a GaN HEMT during the fabrication process, provided as an embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] This application provides an electronic device employing a novel GaN HEMT structure. This structure involves directly growing a barrier layer on a GaN substrate, or growing an ultrathin (below 50 nm) channel layer on a GaN substrate followed by the barrier layer. This structure effectively addresses the leakage current and parasitic effects caused by interface impurities on the GaN substrate in existing technologies.

[0026] This application does not limit the form of the above-mentioned electronic device. The electronic device can be any electronic product that needs to use GaNHEMT, such as consumer electronics, home electronics, automotive electronics, financial terminal products, communication electronics, etc.

[0027] As illustrated, the aforementioned consumer electronics products can include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products can include smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. In-vehicle electronics products can include in-vehicle navigation systems, in-vehicle displays, etc. Financial terminal products can include automated teller machines (ATMs), self-service electronic devices, etc. Communication electronic products can include servers, storage devices, radar, base stations, routers, and other communication equipment.

[0028] Depending on actual needs, the above-mentioned electronic devices may also include other devices electrically connected to the GaN HEMT device, such as printed circuit boards (PCBs), input / output devices, etc. This application does not impose any restrictions on this.

[0029] This application does not limit the application fields of the aforementioned GaN HEMT-based electronic devices. For example, the electronic device may be a radio frequency power amplifier, used in radio frequency circuits in scenarios such as communication base stations, wireless routers (Wi-Fi), and terminals.

[0030] The structure of the GaN HEMT described above will be explained in detail below.

[0031] This embodiment illustrates a GaN HEMT, with reference to... Figure 1 As shown, the GaN HEMT includes a GaN substrate 100 and a barrier functional layer 200, a gate G, a source S, and a drain D disposed on the GaN substrate 100. The gate G, source S, and drain D are disposed on the side of the barrier functional layer 200 away from the GaN substrate 100.

[0032] Continue to refer to Figure 1As shown, in some possible implementations, the barrier functional layer 200 can be directly disposed on the surface of the GaN substrate 100, that is, the barrier functional layer 200 and the GaN substrate 100 can be in direct contact. In this case, the barrier functional layer 200 can form a semiconductor heterostructure with the GaN substrate 100, and a two-dimensional electron gas (2DEG) can be generated at the interface between the barrier functional layer 200 and the GaN substrate 100 (i.e., the heterojunction interface), thereby forming a channel.

[0033] The aforementioned barrier functional layer 200 is mainly composed of a material with a large band gap and is sandwiched between the gate G and the GaN substrate 100. Its main function is to form a barrier layer (see reference). Figure 3 In this band structure, electrons from the barrier layer and surface donor levels fall into the heterojunction quantum well, forming an extremely high electron surface density. At the same time, since the electrons falling into the quantum well are far away from the donor ions, Coulomb scattering is reduced, and its electron mobility is greatly improved compared to the bulk material, thus forming a 2DEG channel.

[0034] refer to Figure 1 As shown, by directly depositing the barrier functional layer 200 on the surface of the GaN substrate 100, the distance between the gate G and the GaN substrate 100 is very small, which can be reduced to below 200 nm (or, in other words, the distance between the gate G and the impurity channel is very small). This distance mainly depends on the thickness of the barrier functional layer 200. Thus, when the gate is in a reverse bias state (a negative voltage is applied to the gate, and a higher positive voltage is applied to the drain), the depletion region a (reference) Figure 1 It can cover the 2DEG channel and the substrate interface, thereby depleting the parasitic channel, reducing off-state leakage current, avoiding RF loss, and improving RF performance.

[0035] As another possible implementation method, refer to Figure 2 As shown, an ultrathin GaN channel layer 300 can be formed between the barrier functional layer 200 and the GaN substrate 100. That is, an ultrathin GaN layer (300) is grown on the GaN substrate 100, and then the barrier functional layer 200 is fabricated. On the one hand, the homoepitaxial GaN (channel layer 300) on the GaN substrate 100 has good crystal quality and lower defect density, which enables higher channel electron mobility, higher output current density of the device, and better device performance. On the other hand, since the channel layer 300 is thin, when the gate G is in reverse bias (the gate is subjected to a negative voltage and the drain is subjected to a higher positive voltage), the depletion region can be ensured to cover the 2DEG channel and the substrate interface, thereby depleting the parasitic channel, reducing off-state leakage current, avoiding RF loss, and improving RF performance.

[0036] Indicatively, in some possible implementations, the aforementioned channel layer 300 can be a GaN layer with a thickness of less than 50 nm (i.e., ≤50 nm).

[0037] It should be noted that although the channel layer 300 and the GaN substrate 100 can have the same material, i.e., homogeneous channels, since the channel layer 300 is epitaxially formed on the GaN substrate 100, there will be an interface between the channel layer 300 and the GaN substrate 100.

[0038] It should be understood that a small amount of impurities may exist at the interface between the channel layer 300 and the GaN substrate 100. The location of the interface and the thickness of the channel layer 300 can be determined by detecting the impurities at the interface. Secondary ion mass spectroscopy can be used for detection, but it is not a limitation.

[0039] In the existing technology, the impurity compensation method is used to introduce the deep master level impurities into the GaN epitaxial material to compensate for the donor impurities. In order to avoid the influence of the deep master level channel mobility, a channel layer with a large thickness (more than 300 nm) needs to be fabricated on the doped buffer layer. This method will introduce additional impurities to generate new traps, causing additional trap effects and increasing the RF loss.

[0040] In contrast, the GaN HEMT provided in this application adopts a novel structure based on a GaN self-supporting substrate. This involves directly fabricating a barrier functional layer 200 on the GaN substrate 100 without fabricating a channel layer, or fabricating an ultra-thin (below 50nm) channel layer 200 before fabricating the barrier functional layer 200. This novel structure allows for a very small distance between the gate G and the impurity channel. Therefore, when the gate G is in reverse bias, the depletion region can cover the 2DEG channel and the substrate interface, thereby depleting the parasitic channel. This reduces off-state leakage current, avoids RF losses, and improves RF performance.

[0041] In addition, compared with the existing technology that uses impurity compensation to introduce parasitic channels on the surface of the GaN substrate with impurity compensation in the main energy level, which will introduce additional impurity atoms and crystal defects, the novel structure provided in this embodiment does not require active impurity compensation, thereby ensuring crystal quality to the greatest extent.

[0042] The following provides further explanation of the aforementioned barrier functional layer 200 and related settings.

[0043] As can be seen, in some possible implementations, the thickness of the aforementioned barrier functional layer 200 can be in the range of 1 nm to 50 nm.

[0044] Additionally, refer to Figure 3As shown, in some possible implementations, the aforementioned barrier functional layer 200 may include a barrier layer 201, which serves as the main functional layer and is capable of forming a two-dimensional electron gas (2DEG) with high electron mobility at the interface between the barrier layer 200 and the GaN substrate 100.

[0045] As illustrated, in some possible implementations, the aforementioned barrier layer 201 may be one or more of materials with a large band gap, such as AlGaN (aluminum gallium nitride), AlInN (aluminum indium nitride), AlScN (aluminum scandium nitride), or AlN (aluminum nitride), but this application is not limited to this, and it can be set as needed in practice.

[0046] Schematic, in some possible implementations, the barrier layer 201 may be an AlGaN layer, in which case an AlGaN / GaN semiconductor heterojunction is formed between the AlGaN layer and the GaN substrate 100.

[0047] As illustrated, when the barrier layer 201 uses Al-containing materials such as AlGaN, AlInN, AlScN or AlN, the Al content in the material can be set to 10%, thereby achieving a higher polarization effect, increasing the density of the two-dimensional electron gas (2DEG), and improving the output current density of the device.

[0048] Of course, depending on actual needs, the barrier functional layer 200 may include other film layers in addition to the barrier layer 201.

[0049] For illustrative purposes only, please refer to the following: Figure 3 As shown, in some possible implementations, the barrier functional layer 200 may further include a cap layer 202 disposed on the upper surface (away from the substrate side) of the barrier layer 201, through which the cap layer 202 can protect the barrier layer 201. Indicatively, the cap layer 202 may include GaN, but is not limited to this.

[0050] In some possible implementations, the cap layer 202 can be a GaN layer with a thickness ranging from 0.1 nm to 1 nm. When the barrier layer 201 contains Al-containing materials such as AlGaN, AlInN, AlScN, or AlN, the cap layer 202 prevents Al oxidation, thereby providing a certain degree of protection for the surface of the barrier layer 201.

[0051] Continue to refer to Figure 3 As shown, in some possible implementations, the barrier functional layer 200 may further include an insertion layer 203 disposed below the barrier layer 201 (i.e., near the substrate side) to reduce alloy disorder scattering at the heterojunction interface and further improve the electron mobility of the device. Indicatively, the insertion layer 203 may include AlN, but is not limited to this.

[0052] As illustrated, in some possible implementations, the insertion layer 203 can be an AlN layer with a thickness ranging from 0.1 nm to 2 nm. When the barrier layer 201 is made of materials such as AlGaN, AlInN, or AlScN, the insertion layer 203 can reduce alloy disorder scattering at the heterojunction interface, thereby improving the electron mobility of the device.

[0053] In practice, the cap layer 202 and the insertion layer 203 can be selected based on the setting of the barrier layer 201, and this application does not impose any restrictions on this.

[0054] In addition, depending on actual needs, a dielectric layer may be provided between the barrier functional layer 200 and the gate G, or no dielectric layer may be provided; this application does not impose any restrictions on this.

[0055] Schematic, in some possible implementations, a dielectric layer is disposed between the barrier functional layer 200 and the gate G. In this structure, the gate G, the dielectric layer, and the barrier functional layer 200 form a MIS (metal insulator semiconductor) gate structure.

[0056] As illustrated, the dielectric layer can be one or more of the following dielectric materials: Si3N4 (silicon nitride), Al2O3 (alumina), HfO2 (hafnium dioxide), and SiO2 (silicon dioxide). The thickness of the dielectric layer can be in the range of 1 nm to 50 nm, and this application does not limit it.

[0057] As shown in the illustration, among some possible implementation methods, you can refer to... Figure 1 and Figure 2 As shown, no dielectric layer is disposed between the gate G and the barrier functional layer 200; the gate G can be directly disposed on the barrier functional layer 200. In this structure, the gate G and the barrier functional layer 200 form a "Schottky gate," that is, a Schottky junction.

[0058] The following description, in conjunction with the fabrication method, further illustrates the GaN HEMT provided in the embodiments of this application.

[0059] Indicative, such as Figure 4 As shown in the embodiment of this application, a method for fabricating a GaN HEMT is provided, which may include:

[0060] Step 11, Reference Figure 5 As shown in (a), a GaN substrate 100 is provided.

[0061] As illustrated, based on the doping type, the GaN substrate 100 can be an n-type doped GaN substrate, a p-type doped GaN substrate, or a high-resistivity GaN substrate. Based on the bevel cutting type, the GaN substrate 100 can be a c-plane substrate, an m-plane substrate, or an r-plane substrate.

[0062] Schematic, in some possible implementations, step 11 above may include: providing a 0° beveled c-plane high-resistivity GaN substrate 100 to ensure that the device has higher RF performance.

[0063] Step 12, Reference Figure 5 As shown in (b), a barrier functional layer 200 is fabricated on a GaN substrate 100.

[0064] Among some possible implementation methods, refer to Figure 3 As shown, step 12 allows for the sequential growth of the insertion layer 203, the barrier layer 201, and the cap layer 202 to form the barrier functional layer 200.

[0065] The aforementioned barrier layer 201, cap layer 202, and insertion layer 203 can be grown using epitaxial methods such as MOCVD (metal-organic chemical vapor deposition), MBE (molecular beam epitaxy), PECVD (plasma enhanced chemical vapor deposition), PLD (pulsed laser deposition), and magnetron sputtering. This application does not impose any restrictions on these methods.

[0066] As illustrated, in some possible implementation methods, combining Figure 3 and Figure 5 As shown in (b), step 12 may include: placing the GaN substrate 100 in the cavity of the MOCVD equipment, and controlling the growth temperature in the cavity to be 900℃~1100℃, the growth pressure to be 50mbar~1000mbar, and using trimethylgallium (TMGa), trimethylaluminum (TMAl), and ammonia (NH3) as the gas source. When the cavity temperature and pressure reach the target values, trimethylaluminum and ammonia are introduced into the cavity to grow an AlN layer with a thickness of 0.1nm~1nm as an insertion layer 203. Then, while maintaining the supply of TMAl and NH3, the TMGa valve is opened to grow an AlGaN layer as a barrier layer 201. After reaching the target thickness, the supply of TMAl is stopped, while maintaining the supply of TMGa and NH3, to grow a GaN layer of a certain thickness as a cap layer 202.

[0067] Step 13, Reference Figure 5 As shown in (c), the source S, drain D, and gate G are fabricated on the barrier functional layer 200.

[0068] Illustratively, in some possible implementations, step 13 above may include: referencing Figure 5 As shown in (c), a source S and a drain D are first fabricated on the barrier functional layer 200 using photolithography, and then a gate G is fabricated on the barrier functional layer 200 between the source S and the drain D. In this case, the gate G and the barrier functional layer 200 form a Schottky junction.

[0069] Of course, depending on the actual requirements of the device, in some possible implementations, the dielectric layer can be fabricated before fabricating the gate G in step 13. In this case, the gate G, the dielectric layer, and the barrier functional layer 200 form a MIS gate structure.

[0070] Using this fabrication method, a barrier functional layer 200 is directly fabricated on the surface of the GaN substrate 100, resulting in a small distance between the gate G and the GaN substrate 100. This distance mainly depends on the thickness of the barrier functional layer 200. In this way, when the gate is in a reverse bias state (the gate is subjected to a negative voltage and the drain is subjected to a higher positive voltage), the depletion region can cover the 2DEG channel and the substrate interface, thereby depleting the parasitic channel, reducing off-state leakage current, avoiding RF loss, and improving RF performance.

[0071] In addition, such as Figure 6 As shown in the embodiments of this application, another method for fabricating a GaN HEMT is also provided, which may include:

[0072] Step 21, Reference Figure 7 As shown in (a), a GaN substrate 100 is provided.

[0073] Step 21 is basically the same as step 11 above. For details, please refer to the relevant explanation of step 11 above.

[0074] Step 22, Reference Figure 7 As shown in (b), a GaN layer with a thickness of less than 50 nm is fabricated on a GaN substrate 100 as a channel layer 300, and a barrier functional layer 200 is fabricated on the channel layer 300.

[0075] As illustrated, among some possible implementation methods, see reference. Figure 7 As shown in (b), a GaN layer with a thickness of less than 50 nm is first epitaxially grown on the GaN substrate 100 as a channel layer 300. Then, an insertion layer 203, a barrier layer 201, and a cap layer 202 are sequentially grown on the channel layer 300 (see reference). Figure 3The fabrication of the insertion layer 203, barrier layer 201, and cap layer 202 can be referred to the relevant description in step 22 above.

[0076] The aforementioned channel layer 300 can be grown using epitaxial methods such as MOCVD, MBE, PECVD, PLD, and magnetron sputtering, and this application does not impose any restrictions on this.

[0077] Step 23: Fabricate the source (S), drain (D), and gate (G) on the barrier functional layer 200.

[0078] Step 23 is basically the same as step 13 above. For details, please refer to the relevant explanation of step 13 above.

[0079] Using this fabrication method, the homoepitaxial GaN (channel layer) on the GaN substrate 100 exhibits excellent crystal quality and lower defect density, resulting in higher channel electron mobility, greater device output current density, and improved device performance. Furthermore, due to the thinness of the channel layer 300, when the gate G is reverse-biased (negative voltage applied to the gate, high positive voltage applied to the drain), the depletion region can cover the 2DEG channel and substrate interface, thereby depleting parasitic channels. This reduces off-state leakage current, avoids RF losses, and improves RF performance.

[0080] After the source S, drain D, and gate G are fabricated through steps 13 and 23, other subsequent fabrication processes, such as field plates and passivation layers, can be carried out as needed. This application does not impose any restrictions on these processes.

[0081] It should be understood that the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0082] For other related content in the above manufacturing method, please refer to the corresponding parts in the aforementioned structural embodiments, which will not be repeated here; for other settings in the aforementioned structural embodiments, please refer to the above manufacturing method and related manufacturing methods for adjustment, which will not be repeated here.

[0083] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A high electron mobility transistor (HEMT), characterized in that, Comprising: a gallium nitride (GaN) substrate, a barrier functional layer, a source electrode, a drain electrode, and a gate electrode; the barrier functional layer is disposed on the GaN substrate, and the source electrode, the drain electrode, and the gate electrode are disposed on a side of the barrier functional layer distal to the GaN substrate; a distance between the barrier functional layer and the GaN substrate is less than or equal to 50 nm.

2. The high electron mobility transistor (HEMT) of claim 1, wherein: the barrier functional layer is in contact with the GaN substrate.

3. The high electron mobility transistor (HEMT) of claim 1, wherein, the HEMT further comprises a channel layer between the barrier functional layer and the GaN substrate; the channel layer comprises GaN, and a thickness of the channel layer is less than or equal to 50 nm.

4. The HEMT of any one of claims 1-3, wherein: the barrier functional layer comprises a barrier layer, and the barrier layer comprises at least one of aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum scandium nitride (AlScN), or aluminum nitride (AlN).

5. The HEMT of claim 4, wherein: the barrier functional layer further comprises a cap layer disposed on a side of the barrier layer distal to the GaN substrate, and the cap layer comprises GaN.

6. The HEMT of claim 4 or 5, wherein: the barrier functional layer further comprises an interposed layer disposed on a side of the barrier layer proximal to the GaN substrate, and the interposed layer comprises AlN.

7. The HEMT of any one of claims 1-6, wherein: a thickness of the barrier functional layer is in a range of 1 nm to 50 nm.

8. The HEMT of any one of claims 1-7, wherein: a distance between the gate electrode and the GaN substrate is in a range of 1 nm to 200 nm.

9. A method of fabricating a high electron mobility transistor (HEMT), comprising: Comprising: providing a GaN substrate; fabricating GaN as a channel layer on the GaN substrate, wherein a thickness of the channel layer is less than or equal to 50 nm, and fabricating a barrier functional layer on the channel layer; or fabricating a barrier functional layer on the GaN substrate; fabricating a source electrode, a drain electrode, and a gate electrode on the barrier functional layer.

10. An electronic device, comprising: comprising a circuit board and the HEMT of any one of claims 1-8, wherein the circuit board is electrically connected to the HEMT.

Images