Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate structure; the channel layer is arranged on one side of the substrate structure; the barrier layer is arranged on one side, far away from the substrate structure, of the channel layer; the strain layer is arranged on one side, far away from the channel layer, of the barrier layer; the strain layer is provided with a source trench, a drain trench and a gate trench; the source trench, the drain trench and the gate trench penetrate through the strain layer in the direction from the strain layer to the substrate structure, and the gate trench penetrates through the strain layer and then extends into the barrier layer; the barrier protection layer is arranged on the side wall of the gate trench, and the barrier protection layer at least covers the barrier layer located on the side wall of the gate trench; a source electrode, a drain electrode and a grid electrode structure; the source electrode is arranged in the source electrode groove, the drain electrode is arranged in the drain electrode groove, and the gate structure is arranged in the gate electrode groove. The performance of the semiconductor device can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] Enhanced high electron mobility transistors (HEMTs) have important applications in the field of modern electronics. The performance of gallium nitride semiconductor devices in the related art needs to be improved. SUMMARY

[0003] The present application provides a semiconductor device and a preparation method thereof to improve the performance of the device.

[0004] According to an aspect of the present application, a semiconductor device is provided, comprising:

[0005] a substrate structure;

[0006] a channel layer, disposed on one side of the substrate structure;

[0007] a barrier layer, disposed on a side of the channel layer away from the substrate structure;

[0008] a strain layer, disposed on a side of the barrier layer away from the channel layer; the strain layer is provided with a source trench, a drain trench and a gate trench; the source trench, the drain trench and the gate trench penetrate the strain layer in a direction of the substrate structure, and the gate trench extends into the barrier layer after penetrating the strain layer;

[0009] a barrier protection layer, disposed on the sidewall of the gate trench, and the barrier protection layer covers at least the barrier layer located on the sidewall of the gate trench;

[0010] a source, a drain and a gate structure; the source is disposed in the source trench, the drain is disposed in the drain trench, and the gate structure is disposed in the gate trench.

[0011] Optionally, the material of the barrier protection layer comprises silicon oxide.

[0012] Optionally, the thickness of the barrier protection layer is greater than or equal to 0.2 nm and less than or equal to 10 nm.

[0013] Optionally, the barrier protection layer extends from the edge of the sidewall of the gate trench adjacent to the bottom of the gate trench to a preset position of the sidewall of the gate trench; wherein the distance between the preset position and the bottom of the gate trench is greater than the thickness of the barrier layer located on the sidewall of the gate trench.

[0014] Optionally, the gate trench comprises a first sub-trench and a second sub-trench which are in communication with each other, and the first sub-trench is arranged on a side of the second sub-trench away from the substrate structure.

[0015] The minimum size of the first sub-trench along a preset direction is greater than the maximum size of the second sub-trench along the preset direction, and the depth of the second sub-trench is greater than the thickness of the barrier layer on the sidewall of the gate trench; wherein the preset direction is a direction parallel to the surface of the substrate structure on which the channel layer is arranged.

[0016] The barrier protection layer covers the sidewall of the second sub-trench.

[0017] Optionally, along a direction of the substrate structure pointing to the strain layer, the first size of the gate trench along a preset direction gradually increases or the first size of the gate trench along a preset direction remains unchanged; wherein the preset direction is a direction parallel to the surface of the substrate structure on which the channel layer is arranged.

[0018] Optionally, the gate structure comprises a first insulating layer and a gate electrode, the barrier protection layer is arranged between the sidewall of the gate trench and the first insulating layer, the first insulating layer covers the barrier protection layer on the sidewall of the gate trench, the region of the sidewall of the gate trench on which the barrier protection layer is not arranged, and the bottom of the gate trench; the gate electrode is arranged on the surface of the first insulating layer away from the sidewall and the bottom of the gate trench.

[0019] The semiconductor device further comprises a second insulating layer and a third insulating layer; the second insulating layer is arranged on a side of the gate structure away from the substrate structure, and the second insulating layer covers the gate structure; the third insulating layer is arranged on a side of the source electrode away from the substrate structure, and the third insulating layer covers the source electrode and the drain electrode.

[0020] According to another aspect of the present application, a preparation method of a semiconductor device is provided, comprising:

[0021] providing a substrate structure;

[0022] arranging a channel layer on a side of the substrate structure;

[0023] arranging a barrier layer, a strain layer, a barrier protection layer, a source electrode, a drain electrode, and a gate structure on a side of the channel layer away from the substrate structure;

[0024] The barrier layer is arranged on the side of the channel layer away from the substrate structure; the strain layer is arranged on the side of the barrier layer away from the channel layer; the strain layer is provided with a source trench, a drain trench and a gate trench; the source trench, the drain trench and the gate trench penetrate the strain layer in the direction of the substrate structure, and the gate trench extends into the barrier layer after penetrating the strain layer; the barrier protection layer is arranged on the sidewall of the gate trench, and the barrier protection layer covers at least the barrier layer on the sidewall of the gate trench; the source is arranged in the source trench, the drain is arranged in the drain trench, and the gate structure is arranged in the gate trench.

[0025] Optionally, the barrier layer, the strain layer, the barrier protection layer, the source, the drain and the gate structure are arranged on the side of the channel layer away from the substrate structure, comprising:

[0026] A first sub-barrier layer is arranged on the side of the channel layer away from the substrate structure;

[0027] A virtual gate is arranged on the surface of the first sub-barrier layer;

[0028] A barrier protection material layer is formed on the surface of the virtual gate;

[0029] A second sub-barrier layer is arranged on the surface of the first sub-barrier layer; wherein the second sub-barrier layer covers the area of the first sub-barrier layer which is not provided with the virtual gate and the barrier protection material layer, the barrier layer comprises the first sub-barrier layer and the second sub-barrier layer; in the direction of the substrate structure pointing to the channel layer, the height of the virtual gate is greater than or equal to the thickness of the second sub-barrier layer;

[0030] A strain material layer is arranged on the side of the virtual gate away from the substrate structure, and the strain material layer covers the virtual gate, the barrier protection material layer and the second sub-barrier layer;

[0031] A source trench, a drain trench, a source and a drain are arranged on the strain material layer;

[0032] The strain material layer and the barrier protection material layer arranged on the side of the virtual gate away from the substrate structure are removed to form a barrier protection layer and the strain layer with a third sub-trench;

[0033] The virtual gate is removed to form a fourth sub-trench; wherein the gate trench comprises the third sub-trench and the fourth sub-trench, and the sidewall of the fourth sub-trench is provided with the barrier protection layer;

[0034] The gate structure is formed in the gate trench.

[0035] Optionally, a barrier protection material layer is formed on the virtual gate surface, comprising:

[0036] The virtual gate is subjected to an oxidation treatment to form the barrier protection material layer; wherein the material of the virtual gate comprises silicon, and the material of the barrier protection material layer comprises silicon oxide.

[0037] Optionally, the strain material layer and the barrier protection material layer disposed on the side of the virtual gate away from the substrate structure are removed to form a barrier protection layer and the strain layer with a third sub-groove, comprising:

[0038] The strain material layer and the barrier protection material layer disposed on the side of the virtual gate away from the substrate structure are removed by dry etching;

[0039] The virtual gate is removed to form a fourth sub-groove, comprising: the virtual gate is removed by wet etching.

[0040] Optionally, a virtual gate is disposed on the surface of the first sub-barrier layer, comprising:

[0041] A sacrificial layer is disposed on the surface of the first sub-barrier layer away from the channel layer; wherein the sacrificial layer comprises an opening, and the second dimension of the opening along a preset direction gradually increases or remains unchanged along the direction of the substrate structure pointing to the sacrificial layer; the preset direction is a direction parallel to the surface of the substrate structure provided with the channel layer;

[0042] A virtual gate is disposed in the opening, and the virtual gate fills the opening;

[0043] The sacrificial layer is removed.

[0044] Optionally, the minimum dimension of the third sub-groove along a preset direction is greater than the maximum dimension of the fourth sub-groove along the preset direction; wherein the preset direction is a direction parallel to the surface of the substrate structure provided with the channel layer.

[0045] The semiconductor device of the embodiment comprises a substrate structure, a channel layer, a barrier layer, a strain layer, a barrier protection layer, a source electrode, a drain electrode and a gate structure, the strain layer is provided with a source electrode groove, a drain electrode groove and a gate groove; the source electrode groove, the drain electrode groove and the gate groove penetrate the strain layer along the direction of the substrate structure pointing to the strain layer, and the gate groove extends into the barrier layer after penetrating the strain layer; the barrier protection layer is disposed on the sidewall of the gate groove, and the barrier protection layer covers at least the barrier layer located on the sidewall of the gate groove, so that the barrier protection layer can protect the barrier layer located on the sidewall of the gate groove, avoid damaging the barrier layer in the process of forming the gate groove, reduce the leakage current and improve the device performance.

[0046] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a schematic diagram of a semiconductor device provided in an embodiment of the present invention.

[0049] Figure 2 This is a schematic diagram of the formation of the first sub-barrier layer provided in an embodiment of the present invention.

[0050] Figure 3 This is a process diagram of forming a sacrificial layer provided in an embodiment of the present invention.

[0051] Figure 4 This is a schematic diagram of the formation of a sacrificial layer provided in an embodiment of the present invention.

[0052] Figure 5 This is a schematic diagram of forming a virtual gate provided in an embodiment of the present invention.

[0053] Figure 6 This is a schematic diagram of removing the sacrificial layer provided in an embodiment of the present invention.

[0054] Figure 7 This is a schematic diagram of the formation of a barrier protection material layer provided in an embodiment of the present invention.

[0055] Figure 8 This is a schematic diagram of the formation of the second sub-barrier layer provided in an embodiment of the present invention.

[0056] Figure 9 This is a schematic diagram of the formation of a strain material layer provided in an embodiment of the present invention.

[0057] Figure 10 This is a schematic diagram of the formation of the source and drain provided in an embodiment of the present invention.

[0058] Figure 11 This is a schematic diagram of the formation of the third insulating material layer provided in an embodiment of the present invention.

[0059] Figure 12 This is a schematic diagram of the formation of the third sub-groove provided in an embodiment of the present invention.

[0060] Figure 13 This is a schematic diagram of forming a gate trench according to an embodiment of the present invention.

[0061] Figure 14 This is a schematic diagram of the formation of the second insulating material layer provided in an embodiment of the present invention.

[0062] Figure 15 This is a schematic diagram of another gate trench provided in an embodiment of the present invention.

[0063] Figure 16 This is a schematic diagram of a gate trench in related technologies.

[0064] Figure 17 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0065] Figure 18 It is a flowchart of the semiconductor device fabrication process in related technologies.

[0066] Figure 19 This is a schematic diagram of the second sub-barrier layer formed in related technologies. Detailed Implementation

[0067] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0068] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0069] This invention provides a semiconductor device. Figure 1 This is a schematic diagram of a semiconductor device provided in an embodiment of the present invention, with reference to... Figure 1 Semiconductor devices include:

[0070] Substrate structure 10;

[0071] The channel layer 20 is disposed on one side of the substrate structure 10;

[0072] Barrier layer 30 is disposed on the side of channel layer 20 away from substrate structure 10;

[0073] A strain layer 40 is disposed on the side of the barrier layer 30 away from the channel layer 20. The strain layer 40 is provided with a source trench 41, a drain trench 42 and a gate trench 43. The source trench 41, the drain trench 42 and the gate trench 43 penetrate the strain layer 40 in the direction pointing from the strain layer 40 to the substrate structure 10, and the gate trench 43 extends into the barrier layer 30 after penetrating the strain layer 40.

[0074] A barrier protection layer 90 is disposed on the sidewall of the gate trench 43, and the barrier protection layer 90 at least covers the barrier layer 30 located on the sidewall of the gate trench 43.

[0075] The source 50, drain 60, and gate structure 70 are provided; the source 50 is disposed in the source trench 41, the drain 60 is disposed in the drain trench 42, and the gate structure 70 is disposed in the gate trench 43.

[0076] The substrate structure 10 may include a substrate and a buffer layer. The substrate may be a Si substrate, a sapphire substrate, or a GaN substrate. The buffer layer alleviates the lattice mismatch problem between the substrate and the channel layer 20. The buffer layer material may include aluminum nitride, aluminum gallium nitride, a multilayer superlattice structure with alternating aluminum nitride / gallium nitride growth, a multilayer superlattice structure with alternating aluminum gallium nitride / gallium nitride growth, or carbon-doped gallium nitride. The channel layer 20 may be one or more of GaN, AlGa, and InGaN. The channel layer 20 and the barrier layer 30 form a heterojunction, and a two-dimensional electron gas is formed at the interface between the channel layer 20 and the barrier layer 30, thereby generating a conductive channel using the two-dimensional electron gas. The barrier layer 30 may include an AlGaN layer. The strain layer 40 is used to adjust the stress within the device, adjust the piezoelectric polarization effect between the channel layer 20 and the barrier layer 30, thereby adjusting the two-dimensional electron gas concentration of the device to achieve a higher two-dimensional electron gas concentration. The strain layer 40 may be made of materials such as AlN. The gate structure 70 may include a first insulating layer 71 and a gate 72. The gate 72, source 50, and drain 60 may be made of a metallic material or other conductive material. When a suitable bias voltage is applied between the gate 72 and the source 50 of the semiconductor device, a conductive channel is formed, thereby turning on the semiconductor device.

[0077] The barrier protection layer 90 is used to protect the barrier layer 30 located on the sidewall of the gate trench 43, so as to avoid damage to the barrier protection layer 90 during the formation of the gate trench 43. Figures 2-14The process of forming the semiconductor device of this embodiment is illustrated, with reference to... Figures 1-13 The fabrication process of semiconductor devices may include: (reference) Figure 2 First, a channel layer 20 is formed on the surface of the substrate structure 10, and then a first sub-barrier layer 31 is formed on the surface of the channel layer 20. (Reference) Figures 3-6 A virtual gate 110 is formed on the surface of the first sub-barrier layer 31. (Reference) Figures 7-8 A barrier protection material layer 91 is formed on the surface of the virtual gate 110, and a second sub-barrier layer 32 is formed on the surface of the first sub-barrier layer 31. (Reference) Figures 9-10 A strain material layer 401 is formed, covering the barrier protection material layer 91 and the second sub-barrier layer 32. The strain material layer 401 is etched to form a source trench 41 and a drain trench 42. A source electrode 50 and a drain electrode 60 are formed within the source trench 41 and drain trench 42, respectively. (Reference) Figures 11-14 Then, the strain material layer 401 and the barrier protection material layer 91 located on the side of the dummy gate 110 away from the substrate structure 10 are etched to expose the dummy gate 110. The dummy gate 110 is then etched away to form a gate trench 43. The barrier protection material layer 91 remaining after removing the dummy gate 110 is the barrier protection layer 90. The barrier protection layer 90 is located on the sidewall of the gate trench 43. During the etching process of removing the dummy gate 110, the barrier protection layer 90 protects the second sub-barrier layer 32 on the sidewall of the gate trench 43, preventing damage to the second sub-barrier layer 32 during the etching of the dummy gate 110. Furthermore, the barrier protection layer 90 also protects the second sub-barrier layer 32 during its formation, preventing material from the dummy gate 110, such as silicon, from diffusing into the second sub-barrier layer 32, thus improving the quality of the formed second sub-barrier layer 32.

[0078] For example, the barrier layer 90 can be made of silicon oxide or other materials. The barrier layer 90 at least covers the barrier layer 30 located on the sidewall of the gate trench 43, that is, the barrier layer 90 at least covers the second sub-barrier layer 32 at the sidewall of the gate trench 43. The coverage area of ​​the barrier layer 90 on the sidewall of the gate trench 43 can be greater than the area of ​​the second sub-barrier layer 32 on the sidewall of the gate trench 43.

[0079] The semiconductor device of this invention includes a substrate structure 10, a channel layer 20, a barrier layer 30, a strain layer 40, a barrier protection layer 90, a source 50, a drain 60, and a gate structure 70. The strain layer 40 is provided with a source trench 41, a drain trench 42, and a gate trench 43. The source trench 41, drain trench 42, and gate trench 43 penetrate the strain layer 40 in the direction pointing from the strain layer 40 to the substrate structure 10, and the gate trench 43 extends into the barrier layer 30 after penetrating the strain layer 40. The barrier protection layer 90 is disposed on the sidewall of the gate trench 43, and the barrier protection layer 90 at least covers the barrier layer 30 located on the sidewall of the gate trench 43. The barrier protection layer 90 can protect the barrier layer 30 located on the sidewall of the gate trench 43, avoid damage to the barrier layer 30 during the formation of the gate trench 43, reduce leakage current, and improve device performance.

[0080] Based on the above embodiments, optionally, the material of the barrier protection layer 90 includes silicon oxide.

[0081] Specifically, silicon oxide has stable properties and can better prevent material diffusion in the dummy gate 110 to form the barrier layer 30, thus better avoiding damage to the barrier layer 30 during the etching process of the dummy gate 110. For example, the dummy gate 110 used to form the gate trench 43 can be made of silicon. A barrier protection layer 90 can be formed by oxidizing the silicon material. Using silicon oxide for the barrier protection layer 90 simplifies its formation process, and the formed barrier protection layer 90 can effectively block silicon from the dummy gate 110, preventing silicon from entering the barrier layer 30 and improving the quality of the barrier layer 30. Furthermore, the silicon oxide barrier protection layer 90 can better prevent damage to the barrier layer 30 during the etching process of the dummy gate 110.

[0082] Based on the above embodiments, optionally, the thickness of the barrier protection layer 90 is greater than or equal to 0.2 nm and less than or equal to 10 nm.

[0083] Specifically, the thickness of the barrier protection layer 90 at a certain location is defined by the direction perpendicular to the sidewall of the gate trench 43 covered by the barrier protection layer 90 at that location, and the size of the barrier protection layer 90 at that location. If the thickness of the barrier protection layer 90 is too thin, its protective effect on the barrier layer 30 is weak; if the thickness of the barrier protection layer 90 is too thick, it affects the space within the gate trench 43, potentially impacting the arrangement of the gate structure 70. By setting the thickness of the barrier protection layer 90 to be greater than or equal to 0.2 nm and less than or equal to 10 nm, it is ensured that the barrier protection layer 90 can effectively protect the barrier layer 30 while avoiding excessive space occupation by the barrier protection layer 90, which would affect the subsequent arrangement of the gate structure 70.

[0084] Based on the above embodiments, optionally, refer to Figure 1The barrier layer 90 extends from the edge of the sidewall of the gate trench 43 near the bottom of the gate trench 43 to a preset position on the sidewall of the gate trench 43; wherein the distance H1 between the preset position and the bottom of the gate trench 43 is greater than the thickness H2 of the barrier layer 30 located on the sidewall of the gate trench 43.

[0085] That is, the barrier protection layer 90 covers the barrier layer 30 located on the sidewall of the gate trench 43 and the part of the sidewall of the gate trench 43 located on the side of the barrier layer 30 away from the substrate structure 10. This arrangement allows the barrier protection layer 90 to better protect the barrier layer 30 during the formation of the gate trench 43.

[0086] Based on the above embodiments, optionally, refer to Figure 1 and Figure 13 The gate trench 43 includes a first sub-trench 431 and a second sub-trench 432 that are interconnected, with the first sub-trench 431 disposed on the side of the second sub-trench 432 away from the substrate structure 10.

[0087] The minimum dimension D1 of the first sub-groove 431 along the preset direction is greater than the maximum dimension D2 of the second sub-groove 432 along the preset direction, and the depth of the second sub-groove 432 is greater than the thickness H2 of the barrier layer 30 located on the sidewall of the gate trench 43; wherein, the preset direction is the direction parallel to the surface of the substrate structure 10 on which the channel layer 20 is provided.

[0088] The barrier protection layer 90 covers the sidewall of the second sub-slot 432.

[0089] Specifically, the minimum dimension D1 of the first sub-slot 431 along the preset direction is greater than the maximum dimension D2 of the second sub-slot 432 along the preset direction. The opening of the first sub-slot 431 is larger. When the gate structure 70 is formed in the first sub-slot 431 and the second sub-slot 432, the material is easier to deposit, which can make the gate structure 70 at the corner of the gate trench 43 more fully filled and improve the device performance.

[0090] In addition, the minimum dimension D1 of the first sub-slot 431 along the preset direction is greater than the maximum dimension D2 of the second sub-slot 432 along the preset direction. The opening of the first sub-slot 431 is larger, making the virtual gate etching process easier to control and further avoiding damage to the barrier layer 30.

[0091] Figure 15 This is a schematic diagram of another gate trench provided in an embodiment of the present invention. Optionally, based on the above embodiments, refer to... Figure 13 and Figure 15 Along the direction X from the substrate structure 10 to the strain layer 40, the first dimension D of the gate trench 43 along the preset direction gradually increases or remains unchanged; wherein, the preset direction is the direction parallel to the surface of the substrate structure 10 on which the channel layer 20 is provided.

[0092] For details, please refer to Figure 15 Along the direction X from the substrate structure 10 to the strain layer 40, the first dimension D of the gate trench 43 along the preset direction remains unchanged. The longitudinal section of the gate trench 43 can be rectangular, which is the section perpendicular to the surface of the substrate structure 10 where the channel layer 20 is provided. The rectangular gate trench 43 has a simpler fabrication process and can reduce the process cost.

[0093] refer to Figure 1 and Figure 13 Along the direction X from the substrate structure 10 to the strain layer 40, the gate trench 43 gradually increases in a first dimension D along a predetermined direction. The first dimension D can increase linearly or non-linearly, for example, it can increase in a gradient or in the form of a set curve. For example, the longitudinal section of the gate trench 43 can be an inverted trapezoid, with the base of the inverted trapezoid away from the substrate structure 10 being larger than the base of the side adjacent to the substrate structure 10. Furthermore, when the gate trench 43 includes a first sub-trench 431 and a second sub-trench 432, the longitudinal sections of both the first sub-trench 431 and the second sub-trench 432 can be inverted trapezoids.

[0094] Figure 16 This is a schematic diagram of a gate trench in related technologies, for reference. Figure 16 In related technologies, after forming the gate trench 43, a portion of the barrier layer at the corner of the gate trench 43 shrinks inward, forming a shrinkage dead angle 4301. This results in the gate structure being unable to fill the shrinkage dead angle 4301 after formation, affecting device performance. By setting a direction X along the substrate structure 10 to the strain layer 40, the first dimension D of the gate trench 43 gradually increases along a preset direction, eliminating the shrinkage dead angle at the corner of the gate trench 43. This makes it easier for the material to be deposited on the sidewall of the gate trench 43 when the gate structure 70 is set in the gate trench 43, thereby ensuring more complete filling at the corner of the gate trench 43 and improving device performance.

[0095] Based on the above embodiments, optionally, refer to Figure 1 The gate structure 70 includes a first insulating layer 71 and a gate 72. A barrier protection layer 90 is disposed between the sidewall of the gate trench and the first insulating layer 71. The first insulating layer 71 covers the barrier protection layer 90 located on the sidewall of the gate trench 43, the area of ​​the sidewall of the gate trench 43 where the barrier protection layer 90 is not disposed, and the bottom of the gate trench 43. The gate 72 is disposed on the surface of the first insulating layer 71 away from the sidewall and bottom of the gate trench 43.

[0096] The semiconductor device further includes a second insulating layer 82 and a third insulating layer 81; the second insulating layer 82 is disposed on the side of the gate structure 70 away from the substrate structure 10, and the second insulating layer 82 covers the gate structure 70; the third insulating layer 81 is disposed on the side of the source 50 away from the substrate structure 10, and the third insulating layer 81 covers the source 50 and the drain 60.

[0097] Specifically, the first insulating layer 71 is a gate insulating layer, and the first insulating layer 71 can be made of materials such as Al2O3. The gate 72 can be made of materials such as TiN. The second insulating layer 82 and the third insulating layer 81 serve an insulating function and can be made of materials such as silicon dioxide.

[0098] This invention also provides a method for fabricating a semiconductor device. Figure 17 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention, see reference. Figure 17 The methods for fabricating semiconductor devices include:

[0099] S110 provides a substrate structure.

[0100] S120. A trench layer is formed on one side of the substrate structure.

[0101] S130. A barrier layer, a strain layer, a barrier protection layer, a source, a drain, and a gate structure are disposed on the side of the channel layer away from the substrate structure.

[0102] The barrier layer is disposed on the side of the channel layer away from the substrate structure; the strain layer is disposed on the side of the barrier layer away from the channel layer; the strain layer has a source trench, a drain trench and a gate trench; the source trench, drain trench and gate trench penetrate the strain layer in the direction of the strain layer towards the substrate structure, and the gate trench extends into the barrier layer after penetrating the strain layer; the barrier protection layer is disposed on the sidewall of the gate trench, and the barrier protection layer at least covers the barrier layer located on the sidewall of the gate trench; the source is disposed in the source trench, the drain is disposed in the drain trench and the gate structure is disposed in the gate trench.

[0103] The semiconductor device formed by the fabrication method of this invention includes a substrate structure, a channel layer, a barrier layer, a strain layer, a barrier protection layer, a source electrode, a drain electrode, and a gate structure. The strain layer is provided with a source trench, a drain trench, and a gate trench. The source trench, drain trench, and gate trench penetrate the strain layer in the direction from the strain layer to the substrate structure, and the gate trench extends into the barrier layer after penetrating the strain layer. The barrier protection layer is disposed on the sidewall of the gate trench, and the barrier protection layer at least covers the barrier layer located on the sidewall of the gate trench. The barrier protection layer can protect the barrier layer located on the sidewall of the gate trench, avoid damage to the barrier layer during the formation of the gate trench, reduce leakage current, and improve device performance.

[0104] Based on the above embodiments, optionally, refer to Figures 1-14 A barrier layer 30, a strain layer 40, a barrier protection layer 90, a source 50, a drain 60, and a gate structure 70 are disposed on the side of the channel layer 20 away from the substrate structure 10, including:

[0105] A first sub-barrier layer 31 is disposed on the side of the channel layer 20 away from the substrate structure 10;

[0106] A virtual gate 110 is disposed on the surface of the first sub-barrier layer 31;

[0107] A barrier protection material layer 91 is formed on the surface of the virtual gate 110;

[0108] A second sub-barrier layer 32 is disposed on the surface of the first sub-barrier layer 31; wherein, the second sub-barrier layer 32 covers the area of ​​the first sub-barrier layer 31 where the dummy gate 110 and the barrier protection material layer 91 are not disposed, and the barrier layer 30 includes the first sub-barrier layer 31 and the second sub-barrier layer 32; along the direction from the substrate structure 10 to the channel layer 20, the height of the dummy gate 110 is greater than or equal to the thickness of the second sub-barrier layer 32;

[0109] A strain material layer 401 is disposed on the side of the virtual gate 110 away from the substrate structure 10. The strain material layer 401 covers the virtual gate 110, the barrier protection material layer 91, and the second sub-barrier layer 32.

[0110] A source trench 41, a drain trench 42, a source 50, and a drain 60 are provided in the strain material layer 401;

[0111] Remove the strain material layer 401 and the barrier protection material layer 91 disposed on the side of the virtual gate 110 away from the substrate structure 10 to form a barrier protection layer 90 and a strain layer 40 with a third sub-groove 433.

[0112] Remove the virtual gate 110 to form a fourth sub-groove 434; wherein, the gate trench 43 includes a third sub-groove 433 and a fourth sub-groove 434, and a barrier protection layer 90 is provided on the sidewall of the fourth sub-groove 434.

[0113] A gate structure 70 is formed within the gate trench 43.

[0114] For details, please refer to Figure 2 First, a channel layer 20 and a first sub-barrier layer 31 are formed on the surface of the substrate structure 10. The first sub-barrier layer 31 is made of AlGaN material. (Reference) Figure 3 and Figure 4 A sacrificial layer 100 with an opening 101 is formed on the surface of the first sub-barrier layer 31. The size and shape of the virtual gate 110 can be adjusted by adjusting the size and shape of the opening 101, thereby adjusting the size and shape of the finally formed gate trench 43.

[0115] refer to Figure 5 and Figure 6 The opening 101 is filled with silicon material, and the sacrificial layer 100 is removed to form the desired shape. Figure 6 The virtual gate 110 is shown. (Reference) Figure 7 A barrier protection material layer 91 is formed on the surface of the virtual gate 110. (Reference) Figure 8 A second sub-barrier layer 32 is formed on the surface of the first sub-barrier layer 31, and the second sub-barrier layer 32 is made of the same material as the first sub-barrier layer 31.

[0116] refer to Figure 9 A strain material layer 401 is formed on the surface of the second sub-barrier layer 32 and the barrier protection material layer 91, covering the second sub-barrier layer 32 and the barrier protection material layer 91. (Reference) Figure 10 A source trench 41 and a drain trench 42 are formed in the strained material layer 401 by an etching process. The source trench 41 and the drain trench 42 penetrate the strained material layer 401. A source 50 is formed in the source trench 41, and a drain 60 is formed in the drain trench 42. The source trench 41 and the drain trench 42 may penetrate only the strained material layer 401, or they may penetrate the strained material layer 401 and extend into or through the barrier layer 30.

[0117] refer to Figure 11 A third insulating material layer 810 is formed on the surface of the source electrode 50 and the drain electrode 60, and the third insulating material layer 810 covers the source electrode 50, the drain electrode 60 and the strain material layer 401.

[0118] refer to Figures 11-13 The third insulating material layer 810 and strain material layer 401 covering the surface of the dummy gate 110 can be etched using a dry etching process to form a strain layer 40 with a third sub-groove 433. The third sub-groove 433 exposes the dummy gate 110, and the dummy gate 110 can be removed by wet etching. Since there is a barrier protection layer 90 between the dummy gate 110, the strain layer 40, and the second sub-barrier layer 32, the barrier protection layer 90 can protect the second sub-barrier layer 32 during the etching of the dummy gate 110, preventing the etching solution from damaging the second sub-barrier layer 32.

[0119] refer to Figure 1 and Figure 14 A first insulating material layer 710, a gate material layer 720, and a second insulating material layer 820 are formed in the gate trench 43. The first insulating material layer 710, the gate material layer 720, and the second insulating material layer 820 are etched to form a first insulating layer 71, a gate 72, and a second insulating layer 82.

[0120] Based on the above embodiments, optionally, refer toFigure 7 A barrier protection material layer 91 is formed on the surface of the virtual gate 110, comprising:

[0121] The virtual gate 110 is oxidized to form a barrier protection material layer 91; wherein the material of the virtual gate 110 includes silicon, and the material of the barrier protection material layer 91 includes silicon oxide.

[0122] Specifically, using silicon as the virtual gate 110 further ensures that the etchant will not damage the barrier layer 30 during wet etching of the virtual gate 110. Furthermore, it allows for the formation of the barrier protection material layer 91 simply by oxidizing the virtual gate 110, reducing process costs.

[0123] Based on the above embodiments, optionally, refer to Figures 11-13 Removing the strain material layer 401 and the barrier protection material layer 91 disposed on the side of the virtual gate 110 away from the substrate structure 10 to form a barrier protection layer 90 and a strain layer having a third sub-groove 433 includes:

[0124] The strain material layer 401 and the barrier protection material layer 91 disposed on the side of the virtual gate 110 away from the substrate structure 10 are removed by dry etching.

[0125] Removing the dummy gate 110 to form the fourth sub-slot 434 includes: removing the dummy gate 110 by wet etching.

[0126] Specifically, the strain material layer 401 may be made of aluminum nitride, which can be etched by dry etching to form a third sub-groove 433. The third sub-groove 433 completely exposes the virtual gate 110. The bottom dimension of the third sub-groove 433 along a preset direction can be greater than the maximum value of the dimension S of the virtual gate 110 along the preset direction. This results in a larger process window when etching the virtual gate 110, making the process easier to control and further avoiding damage to the barrier layer 30.

[0127] Figure 18 This is a flowchart of semiconductor device fabrication in related technologies, for reference. Figure 18 In related technologies, the strain material layer 401 and the trapezoidal virtual gate 02 are first etched using dry etching, and then the trapezoidal virtual gate 02 that was not removed by dry etching is etched using wet etching. In related technologies, in order to avoid the formation of recessed grooves at the corners of the gate trench 43, the remaining thickness of the trapezoidal virtual gate 02 after dry etching is generally small, around 200 Å. The second sub-barrier layer 32 is easily damaged during dry etching.

[0128] refer to Figures 11-13In this embodiment, the strain material layer 401 on the surface of the virtual gate 110 is removed by dry etching, and the virtual gate 110 is removed by wet etching, which can avoid damage to the second sub-barrier layer 32 by dry etching.

[0129] Based on the above embodiments, optionally, Figures 3-6 A virtual gate 110 is disposed on the surface of the first sub-barrier layer 31, including:

[0130] A sacrificial layer 100 is disposed on the surface of the first sub-barrier layer 31 away from the channel layer 20; wherein, the sacrificial layer 100 includes an opening 101, which is in the direction of the substrate structure 10 pointing to the sacrificial layer 100, and the second dimension W of the opening 101 gradually increases or remains unchanged along a preset direction; the preset direction is a direction parallel to the surface of the substrate structure 10 where the channel layer 20 is disposed.

[0131] A virtual gate 110 is provided within the opening 101, and the virtual gate 110 fills the opening;

[0132] Remove sacrificial layer 100.

[0133] Specifically, a virtual gate 110 is formed by setting an opening 101 in the form of a sacrificial layer 100. The virtual gate 110 of the required size and shape can be formed by adjusting the size and shape of the opening 101.

[0134] Continue to refer to Figure 18 In related technologies, after forming the substrate structure 10, the channel layer 20 and the first sub-barrier layer 31, an oxide layer 01 is formed on the surface of the first sub-barrier layer 31. The oxide layer 01 is etched to form a positive trapezoidal virtual gate 02. The width of the positive trapezoidal virtual gate 02 on the side adjacent to the substrate structure 10 is greater than the width on the side away from the substrate structure 10. Figure 19 This is a schematic diagram of the second sub-barrier layer formed in related technologies, for reference. Figure 18 and 19 Because the trapezoidal virtual gate 02 is wider at the bottom and narrower at the top, the second sub-barrier layer 32 does not grow sufficiently at the angle formed by the trapezoidal virtual gate 02 and the first sub-barrier layer 31. Figure 19 In the area circled in red, the second sub-barrier layer 32 has a large gap between its side adjacent to the positive trapezoidal virtual gate 02 and the positive trapezoidal virtual gate 02. This results in a low concentration of two-dimensional electron gas in the region near the gate of the final semiconductor device, affecting the device resistance.

[0135] Furthermore, due to the narrower shape of the trapezoidal virtual gate 02 at the top and wider at the bottom, the etching process window for etching the strain material layer 401 and the trapezoidal virtual gate 02 is difficult to control. If the etching process window is too small, it is easy to form... Figure 16In the structure shown, the opening of the gate trench 43 is too small. After etching the trapezoidal virtual gate 02 near the second sub-barrier layer 32, a recessed dead angle 4301 is formed, shrinking inwards towards both sides of the gate trench 43. This makes it difficult for the material to fill during the subsequent formation of the gate structure 70. (Reference) Figure 18 In the last figure, if the etching process window is too large, it can easily lead to an excessively large opening in the gate trench 43, resulting in damage to the second sub-barrier layer 32.

[0136] In this embodiment, by setting the second dimension W of the opening 101 along the predetermined direction from the substrate structure 10 to the sacrificial layer 100, the dimension S of the virtual gate 110 along the predetermined direction from the substrate structure 10 to the virtual gate 110 gradually increases or remains constant. After etching the strain material layer 401 to expose the virtual gate 110, since the dimension S of the virtual gate 110 along the predetermined direction from the substrate structure 10 to the virtual gate 110 gradually increases or remains constant, the phenomenon of inward shrinkage of the gate trench 43 will not occur after etching the virtual gate 110. This can avoid insufficient filling of the gate structure at the corner of the gate trench 43, which would affect device performance. Furthermore, by etching the virtual gate 110 and the strain material layer 401 in stages, the situation of excessively large etching openings damaging the second sub-barrier layer 32 will not occur.

[0137] Based on the above embodiments, optionally, refer to Figure 13 The minimum dimension of the third sub-groove 433 along the preset direction is greater than the maximum dimension of the fourth sub-groove 434 along the preset direction; wherein, the preset direction is the direction parallel to the surface of the substrate structure 10 on which the channel layer 20 is provided.

[0138] Specifically, when the minimum dimension of the third sub-slot 433 along the preset direction is greater than the maximum dimension of the fourth sub-slot 434 along the preset direction, the third sub-slot 433 is the first sub-slot 431, and the fourth sub-slot 434 is the second sub-slot 432.

[0139] The minimum dimension D1 of the first sub-groove 431 along the preset direction is greater than the maximum dimension D2 of the second sub-groove 432 along the preset direction. The larger opening of the first sub-groove 431 facilitates material deposition when forming the gate structure 70 in both sub-grooves 431 and 432. This allows for more complete filling of the gate structure 70 at the corners of the gate trench 43, improving device performance. Furthermore, the larger opening of the first sub-groove 431 along the preset direction makes the virtual gate etching process easier to control, further preventing damage to the barrier layer 30.

[0140] Based on the above embodiments, optionally, refer to Figures 3-4 A sacrificial layer 100 is disposed on the surface of the first sub-barrier layer 31 away from the channel layer 20, comprising:

[0141] A barrier material layer 11 is disposed on the surface of the first sub-barrier layer 31 away from the channel layer 20;

[0142] A sacrificial material layer 12 is disposed on the surface of the barrier material layer 11;

[0143] A fifth sub-groove is formed by dry etching the patterned sacrificial material layer 12;

[0144] The barrier material layer 11 is patterned by wet etching to form a sixth sub-groove penetrating the barrier material layer 11; wherein, the opening 101 includes a fifth sub-groove and a sixth sub-groove.

[0145] The sacrificial layer 100 includes a barrier layer 111 and a sub-sacrificial layer 121. The barrier layer 111 is the patterned barrier material layer 11, and the sub-sacrificial layer 121 is the patterned sacrificial material layer 12. The barrier material layer 11 protects the first sub-barrier layer 31 from damage during dry etching of the sacrificial material layer 12. After the sacrificial material layer 12 is patterned to form the sub-sacrificial layer 121, the barrier material layer 11 is etched using a wet etching process without damaging the first sub-barrier layer 31. For example, the barrier material layer 11 can be made of materials such as aluminum nitride.

[0146] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0147] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate structure; a channel layer disposed on one side of the substrate structure; a barrier layer disposed on a side of the channel layer away from the substrate structure; a strain layer disposed on a side of the barrier layer away from the channel layer; the strain layer is provided with a source trench, a drain trench and a gate trench; the source trench, the drain trench and the gate trench penetrate the strain layer in a direction pointing to the substrate structure, and the gate trench extends into the barrier layer after penetrating the strain layer; a barrier protection layer disposed on the sidewall of the gate trench, and the barrier protection layer covers at least the barrier layer on the sidewall of the gate trench; a source, a drain and a gate structure; the source is disposed in the source trench, the drain is disposed in the drain trench, and the gate structure is disposed in the gate trench.

2. The semiconductor device according to claim 1, wherein: the material of the barrier protection layer comprises silicon oxide.

3. The semiconductor device according to claim 2, wherein: the thickness of the barrier protection layer is greater than or equal to 0.2 nm and less than or equal to 10 nm.

4. The semiconductor device according to claim 1, wherein: the barrier protection layer extends from the edge of the sidewall of the gate trench adjacent to the bottom of the gate trench to a preset position of the sidewall of the gate trench; wherein the distance between the preset position and the bottom of the gate trench is greater than the thickness of the barrier layer on the sidewall of the gate trench.

5. The semiconductor device according to claim 1 or 4, wherein: the gate trench comprises a first sub-trench and a second sub-trench in communication with each other, and the first sub-trench is disposed on a side of the second sub-trench away from the substrate structure; the minimum size of the first sub-trench in a preset direction is greater than the maximum size of the second sub-trench in the preset direction, and the depth of the second sub-trench is greater than the thickness of the barrier layer on the sidewall of the gate trench; wherein the preset direction is a direction parallel to the surface of the substrate structure provided with the channel layer; the barrier protection layer covers the sidewall of the second sub-trench.

6. The semiconductor device according to claim 1, wherein: in a direction pointing to the strain layer along the substrate structure, the first size of the gate trench in a preset direction gradually increases or the first size of the gate trench in a preset direction remains unchanged; wherein the preset direction is a direction parallel to the surface of the substrate structure provided with the channel layer.

7. The semiconductor device according to claim 1, wherein: the gate structure comprises a first insulating layer and a gate, the barrier protection layer is disposed between the sidewall of the gate trench and the first insulating layer, the first insulating layer covers the barrier protection layer on the sidewall of the gate trench, the area of the sidewall of the gate trench without barrier protection layer and the bottom of the gate trench, and the gate is disposed on the surface of the first insulating layer away from the sidewall and the bottom of the gate trench. The semiconductor device further comprises a second insulating layer and a third insulating layer; the second insulating layer is arranged on the side of the gate structure away from the substrate structure, and covers the gate structure; the third insulating layer is arranged on the side of the source away from the substrate structure, and covers the source and the drain.

8. A method of manufacturing a semiconductor device, characterized by Comprise: providing a substrate structure; arranging a channel layer on one side of the substrate structure; arranging a barrier layer, a strain layer, a barrier protection layer, a source, a drain and a gate structure on the side of the channel layer away from the substrate structure; wherein the barrier layer is arranged on the side of the channel layer away from the substrate structure; the strain layer is arranged on the side of the barrier layer away from the channel layer; the strain layer is provided with a source trench, a drain trench and a gate trench; the source trench, the drain trench and the gate trench penetrate the strain layer in the direction of the substrate structure, and the gate trench extends into the barrier layer after penetrating the strain layer; the barrier protection layer is arranged on the sidewall of the gate trench, and at least covers the barrier layer on the sidewall of the gate trench; the source is arranged in the source trench, the drain is arranged in the drain trench, and the gate structure is arranged in the gate trench.

9. The method of producing a semiconductor device according to Claim 8, wherein arranging a barrier layer, a strain layer, a barrier protection layer, a source, a drain and a gate structure on the side of the channel layer away from the substrate structure, comprising: arranging a first sub-barrier layer on the side of the channel layer away from the substrate structure; arranging a virtual gate on the surface of the first sub-barrier layer; forming a barrier protection material layer on the surface of the virtual gate; arranging a second sub-barrier layer on the surface of the first sub-barrier layer; wherein the second sub-barrier layer covers the region of the first sub-barrier layer which is not provided with the virtual gate and the barrier protection material layer, the barrier layer comprises the first sub-barrier layer and the second sub-barrier layer; in the direction of the substrate structure to the channel layer, the height of the virtual gate is greater than or equal to the thickness of the second sub-barrier layer; arranging a strain material layer on the side of the virtual gate away from the substrate structure, the strain material layer covering the virtual gate, the barrier protection material layer and the second sub-barrier layer; arranging a source trench, a drain trench, a source and a drain in the strain material layer; removing the strain material layer and the barrier protection material layer arranged on the side of the virtual gate away from the substrate structure, to form a barrier protection layer and the strain layer with a third sub-trench; removing the virtual gate to form a fourth sub-trench; wherein the gate trench comprises the third sub-trench and the fourth sub-trench, and the sidewall of the fourth sub-trench is provided with the barrier protection layer; forming the gate structure in the gate trench.

10. The method of producing a semiconductor device according to Claim 9, wherein forming a barrier protection material layer on the surface of the virtual gate, comprising: oxidizing the virtual gate to form the barrier protection material layer; wherein the material of the virtual gate comprises silicon, and the material of the barrier protection material layer comprises silicon oxide.

11. The method of claim 9, wherein: removing the strain material layer and the barrier protection material layer disposed on a side of the dummy gate away from the substrate structure to form a barrier protection layer and the strain layer with third sub-slots comprises: removing the strain material layer and the barrier protection material layer disposed on a side of the dummy gate away from the substrate structure by dry etching; removing the dummy gate to form fourth sub-slots comprises removing the dummy gate by wet etching.

12. The method of producing a semiconductor device according to Claim 9, wherein disposing a dummy gate on the surface of the first sub-barrier layer comprises: disposing a sacrificial layer on a surface of the first sub-barrier layer away from the channel layer; wherein the sacrificial layer comprises an opening gradually increasing or remaining unchanged in a second dimension along a preset direction pointing from the substrate structure to the sacrificial layer; the preset direction is parallel to a surface of the substrate structure on which the channel layer is disposed; disposing a dummy gate in the opening, the dummy gate filling the opening; removing the sacrificial layer.

13. The method of claim 9, wherein: a minimum dimension of the third sub-slot along a preset direction is greater than a maximum dimension of the fourth sub-slot along the preset direction; wherein the preset direction is parallel to a surface of the substrate structure on which the channel layer is disposed.

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