Semiconductor device
By introducing an insulating film containing a negative fixed charge into the semiconductor device, the problem of difficulty in increasing the gate threshold voltage is solved, and higher gate threshold voltage and lower on-resistance are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-21
- Publication Date
- 2026-03-10
AI Technical Summary
In the prior art, it is difficult to increase the gate threshold voltage of semiconductor devices, which affects device performance.
In a semiconductor device, an insulating film containing a negative fixed charge is introduced. By setting the insulating film on the inner side of the source electrode trench, the energy band of the first semiconductor region is increased by the negative fixed charge, which promotes depletion and thereby increases the gate threshold voltage.
The negative fixed charge in the insulating film significantly increases the gate threshold voltage, enhances the current control capability of the device in the off state, and reduces the on-resistance.
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Figure CN121645939A_ABST
Abstract
Description
[0001] Cross-references to related applications
[0002] This application claims priority to Japanese Patent Application No. 2024-151356 (filed on September 3, 2024). This application incorporates the entire contents of that basic application by reference. Technical Field
[0003] Embodiments of the present invention relate to semiconductor devices. Background Technology
[0004] Semiconductor devices, such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), exist that can achieve a cutoff state by performing Schottky junctions, thereby promoting the depletion of the semiconductor region. However, this construction presents the problem of difficulty in increasing the gate threshold voltage. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to provide a semiconductor device capable of increasing the gate threshold voltage.
[0006] The semiconductor device of the embodiment includes a semiconductor component, a drain electrode, a gate electrode, a source electrode, and an insulating film. A first trench and a second trench are provided in the semiconductor component. The first trench and the second trench extend in a first direction. The first trench and the second trench are arranged in a second direction intersecting the first direction. The first trench and the second trench are recessed to one side in a third direction intersecting both the first and second directions. The drain electrode is located on one side of the semiconductor component in the third direction. The gate electrode is disposed inside the first trench. The source electrode is disposed inside the second trench. An insulating film is provided on at least a portion of the inner surface of the second trench. The insulating film contains a negative fixed charge. A first semiconductor region and a second semiconductor region are provided in the semiconductor component. The first semiconductor region has a first conductivity type impurity. The second semiconductor region has a higher concentration of the first conductivity type impurity than the first semiconductor region. The second semiconductor region is located on the other side in the third direction than the first semiconductor region. The source electrode is capable of Schottky bonding with the first semiconductor region. The source electrode is ohmically bonded to the second semiconductor region. At least a portion of the first semiconductor region is located between the gate electrode and the source electrode in a second direction. An insulating film is sandwiched between said portion of the first semiconductor region and the source electrode in the second direction. Attached Figure Description
[0007] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to one embodiment.
[0008] Figure 2This is a partial schematic diagram of a semiconductor device using the first comparison method.
[0009] Figure 3 This is a partial schematic diagram of a semiconductor device using the second comparison method.
[0010] Figure 4 It is a graph showing the simulation results of the transfer characteristics of the semiconductor device in the implementation method and the first comparison method and the second comparison method. Detailed Implementation
[0011] The semiconductor device according to the embodiments will now be described with reference to the accompanying drawings.
[0012] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device 1 according to one embodiment.
[0013] The X-axis, Y-axis, and Z-axis are shown appropriately in the attached diagram. The X-axis, Y-axis, and Z-axis are orthogonal to each other.
[0014] In this specification, "direction" is defined as a vector that includes the concepts of positive and negative parallel to a specific axis. Therefore, "direction" is a concept encompassing two directions (one side and the other side) that are opposite to each other. In the following embodiments, the direction parallel to the Y-axis corresponds to "the first direction," the direction parallel to the X-axis corresponds to "the second direction intersecting the first direction," and the direction parallel to the Z-axis corresponds to "the third direction intersecting both the first and second directions." Furthermore, in the following embodiments, the side opposite to the direction pointed to by the arrow of the Z-axis in the third direction Z (-Z) is called the lower side, or one side of the third direction, and the side pointed to by the arrow of the Z-axis in the third direction Z (+Z) is called the upper side, or the other side of the third direction. Additionally, in this specification, the concepts of "upper" and "lower" are not necessarily terms indicating a relationship with the direction of gravity.
[0015] like Figure 1 As shown, the semiconductor device 1 according to the embodiment includes a semiconductor component 10, a drain electrode (first electrode) 51, a source electrode (second electrode) 52, a gate electrode (third electrode) 53, a field plate (conductive component) 61, an insulating component 41, and an insulating film 45. In this specification, the thickness direction of the semiconductor device 1 (i.e., the direction from the drain electrode 51 toward the source electrode 52) is the third direction Z.
[0016] The semiconductor device 1 in this embodiment is a trench-type metal-oxide-semiconductor field-effect transistor (MOSFET). Alternatively, the semiconductor device 1 in this embodiment is a Schottky contact type transistor. The semiconductor device 1 can control the depletion of the semiconductor region of the semiconductor component 10 by adjusting the potential of the gate electrode 53. That is, the semiconductor device 1 can control the current flowing between the drain electrode 51 and the source electrode 52 by adjusting the potential of the gate electrode 53.
[0017] Semiconductor component 10 includes, for example, at least one selected from the group consisting of silicon (Si), nitride semiconductors (e.g., GaN), silicon carbide (SiC), and oxide semiconductors (e.g., GaO).
[0018] A plurality of gate electrode trenches (first trenches) 21 and a plurality of source electrode trenches (second trenches) 22 are provided in the semiconductor component 10. The gate electrode trenches 21 and the source electrode trenches 22 are recessed downward from the upper surface 10f of the semiconductor component 10 (towards the third direction Z). The gate electrode trenches 21 and the source electrode trenches 22 extend in the first direction Y and are arranged alternately in the second direction X. Therefore, gate electrode trenches 21 are respectively provided on both sides of the source electrode trenches 22 in the second direction X.
[0019] The inner surface of the gate electrode trench 21 has an upward-facing bottom 21a and a pair of sidewall portions 21b facing each other in the second direction X. Similarly, the inner surface of the source electrode trench 22 has an upward-facing bottom 22a and a pair of sidewall portions 22b facing each other in the second direction X. The gate electrode trench 21 is formed deeper than the source electrode trench 22. That is, the bottom 21a of the gate electrode trench 21 is located lower than the bottom 22a of the source electrode trench 22. In addition, the width dimension of the gate electrode trench 21 is larger than the width dimension of the source electrode trench 22. Furthermore, in the following description, the width dimension refers to the dimension in the second direction X.
[0020] Semiconductor component 10 includes a first semiconductor region 11 and a second semiconductor region 12. Both the first semiconductor region 11 and the second semiconductor region 12 are n-type semiconductors. When semiconductor component 10 includes silicon, impurities of the first conductivity type can be, for example, pentavalent elements such as phosphorus and arsenic. That is, impurities of the first conductivity type are n-type impurities. In the silicon-containing semiconductor component 10, the first semiconductor region 11 and the second semiconductor region 12 are formed by adding pentavalent elements as impurities and allowing them to diffuse. Furthermore, the impurities in the second semiconductor region 12 diffuse at a higher concentration than those in the first semiconductor region 11. The first semiconductor region 11 is, for example, an n- layer. The second semiconductor region 12 is an n- layer or an n+ layer. In this embodiment, no p-type semiconductor is formed in semiconductor component 10. Therefore, the manufacturing process of semiconductor device 1 can be simplified.
[0021] The first semiconductor region 11 has a drift region 11a and a cell region 11c. The drift region 11a is a region in the first semiconductor region 11 that is lower than the lower end of the source electrode 52 (i.e., the lower end of the contact portion 52b described later). The lower end of the drift region 11a is in contact with the upper surface 51f of the drain electrode 51. In addition, the cell region 11c is located higher than the drift region 11a. The cell region 11c is a region sandwiched between the gate electrode trench 21 and the source electrode trench 22.
[0022] Cell region 11c is the region in the first semiconductor region 11 located between the gate electrode trench 21 and the source electrode trench 22. That is, cell region 11c is located between the source electrode 52 and the gate electrode 53 in the second direction X. Cell region 11c is located at the upper end of the first semiconductor region 11. The width dimension W of cell region 11c is, for example, 25 nm or more and 100 nm or less.
[0023] The second semiconductor region 12 is formed from the upper surface 10f of the semiconductor component 10 to a certain depth. The second semiconductor region 12 is positioned higher than the first semiconductor region 11. The second semiconductor region 12 is in contact with the cell region 11c of the first semiconductor region 11. The second semiconductor region 12 is located higher than the bottom 21a of the gate electrode trench 21 and the bottom 22a of the source electrode trench 22. Therefore, the second semiconductor region 12 is disconnected by the gate electrode trench 21 and the source electrode trench 22 in the second direction X. The width dimension of the second semiconductor region 12 is approximately equal to the width dimension W of the cell region 11c.
[0024] Drain electrode 51, source electrode 52, gate electrode 53, and field plate 61 extend along the first direction Y. Gate electrode 53 and source electrode 52 are arranged in the second direction X. Gate electrode 53 and field plate 61 are arranged in the third direction Z.
[0025] The drain electrode 51 is disposed on the lower surface 10e of the semiconductor component 10. The drain electrode 51 may contain, for example, Al, Cu, Mo, W, Ta, Co, Ru, Ti, and Pt.
[0026] At least a portion of the source electrode 52 is disposed inside the source electrode trench 22. The source electrode 52 has an electrode portion 52a, a contact portion (metal portion) 52b, and a metal film 70. The electrode portion 52a is located above the upper surface 10f of the semiconductor component 10. The electrode portion 52a is disposed above the contact portion 52b and the insulating component 41. The contact portion 52b is disposed inside the source electrode trench 22. The electrode portion 52a and the contact portion 52b may contain, for example, Al, Cu, Mo, W, Ta, Co, Ru, Ti, and Pt.
[0027] The metal film 70 is made of a different metal material than that used for the electrode portion 52a and the contact portion 52b. The metal material constituting the metal film 70 has a higher work function than the first semiconductor region 11. Therefore, the metal film 70 can be Schottky bonded to the first semiconductor region 11. In this specification, the portion of the metal film 70 that is Schottky bonded to the first semiconductor region 11 is referred to as the Schottky junction portion 32. In this embodiment, the Schottky junction portion 32 is provided at the bottom 22a of the source electrode trench 22. Furthermore, in this specification, when comparing the work functions of multiple portions, the energy levels of each portion are compared.
[0028] The metal material constituting the metal film 70 has a lower work function compared to the second semiconductor region 12. Therefore, the metal film 70 can be ohmically bonded to the second semiconductor region 12. In this specification, the portion where the metal film 70 and the second semiconductor region 12 are ohmically bonded is referred to as the ohmic bonding portion 31. In this embodiment, the ohmic bonding portion 31 is provided at the upper end of the sidewall portion 22b of the source electrode groove 22 (the end on the other side in the third direction Z).
[0029] In one example, when the semiconductor component 10 includes silicon, the metal film 70 capable of Schottky and ohmic bonding includes, for example, at least one selected from the group consisting of Ti, W, Mo, Ta, Zr, Al, Sn, V, Re, Os, Ir, Pt, Pd, Rh, Ru, Nb, Sr and Hf.
[0030] In the source electrode 52 of this embodiment, a metal film 70 with a work function higher than that of the first semiconductor region 11 is formed on the surface of the contact portion 52b. However, the source electrode 52 may also be entirely composed of a metal material with a work function higher than that of the first semiconductor region 11. In this case, the metal film 70 can be omitted.
[0031] A gate electrode 53 is disposed inside a gate electrode trench 21. The lower end of the gate electrode 53 is located below the lower end of the contact portion 52b. The upper end of the gate electrode 53 overlaps with the second semiconductor region 12 in the second direction X. The upper end of the gate electrode 53 is located below the upper end of the contact portion 52b. An insulating member 41 is sandwiched between the first semiconductor region 11 and the gate electrode 53 within the gate electrode trench 21. That is, the insulating member 41 insulates the semiconductor component 10 from the gate electrode 53 within the gate electrode trench 21. The gate electrode 53 faces the surface of the cell region 11c of the first semiconductor region 11 in the second direction X, separated by the insulating member 41. The gate electrode 53 may contain, for example, polysilicon.
[0032] A field plate 61 is disposed inside the gate electrode trench 21. The field plate 61 is located below the gate electrode 53. The width dimension (the dimension in the second direction X) of the field plate 61 is smaller than the width dimension of the gate electrode 53. An insulating member 41 is sandwiched between the field plate 61 and the gate electrode 53 inside the gate electrode trench 21. Therefore, the field plate 61 and the gate electrode 53 are insulated from each other. In addition, an insulating member 41 is sandwiched between the first semiconductor region 11 and the field plate 61 inside the gate electrode trench 21. That is, the insulating member 41 insulates the semiconductor component 10 from the field plate 61 inside the gate electrode trench 21.
[0033] An insulating component 41 is disposed inside the gate electrode trench 21. The insulating component 41 includes a gate insulating film 41a and a field plate insulating film 41b. The gate insulating film 41a is located between the first semiconductor region 11 and the gate electrode 53. On the other hand, the field plate insulating film 41b is located between the first semiconductor region 11 and the field plate 61.
[0034] The field plate 61 is electrically connected to the source electrode 52. The field plate 61 and the source electrode 52 are electrically connected, for example, via wiring 52L. Thus, the field plate 61 and the source electrode 52 are at the same potential. Alternatively, the field plate 61 may be led out to the upper surface of the semiconductor device 1 (not shown) and electrically connected to the source electrode 52.
[0035] A field plate 61 is provided in the gate electrode trench 21, thereby mitigating the electric field strength in the drift region 11a. This improves the withstand voltage characteristics between the drain electrode 51 and the source electrode 52 of the semiconductor device 10. Furthermore, with the increase in withstand voltage, the impurity concentration in the drift region 11a can be set higher, thereby reducing the on-resistance of the semiconductor device 1.
[0036] An insulating film 45 is formed on the inner surface of the source electrode groove 22. The thickness of the insulating film 45 is, for example, 1 nm or more and 30 nm or less. The insulating film 45 is, for example, silicon oxide (SiO2), aluminum oxide (Al2O3), or gallium oxide (Ga2O3). Alternatively, the insulating film 45 can be made of other materials as long as it is an insulating component.
[0037] In this embodiment, the insulating film 45 contains a negative fixed charge. When the insulating film 45 contains a metal oxide, the negative fixed charge is, for example, a defect generated by the recombination of metal atoms, oxygen atoms, and bonding portions. The amount of negative fixed charge contained in the insulating film 45 is preferably 10. 12 cm －2 Above and 10 14 cm －2 the following.
[0038] In this embodiment, the insulating film 45 is formed on the inner side surface of the source electrode groove 22, except for the upper end and bottom 22a of the sidewall portion 22b. That is, the insulating film 45 is not formed on the upper end and bottom 22a of the sidewall portion 22b.
[0039] A second semiconductor region 12 is provided at the upper end of the semiconductor component 10. Therefore, the upper end of the sidewall portion 22b in the inner side surface of the source electrode trench 22 exposes the second semiconductor region 12. Furthermore, in the semiconductor component 10, the second semiconductor region 12 is located above the bottom 22a of the source electrode trench 22, and a first semiconductor region 11 is provided below the second semiconductor region 12. Therefore, the bottom 22a in the inner side surface of the source electrode trench 22 exposes the first semiconductor region 11. Additionally, the metal film 70 of the source electrode 52 is formed integrally along the inner side surface of the source electrode trench 22, including the bottom 22a. Therefore, the metal film 70 directly contacts the semiconductor component 10 at the upper end of the sidewall portion 22b and the bottom 22a in the inner side surface of the source electrode trench 22, and contacts the insulating film 45 in other portions (i.e., the area other than the upper end of the sidewall portion 22b). The metal film 70 contacts the second semiconductor region 12 at the upper end of the sidewall portion 22b to form an ohmic junction 31. Additionally, the metal film 70 contacts the first semiconductor region 11 at the bottom 22a to form a Schottky junction 32.
[0040] The insulating film 45 completely covers the portion of the source electrode 52 that faces the gate electrode 53 in the second direction X. Specifically, the upper end of the insulating film 45 is positioned above the upper end of either the upper end of the contact portion 52b or the upper end of the gate electrode 53 (in this embodiment, the upper end of the gate electrode 53), or at the same position in the third direction Z as the lower end. Similarly, the lower end of the insulating film 45 is positioned below the lower end of either the lower end of the source electrode 52 (in this embodiment, the lower end of the contact portion 52b) or the lower end of the gate electrode 53 (in this embodiment, the lower end of the source electrode 52), or at the same position in the third direction Z as the upper end.
[0041] According to this embodiment, the insulating film 45 is disposed between the metal film 70 with a high work function and the semiconductor component 10. Therefore, the metal film 70, the insulating film 45, and the first semiconductor region 11 of the semiconductor component 10 constitute a MIS (Metal-Insulator-Semiconductor) type junction. In this specification, the portion where the metal film 70, the insulating film 45, and the first semiconductor region 11 are MIS-junctioned is referred to as the MIS junction portion 33. In this embodiment, the MIS junction portion 33 is provided in the sidewall portion 22b of the source electrode trench 22.
[0042] Next, the manufacturing method of the semiconductor device 1 of this embodiment will be described.
[0043] In the manufacturing method of the semiconductor device 1 of this embodiment, firstly, a semiconductor component 10 containing n-type impurities throughout is prepared (i.e., a semiconductor component 10 having a first semiconductor region 11 formed throughout). Next, a gate electrode trench 21 and a source electrode trench 22 are formed in the semiconductor component 10. The process of forming the gate electrode trench 21 and the source electrode trench 22 can, for example, employ reactive ion etching (RIE).
[0044] In the manufacturing method of the semiconductor device 1 of this embodiment, a field plate 61 embedded in the insulating member 41 and a gate electrode 53 are formed inside the gate electrode trench 21. The process of forming the insulating member 41, the field plate 61 and the gate electrode 53 is performed by repeatedly performing the formation of the insulating member 41, the formation of the trench portion of the insulating member 41 and the formation of the conductive member into the trench portion.
[0045] In the manufacturing method of the semiconductor device 1 of this embodiment, an insulating film 45, a metal film 70, and a contact portion 52b are formed inside the source electrode trench 22. In this process, firstly, an insulating film 45 is formed entirely on the inner surface of the source electrode trench 22, including the bottom 22a. The insulating film 45 is formed, for example, by chemical vapor deposition (CVD). Next, the insulating film 45 is partially masked, and the insulating film 45 provided at the upper end of the sidewall portion 22b and the bottom 22a is removed. The removal of the insulating film 45 is performed, for example, by reactive ion etching. Furthermore, a negative fixed charge is introduced into the insulating film 45. In addition, when the insulating film 45 contains aluminum oxide, by controlling the atmosphere during film formation to prevent nitrogen from being mixed into the insulating film 45, a fixed charge is easily retained in the insulating film 45. Furthermore, when the insulating film 45 contains gallium oxide, the amount of fixed charge in the insulating film 45 can be adjusted by performing hydrogen annealing after film formation. Next, a metal film 70 is formed along the entire inner side surface of the source electrode trench 22, including the bottom 22a. The metal film 70 is formed, for example, by chemical vapor deposition (CVD) or atomic layer deposition (ALD). Next, a contact portion 52b is formed within the trench.
[0046] Next, by diffusing impurities in the upper part of the semiconductor component 10, a second semiconductor region 12 is formed in the upper part of the semiconductor component 10. Furthermore, an electrode portion 52a is formed on the upper side of the semiconductor component 10. Additionally, a drain electrode 51 is formed on the lower side of the semiconductor component 10. The semiconductor device 1 is thus obtained.
[0047] Next, the operating principle of the semiconductor device 1 in this embodiment will be explained.
[0048] In this embodiment, since the work function of the metal film 70 is higher than that of the first semiconductor region 11, a depletion layer is formed in the cell region 11c. Without applying a voltage to the gate electrode 53, a cutoff state where no current flows in the cell region 11c is obtained through the depletion layer. By controlling the potential of the gate electrode 53, an electron accumulation layer is formed as a channel in the cell region 11c, resulting in a conduction state where drain current flows in the cell region 11c. Therefore, in the semiconductor device 1, the current between the drain electrode 51 and the source electrode 52 is controlled by the potential of the gate electrode 53. Furthermore, the potential of the gate electrode 53 is a potential referenced to the potential of the source electrode 52.
[0049] In this embodiment, the metal film 70 is ohmically bonded to the second semiconductor region 12 at the upper end of the source electrode trench 22 to form an ohmic junction 31. In the on state, the current passing through the channel formed in the cell region 11c flows to the source electrode 52 through the ohmic junction 31.
[0050] In this embodiment, the metal film 70 is Schottky bonded to the first semiconductor region 11 at the bottom 22a of the source electrode trench 22 to form a Schottky junction 32. Therefore, the boundary between the metal film 70 and the first semiconductor region 11 functions as a diode (body diode) and is able to allow forward current to flow.
[0051] In this embodiment, the insulating film 45 contains a negative fixed charge. This increases the energy band of the first semiconductor region 11, thereby raising the Schottky barrier. Consequently, the depletion of the cell region 11c becomes significant, and current cannot flow in the cell region 11c (i.e., it becomes in a conducting state) unless a large voltage is applied to the cell region 11c from the gate electrode 53. In other words, according to this embodiment, by containing a negative fixed charge in the insulating film 45, the gate threshold voltage can be increased.
[0052] Specifically, in this embodiment, the insulating film 45 completely covers the cell region 11c sandwiched between the gate electrode trench 21 and the source electrode trench 22 from the second direction X. Therefore, due to the negative fixed charge contained in the insulating film 45, the overall energy band of the cell region 11c rises, which can promote the overall depletion of the cell region 11c. As a result, current is less likely to flow in the cell region 11c in the off state, and the gate threshold voltage can be further improved.
[0053] The effects of the semiconductor device 1 of this embodiment and the semiconductor devices C1 and C2 of the comparative embodiment are compared.
[0054] Figure 2 and Figure 3 This is an enlarged view of a portion near cell region 11c of semiconductor devices C1 and C2, representing the comparison method. Furthermore, in Figure 2 and Figure 3 In this document, the same reference numerals are used for structures that are the same as those of the semiconductor device 1 in the embodiment, and their descriptions are omitted.
[0055] Figure 4 This is a graph showing the simulation results of the transfer characteristics of semiconductor device 1 in the embodiment, semiconductor device C1 in the first comparison mode, and semiconductor device C2 in the second comparison mode. That is, Figure 4The diagram shows the change in drain current when the voltage between the drain electrode 51 and the source electrode 52 is set to constant, and the voltage between the gate electrode 53 and the source electrode 52 is varied. Figure 4 The horizontal axis represents the potential difference between the gate electrode 53 and the source electrode 52, and the vertical axis represents the current flowing in the drain electrode 51. Additionally, Figure 4 It is a semi-logarithmic curve graph that displays the vertical axis logarithmically.
[0056] Figure 2 Compared to the semiconductor device 1 of the first comparative embodiment, the semiconductor device C1 shown in the first comparative embodiment lacks the insulating film 45. In the semiconductor device C1 of the first comparative embodiment, the metal film 70 with a high work function directly contacts the cell region 11c of the first semiconductor region 11 to form a Schottky junction. As a result, in the semiconductor device C1 of the first comparative embodiment, depletion of the portion of the cell region 11c along the sidewall portion 22b of the source electrode trench 22 is promoted, making it difficult for current to flow. However, in the semiconductor device C1 of the first comparative embodiment, the degree of depletion of the cell region 11c depends on the work function of the metal film 70. Therefore, in the semiconductor device C1 of the first comparative embodiment, there is a limit to the depletion of the cell region 11c, making it difficult to sufficiently increase the gate threshold voltage.
[0057] Figure 3 Compared to the semiconductor device C1 of the first comparative embodiment, the semiconductor device C2 of the second comparative embodiment has an insulating film 45C that does not contain fixed charges. Compared to the semiconductor device 1 of the embodiment, the semiconductor device C2 of the second comparative embodiment does not contain fixed charges in the insulating film 45C. In the semiconductor device C2 of the second comparative embodiment, the cell region 11c is separated from the metal film 70 by an amount equal to the thickness of the insulating film 45C, and because it is insulated, no charge movement occurs, thus depletion of the cell region 11c is not easily achieved. Therefore, in the semiconductor device C2 of the second comparative embodiment, compared to the semiconductor device C1 of the first comparative embodiment, current flows more easily in the cell region 11c, and the gate threshold voltage is reduced.
[0058] As described above, it is not easy to increase the gate threshold voltage in the semiconductor device C1 of the first comparison scheme, and it is even more difficult to increase the gate threshold voltage in the semiconductor device C2 of the second comparison scheme. Furthermore, the semiconductor device C1 of the first comparison scheme may have a configuration in which an unexpected insulating film is formed on the inner surface of the source electrode trench 22 during the manufacturing process, thereby sandwiching an insulating component between the metal film 70 and the cell region 11c, similar to the semiconductor device C2 of the second comparison scheme. In this case, in the semiconductor device C1 of the first comparison scheme, as in the semiconductor device C2 of the second comparison scheme, depletion of the cell region 11c is difficult to achieve, and the gate threshold voltage decreases.
[0059] In contrast to these comparison methods, in the semiconductor device 1 of this embodiment, the depletion of the cell region 11c progresses due to the effect of the negative fixed charge in the insulating film 45. Therefore, the semiconductor device 1 of this embodiment can improve the gate threshold voltage compared to the semiconductor devices C1 and C2 of the comparison methods.
[0060] like Figure 4 As shown, in the semiconductor device 1 of this embodiment, compared with the semiconductor devices C1 and C2 of the first comparison method and the second comparison method, it can be confirmed that even if the potential of the gate electrode 53 is increased, the current does not easily flow in the semiconductor component 10. That is, in the semiconductor device 1 of this embodiment, the gate threshold voltage can be increased.
[0061] Next, the effects of this implementation method will be described.
[0062] The semiconductor device 1 of this embodiment includes a semiconductor component 10, a drain electrode 51, a gate electrode 53, a source electrode 52, and an insulating film 45. A gate electrode trench 21 and a source electrode trench 22 are provided in the semiconductor component 10. The gate electrode trench 21 and the source electrode trench 22 are arranged in a second direction X, intersecting the first direction Y. The gate electrode trench 21 and the source electrode trench 22 are recessed towards one side (lower side) of a third direction Z, intersecting both the first direction Y and the second direction X. The gate electrode 53 is disposed inside the gate electrode trench 21. The drain electrode 51 is located on one side (lower side) of the semiconductor component 10 in the third direction Z. The gate electrode 53 is disposed inside the gate electrode trench 21. The source electrode 52 is disposed inside the source electrode trench 22. The insulating film 45 is provided on at least a portion of the inner surface of the source electrode trench 22. The insulating film 45 contains a negative fixed charge. Semiconductor component 10 includes a first semiconductor region 11 and a second semiconductor region 12. The first semiconductor region 11 has a first conductivity type impurity. The second semiconductor region 12 has a higher concentration of the first conductivity type impurity than the first semiconductor region 11. The second semiconductor region 12 is located on the opposite side (upper side) in a third direction from the first semiconductor region 11. The source electrode 52 is capable of being Schottky-junctioned with the first semiconductor region 11. The source electrode 52 is capable of being ohmic-junctioned with the second semiconductor region 12. At least a portion (cell region 11c) of the first semiconductor region 11 is located between the gate electrode 53 and the source electrode 52 in the second direction X. An insulating film 45 is sandwiched between the portion (cell region 11c) of the first semiconductor region 11 and the source electrode 52 in the second direction X.
[0063] According to this structure, by including a negative fixed charge in the insulating film 45, the energy band of the first semiconductor region 11 is increased, and the depletion of the portion extending along the contact portion 52b in the third direction Z in the first semiconductor region 11 becomes significant. As a result, if a large voltage is not applied to the gate electrode 53, it cannot be set to the on state, and the gate threshold voltage can be increased.
[0064] In the semiconductor device 1 of this embodiment, the insulating film 45 completely covers the portion of the contact portion 52b that is opposite to the gate electrode 53 in the second direction X.
[0065] According to this structure, the negative fixed charge contained in the insulating film 45 causes an overall increase in the energy band of the portion (cell region 11c) sandwiched between the source electrode 52 and the gate electrode 53 in the first semiconductor region 11, promoting overall depletion of the cell region 11c. As a result, current is less likely to flow throughout the entire region of the cell region 11c in the off state, further increasing the gate threshold voltage. Furthermore, in the source electrode 52 of this embodiment, the portion opposite to the gate electrode 53 in the second direction X is a contact portion 52b located within the source electrode groove 22. The insulating film 45 completely covers the portion of the contact portion 52b opposite to the gate electrode 53.
[0066] In the semiconductor device 1 of this embodiment, at the end (upper end) on the other side of the source electrode trench 22 in the third direction Z, a portion of the source electrode 52, namely the metal film 70, is in direct contact (ohmic contact) with the second semiconductor region 12. According to this structure, current passing through the channel formed in the cell region 11c in the on state can flow to the source electrode 52 through the boundary where the second semiconductor region 12 and the source electrode 52 are ohmically joined.
[0067] In the semiconductor device 1 of this embodiment, the source electrode 52 is in direct contact with the first semiconductor region 11 at the bottom 22a of the source electrode trench 22. According to this structure, the bottom 22a of the source electrode trench 22, which enables the source electrode 52 to form a Schottky junction with the first semiconductor region 11, functions as a diode.
[0068] In the semiconductor device 1 of this embodiment, the source electrode 52 includes: a metal film 70 formed along the inner side of the source electrode groove 22; and a contact portion (metal portion) 52b disposed inside the metal film 70. The metal film 70 can be Schottky bonded to the first semiconductor region 11. Additionally, the metal film 70 can be ohmic bonded to the second semiconductor region 12. The work function of the contact portion 52b is lower than that of the metal film 70. With this structure, only the metal film 70 in the source electrode 52 can be composed of components with a high work function, while the contact portion 52b can be composed of components with a low work function. Therefore, the amount of metal with a high work function can be reduced, enabling the manufacture of a low-cost semiconductor device 1.
[0069] The semiconductor device 1 of this embodiment includes a field plate 61. The field plate 61 is located inside the gate electrode trench 21, below the gate electrode 53, and between the gate electrode 53 and the first semiconductor region 11. The field plate 61 is insulated from the gate electrode 53 but connected to the source electrode 52. With this structure, the electric field strength in the drift region 11a of the first semiconductor region 11 can be mitigated, thereby improving the voltage withstand characteristics of the semiconductor device 1. Furthermore, this embodiment describes the semiconductor device 1 with the field plate 61, but the semiconductor device 1 may also be without the field plate 61.
[0070] According to at least one embodiment described above, an insulating film is provided between the source electrode 52, which is capable of Schottky bonding with the first semiconductor region 11, and the first semiconductor region, thereby promoting the depletion of the first semiconductor region 11 and increasing the gate threshold voltage.
[0071] This invention includes the following appended notations.
[0072] (Postscript 1)
[0073] A semiconductor device, wherein:
[0074] A semiconductor component has a first trench and a second trench, which extend in a first direction, are arranged in a second direction intersecting the first direction, and are recessed to one side in a third direction intersecting both the first and second directions;
[0075] The drain electrode is located on one side of the semiconductor component in the third direction;
[0076] A gate electrode is disposed inside the first trench;
[0077] The source electrode is disposed inside the second trench; and
[0078] An insulating film, disposed on at least a portion of the inner surface of the second groove, contains a negative fixed charge.
[0079] The semiconductor component includes:
[0080] The first semiconductor region has a first conductivity type impurity; and
[0081] The second semiconductor region, having a higher concentration of the first conductivity type impurity than the first semiconductor region, is located on the opposite side in the third direction than the first semiconductor region.
[0082] The source electrode can be Schottky-junctioned with the first semiconductor region.
[0083] The source electrode can be ohmically bonded to the second semiconductor region.
[0084] At least a portion of the first semiconductor region is located between the gate electrode and the source electrode in the second direction.
[0085] The insulating film is sandwiched between the portion of the first semiconductor region and the source electrode in the second direction.
[0086] (Postscript 2)
[0087] As described in Appendix 1, in which,
[0088] The insulating film completely covers the portion of the source electrode that is opposite to the gate electrode in the second direction.
[0089] (Note 3)
[0090] As described in Appendix 1 or 2, in which,
[0091] At the end of the second trench on the other side in the third direction, the source electrode is in direct contact with the second semiconductor region.
[0092] (Postscript 4)
[0093] The semiconductor device described in any of Notes 1 to 3, wherein,
[0094] At the bottom of the second trench, the source electrode is in direct contact with the first semiconductor region.
[0095] (Note 5)
[0096] The semiconductor device described in any of Notes 1 to 4, wherein,
[0097] The source electrode has:
[0098] A metal film is formed along the inner surface of the second groove; and
[0099] The metal portion is disposed on the inner side of the metal film.
[0100] The metal film can be Schottky bonded to the first semiconductor region.
[0101] The metal film can be ohmically bonded to the second semiconductor region.
[0102] The work function of the metal part is lower than that of the metal film.
[0103] (Note 6)
[0104] The semiconductor device described in any of Notes 1 to 5, wherein,
[0105] It has a conductive component located inside the first trench and on one side of the gate electrode in the third direction, and situated between the gate electrode and the first semiconductor region.
[0106] The conductive component is insulated from the gate electrode and connected to the source electrode.
[0107] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are equally included in the scope of the invention as set forth in the claims and its equivalents.
[0108] Explanation of reference numerals in the attached figures
[0109] 1… Semiconductor device, 10… Semiconductor component, 11… First semiconductor region, 12… Second semiconductor region, 21… Gate electrode trench (first trench), 21a, 22a… Bottom, 22… Source electrode trench (second trench), 45, 45C… Insulating film, 51… Drain electrode, 52… Source electrode, 52b… Contact portion (metal portion), 53… Gate electrode, 61… Field plate (conductive component), 70… Metal film, X… Second direction, Y… First direction.
Claims
1. A semiconductor device, wherein, Having: a semiconductor member provided with a first groove and a second groove, the first groove and the second groove extending in a first direction, arranged in a second direction intersecting the first direction, recessed to one side in a third direction intersecting both the first direction and the second direction; a drain electrode on the one side of the semiconductor member in the third direction; a gate electrode disposed inside the first groove; a source electrode disposed inside the second groove; and an insulating film provided to at least a part of an inner side surface of the second groove, containing negative fixed charges, in the semiconductor member, there are provided: a first semiconductor region having a first-conductivity-type impurity; and a second semiconductor region having the first-conductivity-type impurity at a higher concentration than the first-conductivity-type impurity of the first semiconductor region, on the other side in the third direction than the first semiconductor region, the source electrode is capable of Schottky junction with the first semiconductor region, the source electrode is capable of Ohmic junction with the second semiconductor region, at least a part of the first semiconductor region is located between the gate electrode and the source electrode in the second direction, the insulating film is sandwiched between the part of the first semiconductor region and the source electrode in the second direction.
2. The semiconductor device according to claim 1, wherein the insulating film covers an entirety of a part of the source electrode opposite the gate electrode in the second direction.
3. The semiconductor device according to claim 1, wherein at an end portion of the other side of the second groove in the third direction, the source electrode is in direct contact with the second semiconductor region.
4. The semiconductor device according to claim 1, wherein at a bottom portion of the second groove, the source electrode is in direct contact with the first semiconductor region.
5. The semiconductor device according to claim 1, wherein the source electrode has: a metal film formed along an inner side surface of the second groove; and a metal portion disposed inside the metal film, the metal film is capable of Schottky junction with the first semiconductor region, the metal film is capable of Ohmic junction with the second semiconductor region, a work function of the metal portion is lower than a work function of the metal film.
6. The semiconductor device according to any one of claims 1 to 5, wherein there is a conductive member inside the first groove and on the one side of the gate electrode in the third direction, and between the gate electrode and the first semiconductor region, the conductive member is insulated from the gate electrode and is in conduction with the source electrode.
Citation Information
Patent Citations
Health management device, health management system, health management method and health management program
JP2024151356A