Semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device which is low in on-resistance and capable of performing high-efficiency power control. A semiconductor device according to an embodiment includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type provided between the first electrode and the second electrode, and a third electrode extending in a first direction from the first electrode toward the second electrode and provided on an upper portion of the first semiconductor region. In addition, a fourth electrode is provided so as to face the third electrode in a second direction orthogonal to the first direction. The semiconductor device includes a second semiconductor region of the second conductivity type provided between the third electrode and the fourth electrode and in contact with the third electrode at least in the second direction. In addition, an insulating layer is provided which is in contact with the fourth electrode and includes a first insulating region provided so as to face the third electrode in the second direction. A third semiconductor region of the first conductivity type having a higher impurity concentration than the first semiconductor region is provided between the second electrode and the second semiconductor region.

Description

[0001] Related Application

[0002] This application claims priority to Japanese Patent Application No. 2024-153441 (Filing date: September 5, 2024) and Japanese Patent Application No. 2025-028600 (Filing date: February 26, 2025). This application incorporates by reference the entire contents of the base applications. TECHNICAL FIELD

[0003] Embodiments of the present application relate to a semiconductor device. BACKGROUND

[0004] A semiconductor device such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and an Insulated Gate Bipolar Transistor (IGBT) is widely known as a power semiconductor device that controls a high voltage and a large current. For these power semiconductor devices, it is required to perform power control with high efficiency without increasing on-resistance. SUMMARY

[0005] Embodiments of the present application provide a semiconductor device that has low on-resistance and can perform power control with high efficiency.

[0006] The semiconductor device of the embodiment has a first electrode, a second electrode, a first semiconductor region of a first conductivity type provided between the first electrode and the second electrode, and a third electrode extending in a first direction from the first electrode toward the second electrode and provided at an upper portion of the first semiconductor region. In addition, a fourth electrode is provided so as to face the third electrode in a second direction orthogonal to the first direction. The semiconductor device has a second semiconductor region of a second conductivity type provided between the third electrode and the fourth electrode and at least in contact with the third electrode in the second direction. In addition, an insulating layer is in contact with the fourth electrode and includes a first insulating region provided so as to face the third electrode in the second direction. A third semiconductor region of the first conductivity type having a higher impurity concentration than the first semiconductor region is provided between the second electrode and the second semiconductor region. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a schematic cross-sectional view of a semiconductor device 100 of a first embodiment.

[0008] Figure 2 is a cross-sectional view of a dashed line A portion of Figure 1

[0009] Figure 3 ​This is a schematic cross-sectional view of a comparative example semiconductor device 900.

[0010] Figure 4 This is a partial cross-sectional view of the semiconductor device 200 of the first modified example.

[0011] Figure 5 This is a partial cross-sectional view of the semiconductor device 300 of the second variation.

[0012] Figure 6 This is a partial cross-sectional view of the semiconductor device 400 of the third variation.

[0013] Figure 7 This is a partial cross-sectional view of the semiconductor device 500 of the fourth modification.

[0014] Figure 8 This is a partial cross-sectional view of the semiconductor device 600 of the fifth modification.

[0015] Figure 9 This is a partial cross-sectional view of the semiconductor device 700 of the sixth modification.

[0016] Figure 10 This is a partial cross-sectional view of the semiconductor device 800 of the seventh modification.

[0017] Figure 11 This is a schematic cross-sectional view of the first manufacturing process, which is part of the manufacturing process of the third electrode 22.

[0018] Figure 12 This is a schematic cross-sectional view of the second manufacturing process, which is part of the manufacturing process of the third electrode 22.

[0019] Figure 13 This is a schematic cross-sectional view of the third manufacturing process, which is part of the manufacturing process of the third electrode 22.

[0020] Figure 14 This is a schematic cross-sectional view showing the fourth manufacturing process as part of the manufacturing process of the third electrode 22. Detailed Implementation

[0021] The following is a reference to the appendix. Figure 1 Embodiments of the present invention will be described below. In this description, common parts will be labeled with common reference numerals throughout the drawings. Furthermore, these embodiments do not limit the present invention, and the aspect ratio of the drawings is not limited to the ratio shown in the figures. In the following description, the first conductivity type will be described as n-type and the second conductivity type as p-type, but this is not a limitation. Alternatively, the first conductivity type may be p-type and the second conductivity type n-type.

[0022] [First Implementation Method]

[0023] (Semiconductor device 100 configuration)

[0024] pass Figure 1 as well as Figure 2 The configuration of the semiconductor device 100 according to the first embodiment will be described. Here, Figure 2 It shows the result of Figure 1 The dashed line A is surrounded by a dashed line. Figure 1 The semiconductor device 100 shown is, for example, a MOSFET (Metal-Oxide-Silicon Field-Effect Transistor). Figure 1 As shown, the semiconductor device 100 includes a first electrode 10, a second electrode 20, a semiconductor portion 30, a third electrode 22, a fourth electrode 40, an insulating layer 50, and an interlayer insulating layer 46. In this embodiment, a configuration including a fifth electrode 41 will also be described, but it is not limited to this configuration.

[0025] The direction from the first electrode 10 toward the second electrode 20 is defined as the first direction, and is also defined as the Z direction. The direction orthogonal to the Z direction is defined as the second direction, and is also defined as the X direction. The direction orthogonal to both the Z and X directions is defined as the third direction, and is also defined as the Y direction. Furthermore, for ease of explanation, the first direction is defined as upward (+Z direction), and the direction opposite to the first direction is defined as downward (-Z direction).

[0026] Along the Z-direction from the first electrode 10 toward the semiconductor section 30. The semiconductor section 30 includes a first semiconductor region 31, a second semiconductor region 32, a third semiconductor region 33, and a fourth semiconductor region 34. The first semiconductor region 31, the third semiconductor region 33, and the fourth semiconductor region 34 within the semiconductor section 30 are of a first conductivity type (e.g., n-type). The second semiconductor region 32 is of a second conductivity type (e.g., p-type).

[0027] A first semiconductor region 31 is disposed between the first electrode 10 and the second electrode 20. The direction from the first semiconductor region 31 toward the second electrode 20 is along the Z-direction. A third electrode 22 is disposed above the first semiconductor region 31 and extends along the Z-direction. A second semiconductor region 32 is disposed above the first semiconductor region 31 and is connected to the third electrode 22 in the X-direction. A third semiconductor region 33 is disposed between the second electrode 20 and the first semiconductor region 31 and is connected to the third electrode 22 in the X-direction. A fourth semiconductor region 34 is disposed between the first electrode 10 and the first semiconductor region 31 and is connected to the first semiconductor region 31 in the XY plane.

[0028] Furthermore, the third semiconductor region 33 has more n-type impurities than the first semiconductor region 31. Additionally, the fourth semiconductor region 34 has more n-type impurities than the first semiconductor region 31. The impurity concentration of the first conductivity type in the first semiconductor region 31 is, for example, 1 × 10⁻⁶. 15 atoms / cm 3 Above 2×10 17 atoms / cm 3 In the following cases, the impurity concentration of the first conductivity type in the third semiconductor region 33 and the fourth semiconductor region 34 is, for example, 1 × 10⁻⁶. 17 atoms / cm 3 Above 1×10 21 atoms / cm 3 The fourth semiconductor region 34 is provided to reduce the resistance between the first electrode 10 and the second electrode 20, and is not a necessary configuration.

[0029] Furthermore, trenches U are provided from the upper surface 30a of the semiconductor section 30 toward the -Z direction. For example, trenches U extend continuously in the Y direction. Multiple trenches U may also be provided at intervals along the X direction.

[0030] An insulating layer 50 is disposed within the trench U. The fourth electrode 40 and the fifth electrode 41 are surrounded by the insulating layer 50 within the trench U. The insulating layer 50 is in contact with the fourth electrode 40, the fifth electrode 41, and the first semiconductor region 31. The insulating layer 50 provides electrical insulation between the fourth electrode 40 and the first semiconductor region 31, between the fifth electrode 41 and the first semiconductor region 31, and between the fourth electrode 40 and the fifth electrode 41. Additionally, an interlayer insulating layer 46 provides electrical insulation between the fourth electrode 40 and the second electrode 20.

[0031] Between a plurality of arbitrary trenches U arranged along the X direction, a trench T is provided from the upper surface 30a of the semiconductor section 30 toward the -Z direction.

[0032] The third electrode 22 is disposed within the trench T. The third electrode 22 is a trench contact element electrically connected to the second electrode 20. Furthermore, according to... Figure 2 The third electrode 22 has a wall 90 surrounding it along the Z direction, a bottom surface 91 opposite and in contact with the first semiconductor region 31 along the X direction, and an upper surface 92 opposite and in contact with the second electrode 20 along the X direction. Furthermore, the third electrode 22 has a corner 80 where the wall 90 and the bottom surface 91 intersect. The corner 80 can be an acute angle, an obtuse angle, a right angle, or a chamfer. The shape of the corner 80 is determined through design and manufacturing processes. Additionally, the bottom surface 91 is curved, and when continuously connected to the wall surface 90, for example, the portion of the bottom surface 91 with a changing curvature can be used as the corner 80. These wall surfaces 90, bottom surface 91, and upper surface 92 are included in the third electrode 22.

[0033] In addition, such as Figure 2 As shown, the insulating layer 50 includes a first insulating region 51 disposed in the X direction between the first semiconductor region 31 and the fourth electrode 40. A second semiconductor region 32 is disposed between the third electrode 22 and the fourth electrode 40, and is opposite and in contact with the first semiconductor region 31 and the third electrode 22 in the X direction. At this time, the second semiconductor region 32 may or may not be in contact with the third semiconductor region 33 in the Z direction. A first channel region r1 is formed between the second semiconductor region 32 and the first insulating region 51. The first channel region r1 will be described together with the description of the operation of the semiconductor device 1 later.

[0034] Figure 1 The fourth electrode 40 and the fifth electrode 41 shown may contain at least one of polycrystalline silicon and a metal. The second electrode 20 may contain at least one selected from the group consisting of Al, Cu, Mo, W, Ta, Co, Ru, Ti, and Pt. The first electrode 10 may contain at least one selected from the group consisting of Al, Cu, Mo, W, Ta, Co, Ru, Ti, Ni, and Pt. In the case where the first conductivity type is n-type, as in this embodiment, it is preferable to select a metal with a work function such that the first semiconductor region 31 forms a Schottky junction. For example, a metal with a work function of 4.3 eV or higher may include at least one selected from Ir, Pd, Au, Ti, Cr, Fe, Cu, Zr, Mo, Ru, Ag, Pt, Nd, Bi, Ni, and Co. Furthermore, it is preferable to select a metal in such a way that the third electrode 22 and the second semiconductor region 32 form an ohmic junction.

[0035] Figure 1 The fifth electrode 41 shown can also be electrically connected to the second electrode 20 using an electrode (wiring, etc.) not shown. The fifth electrode 41 functions, for example, as a field plate, in which case, when the MOSFET is turned off, it can extend the depletion layer in the first semiconductor region 31 and maintain the withstand voltage.

[0036] (Operation of semiconductor device 100)

[0037] The operation of the semiconductor device 100 will be explained. In the case of a MOSFET, for example, the current flowing between the first electrode 10 and the second electrode 20 can be controlled by controlling the potential of the fourth electrode 40. The first electrode 10 functions as, for example, the drain electrode. The second electrode 20 functions as, for example, the source electrode. Furthermore, the third electrode 22 is at the same potential as the second electrode 20 and is the source electrode. The third semiconductor region 33 functions as, for example, the source region. Figure 2The first channel region r1, indicated by the dashed line, includes a depletion layer formed by the pn junction between the second semiconductor region 32 and the first semiconductor region 31, functioning, for example, as a channel region. The fourth electrode 40 functions, for example, as a gate electrode. The first insulating region 51 functions, for example, as a gate insulating film. Furthermore, a depletion layer based on a Schottky junction is formed at the interface between the third electrode 22 and the first semiconductor region 31.

[0038] The first channel region r1 is, for example, connected in the X direction to the second semiconductor region 32 and the first insulating region 51. Additionally, the first channel region r1 is also connected in the Z direction to the third semiconductor region 33 disposed on the surface of the first semiconductor region 31. The first channel region r1 is a region where the carrier density varies according to the potential of the fourth electrode 40, and is not limited to the region shown by the dashed line.

[0039] Formed in Figure 2 The thickness (distance in the X direction) of the depletion layer formed by the pn junction at the interface between the first channel region r1 and the second semiconductor region 32 is controlled by the potential of the fourth electrode 40. That is, depending on the potential of the fourth electrode 40, when the carrier density in the first channel region r1 is low, substantially no current flows between the third electrode 22 and between the second electrode 20 and the first electrode 10. In other words, a cutoff state is achieved. Depending on the potential of the fourth electrode 40, when the carrier density in the first channel region r1 is high, current flows between the third electrode 22 and between the second electrode 20 and the first electrode 10. In other words, a conduction state is achieved.

[0040] As described above, the semiconductor device 100 in this embodiment is a semiconductor device that forms a depletion layer, which is formed by the first channel region r1. Furthermore, the carrier density of the depletion layer is controlled using the fourth electrode 40.

[0041] here, Figure 3 The semiconductor device 900 of the comparative example is shown. A second semiconductor region 32 of the second conductivity type, located between the second electrode 20 and the first electrode 10, is in contact with both the third electrode 22 and the first insulating region 51 in the X direction. The second semiconductor region 32 has a thickness in the Z direction.

[0042] The semiconductor device 900 forms a depletion layer across the interface where the second semiconductor region 32 and the first semiconductor region 31 meet in the Z direction. The electrical connection between the first electrode 10 and the second electrode 20 is interrupted by the second semiconductor region 32, which includes the depletion layer forming across the X-Y plane. By applying a voltage to the fourth electrode 40, charge carriers accumulate at the interface where the second semiconductor region 32 and the insulating layer 50 meet in the X direction to form a channel, thus achieving a conductive state.

[0043] On the other hand, in the case of the semiconductor device 100 of this embodiment, a depletion layer is formed at the interface where the second semiconductor region 32 and the first semiconductor region 31 are connected in the X direction. That is, the semiconductor device 100 does not have the second semiconductor region 32 that is connected in the X direction to both the third electrode 22 and the first insulating region 51, as is the case in the semiconductor device 900. As a result, the semiconductor device 100 can provide a semiconductor device that can reduce on-resistance.

[0044] (First variation)

[0045] Figure 4 This is a schematic diagram of a semiconductor device 200 of a first variation of the first embodiment.

[0046] Semiconductor device 200 is an example of semiconductor device 100 where the lowest point 32c of the second semiconductor region 32 is located in the Z direction closer to the second electrode 20 than the lowest point 22c of the third electrode 22. Furthermore, the lowest point 22c is contained within the bottom surface 91. This example of semiconductor device 200 can reduce the on-resistance and reverse recovery charge Qrr compared to semiconductor device 100. The reduction in Qrr can shorten the recovery time during shutdown. Additionally, in... Figure 4 In the diagram, the lowest point 32c is described in a planar shape, but is not limited to this. The lowest point can be set as a Z-axis shape based on the concentration distribution that takes into account the diffusion width of the second semiconductor region 32.

[0047] (Second variation)

[0048] Figure 5 This is a schematic diagram of a semiconductor device 300 of a second variation of the first embodiment.

[0049] Semiconductor device 300 is an example where the lowest point 32c of the second semiconductor region 32 of semiconductor device 100 is located in the Z direction closer to the first electrode 10 than the lowest point 22c of the third electrode 22. As a result, the Z-direction length of the depletion layer formed in the first channel region r1 becomes longer. Consequently, the Z-direction distance of the first channel region r1 becomes longer, and the overall withstand voltage of the device increases. That is, leakage current between the source and drain can be reduced.

[0050] (Third variation)

[0051] Figure 6 This is a schematic diagram of a semiconductor device 400 of a third variation of the first embodiment.

[0052] The semiconductor device 400 has a second semiconductor region 32 integrally formed at the interface between the third electrode 22 and the first semiconductor region 31. The second semiconductor region 32 is arranged to surround the outer surface of the third electrode 22. Here, the outer surface is a continuous surface where the third electrode 22 and the second semiconductor region 32 are in contact. Thus, a depletion layer based on a pn junction is formed to cover the outer surface of the third electrode 22. Therefore, a depletion layer is also formed on the bottom surface 91 of the third electrode 22, and the Z-direction distance of the depletion layer that cuts off the source and drain is increased, which can reduce leakage current.

[0053] (Fourth variation)

[0054] Figure 7 This is a schematic diagram of a semiconductor device 500 in the fourth variation of the first embodiment.

[0055] The semiconductor device 500, in the same shape as the semiconductor device 300, also has an insulating layer 53 on the bottom surface 91 of the third electrode 22. Similar to the semiconductor device 400, it has the advantage of reducing leakage current from the bottom surface 91 of the third electrode 22.

[0056] (Fifth variation)

[0057] Figure 8 This is a schematic diagram of a semiconductor device 600 in the fifth variation of the first embodiment.

[0058] The second semiconductor region 32 of the semiconductor device 600, located between the first insulating region 51 and the third electrode 22, is in contact with both the first insulating region 51 and the third electrode 22 in the X direction. Furthermore, the second semiconductor region 32 has a concentration gradient of a second conductivity type in the X direction, with the concentration of the second conductivity type thinning from the third electrode 22 towards the first insulating region 51. For example, the concentration distribution has a slope close to a Gaussian distribution according to the diffusion equation.

[0059] In the region of the second semiconductor region 32 where the concentration of the second conductivity type is thin, an accumulation layer is easily formed when a gate voltage is applied, which reduces channel resistance. On the other hand, when the gate voltage is applied below 0V, the channel is cut off, maintaining a cut-off state. This semiconductor device 600 covers the first channel region r1 through the second semiconductor region 32, thereby providing the second semiconductor region 32 across the X-Y plane. As a result, compared to the semiconductor device 100 of the first embodiment, the leakage current between the source and drain can be reduced. In addition, the concentration of the second conductivity type in the second semiconductor region 32 can also be 0 in the portion connected to the first insulating region 51.

[0060] (Sixth variation)

[0061] Figure 9This is a schematic diagram of a semiconductor device 700 in the sixth variation of the first embodiment.

[0062] The semiconductor device 700 is configured such that the second semiconductor region 32 surrounds the corner 80 of the third electrode 22. That is, as... Figure 9 As shown, at least a portion of the third electrode 22 is opposed to and connected to the second semiconductor region 32 in the X direction. Furthermore, the third electrode 22 is opposed to and connected to both the first semiconductor region 31 and the second semiconductor region 32 in the Z direction. Additionally, the wall surface 90 of the third electrode 22 may also be connected to the first semiconductor region 31 in the X direction.

[0063] This semiconductor device 700 forms a first channel region r1 between the third electrode 22 and the first insulating region 51. In the semiconductor device 700, the depletion layer extends from the interface with the first semiconductor region 31 in a manner that surrounds the second semiconductor region 32, thus cutting off the first channel region r1 between the first insulating region 51 and the second semiconductor region 32. This allows leakage current released from the third electrode 22 to the first channel region r1 to be cut off. Furthermore, leakage current released from the third electrode 22 to the bottom surface 91 can also be cut off. In addition, by not completely covering the wall 90 of the third electrode 22 as in semiconductor devices 300-600, the semiconductor device 700 can reduce channel resistance.

[0064] Semiconductor device 700 does not completely cover the bottom surface 91 of the third electrode 22 with the second semiconductor region 32, thus having a region where a portion of the bottom surface 91 of the third electrode 22 contacts the first semiconductor region 31. Therefore, a body diode is formed at the interface between the third electrode 22 and the first semiconductor region 31. In the comparative examples, semiconductor devices 400 and 900 are formed as body diodes using a pn junction. However, in semiconductor device 700, since it is a Schottky diode, the forward voltage is lower than that of a pn junction, which shortens the reverse recovery time.

[0065] (Seventh variation)

[0066] Figure 10 This is a schematic diagram of a semiconductor device 800 in the seventh variation of the first embodiment.

[0067] The semiconductor device 800 has a shape in which the width of the third electrode 22 gradually narrows in the X direction as it moves towards the -Z direction. That is, the width of the bottom surface 91 of the third electrode 22 in the X direction is smaller than the width of the upper surface 92 of the third electrode 22. Like the semiconductor device 700, the semiconductor device 800 is arranged such that the corner 80 of the third electrode 22 is surrounded by the second semiconductor region 32. Figure 10As shown, at least a portion of the third electrode 22 is opposed to and connected to the second semiconductor region 32 in the X direction. Furthermore, the third electrode 22 is opposed to and connected to both the first semiconductor region 31 and the second semiconductor region 32 in the Z direction. In addition, the wall surface 90 of the third electrode 22 may also be connected to the first semiconductor region 31 in the X direction.

[0068] Such a semiconductor device 800 forms a first channel region between the third electrode 22 and the first insulating region 51. Furthermore, because the bottom surface 91 of the third electrode 22 has a narrow width in the X direction, the area of ​​the bottom surface 91 is reduced, thereby decreasing leakage current from the bottom surface 91. Additionally, a depletion layer formed at the interface between the first semiconductor region 31 and the second semiconductor region 32 is formed on a portion of the bottom surface 91 of the third electrode 22, further reducing leakage current.

[0069] Furthermore, by not completely covering the bottom surface 91 of the third electrode 22 with the second semiconductor region 32, a body diode is formed between the third electrode 22 and the first semiconductor region 31. In the semiconductor device 800, compared to a pn junction, the forward voltage is lower, and the reverse recovery time can be shortened. Alternatively, in the semiconductor device 800, the bottom surface 91 of the third electrode 22 and the second semiconductor region 32 may not be connected in the Z direction.

[0070] The semiconductor devices of the first embodiment and the first to seventh variations described above are all designed to make the MOSFET in the off state based on the depletion layer width determined by the concentration of the first conductivity type and the second conductivity type.

[0071] Here, the width of the depletion layer in a typical pn junction is represented by the following equation (1).

[0072]

[0073] W is the width of the depletion layer (μm), and ε0 is the dielectric constant of vacuum, for example, 8.85 × 10⁻⁶. －14 F / cm, ε r q is the relative permittivity of the semiconductor, for example, 11.9, and q is the elementary charge, for example, 1.60 × 10⁻⁶. －19 C / V, the dielectric constant of a conductor, V bi It is the bulk potential of the unbiased junction, Na is the p-type impurity concentration, and Nd is the n-type impurity concentration.

[0074] When the distance in the X direction of the first channel region r1 formed between the second semiconductor region 32 and the first insulating region 51 is set as the first length L, the first length L can be determined based on the width of the depletion layer. The first length L can be calculated based on the impurity concentration of the first semiconductor region and the impurity concentration of the second semiconductor region 32 according to equation (1).

[0075] Here, for example, in order to avoid providing a second semiconductor region 32 on the wall 90 of the third electrode 22, and instead utilize the Schottky barrier between the third electrode 22 and the first semiconductor region 31 to achieve a cutoff state when not energized, the length of L needs to be about 0.05 μm or less. In this case, due to the need for microfabrication, fabrication is difficult. On the other hand, in the semiconductor device 100 of this embodiment, the n-type impurity concentration is 1 × 10⁻⁶. 15 atoms / cm 3 Above 1×10 17 atoms / cm 3 The following p-type impurity concentration is 1×10 17 atoms / cm 3 Above 1×10 19 atoms / cm 3 In the following cases, the length of L used to achieve a cutoff state when not energized can be ensured to be approximately 0.1 to 1 μm according to equation (1). That is, this embodiment is easier to manufacture from a processability point of view compared to a Schottky barrier-based semiconductor device where the second semiconductor region 32 is not provided on the wall surface 90 of the third electrode 22. Furthermore, according to equation (1), when the n-type impurity concentration is 1 × 10⁻⁶... 15 atoms / cm 3 The concentration of p-type impurities is 1×10⁻⁶. 17 atoms / cm 3 Above 1×10 19 atoms / cm 3 Under the following conditions, the depletion layer is approximately 0.9–1 μm. At an n-type impurity concentration of 1 × 10⁻⁶... 16 atoms / cm 3 The concentration of p-type impurities is 1×10⁻⁶. 17 atoms / cm 3 Above 1×10 19 atoms / cm 3 Under the following conditions, the depletion layer is approximately 0.3 μm. This is achieved when the n-type impurity concentration is 1 × 10⁻⁶. 17 atoms / cm 3 The concentration of p-type impurities is 1 × 10 atoms / 17 cm 3 Above 1×10 19 atoms / cm 3 In the following cases, the depletion layer is approximately 0.07–0.1 μm. By controlling the width of the depletion layer using these values, it is possible to improve the reduction of processing steps, the trade-offs between other components, and the reduction of on-resistance.

[0076] (First manufacturing process)

[0077] Figure 11 (a) to (e) are schematic cross-sectional views of the first manufacturing process, which is a part of the manufacturing process of the third electrode 22.

[0078] like Figure 11 As shown in (a), a trench T is first formed, for example, inside the interlayer insulating layer 46, the insulating layer 50, and the semiconductor portion 30. Here, in the manufacturing method of the semiconductor device 800 of the seventh modification, if the taper angle is adjusted using the Bosch process of RIE, a trench T with a narrower width in the X direction can be formed in the Z direction. Figure 11 After (a), such as Figure 11 As shown in (b), an oxide film 70 is formed by CVD (Chemical Vapor Deposition) in a manner that fills trench T. Then, as... Figure 11 As shown in (c), the upper surface of the oxide layer 70 is moved backward in the -Z direction by means of reactive ion etching (RIE), and the oxide film 70 remains at the bottom of the trench T as a mask material 71. Alternatively, the photoresist used in the photolithography process can be filled into the trench T, and the exposure amount can be adjusted so that the photoresist formed at the bottom of the trench T serves as the mask material 71. In addition, when a positive photoresist is filled into the trench T, development can be performed without exposure, and the mask material 71 can be formed by ashing treatment using oxygen plasma. Then, as Figure 11 As shown in (d), a second conductivity type impurity is implanted by adjusting the implantation angle of ion implantation from the upper surface of the first semiconductor region 31. This creates a first diffusion region r2 formed by the second conductivity type impurity. At this time, the first diffusion region r2 is formed in the exposed silicon first semiconductor region 31 and third semiconductor region 33 within the inner wall of the trench T.

[0079] After the first diffusion region r2 is formed, the mask material 71 is peeled off. To activate the impurities in the first diffusion region r2, an annealing process is performed at a high temperature of 700°C or higher. Through the annealing process, the second diffusion region grows, forming the second semiconductor region 32. If the mask material 71 is an oxide film formed by CVD, the mask material 71 can also be peeled off after the annealing process. Furthermore, the first diffusion region r2 does not diffuse into the third semiconductor region 33, which has a higher impurity concentration.

[0080] In addition, the mask material 71 can be peeled off using chemical peeling, but different methods can also be used.

[0081] Thus, a second semiconductor region 32 can be formed that is connected to the third electrode 22 of the semiconductor device 100 of the first embodiment.

[0082] Schottky metal can be embedded inside the trench T using methods such as CVD, plating, and PVD (Physical Vapor Deposition) to form a trench contact as the third electrode 22.

[0083] In addition, by thickening Figure 11 The thickness of the mask material 71 in (c) can shorten the thickness of the mask material 71 in the mask material 71. Figure 9 The Z-direction length of the first diffusion region r2 formed on the exposed inner wall of the trench T in (d). Thus, the second semiconductor region 32 of the semiconductor device 200 of the first modified example can be formed.

[0084] In addition, during Figure 11 During the annealing process of the first diffusion region r2 in (d), the first diffusion region r2 can also reach the first insulating region 51 with a concentration gradient. In this case, the second semiconductor region 32 of the semiconductor device 600 of the fifth modified example can be formed. For example, a concentration gradient can also be formed by diffusion based on annealing.

[0085] Through these methods, the semiconductor device 600 forms a second semiconductor region 32 having a concentration gradient such that the concentration of the second conductivity type thins from the third electrode 22 toward the first insulating region 51.

[0086] (Second manufacturing process)

[0087] Figure 12 (a) to (d) are schematic cross-sectional views showing a second manufacturing process as part of the manufacturing process of the third electrode 22. They are also different examples of the manufacturing process of the semiconductor device 100 of the first embodiment.

[0088] like Figure 12 As shown in (a), groove T is formed. Then, as... Figure 12 As shown in (b), a second conductivity type impurity is implanted to cover the entire exposed inner wall of the trench T. This forms a second diffusion region r3 covering the entire inner wall of the trench T. The second diffusion region r3 is an impurity layer of the second conductivity type. Furthermore, a portion of the bottom wall and the sidewalls adjacent to the bottom wall in the second diffusion region r3 are removed by a re-emulation (RIE). Subsequently, the second diffusion region r3 is grown through an annealing process to form a second semiconductor region 32.

[0089] An example of the first manufacturing process and an example of the second manufacturing process can also control the thickness of the second semiconductor region 32 in the X direction formed by the temperature and time conditions of the annealing process.

[0090] In addition, the removal process for a portion of the second diffusion region r3 is not limited to RIE and different methods can also be used.

[0091] In addition, Figure 12 (c) and Figure 12 In step (d), by removing only the portion of the second diffusion region r3 that is in contact with the bottom wall of the trench T through RIE and adjusting the annealing time, the second semiconductor region 32 of the semiconductor device 300 of the second modified example can be formed. Furthermore, the second diffusion region r3 does not diffuse into the third semiconductor region 33, which has a higher impurity concentration.

[0092] (Third manufacturing process)

[0093] Figure 13 (a) to (c) are schematic cross-sectional views of a third manufacturing process, which is a part of the manufacturing process of the third electrode 22. The third manufacturing process is an example of the semiconductor device 400 of the third variation.

[0094] like Figure 13 As shown, the groove T is formed in the same manner as described above. Then, as... Figure 13 As shown in (b), a second type of impurity is injected to completely cover the exposed inner wall of the trench T. This forms a third diffusion region r4 that covers the entire inner wall of the trench T. In the third manufacturing process, instead of RIE-based processing, the third diffusion region r4 is grown through an annealing process to form a second semiconductor region 32 that completely covers the inner wall of the trench T. Furthermore, the third diffusion region r4 does not diffuse into the third semiconductor region 33, which has a higher impurity concentration.

[0095] (Fourth manufacturing process)

[0096] Figure 14 (a) to (e) are schematic cross-sectional views showing a fourth manufacturing process as part of the manufacturing process of the third electrode 22. The fourth manufacturing process is an example of the semiconductor device 500 of the fourth variation.

[0097] like Figure 14 As shown, trench T is formed in the same manner as described above. Then, an oxide film 70 is formed to fill the trench T. Next, as... Figure 14 As shown in (c), the upper surface of the oxide film 70 is retracted in the -Z direction by means of RIE, etc., and the mask material 71 remains at the bottom of the trench T as part of the oxide film 70. Then, as Figure 14 As shown in (d), a second conductivity type impurity is implanted from the upper surface of the first semiconductor region 31. A fourth diffusion region r5 is formed on the exposed inner wall of the trench T. At this time, the fourth diffusion region r5 is formed in the exposed silicon first semiconductor region 31 and third semiconductor region 33 in the inner wall of the trench T.

[0098] Mask material 71 remains at the bottom of trench T. Instead of removing it, a fourth diffusion region r5 formed by impurities of the second conductivity type is grown through an annealing process. Furthermore, the fourth diffusion region r5 does not diffuse into the third semiconductor region 33, which has a higher impurity concentration.

[0099] While embodiments of the invention described herein are presented as examples, they are not intended to limit the scope of the invention. Examples could also include insulated-gate bipolar transistors (IGBTs), vertical diodes, or other semiconductor chips.

[0100] These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are also included in the scope of the invention as described in the claims and its equivalents.

[0101] Explanation of reference numerals in the attached figures

[0102] 10 First Electrode

[0103] 20 Second electrode

[0104] 22 Third Electrode

[0105] 30 Semiconductor Division

[0106] 30a upper surface

[0107] 31 First Semiconductor Region

[0108] 32 Second Semiconductor Region

[0109] 33 Third Semiconductor Region

[0110] 34 Fourth Semiconductor Region

[0111] r1 First Channel Area

[0112] r2 First diffusion region

[0113] r3 Second diffusion region

[0114] r4 Third diffusion region

[0115] r5 Fourth diffusion region

[0116] T and U trenches

[0117] 40 Fourth electrode

[0118] 41 Fifth electrode

[0119] 46 interlayer insulation

[0120] Insulation layers 50 and 53

[0121] 51 First Insulation Region

[0122] 70 Oxide film

[0123] 71 Mask Material

[0124] 90 wall

[0125] 91 Bottom

[0126] 92 Upper surface

Claims

1. A semiconductor device, characterized by comprising: has: a first electrode; a second electrode; a first semiconductor region of a first conductivity type, provided between the first electrode and the second electrode; a third electrode, extending in a first direction from the first electrode toward the second electrode, provided at an upper portion of the first semiconductor region; a fourth electrode, provided opposite the third electrode in a second direction orthogonal to the first direction; a second semiconductor region of a second conductivity type, provided between the third electrode and the fourth electrode, and in contact with the third electrode at least in the second direction; an insulating layer, in contact with the fourth electrode, including a first insulating region provided opposite the third electrode in the second direction; and a third semiconductor region of the first conductivity type, provided between the second electrode and the second semiconductor region, and having a higher impurity concentration than the first semiconductor region.

2. The semiconductor device according to claim 1, wherein the second semiconductor region is in contact with both the third electrode and the first semiconductor region in the second direction.

3. The semiconductor device according to claim 1, wherein a first lowermost point of the second semiconductor region in a direction opposite the first direction is located on the second electrode side than a second lowermost point of the third electrode in the direction opposite the first direction.

4. The semiconductor device according to claim 1, wherein a first lowermost point of the second semiconductor region in a direction opposite the first direction is located on the first electrode side than a second lowermost point of the third electrode in the direction opposite the first direction.

5. The semiconductor device according to claim 1, wherein the second semiconductor region is provided between the third electrode and the first semiconductor region in a manner surrounding an outer surface of the third electrode.

6. The semiconductor device according to claim 1, further comprising an insulating layer provided between the third electrode and the first electrode, in contact with the third electrode in the first direction.

7. The semiconductor device according to claim 1, wherein 8. The semiconductor device according to claim 1, wherein a first length of the first semiconductor region in the second direction, provided between the second semiconductor region and the first insulating region, is 0.1 μm to 1 μm. The impurity concentration of the first conductivity type in the first semiconductor region is 1×10⁻⁶. 15 atoms / cm 3 Above and 1×10 17 atoms / cm 3 the following.

9. The semiconductor device according to claim 1, wherein the third electrode has an upper surface opposite and in contact with the second electrode in the first direction, and a bottom surface opposite and in contact with the first semiconductor region in the first direction, the width of the bottom surface in the second direction being smaller than the width of the upper surface in the second direction.

10. The semiconductor device according to claim 1 or 9, wherein the third electrode is in contact with both the first semiconductor region and the second semiconductor region in the first direction. has: a first electrode; 11. A semiconductor device, characterized by comprising: a second electrode; ​ ​ a first semiconductor region of a first conductivity type provided between the first electrode and the second electrode; a third electrode extending in a first direction from the first electrode toward the second electrode, provided at an upper portion of the first semiconductor region; a fourth electrode provided opposite the second electrode in a second direction orthogonal to the first direction; an insulating layer in contact with the fourth electrode, including a first insulating region provided opposite the third electrode in the second direction; and a second semiconductor region of a second conductivity type having a concentration gradient of impurities of the second conductivity type in the second direction, provided between the third electrode and the first insulating region, in contact with both the third electrode and the first insulating region in the second direction.

12. The semiconductor device according to claim 11, wherein the concentration gradient decreases in concentration from the second electrode toward the first insulating region.

13. The semiconductor device according to claim 11, wherein the concentration gradient has a Gaussian distribution.

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