Semiconductor device including fin-shaped pattern

Abstract

A semiconductor device is provided. The semiconductor device includes: a substrate; a first active pattern extending in a first direction on the substrate; a second active pattern extending in the first direction on the substrate, the second active pattern being spaced apart from the first active pattern in a second direction intersecting the first direction; a plurality of nanosheets spaced apart from each other in a third direction perpendicular to the first direction and the second direction on the first active pattern; and a fin-shaped pattern spaced apart from the plurality of nanosheets in the second direction, the fin-shaped pattern including a first portion and a second portion. A gate electrode extends in the second direction on the first active pattern and the second active pattern, the gate electrode at least partially surrounding each of the plurality of nanosheets and the fin-shaped pattern.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0115718, filed on August 28, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Various exemplary embodiments relate to semiconductor devices. Specifically, this disclosure relates to devices including MBCFETs. TM Semiconductor devices (multi-bridge channel field-effect transistors). Background Technology

[0003] As a scaling technology to increase the density of integrated circuit devices, multi-gate transistors have been proposed, in which fin-shaped or nanowire-shaped silicon bodies are formed on a substrate and gates are formed on the surface of the silicon bodies.

[0004] Because these multi-gate transistors utilize three-dimensional channels, they are easily scalable. Furthermore, current control capability can be improved without increasing the gate length of the multi-gate transistor. Additionally, the short-channel effect (SCE), where the potential (or "potential") of the channel region is affected by the drain voltage, can be effectively suppressed. Summary of the Invention

[0005] This disclosure provides a semiconductor device that can simultaneously form a transistor (MBCFET) comprising multiple nanosheets. TM Multiple nanosheets of multi-bridge channel field-effect transistors (MLFETs) and fin patterns of fin field-effect transistors (FinFETs) are used to simplify the manufacturing process.

[0006] The embodiments disclosed herein are not limited to those mentioned above, and other embodiments not mentioned will be clearly understood by those skilled in the art through the following description.

[0007] According to some embodiments of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a substrate; a first active pattern extending on the substrate in a first direction; a second active pattern extending on the substrate in the first direction, the second active pattern being spaced apart from the first active pattern in a second direction intersecting the first direction; a plurality of nanosheets spaced apart from each other on the first active pattern in a third direction perpendicular to the first and second directions; a fin pattern spaced apart from the plurality of nanosheets in a second direction, the fin pattern comprising a first portion and a second portion, the first portion being spaced apart from the second active pattern in a third direction, the second portion contacting an upper surface of the first portion, wherein the width of the bottom surface of the second portion in the second direction is greater than the width of the upper surface of the first portion in the second direction; and a gate electrode extending on the first and second active patterns in the second direction, the gate electrode at least partially surrounding each of the plurality of nanosheets and the fin pattern.

[0008] According to some embodiments of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a substrate; a first active pattern extending on the substrate in a first direction; a second active pattern extending on the substrate in the first direction, the second active pattern being spaced apart from the first active pattern in a second direction intersecting the first direction; a plurality of nanosheets spaced apart from each other on the first active pattern in a third direction perpendicular to the first and second directions; a fin pattern spaced apart from the second active pattern in a third direction, the fin pattern being spaced apart from the plurality of nanosheets in a second direction; a gate electrode extending on the first and second active patterns in the second direction, the gate electrode at least partially surrounding each of the plurality of nanosheets and the fin pattern, at least a portion of the gate electrode being between an upper surface of the second active pattern and a bottom surface of the fin pattern; a first gate insulating layer between the gate electrode and the plurality of nanosheets; and a second gate insulating layer between the gate electrode and the fin pattern, wherein the thickness of the second gate insulating layer is greater than the thickness of the first gate insulating layer.

[0009] According to some embodiments of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a substrate; a first active pattern extending on the substrate in a first direction; a second active pattern extending on the substrate in the first direction, the second active pattern being spaced apart from the first active pattern in a second direction intersecting the first direction, wherein the upper surface of the second active pattern is lower than the upper surface of the first active pattern in a third direction perpendicular to the first and second directions, and the width of the second active pattern in the second direction is the same as the width of the first active pattern in the second direction; a plurality of nanosheets stacked on the first active pattern and spaced apart from each other in a third direction; a fin pattern spaced apart from the plurality of nanosheets in the second direction, the fin pattern comprising a first portion and a second portion, the first portion being spaced apart from the second active pattern in a third direction, the second portion contacting the upper surface of the first portion, wherein the width of the bottom surface of the second portion in the second direction is greater than the width of the upper surface of the first portion. The width of the surface in the second direction; a first gate electrode extending in the second direction on the first active pattern, the first gate electrode at least partially surrounding the plurality of nanosheets; a second gate electrode extending in the second direction on the second active pattern, the second gate electrode spaced apart from the first gate electrode in the second direction, the second gate electrode at least partially surrounding the fin pattern, and at least a portion of the second gate electrode between the upper surface of the second active pattern and the bottom surface of the fin pattern; a first gate insulating layer between the first gate electrode and the plurality of nanosheets; and a second gate insulating layer between the second gate electrode and the fin pattern, wherein the thickness of the second gate insulating layer is greater than the thickness of the first gate insulating layer, wherein the thickness of the second portion of the fin pattern in the third direction is the same as the thickness of the uppermost nanosheet among the plurality of nanosheets in the third direction, and wherein the upper surface of the fin pattern is on the same plane as the upper surface of the uppermost nanosheet among the plurality of nanosheets. Attached Figure Description

[0010] The above and other aspects and features of this disclosure will become clearer by referring to the accompanying drawings and describing in detail the exemplary embodiments of this disclosure.

[0011] Figure 1 This is a plan view illustrating a semiconductor device according to some exemplary embodiments of the present disclosure.

[0012] Figure 2 It is along Figure 1 A sectional view taken by line A-A'.

[0013] Figure 3 It is along Figure 1 The sectional view taken by line B-B'.

[0014] Figure 4 It is along Figure 1 A sectional view taken by line C-C'.

[0015] Figures 5 to 38 This is a diagram illustrating intermediate stages of a method for manufacturing a semiconductor device according to some example embodiments of the present disclosure.

[0016] Figure 39 This is a cross-sectional view illustrating a semiconductor device according to some example embodiments of the present disclosure.

[0017] Figure 40 This is a cross-sectional view illustrating a semiconductor device according to some other example embodiments of the present disclosure.

[0018] Figures 41 to 45 It is shown Figure 40 The diagram shows an intermediate stage of the manufacturing process of the semiconductor device.

[0019] Figure 46 This is a layout diagram illustrating a semiconductor device according to some other example embodiments of the present disclosure.

[0020] Figure 47 It is along Figure 46 A sectional view taken by line D-D'.

[0021] Figure 48 It is shown Figure 46 and Figure 47 The diagram shows an intermediate stage of the manufacturing process of the semiconductor device.

[0022] Figure 49 This is a cross-sectional view illustrating a semiconductor device according to other exemplary embodiments of the present disclosure.

[0023] Figures 50 to 52 It is shown Figure 49 The diagram shows an intermediate stage of the manufacturing process of the semiconductor device. Detailed Implementation

[0024] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings. In the drawings, the same reference numerals denote the same elements, and repeated descriptions thereof are omitted. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should be noted that aspects described with respect to one embodiment may be included in different embodiments, although they are not specifically described therewith. That is, features of all and / or any embodiment may be combined in any manner and / or combination.

[0025] In the following text, reference will be made to Figures 1 to 4 A semiconductor device according to some example embodiments of the present disclosure is described.

[0026] Figure 1These are layout diagrams or plan views used to explain semiconductor devices according to some example embodiments of this disclosure. Figure 2 It is along Figure 1 A sectional view taken by line A-A'. Figure 3 It is along Figure 1 The sectional view taken by line B-B'. Figure 4 It is along Figure 1 A sectional view taken by line C-C'.

[0027] Reference Figures 1 to 4 A semiconductor device according to some example embodiments of the present disclosure includes a substrate 100, a first active pattern 101 and a second active pattern 102, a field insulating layer 105, a plurality of nanosheets NW, a fin pattern 110, a gate electrode G1, a first gate spacer 121 and a second gate spacer 122, a first gate insulating layer 131 and a second gate insulating layer 132, a first cover pattern 141 and a second cover pattern 142, a first source / drain region SD1 and a second source / drain region SD2, a first etch stop layer 150, a first interlayer insulating layer 160, a gate cut GC, a first source / drain contact CA1 and a second source / drain contact CA2, a silicide layer SL, a first gate contact CB1 and a second gate contact CB2, a second etch stop layer 170, a second interlayer insulating layer 180, and a first via V1 and a second via V2.

[0028] The substrate 100 may be a silicon substrate or SOI (silicon-on-insulator). Optionally, the substrate 100 may include silicon germanium, SGOI (silicon-germanium-on-insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but this disclosure is not limited thereto. In the following, the first horizontal direction DR1 and the second horizontal direction DR2 may each be defined as a direction parallel to the upper surface of the substrate 100. The second horizontal direction DR2 may be defined as a direction different from the first horizontal direction DR1. The vertical direction DR3 may be defined as a direction perpendicular to each of the first horizontal direction DR1 and the second horizontal direction DR2. That is, the vertical direction DR3 may be defined as a direction perpendicular to the upper surface of the substrate 100.

[0029] Each of the first active pattern 101 and the second active pattern 102 may extend on the upper surface of the substrate 100 in a first horizontal direction DR1. The second active pattern 102 may be spaced apart from the first active pattern 101 in a second horizontal direction DR2. Each of the first active pattern 101 and the second active pattern 102 may protrude from the upper surface of the substrate 100 in a vertical direction DR3. For example, each of the first active pattern 101 and the second active pattern 102 may be a part of the substrate 100, or may include an epitaxial layer grown from the substrate 100. For example, the width of the second active pattern 102 in the second horizontal direction DR2 may be the same as the width of the first active pattern 101 in the second horizontal direction DR2. For example, the upper surface of the second active pattern 102 may be formed lower than the upper surface of the first active pattern 101.

[0030] A field insulating layer 105 may be disposed on the upper surface of the substrate 100. The field insulating layer 105 may at least partially surround the sidewalls of each of the first active pattern 101 and the second active pattern 102. For example, the upper surface of the first active pattern 101 may protrude beyond the upper surface of the field insulating layer 105 in the vertical direction DR3. Figure 4 In the diagram, the upper surface of the second active pattern 102 is shown as being formed on the same plane as the upper surface of the field insulating layer 105, but this disclosure is not limited thereto. The field insulating layer 105 may include, for example, an oxide layer, a nitride layer, an oxynitride layer, or a combination thereof.

[0031] Multiple nanosheets (NWs) can be disposed on the upper surface of the first active pattern 101. The multiple nanosheets (NWs) can be spaced apart from the upper surface of the first active pattern 101 in the vertical direction DR3. The multiple nanosheets (NWs) can include multiple nanosheets stacked on the first active pattern 101 in the vertical direction DR3 and spaced apart from each other. Figures 2 to 4 In this illustration, a plurality of nanosheets NWs are shown as comprising three nanosheets stacked and spaced apart from each other in a vertical direction DR3, but this is for illustrative purposes and the present disclosure is not limited thereto. In other exemplary embodiments, a plurality of nanosheets NWs may comprise four or more nanosheets stacked and spaced apart from each other in a vertical direction DR3. For example, a plurality of nanosheets NWs may comprise silicon (Si).

[0032] A fin-shaped pattern 110 may be disposed on the upper surface of the second active pattern 102. The fin-shaped pattern 110 may be spaced apart from the upper surface of the second active pattern 102 in the vertical direction DR3. The fin-shaped pattern 110 may be spaced apart from a plurality of nanosheets NW in the second horizontal direction DR2. The fin-shaped pattern 110 may include a first portion 111 and a second portion 112. The first portion 111 of the fin-shaped pattern 110 may be spaced apart from the upper surface of the second active pattern 102 in the vertical direction DR3. The second portion 112 of the fin-shaped pattern 110 may contact the upper surface of the first portion 111 of the fin-shaped pattern 110. For example, the first portion 111 and the second portion 112 of the fin-shaped pattern 110 may be integrally formed.

[0033] For example, the width W2 of the second portion 112 of the fin pattern 110 in the second horizontal direction DR2 may be greater than the width W1 of the first portion 111 of the fin pattern 110 in the second horizontal direction DR2. In other words, the width of the bottom surface of the second portion 112 of the fin pattern 110 in the second horizontal direction DR2 may be greater than the width of the upper surface of the first portion 111 of the fin pattern 110 in the second horizontal direction DR2. For example, the width W2 of the second portion 112 of the fin pattern 110 in the second horizontal direction DR2 may be the same as the width of the uppermost nanosheet among the plurality of nanosheets NW in the second horizontal direction DR2. For example, the width W1 of the first portion 111 of the fin pattern 110 in the second horizontal direction DR2 may be smaller than the width of the plurality of nanosheets NW in the second horizontal direction DR2.

[0034] For example, the thickness of the second portion 112 of the fin pattern 110 in the vertical direction DR3 may be the same as the thickness of the uppermost nanosheet among the plurality of nanosheets NW in the vertical direction DR3. For example, the upper surface of the fin pattern 110 may be formed on the same plane as the upper surface of the uppermost nanosheet among the plurality of nanosheets NW. In other words, the upper surface of the second portion 112 of the fin pattern 110 may be formed on the same plane as the upper surface of the uppermost nanosheet among the plurality of nanosheets NW. For example, the distance from the upper surface of the fin pattern 110 (e.g., the second portion 112 of the fin pattern 110) to the substrate 100 (e.g., one of the upper and bottom surfaces of the substrate 100) in the vertical direction DR3 may be the same as the distance from the upper surface of the uppermost nanosheet NW to the substrate 100 (e.g., said one of the upper and bottom surfaces of the substrate 100) in the vertical direction DR3. For example, the fin pattern 110 may comprise the same material as the plurality of nanosheets NW. In other words, the fin pattern 110 can be made of silicon (Si).

[0035] The gate electrode G1 may extend along a second horizontal direction DR2 on the field insulating layer 105 and the first active pattern 101 and the second active pattern 102. The gate electrode G1 may at least partially surround each of the plurality of nanosheets NW and the fin pattern 110. For example, the gate electrode G1 may include a first gate electrode G11 and a second gate electrode G12. The second gate electrode G12 may be spaced apart from the first gate electrode G11 along the second horizontal direction DR2. For example, the first gate electrode G11 may at least partially surround the plurality of nanosheets NW. The second gate electrode G12 may at least partially surround the fin pattern 110.

[0036] For example, at least a portion of the second gate electrode G12 may be disposed between the upper surface of the second active pattern 102 and the bottom surface of the fin pattern 110. That is, at least a portion of the second gate electrode G12 may be disposed between the upper surface of the second active pattern 102 and the bottom surface of the first portion 111 of the fin pattern 110. However, this disclosure is not limited thereto. In some other exemplary embodiments, the second gate electrode G12 may not be disposed between the upper surface of the second active pattern 102 and the bottom surface of the first portion 111 of the fin pattern 110. For example, the upper surface of the second gate electrode G12 may be formed on the same plane as the upper surface of the first gate electrode G11. For example, the distance of the upper surface of the second gate electrode G12 from the substrate 100 (e.g., one of the upper and bottom surfaces of the substrate 100) in the vertical direction DR3 may be the same as the distance of the upper surface of the first gate electrode G11 from the substrate 100 (e.g., said one of the upper and bottom surfaces of the substrate 100) in the vertical direction DR3.

[0037] For example, the first gate electrode G11 and the second gate electrode G12 may comprise the same material. For example, each of the first gate electrode G11 and the second gate electrode G12 may comprise titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (T... At least one of the following: aCN, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and / or combinations thereof. Each of the first gate electrode G11 and the second gate electrode G12 may include conductive metal oxides, conductive metal nitrides, etc., and may include oxide forms of the aforementioned materials.

[0038] The first gate spacer 121 may be disposed on the upper surface of the uppermost nanosheet among a plurality of nanosheets NW and on the upper surface of the field insulating layer 105 on two sidewalls of the first gate electrode G11 in the first horizontal direction DR1. The second gate spacer 122 may be disposed on the upper surface of the second portion 112 of the fin pattern 110 and on the upper surface of the field insulating layer 105 on two sidewalls of the second gate electrode G12 in the first horizontal direction DR1. For example, the second gate spacer 122 may be spaced apart from the first gate spacer 121 in the second horizontal direction DR2. For example, each of the first gate spacer 121 and the second gate spacer 122 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and / or combinations thereof. However, this disclosure is not limited thereto.

[0039] A first source / drain region SD1 may be disposed on two sidewalls of a plurality of nanosheets NW in the first horizontal direction DR1 on the first active pattern 101. For example, the first source / drain region SD1 may be in contact with the two sidewalls of the plurality of nanosheets NW in the first horizontal direction DR1. A second source / drain region SD2 may be disposed on two sidewalls of a fin pattern 110 in the first horizontal direction DR1 on the second active pattern 102. For example, the second source / drain region SD2 may be in contact with the two sidewalls of the fin pattern 110 in the first horizontal direction DR1. For example, the bottom surface of the second source / drain region SD2 may be formed lower than the bottom surface of the fin pattern 110. For example, the bottom surface of the second source / drain region SD2 may be formed on the same plane as the bottom surface of the first source / drain region SD1. For example, the upper surface of the second source / drain region SD2 may be formed on the same plane as the upper surface of the first source / drain region SD1. For example, the distance from the upper surface of the second source / drain region SD2 to the substrate 100 (e.g., one of the upper and lower surfaces of the substrate 100) in the vertical direction DR3 may be the same as the distance from the upper surface of the first source / drain region SD1 to the substrate 100 (e.g., one of the upper and lower surfaces of the substrate 100) in the vertical direction DR3.

[0040] A first gate insulating layer 131 may be disposed between the first gate electrode G11 and the first gate spacer 121. The first gate insulating layer 131 may be disposed between the first gate electrode G11 and the first active pattern 101. The first gate insulating layer 131 may be disposed between the first gate electrode G11 and the field insulating layer 105. The first gate insulating layer 131 may be disposed between the first gate electrode G11 and a plurality of nanosheets NW. The first gate insulating layer 131 may be disposed between the first gate electrode G11 and the first source / drain region SD1. A second gate insulating layer 132 may be disposed between the second gate electrode G12 and the second gate spacer 122. The second gate insulating layer 132 may be disposed between the second gate electrode G12 and the second active pattern 102. The second gate insulating layer 132 may be disposed between the second gate electrode G12 and the field insulating layer 105. The second gate insulating layer 132 may be disposed between the second gate electrode G12 and the fin pattern 110. The second gate insulating layer 132 may be disposed between the second gate electrode G12 and the second source / drain region SD2.

[0041] For example, at least a portion of the bottom surface of the second portion 112 of the fin pattern 110 may contact the second gate insulating layer 132. For example, the thickness t2 of the second gate insulating layer 132 may be greater than the thickness t1 of the first gate insulating layer 131. For example, each of the first gate insulating layer 131 and the second gate insulating layer 132 may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k dielectric material having a dielectric constant higher than that of silicon oxide. The high-k dielectric material may include, for example, one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0042] In some example embodiments, the semiconductor device may include an NC (negative capacitance) FET utilizing a negative capacitor. For example, each of the first gate insulating layer 131 and the second gate insulating layer 132 may include a ferroelectric material layer exhibiting ferroelectric properties and a paraelectric material layer exhibiting paraelectric properties.

[0043] Ferroelectric material layers can have negative capacitance, while paraelectric material layers can have positive capacitance. For example, when two or more capacitors are connected in series and each of their capacitances has a positive value, the total capacitance is smaller than the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance can be positive and greater than the absolute value of each individual capacitor.

[0044] When a ferroelectric material layer with negative capacitance and a paraelectric material layer with positive capacitance are connected in series, the total capacitance of the series-connected ferroelectric and paraelectric material layers can be increased. By utilizing the increase in total capacitance, a transistor including a ferroelectric material layer can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0045] The ferroelectric material layer may possess ferroelectric properties. The ferroelectric material layer may include at least one of, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and / or lead zirconium titanium oxide. As another example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. In yet another example, hafnium zirconium oxide may be a compound of hafnium (Hf) and zirconium (Zr) with oxygen (O).

[0046] The ferroelectric material layer may also include dopants. For example, dopants may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and / or tin (Sn). The type of dopant included in the ferroelectric material layer may vary depending on the ferroelectric material included in the ferroelectric material layer.

[0047] When the ferroelectric material layer includes hafnium oxide, the dopants included in the ferroelectric material layer may include at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al) and / or yttrium (Y).

[0048] When the dopant is aluminum (Al), the ferroelectric material layer may include 3 at% (atomic%) to 8 at% aluminum. Here, the dopant ratio can be the ratio of aluminum to the sum of hafnium and aluminum.

[0049] When the dopant is silicon (Si), the ferroelectric material layer may include 2 at% to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material layer may include 2 at% to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material layer may include 1 at% to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material layer may include 50 at% to 80 at% zirconium.

[0050] The paraelectric material layer may have paraelectric properties. The paraelectric material layer may include at least one of, for example, silicon oxide and a high-k metal oxide. The metal oxide included in the paraelectric material layer may include, for example, at least one of, hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0051] The ferroelectric material layer and the paraelectric material layer may contain the same material. While the ferroelectric material layer has ferroelectric properties, the paraelectric material layer may not have ferroelectric properties. For example, when both the ferroelectric and paraelectric material layers contain hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material layer is different from the crystal structure of the hafnium oxide included in the paraelectric material layer.

[0052] The ferroelectric material layer can have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material layer can be, for example, from 0.5 nm to 10 nm, but is not limited to this. Since each ferroelectric material can have a different critical thickness for exhibiting ferroelectric properties, the thickness of the ferroelectric material layer can vary depending on the specific ferroelectric material.

[0053] For example, each of the first gate insulating layer 131 and the second gate insulating layer 132 may include a single ferroelectric material layer. In another example, each of the first gate insulating layer 131 and the second gate insulating layer 132 may include a plurality of ferroelectric material layers spaced apart from each other. Each of the first gate insulating layer 131 and the second gate insulating layer 132 may have a stacked layer structure in which a plurality of ferroelectric material layers are alternately stacked with a plurality of paraelectric material layers.

[0054] The first etch stop layer 150 may be disposed on the sidewall of each of the first gate spacer 121 and the second gate spacer 122 in the first horizontal direction DR1. The first etch stop layer 150 may be disposed on the upper surface of each of the first source / drain region SD1 and the second source / drain region SD2. Although not shown, the first etch stop layer 150 may be disposed on the upper surface of the field insulating layer 105. Furthermore, although not shown, the first etch stop layer 150 may be disposed on both sidewalls of each of the first source / drain region SD1 and the second source / drain region SD2 in the second horizontal direction DR2. For example, the first etch stop layer 150 may be conformally formed. For example, the first etch stop layer 150 may include at least one of alumina, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric material.

[0055] The first overlay pattern 141 may extend on each of the first gate spacer 121, the first gate insulating layer 131, the first gate electrode G11, and the first etch stop layer 150 in the second horizontal direction DR2. The second overlay pattern 142 may extend on each of the second gate spacer 122, the second gate insulating layer 132, the second gate electrode G12, and the first etch stop layer 150 in the second horizontal direction DR2. For example, the second overlay pattern 142 may be spaced apart from the first overlay pattern 141 in the second horizontal direction DR2. For example, each of the first overlay pattern 141 and the second overlay pattern 142 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and / or combinations thereof. However, this disclosure is not limited thereto.

[0056] A first interlayer insulating layer 160 may be disposed on the first etch stop layer 150. The first interlayer insulating layer 160 may at least partially surround the sidewalls of each of the first cover pattern 141 and the second cover pattern 142. For example, the upper surface of the first interlayer insulating layer 160 may be formed on the same plane as the upper surface of each of the first cover pattern 141 and the second cover pattern 142. For example, the first interlayer insulating layer 160 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric material. Low-k dielectric materials may include, for example, tetraethyl orthosilicate (FTEOS), silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditert-butoxysiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ (Tonen SilaZen), FSG (fluorinated silicate glass), nanofoams (such as polyimide or polypropylene oxide), CDO (carbon-doped silicon oxide), OSG (organosilicon glass), SiLK, amorphous (non-crystalline) fluorinated carbon, silica aerogel, silica dry gel, mesoporous silica, or combinations thereof, but this disclosure is not limited thereto.

[0057] The gate notch GC may extend in a first horizontal direction DR1 between the first gate electrode G11 and the second gate electrode G12. For example, the gate notch GC may penetrate the gate electrode G1 in a vertical direction DR3. For example, the gate notch GC may extend in a vertical direction DR3 from inside the field insulating layer 105. That is, the bottom surface of the gate notch GC may be formed between the bottom surface and the top surface of the field insulating layer 105. For example, the bottom surface of the gate notch GC may be formed to be higher than the bottom surface of the field insulating layer 105 and lower than the top surface of the field insulating layer 105. For example, the top surface of the gate notch GC may be formed on the same plane as the top surface of each of the first cover pattern 141 and the second cover pattern 142.

[0058] For example, the first gate electrode G11 and the second gate electrode G12 can be separated on the second horizontal direction DR2 via a gate notch GC. For example, the first gate spacer 121 and the second gate spacer 122 can be separated on the second horizontal direction DR2 via a gate notch GC. For example, the first gate insulating layer 131 and the second gate insulating layer 132 can be separated on the second horizontal direction DR2 via a gate notch GC. For example, the first cover pattern 141 and the second cover pattern 142 can be separated on the second horizontal direction DR2 via a gate notch GC. For example, the gate notch GC may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0059] The first source / drain contact CA1 may be disposed on a first side of the gate electrode G1 in the first horizontal direction DR1. The first source / drain contact CA1 may penetrate the first interlayer insulating layer 160 and the first etch stop layer 150 in the vertical direction DR3, and extend into the interior of the first source / drain region SD1 and the second source / drain region SD2 disposed on the first side of the gate electrode G1. For example, the first source / drain contact CA1 may be electrically connected to each of the first source / drain region SD1 and the second source / drain region SD2 disposed on the first side of the gate electrode G1. However, this disclosure is not limited thereto. In some other exemplary embodiments, the first source / drain contact CA1 connected to the first source / drain region SD1 and the first source / drain contact CA1 connected to the second source / drain region SD2 may be separated in the second horizontal direction DR2.

[0060] The second source / drain contact CA2 may be disposed on the second side of the gate electrode G1, which is opposite to the first side of the gate electrode G1 in the first horizontal direction DR1. The second source / drain contact CA2 may penetrate the first interlayer insulating layer 160 and the first etch stop layer 150 in the vertical direction DR3, and extend into the interior of the first source / drain region SD1 and the second source / drain region SD2 disposed on the second side of the gate electrode G1. For example, the second source / drain contact CA2 may be electrically connected to each of the first source / drain region SD1 and the second source / drain region SD2 disposed on the second side of the gate electrode G1. However, this disclosure is not limited thereto. In some other exemplary embodiments, the second source / drain contact CA2 connected to the first source / drain region SD1 and the second source / drain contact CA2 connected to the second source / drain region SD2 may be separated in the second horizontal direction DR2.

[0061] For example, the upper surface of each of the first source / drain contact CA1 and the second source / drain contact CA2 may be formed on the same plane as the upper surface of the first interlayer insulating layer 160. Each of the first source / drain contact CA1 and the second source / drain contact CA2 may include a conductive material. A silicide layer SL may be disposed along the interface between the first source / drain contact CA1 and each of the first source / drain region SD1 and the second source / drain region SD2. Furthermore, the silicide layer SL may be disposed along the interface between the second source / drain contact CA2 and each of the first source / drain region SD1 and the second source / drain region SD2. For example, the silicide layer SL may include a metal silicide material. The first gate contact CB1 may penetrate the first overlay pattern 141 in the vertical direction DR3 to connect to the first gate electrode G11. The second gate contact CB2 may penetrate the second overlay pattern 142 in the vertical direction DR3 to connect to the second gate electrode G12. Each of the first gate contact CB1 and the second gate contact CB2 may include a conductive material.

[0062] A second etch stop layer 170 may be disposed on the upper surface of each of the first interlayer insulating layer 160, the first cover pattern 141 and the second cover pattern 142, the first source / drain contact CA1 and the second source / drain contact CA2, the first gate contact CB1 and the second gate contact CB2, and the gate notch GC. For example, the second etch stop layer 170 may be conformally formed. Figures 2 to 4 In this embodiment, the second etch stop layer 170 is shown as a single layer, but this disclosure is not limited thereto. In some other example embodiments, the second etch stop layer 170 may be formed as multiple layers. For example, the second etch stop layer 170 may include at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric material. A second interlayer insulating layer 180 may be disposed on the second etch stop layer 170. For example, the second interlayer insulating layer 180 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material.

[0063] A first via V1 may penetrate the second interlayer insulating layer 180 and the second etch stop layer 170 in the vertical direction DR3 to connect to the first gate contact CB1. A second via V2 may penetrate the second interlayer insulating layer 180 and the second etch stop layer 170 in the vertical direction DR3 to connect to the second gate contact CB2. Each of the first via V1 and the second via V2 may include a conductive material.

[0064] In the following text, refer to Figures 2 to 38 The present disclosure will describe a method for manufacturing a semiconductor device according to some example embodiments.

[0065] Figures 5 to 38 This is an intermediate stage diagram used to explain a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure.

[0066] Reference Figures 5 to 7 A stacked structure 10 can be formed on a substrate 100. The stacked structure 10 may include a first sacrificial layer 11 and a first semiconductor layer 12 alternately stacked on the substrate 100. For example, the first sacrificial layer 11 may be formed at the bottommost portion of the stacked structure 10, and the first semiconductor layer 12 may be formed at the topmost portion of the stacked structure 10. For example, the first sacrificial layer 11 may include silicon germanium (SiGe). For example, the first semiconductor layer 12 may include silicon (Si). Subsequently, a first mask pattern M1 may be formed on the upper surface of the stacked structure 10.

[0067] Reference Figure 8 and Figure 9 Using a first mask pattern M1 as a mask, a fin trench FT1 can be formed inside the stacked structure 10 by etching. For example, the fin trench FT1 can extend into the interior of the substrate 100. That is, the bottom surface of the fin trench FT1 can be formed lower than the bottom surface of the stacked structure 10.

[0068] Reference Figures 10 to 12 The first mask pattern M1 can be removed (see...) Figure 9 Subsequently, a second sacrificial layer 21 and a second semiconductor layer 22 may be sequentially formed along the upper surface of the stacked structure 10 and the bottom surface and sidewalls of the fin trench FT1. For example, each of the second sacrificial layer 21 and the second semiconductor layer 22 may be formed conformally. For example, the thickness of the second sacrificial layer 21 may be the same as the thickness of the first sacrificial layer 11. Furthermore, the thickness of the second semiconductor layer 22 may be the same as the thickness of the first semiconductor layer 12. However, this disclosure is not limited thereto.

[0069] For example, the fin trench FT1 may be completely filled by the second sacrificial layer 21 and the second semiconductor layer 22. For example, the upper surface of the second semiconductor layer 22 formed on the fin trench FT1 may be formed on the same plane as the upper surface of the second semiconductor layer 22 formed on the stacked structure 10. However, this disclosure is not limited thereto. In some other example embodiments, at least a portion of the upper surface of the second semiconductor layer 22 formed on the fin trench FT1 may be formed convexly toward the substrate 100. For example, the second sacrificial layer 21 may comprise silicon germanium (SiGe), and the second semiconductor layer 22 may comprise silicon (Si).

[0070] Reference Figures 13 to 15A second mask pattern M2 can be formed on the second semiconductor layer 22. For example, the second mask pattern M2 can be formed at the portion overlapping each of the first active pattern 101 and the second active pattern 102, which will be described later, along the vertical direction DR3. Subsequently, using the second mask pattern M2 as a mask, the stacked structure 10, the second sacrificial layer 21, and the second semiconductor layer 22 can each be etched. While etching each of the stacked structure 10, the second sacrificial layer 21, and the second semiconductor layer 22, a portion of the substrate 100 can also be etched.

[0071] Through this etching process, a first active pattern 101 can be defined below the stacked structure 10 on the upper surface of the substrate 100, and a second active pattern 102 can be defined below the second sacrificial layer 21 and the second semiconductor layer 22. For example, each of the first active pattern 101 and the second active pattern 102 can extend in a first horizontal direction DR1. The second active pattern 102 can be spaced apart from the first active pattern 101 in a second horizontal direction DR2. For example, the upper surface of the second active pattern 102 can be formed lower than the upper surface of the first active pattern 101.

[0072] Reference Figure 16 The second mask pattern M2 can be removed (see...) Figures 13 to 15 Subsequently, a field insulating layer 105 may be formed on the upper surface of the substrate 100. The field insulating layer 105 may at least partially surround the sidewalls of each of the first active pattern 101 and the second active pattern 102. Figure 16 In the illustration, the upper surface of the field insulating layer 105 is shown formed on the same plane as the upper surface of the second active pattern 102, but this disclosure is not limited thereto. In some other example embodiments, the upper surface of the field insulating layer 105 may be formed lower than the upper surface of the second active pattern 102. Subsequently, a pad oxide layer 30 may be formed to cover the upper surface of the field insulating layer 105, the exposed sidewalls of the first active pattern 101, the sidewalls of the stacked structure 10, the sidewalls of the second sacrificial layer 21, and the sidewalls and upper surface of the second semiconductor layer 22. For example, the pad oxide layer 30 may be conformally formed. For example, the pad oxide layer 30 may include silicon oxide (SiO2).

[0073] Reference Figures 17 to 19 A dummy gate DG and a dummy overlay pattern DC extending in the second horizontal direction DR2 can be formed on the pad oxide layer 30 on the second semiconductor layer 22 and the field insulating layer 105. The dummy overlay pattern DC can be disposed on the dummy gate DG. While the dummy gate DG and the dummy overlay pattern DC are being formed, the remaining portion of the pad oxide layer 30, except for the portion that overlaps with the dummy gate DG in the vertical direction DR3 on the substrate 100, can be removed.

[0074] Subsequently, a spacer material layer SM can be formed to cover the sidewalls of the dummy gate DG, the sidewalls and top surface of each of the dummy cover patterns DC, the exposed sidewalls of the stacked structure 10, the exposed sidewalls of the second sacrificial layer 21, the exposed sidewalls and top surface of the second semiconductor layer 22, and the top surface of the field insulating layer 105. For example, the spacer material layer SM can be formed conformally. The spacer material layer SM may include at least one of, for example, silicon nitride (SiN), silicon carbonitride oxynitride (SiOCN), silicon boron carbonitride (SiBCN), silicon carbonitride (SiCN), silicon oxynitride (SiON), and / or combinations thereof.

[0075] Reference Figure 20 and Figure 21 Using a dummy gate (DG) and a dummy overlay pattern (DC) as a mask, the stacked structure 10 can be etched (see...). Figures 17 to 19 ), second sacrificial layer 21 and second semiconductor layer 22 (see Figures 17 to 19 The first source / drain trench ST1 and the second source / drain trench ST2 are formed, respectively. For example, the first source / drain trench ST1 may be formed on the first active pattern 101. The second source / drain trench ST2 may be formed on the second active pattern 102. While each of the first source / drain trench ST1 and the second source / drain trench ST2 is being formed, the spacer material layer SM formed on the upper surface of the dummy overlay pattern DC (see...) can be etched. Figures 17 to 19 ) and a portion of each of the dummy overlay patterns in DC.

[0076] For example, after forming the first source / drain trench ST1 and the second source / drain trench ST2 respectively, a spacer material layer SM is retained on the sidewalls of each of the dummy overlay pattern DC and the dummy gate DG (see Figures 17 to 19 The first gate spacer 121 and the second gate spacer 122 may be defined. For example, after forming the first source / drain trench ST1, a first semiconductor layer 12 (see [reference]) is retained on the first active pattern 101 below the dummy gate DG. Figure 17 ) and the second semiconductor layer 22 (see Figure 17 Each of the nanosheets (NW) can be defined as a plurality of nanosheets (NW). Furthermore, after forming the second source / drain trench ST2, a second semiconductor layer 22 (see [reference]) is retained on the second active pattern 102 below the dummy gate DG. Figure 18 It can be defined as a fin-shaped pattern 110.

[0077] Reference Figure 22 and Figure 23 It can be done in the first source / drain trench ST1 (see Figure 20A first source / drain region SD1 is formed inside the nanosheet NW, the first sacrificial layer 11, and the second sacrificial layer 21. For example, the first source / drain region SD1 may contact the two sidewalls of each of the plurality of nanosheets NW, the first sacrificial layer 11, and the second sacrificial layer 21 in the first horizontal direction DR1. Furthermore, a second source / drain trench ST2 (see...) may be formed... Figure 21 A second source / drain region SD2 is formed inside. For example, the second source / drain region SD2 may contact the two sidewalls of each of the fin pattern 110 and the second sacrificial layer 21 in the first horizontal direction DR1.

[0078] Subsequently, a first etch stop layer 150 may be formed on the surface of each of the first source / drain regions SD1 and the second source / drain regions SD2, and on the sidewalls of each of the first gate spacers 121 and the second gate spacers 122. Although not shown, the first etch stop layer 150 may also be formed on the upper surface of the field insulating layer 105. For example, the first etch stop layer 150 may be formed conformally. Subsequently, a first interlayer insulating layer 160 may be formed on the first etch stop layer 150. Subsequently, the upper surface of the dummy gate DG may be exposed by a planarization process.

[0079] Reference Figures 24 to 26 The dummy gate DG (see Figure 22 and Figure 23 ), Pad oxide layer 30 (see) Figure 22 and Figure 23 ), First Sacrificial Layer 11 (see Figure 22 and Figure 23 ) and the second sacrificial layer 21 (see Figure 22 and Figure 23 Each is etched individually. For example, the dummy gate DG (see...) Figure 22 and Figure 23 ), Pad oxide layer 30 (see) Figure 22 and Figure 23 ), First Sacrificial Layer 11 (see Figure 22 and Figure 23 ) and the second sacrificial layer 21 (see Figure 22 and Figure 23 Each etched portion can be defined as the first gate trench GT1.

[0080] Now refer to Figures 27 to 29 It can be along the first gate trench GT1 (see Figure 24 and Figure 25The exposed surface inside forms a first liner 40. For example, the first liner 40 may be formed conformally. For example, the first liner 40 may be formed on the upper surface of each of the first gate spacer 121 and the second gate spacer 122, the first etch stop layer 150, and the first interlayer insulating layer 160. For example, the first liner 40 may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k dielectric material having a dielectric constant greater than that of silicon oxide.

[0081] Subsequently, a protective layer 50 may be formed on the first substrate 40 in the region adjacent to the second active pattern 102. For example, the protective layer 50 may at least partially surround the fin pattern 110. For example, the protective layer 50 may include a spin-on hard mask (SOH). After the protective layer 50 is formed, the exposed area on the first substrate 40 may be defined as the second gate trench GT2.

[0082] Reference Figure 30 and Figure 31 The first liner 40 can be etched in the second gate trench GT2 (see Figure 27 The exposed portion of the first liner 40. For example, another portion of the portion in which the protective layer 50 is formed may be left. For example, after etching a portion of the first liner 40, the exposed area may be defined as the third gate trench GT3.

[0083] Reference Figures 32 to 34 The protective layer 50 can be removed (see...) Figure 31 Therefore, the first liner 40 can be exposed (see...). Figure 31 Subsequently, it can be applied in the third gate trench GT3 (see...). Figure 31 On the exposed surfaces inside and in the first liner 40 (see) Figure 31 A second liner 60 is formed on the first gate spacer 121 and the second gate spacer 122, the first etch stop layer 150, and the first interlayer insulating layer 160. For example, the second liner 60 may be formed on the upper surface of each of the first gate spacer 121 and the second gate spacer 122, the first etch stop layer 150, and the first interlayer insulating layer 160. For example, the second liner 60 may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k dielectric material having a dielectric constant greater than that of silicon oxide.

[0084] For example, after the second liner 60 is formed, the first liner 40 (see...) is included. Figure 31 ) and formed in the first liner 40 (see Figure 31 The second liner 60 on the gate can be defined as a third liner 70. For example, the thickness of the third liner 70 can be greater than the thickness of the second liner 60. For example, after the second liner 60 and the third liner 70 are formed, the exposed area on each of the second liner 60 and the third liner 70 can be defined as a fourth gate trench GT4.

[0085] In some other example embodiments, the first gate insulating layer 131 and the second gate insulating layer 132 may be formed by the following manufacturing process: forming the second gate insulating layer 132 on the surface of each of the plurality of nanosheets NW and the fin pattern 110; covering the second gate insulating layer 132 formed on the surface of the fin pattern 110 with a protective layer; and etching a portion of the second gate insulating layer 132 formed on the surface of the plurality of nanosheets NW to form the first gate insulating layer 131.

[0086] Reference Figures 35 to 37 In the fourth gate trench GT4 (see Figure 32 and Figure 33 Inside, in the second liner 60 (see) Figure 32 and Figure 34 ) and the third liner 70 (see Figure 33 and Figure 34 A gate material layer GM is formed on each of the plurality of nanosheets NW and fin patterns 110. For example, the gate material layer GM may extend on the second horizontal direction DR2. For example, the gate material layer GM may at least partially surround each of the plurality of nanosheets NW and fin patterns 110. The gate material layer GM may comprise the same material as the gate electrode G1. After the gate material layer GM is formed, the second substrate 60 (see Figure 32 and Figure 34 ) can be defined as a first gate insulating layer 131, and a third liner 70 (see Figure 33 and Figure 34 It can be defined as a second gate insulating layer 132.

[0087] Subsequently, a cover material layer 140 may be formed on the upper surface of each of the first etch stop layer 150, the first gate spacer 121 and the second gate spacer 122, the first gate insulating layer 131 and the second gate insulating layer 132, and the gate material layer GM. For example, the cover material layer 140 may extend in the second horizontal direction DR2. The cover material layer 140 may include the same material as each of the first cover pattern 141 and the second cover pattern 142.

[0088] Reference Figure 38 This can form a gate notch GC, which penetrates the overlay material layer 140 in the vertical direction DR3 (see...). Figure 37 ), gate material layer GM (see Figure 37 The gate notch GC extends into the interior of the field insulating layer 105, including each of the first gate insulating layer 131 and the second gate insulating layer 132. The gate notch GC can cover the material layer 140 (see...). Figure 37 The gate is separated into a first cover pattern 141 and a second cover pattern 142. Furthermore, the gate notch GC can separate the gate material layer GM (see...) Figure 37It is separated into a first gate electrode G11 and a second gate electrode G12.

[0089] Reference Figures 2 to 4 The first gate contact CB1 and the second gate contact CB2, the first source / drain contact CA1 and the second source / drain contact CA2, the silicide layer SL, the second etch stop layer 170, the second interlayer insulating layer 180, and the first via V1 and the second via V2 can each be formed. Through this manufacturing process, a product can be manufactured. Figures 2 to 4 The semiconductor device shown.

[0090] A method for manufacturing a semiconductor device according to some embodiments of the present disclosure can simultaneously form a transistor (MBCFET) comprising multiple nanosheets (NW). TM The manufacturing process is simplified by using multiple nanosheets (NWs) of a multi-bridge channel field-effect transistor (Multi-Channel Field-Effect Transistor) and a fin pattern 110 of a FinFET. In semiconductor devices manufactured by the above-described manufacturing method according to some embodiments of the present disclosure, the fin pattern 110 may be spaced apart from the multiple nanosheets (NWs) in a second horizontal direction DR2 and may be spaced apart from the upper surface of the second active pattern 102 in a vertical direction DR3. Furthermore, in semiconductor devices according to some exemplary embodiments of the present disclosure, the fin pattern 110 may include a first portion 111 spaced apart from the upper surface of the second active pattern 102 in the vertical direction DR3 and a second portion 112 contacting the upper surface of the first portion 111, and the width W2 of the second portion 112 of the fin pattern 110 in the second horizontal direction DR2 may be greater than the width W1 of the first portion 111 of the fin pattern 110 in the second horizontal direction DR2.

[0091] In the following text, reference will be made to Figure 39 This description includes several other exemplary embodiments of a semiconductor device according to this disclosure. The explanation will focus on... Figures 1 to 4 The differences in the semiconductor devices shown.

[0092] Figure 39 This is a cross-sectional view used to explain some other example embodiments of a semiconductor device according to this disclosure.

[0093] Reference Figure 39 In some other example embodiments of the semiconductor device according to this disclosure, a plurality of nanosheets NW and fin pattern 110 may be at least partially surrounded by a single gate electrode G2.

[0094] For example, overlay pattern 241 may extend on gate electrode G2 in the second horizontal direction DR2. Gate contact CB21 may penetrate overlay pattern 241 in the vertical direction DR3 to connect to gate electrode G2. Via V21 may penetrate the second interlayer insulating layer 180 and the second etch stop layer 170 in the vertical direction DR3 to connect to gate contact CB21. For example, the first gate insulating layer 131 and the second gate insulating layer 132 may have a step difference on the upper surface of field insulating layer 105.

[0095] In the following text, reference will be made to Figure 40 The description focuses on semiconductor devices according to other exemplary embodiments of this disclosure. Figures 1 to 4 The differences in the semiconductor devices shown.

[0096] Figure 40 This is a cross-sectional view used to explain a semiconductor device according to several other exemplary embodiments of this disclosure.

[0097] Reference Figure 40 In a semiconductor device according to some other example embodiments of the present disclosure, the upper surface 310a of the fin pattern 310 may be formed at a height higher than the upper surface NWa of the uppermost nanosheet among a plurality of nanosheets NW.

[0098] For example, the fin pattern 310 may include a first portion 311 spaced apart from the upper surface of the second active pattern 102 in the vertical direction DR3 and a second portion 312 in contact with the upper surface of the first portion 311. For example, the upper surface 310a of the second portion 312 of the fin pattern 310 may be formed higher than the upper surface NWa of the uppermost nanosheet among the plurality of nanosheets NW.

[0099] In the following text, reference will be made to Figures 40 to 45 describe Figure 40 The semiconductor device shown is manufactured using a method described in the illustration. The description will focus on... Figures 5 to 38 The differences in the manufacturing methods of the semiconductor devices shown.

[0100] Figures 41 to 45 It is used for explanation Figure 40 The diagram shows an intermediate stage of the manufacturing process of the semiconductor device.

[0101] Reference Figure 41 A stacked structure 10 may be formed on a substrate 100. The stacked structure 10 may include a first sacrificial layer 11 and a first semiconductor layer 12 alternately stacked on the substrate 100. For example, the first sacrificial layer 11 may be formed at the bottommost portion of the stacked structure 10, and the first semiconductor layer 12 may be formed at the topmost portion of the stacked structure 10. For example, the first sacrificial layer 11 may include silicon germanium (SiGe). For example, the first semiconductor layer 12 may include silicon (Si).

[0102] Subsequently, a first mask pattern M31 can be formed on the upper surface of the stacked structure 10. Then, using the first mask pattern M31 as a mask, the stacked structure 10 can be etched to form a fin trench FT31 inside the stacked structure 10. For example, the fin trench FT31 can extend into the interior of the substrate 100. That is, the bottom surface of the fin trench FT31 can be formed lower than the bottom surface of the stacked structure.

[0103] Reference Figure 42 A third sacrificial layer 80 may be formed on the bottom surface and sidewalls of the fin trench FT31. For example, the third sacrificial layer 80 may also be formed on a portion of the sidewalls of the first mask pattern M31. For example, the uppermost surface of the third sacrificial layer 80 may be formed between the bottom surface and the upper surface of the first mask pattern M31. For example, the uppermost surface of the third sacrificial layer 80 may be formed higher than the upper surface of the stacked structure 10. For example, the third sacrificial layer 80 may be formed conformally. For example, the third sacrificial layer 80 may include the same material as the first sacrificial layer 11. That is, the third sacrificial layer 80 may include silicon germanium (SiGe).

[0104] Reference Figure 43 The first mask pattern M31 can be removed (see...) Figure 42 Therefore, the upper surface of the stacked structure 10 can be exposed.

[0105] Reference Figure 44 The second sacrificial layer 21 and the second semiconductor layer 22 can be sequentially formed along the upper surface of the stacked structure 10 and the sidewalls and upper surface of the third sacrificial layer 80. For example, each of the second sacrificial layer 21 and the second semiconductor layer 22 can be formed conformally. For example, the fin trench FT31 can be completely filled by the second sacrificial layer 21 and the second semiconductor layer 22. For example, the upper surface of the second sacrificial layer 21 formed on the fin trench FT31 can be formed higher than the upper surface of the second sacrificial layer 21 formed on the stacked structure 10. Furthermore, the upper surface of the second semiconductor layer 22 formed on the fin trench FT31 can be formed higher than the upper surface of the second semiconductor layer 22 formed on the stacked structure 10. For example, the second sacrificial layer 21 may include silicon germanium (SiGe), and the second semiconductor layer 22 may include silicon (Si).

[0106] Reference Figure 45A second mask pattern M32 can be formed on the second semiconductor layer 22. Subsequently, using the second mask pattern M32 as a mask, each of the stacked structure 10, the second sacrificial layer 21, the second semiconductor layer 22, and the third sacrificial layer 80 can be etched. While the stacked structure 10, the second sacrificial layer 21, the second semiconductor layer 22, and the third sacrificial layer 80 are being etched, a portion of the substrate 100 can also be etched. Through this etching process, the first active pattern 101 can be defined below the stacked structure 10 on the upper surface of the substrate 100, and the second active pattern 102 can be defined below the third sacrificial layer 80.

[0107] Reference Figure 40 In execution Figures 16 to 38 Following the manufacturing process shown, the first gate contact CB1 and the second gate contact CB2, the second etch stop layer 170, the second interlayer insulating layer 180, and the first via V1 and the second via V2 can each be formed. Through this manufacturing process, a product can be manufactured. Figure 40 The semiconductor device shown.

[0108] In the following text, reference will be made to Figure 46 and Figure 47 This description describes a semiconductor device according to several other exemplary embodiments of the present disclosure. The description will focus on... Figures 1 to 4 The differences in the semiconductor devices shown.

[0109] Figure 46 This is a layout diagram used to explain a semiconductor device according to several other exemplary embodiments of this disclosure. Figure 47 It is along Figure 46 A sectional view taken by line D-D'.

[0110] Reference Figure 46 and Figure 47 In a semiconductor device according to several other exemplary embodiments of the present disclosure, the fin pattern 410 may include a first portion 411, a second portion 412, a third portion 413, and a fourth portion 414.

[0111] For example, the width of the second active pattern 402 in the second horizontal direction DR2 may be greater than the width of the first active pattern 101 in the second horizontal direction DR2. For example, the second active pattern 402 may include a first portion 402_1, a second portion 402_2, and a third portion 402_3. The first portion 402_1 of the second active pattern 402 may be disposed within a portion of the field insulating layer 105 or between portions of the field insulating layer 105. The width of the first portion 402_1 of the second active pattern 402 in the second horizontal direction DR2 may be greater than the width of the first active pattern 101 in the second horizontal direction DR2. Each of the second portion 402_2 and the third portion 402_3 of the second active pattern 402 may protrude from the upper surface of the first portion 402_1 of the second active pattern 402 in the vertical direction DR3. The third portion 402_3 of the second active pattern 402 may be spaced apart from the second portion 402_2 of the second active pattern 402 in the second horizontal direction DR2. For example, the upper surface of each of the second portion 402_2 and the third portion 402_3 of the second active pattern 402 may be formed on the same plane as the upper surface of the first active pattern 101.

[0112] For example, the first portion 411 of the fin pattern 410 may be spaced apart from the upper surface of the first portion 402_1 of the second active pattern 402 in the vertical direction DR3. For example, the first portion 411 of the fin pattern 410 may be disposed between the second portion 402_2 and the third portion 402_3 of the second active pattern 402. The second portion 412 of the fin pattern 410 may contact the upper surface of the first portion 411 of the fin pattern 410. For example, the first portion 411 and the second portion 412 of the fin pattern 410 may be integrally formed. For example, the width of the second portion 412 of the fin pattern 410 in the second horizontal direction DR2 may be greater than the width of the plurality of nanosheets NW in the second horizontal direction DR2.

[0113] For example, the third portion 413 of the fin pattern 410 may be disposed on the two sidewalls of the first portion 411 of the fin pattern 410 in the second horizontal direction DR2. The third portion 413 of the fin pattern 410 may be spaced apart from the two sidewalls of the first portion 411 of the fin pattern 410 in the second horizontal direction DR2. The third portion 413 of the fin pattern 410 may be disposed between the upper surface of the second portion 402_2 of the second active pattern 402 and the bottom surface of the second portion 412 of the fin pattern 410. Furthermore, the third portion 413 of the fin pattern 410 may be disposed between the upper surface of the third portion 402_3 of the second active pattern 402 and the bottom surface of the second portion 412 of the fin pattern 410. The third portion 413 of the fin pattern 410 may be spaced apart from each of the second portions 402_2 and the third portion 402_3 of the second active pattern 402 in the vertical direction DR3.

[0114] For example, the fourth portion 414 of the fin pattern 410 may be disposed on the two sidewalls of the first portion 411 of the fin pattern 410 in the second horizontal direction DR2. The fourth portion 414 of the fin pattern 410 may be spaced apart from the two sidewalls of the first portion 411 of the fin pattern 410 in the second horizontal direction DR2. The fourth portion 414 of the fin pattern 410 may be disposed between the upper surface of the third portion 413 of the fin pattern 410 and the bottom surface of the second portion 412 of the fin pattern 410. The fourth portion 414 of the fin pattern 410 may be spaced apart from the third portion 413 of the fin pattern 410 in the vertical direction DR3. Furthermore, the second portion 412 of the fin pattern 410 may be spaced apart from the fourth portion 414 of the fin pattern 410 in the vertical direction DR3. For example, the third portion 413 and the fourth portion 414 of the fin pattern 410 may each be superimposed on each of the second portion 402_2 and the third portion 402_3 of the second active pattern 402 in the vertical direction DR3.

[0115] For example, the second gate insulating layer 432 may be disposed between the second gate electrode G12 and each of the first portion 402_1, the second portion 402_2, and the third portion 402_3 of the second active pattern 402. The second gate insulating layer 432 may be disposed between the second gate electrode G12 and each of the first portion 411, the second portion 412, the third portion 413, and the fourth portion 414 of the fin pattern 410.

[0116] In the following text, reference will be made to Figure 47 and Figure 48 explain Figure 46 and Figure 47 The semiconductor device shown is manufactured using a method described above. The explanation will focus on the method described above. Figures 5 to 38 The differences in the manufacturing methods of the semiconductor devices shown.

[0117] Figure 48 It is used for explanation Figure 46 and Figure 47 The diagram shows an intermediate stage of the manufacturing process of the semiconductor device.

[0118] Reference Figure 48 In execution Figures 5 to 12 Following the manufacturing process shown, a second mask pattern M42 can be formed on the second semiconductor layer 22. For example, the width of the second mask pattern M42 disposed on the upper surface of the second active pattern 402 (described later) in the second horizontal direction DR2 can be greater than the width of the second mask pattern M42 disposed on the upper surface of the first active pattern 101 (described later) in the second horizontal direction DR2. Subsequently, using the second mask pattern M42 as a mask, the stacked structure 10, the second sacrificial layer 21, and the second semiconductor layer 22 can each be etched. While the stacked structure 10, the second sacrificial layer 21, and the second semiconductor layer 22 are being etched, a portion of the substrate 100 can also be etched. Through this etching process, the first active pattern 101 can be defined below the stacked structure 10 on the upper surface of the substrate 100, and the second active pattern 402 can be defined below the second sacrificial layer 21 and the second semiconductor layer 22.

[0119] For example, the second active pattern 402 may include a first portion 402_1, a second portion 402_2, and a third portion 402_3. Each of the second portions 402_2 and 402_3 of the second active pattern 402 may protrude from the upper surface of the first portion 402_1 of the second active pattern 402 in the vertical direction DR3. The third portion 402_3 of the second active pattern 402 may be spaced apart from the second portion 402_2 of the second active pattern 402 in the second horizontal direction DR2. For example, each of the first sacrificial layer 11 and the first semiconductor layer 12 may remain on each of the second portions 402_2 and 402_3 of the second active pattern 402.

[0120] Reference Figure 47 In execution Figures 16 to 38 Following the manufacturing process shown, the first gate contact CB1 and the second gate contact CB2, the second etch stop layer 170, the second interlayer insulating layer 180, and the first via V1 and the second via V2 can each be formed. Through this manufacturing process, a product can be manufactured. Figure 47 The semiconductor device shown.

[0121] In the following text, reference will be made to Figure 49 The description describes semiconductor devices according to some other exemplary embodiments of the present disclosure. The description will focus on those related to... Figures 1 to 4 The differences in the semiconductor devices shown.

[0122] Figure 49 This is a cross-sectional view used to explain a semiconductor device according to several other exemplary embodiments of this disclosure.

[0123] Reference Figure 49 The semiconductor device according to several other example embodiments of the present disclosure may have a U-shaped fin pattern 510.

[0124] For example, the width of the second active pattern 502 in the second horizontal direction DR2 may be greater than the width of the first active pattern 101 in the second horizontal direction DR2. For example, the fin pattern 510 may include a first portion 511, a second portion 512, a third portion 513, a fourth portion 514, and a fifth portion 515. For example, the first portion 511 of the fin pattern 510 may be spaced apart from the upper surface of the second active pattern 502 in the vertical direction DR3. The second portion 512 of the fin pattern 510 may contact the upper surface of the first portion 511 of the fin pattern 510. The third portion 513 of the fin pattern 510 may be spaced apart from the upper surface of the second active pattern 502 in the vertical direction DR3. The third portion 513 of the fin pattern 510 may be spaced apart from the first portion 511 of the fin pattern 510 in the second horizontal direction DR2. The fourth portion 514 of the fin pattern 510 may contact the upper surface of the third portion 513 of the fin pattern 510. The fourth portion 514 of the fin pattern 510 may be spaced apart from the second portion 512 of the fin pattern 510 in the second horizontal direction DR2.

[0125] The fifth portion 515 of the fin pattern 510 may be spaced apart from the upper surface of the second active pattern 502 in the vertical direction DR3. The fifth portion 515 of the fin pattern 510 may connect the lower sidewall of the first portion 511 of the fin pattern 510 to the lower sidewall of the third portion 513 of the fin pattern 510. For example, the bottom surfaces of each of the first portion 511, the third portion 513, and the fifth portion 515 of the fin pattern 510 may be formed on the same plane. For example, the bottom surfaces of the first portion 511, the third portion 513, and the fifth portion 515 of the fin pattern 510 may each be equidistant from the substrate 100 (e.g., the upper or lower surface of the substrate 100) in the vertical direction DR3. For example, the second gate insulating layer 532 may be disposed between the second gate electrode G12 and the second active pattern 502. The second gate insulating layer 532 may be disposed between the second gate electrode G12 and each of the first portion 511, the second portion 512, the third portion 513, the fourth portion 514 and the fifth portion 515 of the fin pattern 510.

[0126] In the following text, reference will be made to Figures 49 to 52 describe Figure 49 The semiconductor device shown is manufactured using a method described in the illustration. The description will focus on... Figures 5 to 38 The differences in the manufacturing methods of the semiconductor devices shown.

[0127] Figures 50 to 52 It is used for explanation Figure 49 The diagram shows an intermediate stage of the manufacturing process of the semiconductor device.

[0128] Reference Figure 50 A stacked structure 10 may be formed on a substrate 100. The stacked structure 10 may include a first sacrificial layer 11 and a first semiconductor layer 12 alternately stacked on the substrate 100. For example, the first sacrificial layer 11 may be formed at the bottommost portion of the stacked structure 10, and the first semiconductor layer 12 may be formed at the topmost portion of the stacked structure 10. For example, the first sacrificial layer 11 may include silicon germanium (SiGe). For example, the first semiconductor layer 12 may include silicon (Si).

[0129] Subsequently, a first mask pattern M51 can be formed on the upper surface of the stacked structure 10. Then, using the first mask pattern M51 as a mask, the stacked structure 10 can be etched to form a fin trench FT51 inside the stacked structure 10. For example, the fin trench FT51 can extend into the interior of the substrate 100. That is, the bottom surface of the fin trench FT51 can be formed lower than the bottom surface of the stacked structure 10.

[0130] Reference Figure 51 The first mask pattern M51 can be removed (see...) Figure 50 Subsequently, a second sacrificial layer 21 and a second semiconductor layer 22 may be sequentially formed on the upper surface of the stacked structure 10 and on the bottom surface and sidewalls of the fin trench FT51. For example, each of the second sacrificial layer 21 and the second semiconductor layer 22 may be formed conformally. For example, voids may be formed on the second semiconductor layer 22 inside the fin trench FT51. For example, the second sacrificial layer 21 may include silicon germanium (SiGe), and the second semiconductor layer 22 may include silicon (Si).

[0131] Reference Figure 52 A second mask pattern M52 can be formed on the second semiconductor layer 22. For example, the second mask pattern M52 can fill the fin trench FT51 (see...). Figure 51The voids formed inside the second semiconductor layer 22. For example, the width of the second mask pattern M52 disposed on the upper surface of the second active pattern 502 (described later) in the second horizontal direction DR2 may be greater than the width of the second mask pattern M52 disposed on the upper surface of the first active pattern 101 (described later) in the second horizontal direction DR2. Subsequently, using the second mask pattern M52 as a mask, the stacked structure 10, the second sacrificial layer 21, and the second semiconductor layer 22 can be etched respectively. While the stacked structure 10, the second sacrificial layer 21, and the second semiconductor layer 22 are being etched respectively, a portion of the substrate 100 may also be etched. Through this etching process, the first active pattern 101 can be defined below the stacked structure 10 on the upper surface of the substrate 100, and the second active pattern 502 can be defined below the second sacrificial layer 21 and the second semiconductor layer 22.

[0132] Reference Figure 49 In execution Figures 16 to 38 Following the manufacturing process shown, the first gate contact CB1 and the second gate contact CB2, the second etch stop layer 170, the second interlayer insulating layer 180, and the first via V1 and the second via V2 can each be formed. Through this manufacturing process, a product can be manufactured. Figure 49 The semiconductor device shown.

[0133] While exemplary embodiments according to this disclosure have been described above with reference to the accompanying drawings, it will be understood that this disclosure is not limited to the above embodiments and can be made or implemented in various different forms. Those skilled in the art to which this disclosure pertains will recognize that this disclosure can be implemented in other specific forms without altering the technical concept or essential characteristics of this disclosure. Therefore, it should be understood that the above embodiments are exemplary in all respects and not restrictive.

Claims

1. A semiconductor device comprising: a substrate; a first active pattern extending in a first direction on the substrate; a second active pattern extending in the first direction on the substrate, the second active pattern spaced apart from the first active pattern in a second direction intersecting the first direction; a plurality of nanosheets spaced apart from each other in a third direction perpendicular to the first and second directions on the first active pattern; a fin-shaped pattern spaced apart from the plurality of nanosheets in the second direction, the fin-shaped pattern including: a first portion spaced apart from the second active pattern in the third direction; and a second portion in contact with an upper surface of the first portion, wherein a width of a bottom surface of the second portion in the second direction is greater than a width of the upper surface of the first portion in the second direction; and a gate electrode extending in the second direction on the first and second active patterns, the gate electrode at least partially surrounding each of the plurality of nanosheets and the fin-shaped pattern.

2. The semiconductor device of claim 1, further comprising: a first gate insulating layer between the gate electrode and the plurality of nanosheets; and a second gate insulating layer between the gate electrode and the fin-shaped pattern, wherein a thickness of the second gate insulating layer is greater than a thickness of the first gate insulating layer. At least a portion of the gate electrode is between an upper surface of the second active pattern and a bottom surface of the fin-shaped pattern.

3. The semiconductor device according to claim 1, wherein A thickness of the second portion of the fin-shaped pattern in the third direction is the same as a thickness of an uppermost nanosheet of the plurality of nanosheets in the third direction.

4. The semiconductor device according to claim 1, wherein A width of the first portion of the fin-shaped pattern in the second direction is less than a width of the plurality of nanosheets in the second direction.

5. The semiconductor device according to claim 1, wherein 6. The semiconductor device of claim 1, further comprising: a first source / drain region on the first active pattern on sidewalls of the plurality of nanosheets in the first direction; and a second source / drain region on the second active pattern on sidewalls of the fin-shaped pattern in the first direction, wherein an upper surface of the second source / drain region is the same distance from the substrate in the third direction as an upper surface of the first source / drain region.

7. The semiconductor device of claim 1, further comprising: a gate cut penetrating the gate electrode in the third direction, the gate cut separating the gate electrode into a first gate electrode and a second gate electrode, wherein the first gate electrode at least partially surrounds the plurality of nanosheets and the second gate electrode at least partially surrounds the fin-shaped pattern. An upper surface of the second gate electrode is the same distance from the substrate in the third direction as an upper surface of the first gate electrode. An upper surface of the fin-shaped pattern is the same distance from the substrate in the third direction as an upper surface of an uppermost nanosheet of the plurality of nanosheets.

8. The semiconductor device according to claim 7, wherein A width of the second active pattern in the second direction is the same as a width of the first active pattern in the second direction.

9. The semiconductor device according to claim 1, wherein The fin-shaped pattern further includes:

10. The semiconductor device according to claim 1, wherein a third portion spaced apart from sidewalls of the first portion in the second direction and between an upper surface of the second active pattern and a bottom surface of the second portion; and 11. The semiconductor device according to claim 1, wherein a fourth portion spaced apart from the sidewalls of the first portion in the second direction and between an upper surface of the third portion and the bottom surface of the second portion, and wherein the third portion, the fourth portion, and the second portion are spaced apart in the third direction. ​ ​ 12. The semiconductor device according to claim 1, wherein The fin-shaped pattern further includes: a third portion spaced apart from the first portion in the second direction; a fourth portion spaced apart from the second portion in the second direction, the fourth portion in contact with an upper surface of the third portion; and a fifth portion in contact with a lower sidewall of the first portion and a lower sidewall of the third portion, and wherein a bottom surface of the first portion, a bottom surface of the third portion, and a bottom surface of the fifth portion are at a same distance from the base in the third direction.

13. A semiconductor device comprising: a base; a first active pattern extending on the base in a first direction; a second active pattern extending on the base in the first direction, the second active pattern spaced apart from the first active pattern in a second direction intersecting the first direction; a plurality of nanosheets spaced apart from each other on the first active pattern in a third direction perpendicular to the first and second directions; a fin-shaped pattern spaced apart from the second active pattern in the third direction, the fin-shaped pattern spaced apart from the plurality of nanosheets in the second direction; a gate electrode extending on the first and second active patterns in the second direction, the gate electrode at least partially surrounding each of the plurality of nanosheets and the fin-shaped pattern, at least a portion of the gate electrode between an upper surface of the second active pattern and a bottom surface of the fin-shaped pattern; a first gate insulating layer between the gate electrode and the plurality of nanosheets; and a second gate insulating layer between the gate electrode and the fin-shaped pattern, wherein a thickness of the second gate insulating layer is greater than a thickness of the first gate insulating layer.

14. The semiconductor device according to claim 13, wherein The fin-shaped pattern includes: a first portion spaced apart from the second active pattern in the third direction; and a second portion in contact with an upper surface of the first portion, and wherein a width of a bottom surface of the second portion in the second direction is greater than a width of the upper surface of the first portion in the second direction.

15. The semiconductor device according to claim 14, wherein At least a portion of the bottom surface of the second portion of the fin-shaped pattern is in contact with the second gate insulating layer.

16. The semiconductor device according to claim 14, wherein A width of the second portion of the fin-shaped pattern in the second direction is the same as a width of an uppermost nanosheet of the plurality of nanosheets in the second direction.

17. The semiconductor device according to claim 13, wherein The upper surface of the second active pattern is lower than the upper surface of the first active pattern in the third direction.

18. The semiconductor device according to claim 13, wherein The upper surface of the fin-shaped pattern is higher than an upper surface of an uppermost nanosheet of the plurality of nanosheets in the third direction.

19. The semiconductor device according to claim 13, wherein A width of the second active pattern in the second direction is greater than a width of the first active pattern in the second direction.

20. A semiconductor device comprising: a base; a first active pattern extending on the base in a first direction; a second active pattern extending on the base in the first direction, the second active pattern spaced apart from the first active pattern in a second direction intersecting the first direction, wherein at least a portion of an upper surface of the second active pattern is lower than an upper surface of the first active pattern in a third direction perpendicular to the first and second directions, wherein a width of the second active pattern in the second direction is the same as a width of the first active pattern in the second direction; a plurality of nanosheets spaced apart from each other on the first active pattern in the third direction; a fin-shaped pattern spaced apart from the plurality of nanosheets in the second direction, the fin-shaped pattern including: a first portion spaced apart from the second active pattern in the third direction; and a second portion in contact with an upper surface of the first portion, wherein a width of a bottom surface of the second portion in the second direction is greater than a width of the upper surface of the first portion in the second direction; a first gate electrode extending in the second direction on the first active pattern, the first gate electrode at least partially surrounding the plurality of nanosheets; a second gate electrode extending in the second direction on the second active pattern, the second gate electrode spaced apart from the first gate electrode in the second direction, the second gate electrode at least partially surrounding the fin-shaped pattern, and at least a portion of the second gate electrode being between an upper surface of the second active pattern and a bottom surface of the fin-shaped pattern; a first gate insulating layer between the first gate electrode and the plurality of nanosheets; and a second gate insulating layer between the second gate electrode and the fin-shaped pattern, wherein a thickness of the second gate insulating layer is greater than a thickness of the first gate insulating layer, wherein a thickness of the second portion of the fin-shaped pattern in the third direction is the same as a thickness of an uppermost nanosheet of the plurality of nanosheets in the third direction, and wherein an upper surface of the fin-shaped pattern is on a same plane as an upper surface of the uppermost nanosheet of the plurality of nanosheets.

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