Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device comprises a substrate; the doped region is positioned in the substrate; and the embedded structure extends downwards from the upper surface of the substrate and at least comprises a contact metal, the contact metal is in contact with the doped region, and the contact metal is configured as an electrode end of the semiconductor device. The doped region is configured as a drain region of the semiconductor device, and the embedded structure is used for improving the withstand voltage of the semiconductor device; when the doped region is configured as a source region of the semiconductor device, the embedded structure is used for improving a safe working region of the semiconductor device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a semiconductor device. Background Technology

[0002] High voltage and high current place increasingly higher demands on laterally diffused metal oxide semiconductors (LDMOS): on the one hand, the chip area of ​​high current application products depends on the successive reduction of the specific on-resistance Rsp, which puts forward higher requirements for the extreme optimization of breakdown voltage BV and specific on-resistance Rsp; on the other hand, it also puts forward higher requirements for the reliability of the device's high current short-circuit capability. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor device to solve the problems existing in the prior art.

[0004] According to a first aspect of the present invention, a semiconductor device is provided, comprising: a substrate; a doped region located in the substrate; and a buried structure extending downward from an upper surface of the substrate, including at least a contact metal, wherein the contact metal contacts the doped region, and the contact metal is configured as an electrode of the semiconductor device.

[0005] Preferably, the contact metal is not higher than the upper surface of the substrate.

[0006] Preferably, it further includes a lead-out metal located on the substrate and in contact with the contact metal, the lead-out metal and the contact metal being configured together as electrical terminals of the semiconductor device.

[0007] Preferably, the doped region is configured as the drain region of the semiconductor device, and the buried structure is used to improve the breakdown voltage of the semiconductor device.

[0008] Preferably, the doped region extends from the upper surface of the substrate into its interior, and at least the side and bottom surfaces of the contact metal are surrounded by the doped region.

[0009] Preferably, the doped region is located below the contact metal and is in contact with the contact metal.

[0010] Preferably, the embedded structure further includes a side insulating layer disposed on at least one side of the contact metal, the side insulating layer extending downward from the upper surface of the substrate to the doped region.

[0011] Preferably, a side insulating layer is provided on the side of the contact metal near the other electrode of the semiconductor device.

[0012] Preferably, a side insulating layer is provided on both sides of the contact metal.

[0013] Preferably, the thickness of the side insulating layer is adjusted according to the manufacturing process of the device.

[0014] Preferably, the greater the thickness of the side insulating layer, the higher the withstand voltage of the semiconductor device.

[0015] Preferably, the embedded structure includes a side insulating layer and a top insulating layer, the contact metal includes a first portion spaced from the upper surface of the substrate and a second portion in contact with the upper surface of the substrate, the top insulating layer extends downward from the upper surface of the substrate to the first portion of the contact metal, and the side insulating layer covers the top insulating layer and the side surfaces of the contact metal.

[0016] Preferably, the greater the thickness of the top insulating layer, the higher the withstand voltage of the semiconductor device.

[0017] Preferably, it further includes a drift region extending from the upper surface of the substrate into its interior, wherein the embedded structure and the doped region are located in the drift region, and the conductivity type of the drift region is the same as that of the doped region.

[0018] Preferably, when the doped region is configured as the source region of the semiconductor device, the buried structure is used to improve the safe operating area of ​​the semiconductor device.

[0019] Preferably, it further includes a body region extending from the upper surface of the substrate into its interior, wherein the embedded structure and the doped region are located in the body region, and the conductivity type of the body region is opposite to that of the source region.

[0020] Preferably, the doped region further includes a bulk contact region that contacts the contact metal.

[0021] Preferably, the source region extends from the upper surface of the body region into its interior, the body contact region is located on the side of the source region away from the drain region and extends laterally to the bottom of the source region, and the conductivity type of the body contact region is opposite to that of the source region.

[0022] Preferably, the body contact area extends from the upper surface of the body region to the interior of the body region.

[0023] Preferably, the upper surface of the body contact area does not contact the upper surface of the substrate.

[0024] Preferably, the contact metal extends downward from the upper surface of the body region to at least the upper surface of the body contact region, and at least a portion of the side surface of the contact metal contacts the side surface of the source region.

[0025] Preferably, the upper surface of the body contact region is in contact with the lower surface of the source region.

[0026] Preferably, the upper surface of the body contact region is spaced apart from the lower surface of the source region.

[0027] Preferably, the embedded structure is configured as a rectangular, trapezoidal, inverted trapezoidal, or rounded trapezoidal structure.

[0028] Preferably, it further includes a gate structure, a portion of which is located on a portion of the embedded structure.

[0029] In the semiconductor device provided by this invention, when the buried structure is applied to the drain region, by placing the contact metal (as the drain metal) inside the substrate, the lateral geometry of the device can be scaled with advanced process nodes. The lateral short channel length can be precisely controlled under advanced node processes, thereby reducing the die size of the device. Furthermore, it also extends the effective length of the drift region between the gate and drain regions, achieving the target breakdown voltage with a minimized die area. In this embodiment, the buried structure is suitable for devices requiring specific voltage withstand capabilities. Further, the buried structure shifts the breakdown point of the device from the traditional substrate surface to the bulk, enhancing the device's heat dissipation capacity and improving its unclamped inductive switching (UIS) capability.

[0030] When the embedded structure is applied to the source region, the contact metal (as the source metal) is moved from the upper surface of the traditional substrate to the interior of the substrate, which improves the efficiency of the source in collecting minority carriers and effectively reduces the lateral resistance below the source region, thereby significantly enhancing the safe operating area (SOA) of the device. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the cross-sectional structure of a semiconductor device provided in Embodiment 1 of the present invention;

[0032] Figure 2 This is a schematic diagram of the cross-sectional structure of the semiconductor device provided in Embodiment 2 of the present invention;

[0033] Figure 3a This is a schematic diagram of the cross-sectional structure of the semiconductor device along the x-axis provided in Embodiment 3 of the present invention;

[0034] Figure 3b This is a schematic diagram of the cross-sectional structure of the contact metal of the semiconductor device along the y-axis direction provided in Embodiment 3 of the present invention;

[0035] Figure 4a This is a schematic diagram of the cross-sectional structure of the semiconductor device provided in Embodiment 4 of the present invention;

[0036] Figure 4b This is a schematic diagram of the cross-sectional structure of a semiconductor device provided in Embodiment 5 of the present invention. Detailed Implementation

[0037] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0038] A semiconductor process node refers to the size of a transistor's feature dimensions (such as gate length) during semiconductor manufacturing. It is commonly used to describe the level of precision in integrated circuit manufacturing technology. A smaller process node number means smaller transistor sizes, higher integration density, and thus the ability to manufacture smaller, more efficient chips.

[0039] From the perspective of process node scaling, lateral high voltage (HV) and power devices are limited by lateral geometry (constant electric field) scaling. That is, at the target breakdown voltage (BV), the lateral drift region of lateral devices cannot be reduced, and even with process node scaling, it is limited by the same constant silicon peak value required for the same target BV. Therefore, this invention proposes changing the device drift region design from lateral geometry to quasi-lateral or quasi-vertical design in advanced process nodes.

[0040] This invention provides a semiconductor device, comprising: a substrate; a doped region located in the substrate; and a buried structure extending downward from the upper surface of the substrate, including at least one contact metal, wherein the contact metal is in contact with the doped region, and the contact metal is configured as a terminal of the semiconductor device. The contact metal is not higher than the upper surface of the substrate. The semiconductor device further includes a lead-out metal located on the substrate and in contact with the contact metal, the lead-out metal and the contact metal being jointly configured as terminals of the semiconductor device. Specifically, the following uses an LDMOS device as an example of the semiconductor device, referring to... Figure 1 The semiconductor device of the first embodiment of the present invention will be explained and described in detail.

[0041] As an example, the semiconductor device of the present invention includes: a substrate, a doped region 205 located in the substrate, and a buried structure, the buried structure including at least a contact metal 108 and a side insulating layer 203. The buried structure extends from the upper surface of the substrate into its interior, and the doped region 205 is located below the buried structure. The buried structure contacts the doped region 205; specifically, the contact metal 108 extends from the upper surface of the substrate to the top of the doped region 205, and the side insulating layer 203 extends from the upper surface of the substrate to the top of the doped region 205. The contact metal 108 is configured as a terminal of the semiconductor device, and the semiconductor device further includes a lead-out metal (not shown) located on the substrate and in contact with the contact metal, the lead-out metal and the contact metal being jointly configured as terminals of the semiconductor device. The buried structure includes a trench extending from the upper surface of the substrate into its interior, and a side insulating layer 203 and a contact metal 108 filling the trench. The width of the embedded structure is greater than the width of the doped region 205.

[0042] For example, the doped region 205 is configured as a drain region, that is, the contact metal is configured as a drain metal, and the buried structure is used to improve the breakdown voltage of the semiconductor device.

[0043] For example, the embedded structure includes a side insulating layer disposed on at least one side of the contact metal 108, the side insulating layer extending downward from the upper surface of the substrate to the doped region.

[0044] For example, a side insulating layer is provided on the side of the contact metal near the other electrode of the semiconductor device. In this embodiment, a side insulating layer is provided on the side of the contact metal 108 near the source region 107.

[0045] In this embodiment, side insulating layers 203 are provided on both sides of the contact metal 108. The depth of the side insulating layers 203 is substantially the same as that of the contact metal 108. Within the limitations of the device's process node, the greater the thickness A of the side insulating layers 203, the higher the drain voltage withstand capability of the device. The semiconductor device structure of this embodiment can be applied to devices with medium voltage withstand requirements.

[0046] The side insulating layer can be formed by thermal oxidation or deposition, and the material of the side insulating layer can include SiO2, SiN, etc.

[0047] In this embodiment, the drain region 205 is also partially located below the side insulating layer 203, so that the contact metal 108 and the doped region have better contact characteristics.

[0048] In this embodiment, a portion of the gate structure is located above the side insulating layer 203, and the overlapping area is small, which significantly reduces the gate leakage charge, thereby meeting the requirements of high-frequency applications.

[0049] The embedded structure provided in this embodiment includes a side insulating layer located on at least one side of the contact metal. Since the breakdown electric field of the insulating layer is higher than that of the silicon bulk, it effectively improves the overall breakdown voltage of the semiconductor device. Specifically, the greater the thickness of the side insulating layer, the greater its withstand voltage. Furthermore, this design, which relies on the side insulating layer to bear the withstand voltage, can reduce the length of the gate conductor, allowing the gate conductor length to reach the minimum value specified by the process specifications, thereby significantly reducing the gate-source charge.

[0050] The embedded structure (i.e., trench) can be rectangular, trapezoidal, inverted trapezoidal, or rounded trapezoidal, etc. The depth and width of the embedded structure can be adjusted according to the voltage withstand requirements of the device. Specifically, the greater the depth of the embedded structure, the higher the voltage withstand of the device; the greater the width of the side insulation layer of the embedded structure, the higher the voltage withstand of the device.

[0051] For example, the substrate can be made of silicon, silicon carbide, gallium nitride, etc. In this embodiment, the substrate is made of silicon. The structure of the substrate may include one or more combinations of a semiconductor substrate, an epitaxial layer, a well region, a buried layer, and an isolation structure. In this embodiment, the structure of the substrate includes a semiconductor substrate and a well region, wherein the well region and the semiconductor substrate have opposite conductivity types.

[0052] As an example, the semiconductor device further includes a drift region 103, in which the drain region 205 is located. The doping concentration of the drift region 103 is lower than that of the drain region 205, which is equivalent to forming a high-resistivity layer between the gate and drain, thereby improving the breakdown voltage. The conductivity type of the drift region is the same as that of the drain region.

[0053] As an example, the semiconductor device further includes an injection region located below the drift region 103, the injection region having the opposite conductivity type to the drift region 103, for reducing the specific on-resistance of the device.

[0054] The semiconductor device further includes a body region 104 extending from the upper surface of the substrate into its interior, a source region 107 extending from the upper surface of the body region 104 into its interior, and a body contact region 106, wherein the body region 104 and the body contact region 106 have the same conductivity type, and the body contact region 106 and the source region 107 have opposite conductivity types. The body region is generally configured as the channel region of the device. The source region 107 and the drain region 105 have the same conductivity type. In one example, the drift region 103 is in contact with the body region 104, and the well region 102 can have a P-type or N-type conductivity type. In another example, the drift region 103 and the body region 104 are not in contact, and the well region 102 has the same conductivity type as the drain region.

[0055] It also includes a source metal 109, which is disposed on the upper surface of the substrate and contacts the source region 107 and the body contact region 106.

[0056] The semiconductor device further includes a gate structure 120 located between the drain region 105 and the source region 107. The gate structure 120 includes a gate dielectric layer 110 located on the upper surface of the substrate and a gate conductor 111 located on the gate dielectric layer 110.

[0057] In this embodiment, LDMOS is used as an example for illustration. In other optional embodiments, the semiconductor device can also be configured as other MOS structures, etc. In this embodiment, the doped region is described as the drain region. In other devices, the doped region can also be configured as the source region, etc. The buried structure (contact metal in this embodiment) is basically the same.

[0058] In this embodiment, by placing the drain metal inside the substrate, the lateral geometry of the device can be scaled with advanced process nodes. The lateral short channel length can be precisely controlled under advanced node processes, thereby reducing the die size of the device. Furthermore, it extends the effective length of the drift region between the gate and drain regions, achieving the target breakdown voltage with a minimized die area. This embedded structure is suitable for devices requiring specific voltage withstand capabilities. Further, the embedded structure shifts the breakdown point of the device from the traditional substrate surface to the bulk, enhancing heat dissipation and improving the device's unclamped inductive switching (UIS) capability.

[0059] refer to Figure 2The semiconductor device according to the second embodiment of the present invention will be explained and described in detail. This embodiment differs from the first embodiment in that the buried structure is different; other structures are basically the same and will not be described again here. In this embodiment, the buried structure only includes the contact metal 108, i.e., the case where the thickness A of the side insulating layer is 0. The bottom and side of the contact metal are surrounded by the doped region, and the contact metal 108 is configured as the electrode of the semiconductor device.

[0060] In this embodiment, the doped region 105 is configured as a drain region, and the contact metal 108 extends from the upper surface of the doped region 105 into its interior. Specifically, the embedded structure includes a trench extending from the upper surface of the doped region into its interior, and contact metal 108 filling the trench. The embedded structure can be configured as a rectangular, trapezoidal, inverted trapezoidal, or rounded trapezoidal structure, etc. The depth and width of the embedded structure can be adjusted according to the voltage withstand requirements of the device. Specifically, the greater the depth of the embedded structure, the higher the voltage withstand of the device; the greater the width of the side insulating layer of the embedded structure, the higher the voltage withstand of the device.

[0061] The depth of the contact metal can be adjusted according to the current distribution requirements of the device. Specifically, the greater the depth of the contact metal, the wider the leakage current distribution from the substrate surface. This enhances the heat dissipation capability of the device and improves its non-clamped inductive switching (UIS) capability. The semiconductor device structure of this embodiment can be applied to devices with low voltage withstand requirements.

[0062] refer to Figure 3a and 3b The semiconductor device of the third embodiment of the present invention will be explained and described in detail. Figure 3a The diagram shows a cross-sectional view of a semiconductor device according to Embodiment 3 of the present invention along the x-axis. Figure 3b The diagram shown is a cross-sectional view of the contact metal of a semiconductor device according to Embodiment 3 of the present invention along the y-axis. This embodiment differs from the second embodiment in the embedded structure; other structures are essentially the same and will not be described further here.

[0063] In this embodiment, the embedded structure includes a side insulating layer 203 and a top insulating layer 303. The contact metal 108 includes a first portion spaced from the upper surface of the substrate and a second portion in contact with the upper surface of the substrate, such as... Figure 3b As shown. The top insulating layer 303 extends downward from the upper surface of the substrate to a first portion of the contact metal 108, and the side insulating layer 203 covers the top insulating layer 303 and the side surface of the contact metal 108. The lead-out metal contacts a second portion of the contact metal 108 and together serve as the electrode terminals of the semiconductor device.

[0064] In the semiconductor device structure of this embodiment, the doped region 205 (serving as the drain region) is located inside the drift region and below the buried structure. Therefore, majority carriers injected from the source to the drain sequentially pass through the source region, the top insulating layer of the buried structure, and the side insulating layer, finally reaching the drain region. By increasing the thickness of the top insulating layer 303, the effective path of the breakdown voltage drift region can be effectively extended, thereby improving the breakdown voltage capability of the semiconductor device. The semiconductor device structure design of this embodiment can be applied to devices with higher breakdown voltage requirements.

[0065] refer to Figure 4a The semiconductor device according to the fourth embodiment of the present invention will be explained and described in detail. This embodiment differs from the second embodiment in the arrangement of the body contact region and the source metal; other structures are basically the same and will not be described again here.

[0066] In this embodiment, the doped region can also be configured as a source region, and the contact metal can also be configured as a source metal.

[0067] In this embodiment, the source region 107 extends from the upper surface of the body region 104 into its interior, and the body contact region 606 is located on the side of the source region away from the drain region and extends laterally to the lower part of the source region 107. The doping type of the body region 104 and the body contact region 606 is opposite to that of the source region 107.

[0068] In this embodiment, the upper surface of the body contact region 706 is separated from the upper surface of the body region 104, and the upper surface of the body contact region 706 contacts the lower surface of the source region 107. The contact metal 609 extends downward from the upper surface of the body region 104 to at least the upper surface of the body contact region 606, and at least a portion of the side surface of the contact metal 609 contacts the side surface of the source region 107. In this embodiment, moving the source metal structure from the conventional upper surface of the substrate to the interior of the substrate improves the efficiency of minority carrier collection at the source, while effectively reducing the lateral resistance below the source region 107, thereby significantly enhancing the SOA of the device.

[0069] In an optional example, the upper surface of the body contact region 606 is spaced apart from the upper surface of the body region 104, and the upper surface of the body contact region 606 is spaced apart from the lower surface of the source region 107. A contact metal 609 extends downward from the upper surface of the body region 104 to at least the upper surface of the body contact region 606, and at least a portion of the side surface of the contact metal 609 contacts the side surface of the source region 107, such as... Figure 4bAs shown. In this embodiment, the upper surface of the body contact region 606 is spaced apart from the lower surface of the source region 107. The source metal contacts the body region to form a Schottky contact. Charge carriers can reach the source metal 609 more quickly through the gap between the upper surface of the body contact region 606 and the source region 107, further improving the reverse recovery capability of the device. At the same time, it effectively reduces the lateral resistance below the source region 107, thereby significantly enhancing the SOA of the device.

[0070] In an optional example, the body contact region 606 extends from the upper surface of the body region 104 into the interior of the body region. The contact metal 609 extends from the upper surface of the body contact region into it and contacts the source region. This arrangement simplifies the process flow and reduces process costs.

[0071] It should be noted that the arrangement of the source metal and the body contact area in this embodiment can also be used for Figure 1 , Figure 2 and Figure 3a No restrictions are placed on the structure shown or any other required device structure.

[0072] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor device, characterized by, Comprising: a substrate; a doped region in the substrate; a buried structure extending downward from an upper surface of the substrate, comprising at least a contact metal, wherein the contact metal is in contact with the doped region, and the contact metal is configured as an electrode terminal of the semiconductor device.

2. The semiconductor device according to claim 1, wherein The contact metal is not higher than the upper surface of the substrate.

3. The semiconductor device of claim 2, wherein, Further comprising a lead-out metal on the substrate and in contact with the contact metal, the lead-out metal and the contact metal are collectively configured as the electrode terminal of the semiconductor device.

4. The semiconductor device of claim 1, wherein The doped region is configured as a drain region of the semiconductor device, and the buried structure is used to increase the withstand voltage of the semiconductor device.

5. The semiconductor device of claim 1, wherein The doped region extends from the upper surface of the substrate to the inside of the substrate, and at least the side surface and the bottom surface of the contact metal are surrounded by the doped region.

6. The semiconductor device of claim 1, wherein The doped region is located below the contact metal and in contact with the contact metal.

7. The semiconductor device of claim 6, wherein, The buried structure further comprises a side insulating layer provided on at least one side of the contact metal, the side insulating layer extends downward from the upper surface of the substrate to the doped region.

8. The semiconductor device of claim 6, wherein, The contact metal is provided with a side insulating layer on the side close to the other electrode terminal of the semiconductor device.

9. The semiconductor device of claim 6, wherein, The contact metal is provided with a side insulating layer on both sides.

10. The semiconductor device of claim 7, wherein The thickness of the side insulating layer is adjusted according to the manufacturing process of the device.

11. The semiconductor device of claim 7, wherein The greater the thickness of the side insulating layer, the higher the withstand voltage of the semiconductor device.

12. The semiconductor device of claim 6, wherein, The buried structure comprises a side insulating layer and a top insulating layer, the contact metal comprises a first part spaced from the upper surface of the substrate and a second part in contact with the upper surface of the substrate, the top insulating layer extends downward from the upper surface of the substrate to the first part of the contact metal, and the side insulating layer covers the top insulating layer and the side surface of the contact metal.

13. The semiconductor device of claim 12, wherein, The greater the thickness of the top insulating layer, the higher the withstand voltage of the semiconductor device.

14. The semiconductor device of claim 4, wherein Further comprising a drift region extending from the upper surface of the substrate to the inside of the substrate, the buried structure and the doped region are located in the drift region, and the conductivity type of the drift region is the same as that of the doped region.

15. The semiconductor device of claim 1, wherein When the doped region is configured as a source region of the semiconductor device, the buried structure is used to increase the safe operating area of the semiconductor device.

16. The semiconductor device of claim 15, wherein, Further comprising a body region extending from the upper surface of the substrate to the inside of the substrate, the buried structure and the doped region are located in the body region, and the conductivity type of the body region is opposite to that of the source region.

17. The semiconductor device of claim 16, wherein, The doped region further comprises a body contact region in contact with the contact metal.

18. The semiconductor device of claim 17, wherein, The source region extends from the upper surface of the body region to the inside of the body region, the body contact region is located on the side of the source region away from the drain region, and extends laterally to the lower side of the source region, and the conductivity type of the body contact region is opposite to that of the source region.

19. The semiconductor device of claim 17, wherein, The body contact region extends from the upper surface of the body region to the inside of the body region.

20. The semiconductor device of claim 17, wherein, The upper surface of the body contact region is not in contact with the upper surface of the substrate.

21. The semiconductor device of claim 20, wherein, The contact metal extends downward from the upper surface of the body region to at least the upper surface of the body contact region, and at least part of the side surface of the contact metal is in contact with the side surface of the source region.

22. The semiconductor device of claim 20, wherein, An upper surface of the body contact region is in contact with a lower surface of the source region.

23. The semiconductor device of claim 20, wherein, An upper surface of the body contact region is spaced apart from a lower surface of the source region.

24. The semiconductor device of claim 1, wherein, The embedded structure is arranged in a rectangular or trapezoidal or inverted trapezoidal or rounded trapezoidal structure.

25. The semiconductor device of claim 1, wherein, A gate structure is further included, and part of the gate structure is located on part of the embedded structure.

Images