Semiconductor device and method of manufacturing the same
By employing a multi-control electrode and Schottky electrode structure design in semiconductor devices and optimizing the configuration of the insulation and diffusion regions, the problems of on-resistance and parasitic capacitance are solved, achieving low on-resistance and high-speed switching.
Patent Information
- Application Number
- CN202411607239.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-09-09
- Filing Date
- 2024-11-12
- Publication Date
- 2026-03-10
AI Technical Summary
Existing semiconductor devices struggle to balance reducing on-resistance and increasing the Schottky barrier when switching between on and off states, and they also exhibit significant parasitic capacitance, which affects switching speed and voltage withstand performance.
By employing a structural design with multiple control electrodes and Schottky electrodes, and by forming insulating portions and diffusion regions within the semiconductor layer, combined with trench formation technology, the configuration of Schottky electrodes and diffusion regions is optimized, thereby reducing source contact resistance and parasitic capacitance.
This achieves low on-resistance and high-speed switching characteristics in semiconductor devices, while reducing parasitic capacitance and improving withstand voltage and switching speed.
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Figure CN121645947A_ABST
Abstract
Description
[0001] Related applications
[0002] This application claims priority to Japanese Patent Application No. 2024-155190 (filed on September 9, 2024). This application incorporates the entire contents of that basic application by reference. Technical Field
[0003] This embodiment relates to a semiconductor device and a method for manufacturing the same. Background Technology
[0004] A semiconductor device is known that switches between on and off states by controlling the height of the Schottky barrier through a voltage applied to the gate electrode. Summary of the Invention
[0005] The semiconductor device of this embodiment includes: a first electrode; a second electrode disposed separately from the first electrode in a first direction; a plurality of control electrodes disposed between the first electrode and the second electrode and extending in a second direction intersecting the first direction; a semiconductor layer disposed between the first electrode and the second electrode and having a first semiconductor region in ohmic contact with the first electrode; a plurality of insulating portions disposed within the semiconductor layer and respectively disposed between the semiconductor layer and the control electrodes; a plurality of third electrodes disposed opposite to the control electrodes in a third direction intersecting the first and second directions, sandwiched by adjacent insulating portions in the third direction, electrically connected to the second electrode, and disposed separately from each other along the second direction; and a second semiconductor region disposed within the semiconductor layer on the first semiconductor region, having a higher impurity concentration than the first semiconductor region, sandwiched by the third electrodes along the second direction, in Schottky contact with the third electrodes, and having a width along the third direction that is wider than its width along the second direction.
[0006] The semiconductor device manufacturing method of this embodiment is a method for manufacturing a semiconductor device having a first electrode, a second electrode, and a control electrode. The second electrode is disposed separately from the first electrode in a first direction. The control electrode is disposed opposite to the second electrode in the first direction and extends in a second direction intersecting the first direction. In the semiconductor device manufacturing method, control electrodes are formed in a plurality of insulating portions disposed in a semiconductor layer and arranged in a third direction intersecting the first and second directions, respectively. On a main surface of the semiconductor layer, a plurality of trenches are formed between the plurality of control electrodes in a manner arranged in the second direction. The semiconductor layer is removed until the sidewalls of the plurality of trenches reach the insulating portion. A plurality of third electrodes that are in Schottky contact with the semiconductor layer and a second electrode connected to the plurality of third electrodes are formed in the plurality of trenches.
[0007] According to this embodiment, a semiconductor device capable of reducing on-resistance and a method for manufacturing the same can be provided. Attached Figure Description
[0008] Figure 1 This is a top view schematic diagram illustrating an embodiment of the semiconductor device disclosed herein.
[0009] Figure 2A It is along Figure 1 The first sectional view of line AA.
[0010] Figure 2B It is along Figure 1 The second sectional view of the BB line.
[0011] Figure 3 This is an example. Figure 1 A three-dimensional schematic diagram of a semiconductor device centered on the range D.
[0012] Figure 4A It is in the cutoff state. Figure 1 An enlarged view of the range D.
[0013] Figure 4B It is in the on state Figure 1 An enlarged view of the range D.
[0014] Figure 5 This is a diagram illustrating the parasitic capacitance in a semiconductor device according to an embodiment of the present disclosure.
[0015] Figure 6 This is a diagram illustrating the parasitic capacitance of a modified semiconductor element.
[0016] Figure 7 This is a top view schematic diagram showing the structure of a comparative example semiconductor device.
[0017] Figure 8 It means along Figure 7 A cross-sectional schematic diagram of the structure of a semiconductor device with DD lines.
[0018] Figure 9A This is a diagram illustrating the formation process of the insulating portion of a semiconductor device according to an embodiment of the present disclosure.
[0019] Figure 9B It continues Figure 9A The diagram illustrates the trench formation process of a semiconductor device according to an embodiment of this disclosure.
[0020] Figure 9C It continues Figure 9B The diagram illustrates the etching process of the trench in a semiconductor device according to an embodiment of this disclosure.
[0021] Figure 9D It continues Figure 9C The figure shows the Schottky metal film formation process of the semiconductor device according to an embodiment of the present disclosure.
[0022] Explanation of reference numerals in the attached figures
[0023] 1. 100 Semiconductor Devices
[0024] 2.200 semiconductor components
[0025] 3. 201 Control Electrode (Gate Electrode)
[0026] 4 Insulation Part
[0027] 5 semiconductor layers
[0028] 6-electrode (drain electrode)
[0029] 7. Electrode (Source Electrode)
[0030] 11. 101 Schottky electrode
[0031] 12, 102 diffusion areas
[0032] 13 Semiconductor Regions
[0033] 14 Conductive Part (FP Electrode)
[0034] 31, 103, 202 depletion layers
[0035] 32, 104 Ditch
[0036] Parasitic capacitances 41, 203, and 204
[0037] 51a, 51b trenches Detailed Implementation
[0038] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the scope of the invention. The drawings are schematic or conceptual, and the proportions of the parts may not be identical to reality. In the specification and drawings, elements identical to those already described in the accompanying drawings are labeled with the same reference numerals, and detailed descriptions are omitted where appropriate.
[0039] In addition, for ease of explanation, such as Figure 1 As shown, an XYZ orthogonal coordinate system is used. The Z-axis direction is the stacking direction (thickness direction) of the semiconductor device. The Y-axis direction is one of the top views of the semiconductor device, and more specifically, the direction in which multiple semiconductor elements are arranged. Additionally, the source electrode side in the Z-axis direction is also called "upper," and the drain electrode side is also called "lower." However, this expression is for convenience and is independent of the direction of gravity.
[0040] Additionally, in the following explanation, to indicate the relative levels of impurity concentration in each conductivity type, n is sometimes used. + n, n - and p + p, p - These statements. That is, n + This indicates that the concentration of n-type impurities is relatively high compared to n. - This indicates that the concentration of n-type impurities is relatively low compared to n. Additionally, p... + This indicates that the concentration of p-type impurities is relatively high compared to p-type impurities. - This indicates that the concentration of p-type impurities is relatively low compared to p-type impurities. In cases where both p-type and n-type impurities are present in various regions, these statements represent the relative levels of net impurity concentration after these impurities compensate for each other. In this specification, n-type, n... + type and n - This type is also called the first conductivity type. Furthermore, in this specification, p-type, p... + Type and p - This type is also called the second conductivity type. Furthermore, in the following explanation, the n-type and p-type can also be reversed.
[0041] Furthermore, the impurity concentration in the semiconductor region can be determined, for example, by secondary ion mass spectrometry (SIMS). Additionally, the relative level of impurity concentration can be determined, for example, by the level of carrier concentration obtained through scanning capacitance microscopy (SCM).
[0042] In addition, dimensions such as the width of the diffusion region can be determined, for example, by surface and / or cross-sectional analysis based on transmission electron microscopy (TEM), energy dispersive X-ray spectroscopy (EDX), or scanning electron microscopy (SEM).
[0043] Furthermore, the composition of conductive parts, etc., can be analyzed using methods such as energy-dispersive X-ray spectroscopy.
[0044] <Implementation Methods of this Disclosure>
[0045] Reference Figure 1 , Figure 2A and Figure 2B The semiconductor device 1 according to the embodiments of the present disclosure will be described. Figure 1 This is a top view schematic diagram illustrating an embodiment of the semiconductor device 1 of the present disclosure. Figure 1 The horizontal and vertical directions correspond to the X-axis direction (third direction) and Y-axis direction (second direction) mentioned above, respectively. Figure 1 The depth direction corresponds to the Z-axis direction (first direction) mentioned above. Furthermore, Figure 1 The top view is equivalent to Figure 2A and Figure 2B The plane at the CC line.
[0046] Figure 2A It is along Figure 1 First sectional view of line AA Figure 2B It is along Figure 1 The second sectional view of the BB line. Figure 2A A cross-section of the Schottky electrode 11 is illustrated. Figure 2B A cross-section of diffusion region 12 is illustrated. Figure 2A and Figure 2B The horizontal and vertical directions correspond to the X-axis and Z-axis directions, respectively. For example... Figure 2A and Figure 2B As shown, the semiconductor element 2 in this embodiment is a MOSFET with a field plate (FP) electrode, i.e., FPMOS.
[0047] Figure 1 , Figure 2A and Figure 2BThe semiconductor device 1 shown has a control electrode 3, an insulating portion 4, a semiconductor layer 5, an electrode (first electrode) 6, an electrode (second electrode) 7, a Schottky electrode (third electrode) 11, a diffusion region (second semiconductor region) 12, a semiconductor region (first semiconductor region) 13, and a conductive portion 14. The semiconductor device 1 has a plurality of semiconductor elements 2.
[0048] Semiconductor element 2 is a vertically oriented transistor through which current flows in the Z-axis direction. More specifically, semiconductor element 2 is a vertically oriented MOSFET (Metal Oxide Silicon Field Effect Transistor) that switches between on and off states by controlling the thickness of the Schottky barrier through the control electrode 3. Figure 1 In the example, there are multiple semiconductor elements 2 arranged in the X-axis and Y-axis directions.
[0049] Control electrode 3 extends in the Y-axis direction. Additionally, in Figure 1 In the example, multiple control electrodes 3 are arranged in the X-axis direction. For example... Figure 2A As shown, control electrode 3 is arranged opposite electrode 7 in the Z-axis direction. Control electrode 3, for example, comprises polysilicon containing p-type or n-type impurities. Control electrode 3 functions as the gate electrode of the MOSFET, controlling the current flowing between electrode 6 and electrode 7.
[0050] The insulating part 4 is arranged to surround the control electrode 3. For example... Figure 1 As shown, the insulating portion 4 insulates the control electrode 3 from the Schottky electrode 11. Additionally, the insulating portion 4 insulates the control electrode 3 from the diffusion region 12. The insulating portion 4 is, for example, a silicon oxide film (SiO2).
[0051] like Figure 1 As shown, the Schottky electrode 11 is arranged such that it is sandwiched between adjacent insulating portions 4 in the X-axis direction. Furthermore, multiple Schottky electrodes 11 are arranged along the Y-axis direction. More specifically, in Figure 1 In the example, there are multiple Schottky electrodes 11 arranged along the Y-axis between the two control electrodes 3.
[0052] The diffusion region 12 is configured such that it is sandwiched between two Schottky electrodes 11 (a first Schottky electrode and a second Schottky electrode). For example... Figure 1 As shown, the Schottky electrode 11 and the diffusion region 12 are alternately arranged between the two control electrodes 3 along the Y-axis. The diffusion region 12, in addition to being in contact with the two Schottky electrodes 11, is as follows: Figure 2B It is also connected to electrode 7 in the Z-axis direction.
[0053] Furthermore, the Schottky electrode 11 and the diffusion region 12 are not limited to being disposed between the insulating portions 4, but may also be disposed between the control electrode 3 and an element separation film or protective film (not shown) that separates the semiconductor element 2 from other components (e.g., other transistors, diodes, or wiring layers that are controlled independently of the semiconductor device 1).
[0054] Semiconductor layer 5 is an n-type (first conductivity type) semiconductor region. Semiconductor layer 5 can be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate and an epitaxial layer disposed on the semiconductor substrate. In this specification, an example in which semiconductor layer 5 is made of silicon (Si) will be described.
[0055] like Figure 2B As shown, semiconductor layer 5 includes a diffusion region 12 and a semiconductor region 13 that are electrically connected to each other. Alternatively, a semiconductor region (not shown) with a higher n-type impurity concentration than semiconductor region 13 may be provided between semiconductor region 13 and electrode 6.
[0056] A diffusion region 12 is disposed above the semiconductor region 13. The diffusion region 12 is an n-type semiconductor region with a higher impurity concentration than the semiconductor region 13. The n-type impurity concentration of the semiconductor region 13 is, for example, 1 × 10⁻⁶. 15 cm -3 Above and 2×10 18 cm -3 The following is a comparison. In contrast, the n-type impurity concentration in diffusion region 12 is, for example, 1 × 10⁻⁶. 18 cm -3 Above and 2×10 22 cm -3 Below. In the diffusion region 12, for example, arsenic (As), phosphorus (P) or antimony (Sb) are implanted as n-type (first conductivity type) impurities.
[0057] Electrode 6 is disposed on the first surface A1 side of semiconductor layer 5. Electrode 6 is a plate-shaped electrode extending in the X-axis and Y-axis directions. Electrode 6 is electrically connected to semiconductor layer 5. Electrode 6 has an ohmic contact with semiconductor layer 5. Electrode 6 is made of, for example, Cu, Ti, W, or Al. Electrode 6 functions as the drain electrode of a MOSFET.
[0058] Electrode 7 is disposed separately from electrode 6 in the Z-axis direction. Electrode 7 is a plate-shaped electrode extending in the X-axis and Y-axis directions. Electrode 7 is disposed on the second surface A2 side of semiconductor layer 5 and is electrically connected to semiconductor layer 5. Figure 2A As shown, electrode 7 is electrically connected to Schottky electrode 11.
[0059] A Schottky electrode 11 extends from electrode 7 toward the first surface A1 between adjacent insulating portions 4. The Schottky electrode 11 is arranged opposite the control electrode 3 in the X-axis direction. The Schottky electrode 11 makes Schottky contact with the diffusion region 12, forming a Schottky barrier at the interface between the Schottky electrode 11 and the diffusion region 12. The Schottky electrode 11 may be made of a metal with a higher work function than electrode 7, for example.
[0060] Schottky electrode 11 contains, for example, at least one of Ti, W, Mo, Ta, Zr, Al, Sn, V, Re, Os, Ir, Pt, Pd, Rh, Ru, Nb, Sr, Co, or Hf (e.g., Pt). Electrode 7 contains, for example, at least one of Al, Cu, Mo, W, Ta, Co, Ru, Ti, or Pt (e.g., W).
[0061] Furthermore, the Schottky electrode 11 and electrode 7 can also be made of the same metal. When made of the same metal, the Schottky electrode 11 and electrode 7 can also be integrally formed.
[0062] The Schottky electrode 11 is preferably buried in the depth direction (Z-axis direction) of the semiconductor layer 5 at a position shallower than or approximately the same as the control electrode 3. Specifically, the lower end face A3 of the Schottky electrode 11 is preferably disposed in the depth direction of the semiconductor layer 5 at a position higher than or approximately the same as the lower end face A4 of the control electrode 3. As a result, the lower end face of the depletion layer (depletion layer 31 described later) formed in the diffusion region 12 is formed at a position higher than, and more preferably approximately the same as, the lower end face A3 of the Schottky electrode 11. As a result, the parasitic capacitance between the gate and drain (parasitic capacitance 41 described later) can be further reduced.
[0063] In this specification, the state in which a predetermined voltage is applied to the control electrode 3 and current flows between the electrodes 6 and 7 is referred to as the conducting state of the semiconductor element 2. Conversely, the state in which a smaller current flows between the electrodes 6 and 7 than in the conducting state, or where no current flows, is referred to as the cutting state of the semiconductor element 2. When the semiconductor element 2 is in the conducting state, a channel (channel 32 described later) is formed in the diffusion region 12 for the current to flow between the electrodes 6 and 7.
[0064] Furthermore, by increasing the Schottky barrier at the interface between the Schottky electrode 11 and the diffusion region 12, the threshold voltage of the semiconductor element 2 can be increased. Thus, the semiconductor element 2 can also be configured as a normally closed MOSFET.
[0065] On the other hand, the source contact resistance between electrode 7 and diffusion region 12 is preferably low. By reducing the source contact resistance, the on-resistance of semiconductor element 2 can be reduced, enabling high-speed switching of semiconductor element 2 and suppression of on-state and off-state losses.
[0066] like Figure 2A As shown, the conductive portion 14 is disposed inside the insulating portion 4 below the control electrode 3, functioning as a field plate electrode. The conductive portion 14 is electrically connected to the electrode 7. The conductive portion 14 may contain, for example, polycrystalline silicon containing p-type or n-type impurities. By providing the conductive portion 14, when the semiconductor device 1 is in the off state, by applying a reverse voltage between the drain electrode and the source electrode, the depletion layer extends from the conductive portion 14 to the surrounding drift region. By connecting this depletion layer to the depletion layer of the adjacent conductive portion 14, the withstand voltage of the semiconductor device 1 is increased.
[0067] Furthermore, semiconductor element 2 may also be a structure in which the conductive portion 14 is omitted. That is, semiconductor element 2 may also be a trench MOS structure as described in the modified example below.
[0068] Figure 3 This is an example. Figure 1 A three-dimensional schematic diagram of a semiconductor device 1 centered on region D. Figure 3 The diagram shows two control electrodes 3, two insulating portions 4, two Schottky electrodes 11, a diffusion region 12, a semiconductor region 13, and a conductive portion 14.
[0069] Next, refer to Figure 4A and Figure 4B Semiconductor element 2 will be described in detail. Figure 4A and Figure 4B It is Figure 1 The magnified view of range D. Figure 4A The diagram illustrates the off-state of semiconductor element 2. Figure 4B The diagram shows the conduction state of semiconductor element 2.
[0070] exist Figure 4A and Figure 4B The diagram illustrates two control electrodes 3, two insulating portions 4, two Schottky electrodes 11, and a diffusion region 12. The two control electrodes 3 are arranged opposite each other along the X-axis. The two Schottky electrodes 11 are arranged opposite each other along the Y-axis. The two insulating portions 4 insulate the control electrodes 3 from the Schottky electrodes 11 and the diffusion region 12, respectively. The diffusion region 12 is disposed between adjacent control electrodes 3 and between adjacent Schottky electrodes 11.
[0071] A depletion layer 31 is formed at the interface between the diffusion region 12 and the Schottky electrode 11. The depletion layer 31 is a region with less or no charge compared to other regions of the diffusion region 12.
[0072] like Figure 4A As shown, when the semiconductor element 2 is in the off state, the depletion layer 31 is formed along the X-axis and Y-axis directions on approximately the entire surface of the diffusion region 12.
[0073] The depletion layer 31 is formed, for example, by combining two depletion layers formed at two interfaces of the diffusion region 12. Specifically, a first depletion layer is formed at the interface between the diffusion region 12 and one of the two Schottky electrodes 11 (hereinafter also referred to as the first Schottky electrode 11). A second depletion layer is formed at the interface between the diffusion region 12 and the other of the two Schottky electrodes 11 (hereinafter also referred to as the second Schottky electrode 11). The depletion layer 31 is formed by combining the first and second depletion layers described above.
[0074] exist Figure 4B In this process, a voltage is applied to the control electrode 3, and the semiconductor element 2 becomes conductive. When the semiconductor element 2 is conductive, the depletion layer 31 shrinks (recedes) from the interface between the insulating portion 4 and the diffusion region 12 along the X-axis. Thus, as... Figure 4B As shown, a channel (conductive region) 32 is formed in the diffusion region 12. The channel 32 does not extend to the entire surface of the diffusion region 12 in the X-axis direction. That is, the channel 32 is formed at the interface between one insulating part 4 and the diffusion region 12 and at the interface between another insulating part 4 and the diffusion region 12.
[0075] In this specification, the length from the interface between the diffusion region 12 and the first Schottky electrode 11 to the interface between the diffusion region 12 and the second Schottky electrode 11 (i.e., the width of the diffusion region 12 along the Y-axis) is referred to as the thickness T of the diffusion region 12. Furthermore, the length from the interface between the diffusion region 12 and the first insulating portion 4 to the interface between the diffusion region 12 and the second insulating portion 4 (i.e., the width of the diffusion region 12 along the X-axis) is referred to as the width W of the diffusion region. Additionally, the width W is sometimes referred to as the mesa width or pitch of the semiconductor element 2.
[0076] exist Figure 4A and Figure 4B In this example, the thickness T is smaller than the width W. More specifically, the thickness T can be less than half the width W. For example, the thickness T is 50 nm to 100 nm. The width W is, for example, 100 nm to 200 nm. This range of thickness T and width W is a reference for forming the channel 32 separately at the interface between the insulating portion 4 and the diffusion region 12.
[0077] like Figure 4B As shown, in the diffusion region 12 in the conducting state, the first boundary surface forming the Schottky barrier (i.e., the interface between the diffusion region 12 and the Schottky electrode 11) and the second boundary surface forming the channel 32 (i.e., the interface between the diffusion region 12 and the insulating portion 4) are not opposite. Compared to the configuration where the first and second boundary surfaces are opposite, the semiconductor element 2 forms a wider channel at the second boundary surface when a voltage is applied to the control electrode 3. This reduces the on-resistance of the semiconductor element 2.
[0078] Furthermore, in the on-state, the channel 32 is locally formed at the interface between the insulating portion 4 and the diffusion region 12, and does not extend to the entire surface of the diffusion region 12 in the X-axis direction. Therefore, the semiconductor element 2 can be switched to the off-state at high speed.
[0079] Furthermore, not limited to the above, the thickness T of the diffusion region 12 only needs to be thin enough to combine the first depletion layer formed at the interface between the diffusion region 12 and the first Schottky electrode 11 and the second depletion layer formed at the interface between the diffusion region 12 and the second Schottky electrode 11. Additionally, the width W only needs to be large enough that the channel 32 does not extend to the entire surface of the diffusion region 12 in the X-axis direction when the semiconductor element 2 is in the on state.
[0080] The thickness T and width W can be adjusted arbitrarily, for example, according to the raw materials of the Schottky electrode 11 and the diffusion region 12, the type or concentration of impurities injected into the diffusion region 12, the voltage applied to the control electrode 3 to achieve a conductive state, or the temperature design of the semiconductor element 2.
[0081] The thickness T and width W of the semiconductor element 2 can be arbitrarily adjusted within the range where the channel 32 is locally formed at the interface between the diffusion region 12 and the insulating portion 4. For example, by reducing the width W of the semiconductor element 2, the pitch can be reduced (pitch shrinkage), thereby miniaturizing the semiconductor device 1. Furthermore, by increasing the density of the drift current, the on-resistance can be reduced.
[0082] In this embodiment, the diffusion region 12 is connected to both the first Schottky electrode 11 and the second Schottky electrode 11. Therefore, compared to a structure where the diffusion region 12 is connected to only one Schottky electrode, the contact area between the Schottky electrode 11 and the diffusion region 12 can be increased, thus reducing the source contact resistance. Furthermore, with the increase in contact area, the degree of freedom regarding the thickness T increases, allowing for an increase in the thickness T.
[0083] Figure 5 This is a diagram illustrating the reduction effect of parasitic capacitance achieved by the semiconductor element 2 according to the embodiments of this disclosure. Figure 5 The diagram illustrates a parasitic capacitance 41 formed between control electrode 3 and electrode 6. The parasitic capacitance 41 is formed between control electrode 3 and electrode 6 via a semiconductor layer 5 opposite to control electrode 3 in the X-axis direction.
[0084] The parasitic capacitance 41 is the gate-drain capacitance (Cgd). Additionally, the parasitic capacitance 41 constitutes the feedback capacitance (Crss). When the parasitic capacitance 41 is large, the rise and fall of the drain-source voltage of the semiconductor device 2 slows down, resulting in a slower switching speed of the semiconductor device 2.
[0085] Semiconductor element 2 forms a depletion layer 31 extending along the X-axis direction via Schottky electrode 11. This reduces the capacitance of parasitic capacitance 41.
[0086] Furthermore, regarding the semiconductor element 2, in the off state, a depletion layer 31 is formed along the X-axis direction on approximately the entire surface of the diffusion region 12 (i.e., from one insulating portion 4 to another insulating portion 4). Therefore, compared to a structure in which a depletion layer is formed only in a portion of the diffusion region 12, the capacitance reduction effect of the parasitic capacitance 41 is greater.
[0087] The portion of the depletion layer 31 positioned at the same height as the control electrode 3 contributes to a greater reduction in parasitic capacitance. Therefore, the depletion layer 31 is preferably formed at approximately the same height as the lower end of the control electrode 3. Alternatively, the lower end of the depletion layer 31 may be formed at a position higher than the lower end of the control electrode 3. To form a depletion layer 31 as described above, such as... Figure 2B As shown, the Schottky electrode 11 is preferably buried in the depth direction (Z-axis direction) of the semiconductor layer 5 at a position shallower than or approximately the same as that of the control electrode 3.
[0088] <Variation Example>
[0089] Figure 6 This is a diagram illustrating the parasitic capacitance of the modified semiconductor element 200. (See diagram for example.) Figure 6 As shown, semiconductor device 200 differs from semiconductor device 2 in that it does not have a conductive portion 14. Semiconductor device 200 has a trench MOS structure in which a control electrode 201 is buried in a trench of a semiconductor layer. In addition, in semiconductor device 200, a depletion layer 202 is formed through a Schottky electrode (not shown).
[0090] In semiconductor device 200, a parasitic capacitance 203 is formed between control electrode 201 and electrode 6 via semiconductor layer 5, which is opposite to control electrode 201 in the X-axis direction. Additionally, in semiconductor device 200, a parasitic capacitance 204 is formed between control electrode 201 and electrode 6 via semiconductor layer 5, which is opposite to control electrode 201 in the Z-axis direction. Parasitic capacitances 203 and 204 constitute the gate-drain capacitance Cgd that forms the feedback capacitance Crss.
[0091] Since the parasitic capacitance 204 does not form a depletion layer 202 in the vicinity, the reduction effect of the parasitic capacitance brought by the depletion layer 202 is not obtained.
[0092] and Figure 6 Compared to semiconductor device 200, in Figure 5 In the semiconductor element 2, a conductive portion 14 is disposed between the control electrode 3 and the semiconductor layer 5 opposed in the Z-axis direction. Therefore, inFigure 5 In semiconductor element 2, no parasitic capacitance equivalent to parasitic capacitance 204 is formed. Therefore, compared with semiconductor element 200 of the modified example, semiconductor element 2 can achieve a greater reduction in parasitic capacitance.
[0093] Next, a comparative example for comparison with the above-described embodiments will be described.
[0094] <Comparative Example>
[0095] Figure 7 This is a top view schematic diagram showing the structure of a comparative example semiconductor device 100. For example... Figure 7 As shown, the semiconductor device 100 has only one Schottky electrode 101 extending along the Y-axis between adjacent control electrodes 3, which differs from the semiconductor device 1 of the embodiment. Furthermore, in Figure 7 In the middle, between the Schottky electrode 101 and the insulating part 4, there is a diffusion region 102 that forms a channel (channel 104 described later) in the conducting state.
[0096] Figure 8 This is a cross-sectional schematic diagram showing the structure of a comparative example semiconductor device 100. Figure 8 express Figure 7 The cross-section at the DD line. Additionally, in Figure 8 The diagram illustrates a depletion layer 103 formed in the diffusion region 102 and a channel 104 formed when a predetermined voltage is applied to the control electrode 3 to make it conductive.
[0097] like Figure 8 As shown, in a comparative example, the depletion layer 103 and the channel 104 are formed on opposing boundary surfaces. In particular, in the semiconductor device 100, if the Schottky barrier is increased to reduce leakage current, it is difficult to form the channel 104, which would affect the resistance of the channel 104. Therefore, it is difficult to simultaneously increase the Schottky barrier and decrease the on-resistance. Furthermore, if the width (length in the X-axis direction) of the diffusion region 102 is narrowed, the source contact resistance increases, making it difficult to reduce the spacing.
[0098] Compared to a comparative example semiconductor device 100, in the semiconductor device 1 of the present disclosure, a channel 32 is formed at an interface different from the interface between the diffusion region 12 and the Schottky electrode 11 (i.e., the interface between the diffusion region 12 and the insulating portion 4). This allows for both an increase in the Schottky barrier and a decrease in the source contact resistance.
[0099] Furthermore, in semiconductor device 1, the diffusion region 12 has a larger contact area with the Schottky electrodes 11 because it is in contact with the two Schottky electrodes 11. This reduces the source contact resistance. Additionally, it maintains a lower source contact resistance and makes pitch reduction easier compared to semiconductor device 100. For example, the semiconductor device 1 of the present disclosure can reduce the pitch of the semiconductor elements 2 by approximately 10 times that of the comparative semiconductor device 100.
[0100] <Manufacturing Method of Semiconductor Device 1>
[0101] Next, an example of the manufacturing method of the semiconductor device 1 according to the embodiment will be described. Figures 9A-9D This is a diagram illustrating the manufacturing process of the semiconductor device 1 according to an embodiment of the present disclosure.
[0102] Figure 9A This diagram illustrates the formation process of the interlayer film (insulating portion 4). In this process, a control electrode 3 and an insulating portion 4, which serves as the interlayer film for the semiconductor element 2, are formed. For example, a trench (not shown) is formed from a main surface of the semiconductor layer 5 by etching or the like, and an insulating portion is formed to cover the sidewalls of the trench. Then, the control electrode 3 is formed within this insulating portion. Subsequently, the insulating portion 4 is formed by embedding the control electrode 3 within it. Multiple control electrodes 3 are formed in an arrangement along the X-axis direction.
[0103] Figure 9B This diagram illustrates the formation process of the trench contact portion. In this process, multiple trenches 51a for embedding the Schottky electrode 11 are formed in the semiconductor layer 5. The multiple trenches 51a are formed in a dotted pattern between adjacent control electrodes 3, arranged in the extension direction of the control electrodes 3, i.e., the Y-axis direction. The multiple trenches 51a are formed by methods such as PEP (Photo Engraving Process) or Reactive Ion Etching (RIE).
[0104] Figure 9C This diagram illustrates the etching process at the trench contact area. In this process, the sidewalls of trench 51a are etched using a high selectivity (SiO2 / Si) CDE (Chemical Dry Etching) method to form a trench 51b with a wide contact width. The trench 51b is formed such that it extends from one end of the insulating portion 4 to one end of another adjacent insulating portion 4.
[0105] Figure 9DThis diagram illustrates the film-forming process of Schottky metal. In this process, a Schottky electrode 11 is formed by depositing metal material within trench 51b. Alternatively, an electrode 7 may be formed integrally and continuously with the Schottky electrode 11 in this process. Or, the electrode 7 may be formed after this process.
[0106] exist Figure 9D The subsequent processes or Figures 9A-9D In the preceding process of either of the processes, impurities are injected from a main surface of the semiconductor layer 5, and a diffusion region 12 is formed through a thermal diffusion process or the like. Alternatively, the thermal diffusion process can also be performed as another process.
[0107] As shown above Figures 9A-9D The process can form Figure 1 The Schottky electrode 11 and diffusion region 12 are shown. According to this embodiment, compared with the aforementioned comparative example, even if the formation position of the Schottky electrode is slightly deviated, it will not have a significant impact on the characteristics of the semiconductor device.
[0108] In the manufacturing process of the embodiments of this disclosure, even Figure 9B In the process, the width of groove 51a may deviate, which can also be addressed by... Figure 9C The etching process homogenizes the width W of the Schottky electrode 11. Specifically, in Figure 9C In the CDE process, the etching rate of silicon (Si) in semiconductor layer 5 is higher than that of the oxide film (SiO2) in insulating portion 4, and insulating portion 4 functions as an etching barrier layer. Therefore, even if the width of trench 51a deviates, the width of trench 51b can be uniformized. Consequently, the width W of Schottky electrode 11 can be uniformized. Therefore, in Figure 9C In the etching process, alignment allowance can be ensured.
[0109] Furthermore, as described above, in the semiconductor device 1 of this disclosure, it is possible to improve... Figure 4A The design freedom of the thickness T of the diffusion region 12 shown is increased. That is, the freedom of the formation spacing of adjacent Schottky electrodes 11 in the Y-axis direction can be improved. Therefore, the manufacturing process of the semiconductor device 2 can also be simplified.
[0110] Thus, the semiconductor device 1 of this embodiment has a diffusion region 12 sandwiched between adjacent Schottky electrodes 11. In the diffusion region 12 of this embodiment, when the semiconductor element 2 is in a conducting state, a channel 32 is formed on a boundary surface that does not face the boundary surface connected to the Schottky electrode 11. Furthermore, the channel 32 is not formed across the entire surface of the diffusion region 12 in the X-axis direction. This reduces the on-resistance of the semiconductor device 1. Additionally, it enables faster cut-off operation of the semiconductor device 1.
[0111] Furthermore, since the diffusion region 12 is in contact with the two Schottky electrodes 11, it has a large contact area with the Schottky electrodes 11. This reduces the source contact resistance. Moreover, even with a narrower spacing, the semiconductor device 1 can achieve a low source contact resistance. In other words, the semiconductor device 1 can achieve miniaturization and a reduction in source contact resistance.
[0112] Furthermore, in the manufacturing process of semiconductor device 1, after the trench contact portion into which the Schottky electrode 11 is embedded is formed, the sidewalls are etched. This sidewall etching process ensures the alignment allowance for the width of the trench contact portion. This simplifies the manufacturing process.
[0113] Furthermore, the present invention is not limited to the embodiments described above. During implementation, the constituent elements can be modified and customized without departing from its spirit. Additionally, various inventions can be formed by appropriately combining the multiple constituent elements disclosed in the above embodiments. For example, a structure in which several constituent elements are deleted from all the constituent elements shown in each embodiment can also be considered. Moreover, constituent elements described in different embodiments can be appropriately combined.
Claims
1. A semiconductor device, characterized by comprising: Possessing: a first electrode; a second electrode disposed apart from the first electrode in a first direction; a plurality of control electrodes disposed between the first electrode and the second electrode, extending in a second direction intersecting the first direction; a semiconductor layer disposed between the first electrode and the second electrode, having a first semiconductor region in ohmic contact with the first electrode; a plurality of insulating portions disposed within the semiconductor layer, and disposed between the semiconductor layer and the control electrodes, respectively; a plurality of third electrodes disposed in opposition to the control electrodes in a third direction intersecting the first and second directions, sandwiched by adjacent insulating portions in the third direction, electrically connected to the second electrode, and disposed apart from each other in the second direction; and a second semiconductor region disposed on the first semiconductor region within the semiconductor layer, having a higher impurity concentration than the first semiconductor region, sandwiched by the third electrodes in the second direction, in Schottky contact with the third electrodes, and having a width in the third direction wider than a width in the second direction.
2. The semiconductor device according to claim 1, wherein when the semiconductor device is in an on state, the control electrodes form conductive regions in interfaces with the insulating portions sandwiching the third electrodes in the second semiconductor region, and do not form the conductive regions in other regions of the second semiconductor region.
3. The semiconductor device according to claim 1, wherein when the semiconductor device is in an off state, a depletion layer is formed in the second semiconductor region from one of the insulating portions sandwiching the third electrodes to the other insulating portion.
4. The semiconductor device according to claim 3, wherein when the semiconductor device changes from the off state to the on state, the depletion layer shrinks in the third direction from the insulating portions.
5. The semiconductor device according to claim 1, wherein a width of the second semiconductor region in the second direction is half or less of a width of the second semiconductor region in the third direction.
6. The semiconductor device according to claim 1, wherein a width of the second semiconductor region in the second direction is 50 nm or more and 100 nm or less, a width of the second semiconductor region in the third direction is 100 nm or more and 200 nm or less.
7. The semiconductor device according to any one of claims 1 to 6, further comprising: a conductive portion disposed between the control electrodes and the first electrode, and electrically connected to the second electrode.
8. A semiconductor device, characterized by comprising: Possessing: a first electrode; a second electrode disposed apart from the first electrode in a first direction; a plurality of control electrodes disposed between the first electrode and the second electrode, extending in a second direction intersecting the first direction; a semiconductor layer disposed between the first electrode and the second electrode, having a first semiconductor region in ohmic contact with the first electrode; a plurality of insulating portions provided in the semiconductor layer and each provided between the semiconductor layer and the control electrode; a plurality of third electrodes provided so as to face the control electrode in a third direction intersecting the first direction and the second direction, sandwiched by the insulating portions adjacent in the third direction, electrically connected to the second electrode, and provided separately from each other along the second direction; a second semiconductor region provided in the semiconductor layer on the first semiconductor region, having a higher impurity concentration than the first semiconductor region, sandwiched by the third electrode along the second direction, and in Schottky contact with the third electrode; and a conductive portion provided between the control electrode and the first electrode and electrically connected to the second electrode.
9. A method for manufacturing a semiconductor device, the semiconductor device having: a first electrode; a second electrode provided separately from the first electrode in a first direction; a control electrode provided so as to face the second electrode in the first direction and extending in a second direction intersecting the first direction; the method for manufacturing the semiconductor device characterized by: forming the control electrode in a plurality of the control electrodes arranged in a third direction intersecting the first direction and the second direction, in a plurality of insulating portions provided in a semiconductor layer, forming a plurality of trenches between the plurality of control electrodes in the semiconductor layer in a manner arranged in the second direction on a main surface of the semiconductor layer, removing the semiconductor layer until side walls of the plurality of trenches reach the insulating portions, forming a plurality of third electrodes in Schottky contact with the semiconductor layer and the second electrode connected to the plurality of third electrodes in the plurality of trenches.
10. The method for manufacturing the semiconductor device according to claim 9, characterized by: forming the third electrode in a manner in which a pitch of the plurality of third electrodes is narrower than a pitch of a plurality of insulating portions each insulating the plurality of control electrodes from the semiconductor layer.
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JP2024155190A