Semiconductor device and manufacturing method

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method for preventing withstand voltage reduction through shape control of a gate electrode. According to one embodiment, a semiconductor device includes a first electrode, a second electrode, and a first semiconductor layer of a first conductivity type provided between the first electrode and the second electrode and electrically connected to the first electrode. A second semiconductor layer of the second conductivity type is arranged on the second electrode, and a third semiconductor layer of the first conductivity type is arranged between the second semiconductor layer and the second electrode. The field plate electrode extends in a first direction from the first semiconductor layer toward the second semiconductor layer, and has a field plate insulating layer surrounding the periphery thereof. The semiconductor device further comprises a gate electrode having a first side surface provided between the first semiconductor layer and the field plate electrode, a second side surface facing the first side surface, and a first surface connected to the first side surface and the second side surface and in contact with the field plate insulating layer. The first surface has an apex which is separated from the first side surface and the second side surface and protrudes toward the first electrode side.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2024-148168 (filed on August 30, 2024). This application incorporates all contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices and manufacturing methods. Background Technology

[0004] Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) are used as switching elements. In the manufacturing process of semiconductor devices, the etching process of the insulating layer surrounding the field plate determines the shape of the gate electrode based on polysilicon.

[0005] At the interface between the gate electrode and the thinner insulating layer, if the gate electrode has an acute angle, it is easy to cause local electric field concentration, leading to damage to the gate insulating layer. Summary of the Invention

[0006] Embodiments of the present invention provide a semiconductor device and a method of manufacturing which prevent voltage drop by controlling the shape of the gate electrode.

[0007] According to this embodiment, the semiconductor device includes a first electrode, a second electrode, and a first semiconductor layer of a first conductivity type disposed between the first electrode and the second electrode and electrically connected to the first electrode. A second semiconductor layer of a second conductivity type is disposed thereon, and a third semiconductor layer of a first conductivity type is disposed between the second semiconductor layer and the second electrode. A field plate electrode extends in a first direction from the first semiconductor layer toward the second semiconductor layer and has a field plate insulating layer surrounding it. Furthermore, a gate electrode is provided, having a first side surface disposed between the first semiconductor layer and the field plate electrode, a second side surface opposite to the first side surface, and a first surface connected to and in contact with the first and second side surfaces and the field plate insulating layer. This first surface has a vertex that is separate from the first and second side surfaces and protrudes toward the first electrode side. Attached Figure Description

[0008] Figure 1 This is a schematic cross-sectional view of the semiconductor device 100 according to the first embodiment.

[0009] Figure 2 It means by Figure 1 A cross-sectional view of part A enclosed by the dashed line.

[0010] Figure 3This is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device 100 according to the first embodiment.

[0011] Figure 4 It means to continue Figure 3 A schematic cross-sectional view of a part of the manufacturing process.

[0012] Figure 5 It means to continue Figure 4 A schematic cross-sectional view of a part of the manufacturing process.

[0013] Figure 6 It means to continue Figure 5 A schematic cross-sectional view of a part of the manufacturing process.

[0014] Figure 7 It means to continue Figure 6 A schematic cross-sectional view of a part of the manufacturing process.

[0015] Figure 8 It means to continue Figure 7 A schematic cross-sectional view of a part of the manufacturing process.

[0016] Figure 9 It means by Figure 8 A cross-sectional view of part B enclosed by the dashed line.

[0017] Figure 10 It means to continue Figure 8 A schematic cross-sectional view of a part of the manufacturing process.

[0018] Figure 11 It means to continue Figure 10 A schematic cross-sectional view of a part of the manufacturing process.

[0019] Figure 12 It means to continue Figure 11 A schematic cross-sectional view of a part of the manufacturing process.

[0020] Figure 13 It means to continue Figure 12 A schematic cross-sectional view of a part of the manufacturing process.

[0021] Figure 14 It means to continue Figure 13 A schematic cross-sectional view of a part of the manufacturing process.

[0022] Figure 15 It means to continue Figure 14 A schematic cross-sectional view of a part of the manufacturing process.

[0023] Figure 16 It means to continue Figure 15 A schematic cross-sectional view of a part of the manufacturing process.

[0024] Figure 17 This is a schematic cross-sectional view of the semiconductor device 200 of the first comparative example.

[0025] Figure 18 It means by Figure 17 A cross-sectional view of part C enclosed by the dashed line.

[0026] Figure 19 This is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device 200 of the first comparative example. Detailed Implementation

[0027] The following is a reference to the appendix. Figure 1 Embodiments of the present invention will now be described. In this description, common reference numerals will be used for common parts throughout the drawings.

[0028] Furthermore, this embodiment does not limit the present invention, and the scale of the accompanying drawings is not limited to the scale shown in the drawings. In the following description, the first conductivity type is described as n-type and the second conductivity type as p-type, but this is not a limitation. The first conductivity type may also be p-type and the second conductivity type may be n-type.

[0029] Additionally, in the following explanation, n + n, n － and p + p, p － The expression represents the relative concentration of impurities in each conductivity type. That is, n + This indicates that the concentration of impurities of type n is relatively higher than that of type n. － This indicates that the concentration of impurities in the n-type group is relatively lower than that in the n-type group. Additionally, p... + This indicates that the concentration of p-type impurities is relatively higher than that of p-type impurities. － This indicates that the impurity concentration of p-type is relatively lower than that of p-type. Additionally, sometimes n-type is used... + type, n － The type is abbreviated as n-type, and p + Type, p － The type is abbreviated as p-type.

[0030] [First Implementation Method]

[0031] (Structure of semiconductor device 100)

[0032] Reference Figures 1-2 The detailed structure of the semiconductor device 100 according to the first embodiment will be described. Figure 1 This is a schematic cross-sectional view of the semiconductor device 100 according to the first embodiment. Figure 2 It means by Figure 1 A cross-sectional view of part A enclosed by the dashed line.

[0033] The semiconductor device 100 in the first embodiment is, for example, a MOSFET. Figure 1 As shown, the semiconductor device 100 has a drain electrode 10, a gate electrode 13, a source electrode 14, an n-type semiconductor region 22, a p-type semiconductor region 23, an n-type source layer 26, a field plate electrode 30, and a field plate insulating layer 40.

[0034] Here, the drain electrode 10 is an example of the first electrode, and the source electrode 14 is an example of the second electrode.

[0035] The direction from the drain electrode 10 toward the n-type semiconductor region 22 is defined as the Z direction (first direction). Furthermore, the direction orthogonal to the Z direction is defined as the X direction (second direction), and the direction orthogonal to both the X and Z directions is defined as the Y direction (third direction). Figure 1 The semiconductor device 100 shown is illustrated in a cross-sectional view on the X-Z plane. Here, for the sake of explanation, the direction from the drain electrode 10 toward the n-type semiconductor region 22 is referred to as "up" and the opposite direction is referred to as "down".

[0036] Figure 1 The semiconductor device 100 includes, for example, an n-type drift layer 20 and a p-type substrate layer 24. The p-type substrate layer 24 is disposed on the n-type drift layer 20 in the Z direction.

[0037] An n-type source layer 26 and a p-type contact layer 25 are disposed side by side on the p-type substrate layer 24. On the other hand, an n-type drain layer 21 is disposed in the -Z direction of the n-type drift layer 20.

[0038] The n-type semiconductor region 22 is composed of an n-type drift layer 20 and an n-type drain layer 21. The p-type semiconductor layer 23 is composed of a p-type substrate layer 24 and a p-type contact layer 25. However, the n-type drain layer 21 and the p-type contact layer 25 are not mandatory. The n-type semiconductor region 22 may also consist only of the n-type drift layer 20. The p-type semiconductor layer 23 may also consist only of the p-type substrate layer 24.

[0039] Here, the n-type drift layer 20 is an example of a first semiconductor layer of a first conductivity type, the p-type base layer 24 is an example of a second semiconductor layer of a second conductivity type, the n-type source layer 26 is an example of a third semiconductor layer of a first conductivity type, the n-type drain layer 21 is a fourth semiconductor layer of a first conductivity type, and the p-type contact layer 25 is a fifth semiconductor layer of a second conductivity type.

[0040] Furthermore, the n-type impurity concentration in the n-type drain layer 21 is higher than that in the n-type drift layer 20. The p-type impurity concentration in the p-type contact layer 25 is higher than that in the p-type substrate layer 24.

[0041] Here, the n-type drain layer 21, n-type drift layer 20, p-type substrate layer 24, n-type source layer 26, and p-type contact layer 25 are made of silicon (Si) or silicon carbide (SiC) as semiconductor materials. When silicon is used as the semiconductor material, arsenic (As), phosphorus (P), or antimony (Sb) can be used as n-type impurities. Boron (B) can be used as a p-type impurity.

[0042] The semiconductor device 100 has a trench U extending from the upper surface of the n-type source layer 26 through the n-type source layer 26 and the p-type substrate layer 24 to the n-type drift layer 20. Inside the trench U, a field plate electrode 30 extending from the p-type substrate layer 24 toward the n-type drain layer 21 is disposed. The field plate electrode 30 is surrounded by the n-type drift layer 20 through a field plate insulating layer 40.

[0043] Inside the trench U, a gate electrode 13 is disposed at the upper end of the field plate insulating layer 40 in the Z direction. The gate electrode 13 faces the p-type substrate layer 24 in the X direction. A gate insulating layer 44 is disposed between the gate electrode 13 and the p-type substrate layer 24. The thickness of the gate insulating layer 44 is thinner than that of the field plate insulating layer 40.

[0044] Additionally, an upper end portion 30c of the field plate electrode 30 is provided at its upper end in the Z direction. The upper end portion 30c of the field plate electrode extends in the X direction between the two gate electrodes 13. That is, the gate electrode 13 is located between the field plate electrode 30 and the p-type substrate layer 24. A first interlayer insulating layer 45 is provided between the upper end portion 30c of the field plate electrode and the gate electrode 13.

[0045] A second interlayer insulating layer 46 is provided on the gate electrode 13 and the upper end 30c of the field plate electrode. A source electrode 14 is provided on the second interlayer insulating layer 46, the n-type source layer 26, and the p-type contact layer 25. The source electrode 14 is electrically connected to the n-type source layer 26 and electrically connected to the p-type substrate layer 24 via the p-type contact layer 25. On the other hand, a drain electrode 10 is provided on the back side of the n-type drain layer 21 in the -Z direction of the n-type drift layer 20.

[0046] Here, the drain electrode 10 and source electrode 14 contain metals such as Al and Cu. The field electrode 30 and gate electrode 13 are, for example, polysilicon, and contain phosphorus and boron as conductive impurities. The field insulating layer 40, gate insulating layer 44, first interlayer insulating layer 45, and second interlayer insulating layer 46 are, for example, insulating films containing silicon.

[0047] In the semiconductor device 100, the drain current flowing between the drain electrode 10 and the source electrode 14 is controlled by the gate electrode 13. The field plate electrode 30 is wired to be connected to the source electrode 14 in a portion not shown, and is electrically connected to the source electrode 14. Furthermore, the field plate electrode 30 controls the electric field in the n-type drift layer 20 located in the -Z direction relative to the gate electrode 13, thereby increasing the breakdown voltage between the drift and the source.

[0048] Additionally, in a portion of the semiconductor device 100, a gate pad (not shown) is provided separately from the aforementioned component area and is connected to an external power supply (or gate controller). Gate wiring is electrically connected to the gate pad, and the gate wiring is disposed on the surface of the semiconductor device 100. This gate wiring is connected to a gate electrode 13 extending from the surface of the semiconductor device 100.

[0049] Next, by indicating that by Figure 1 The part A enclosed by the dashed line Figure 2 The structure of the gate electrode 13 will be described.

[0050] exist Figure 2 In this embodiment, the gate electrode 13 has sidewalls 13a and 13b, and a lower surface 13c. Sidewall 13a is opposed to the p-type substrate layer 24 across the gate insulating layer 44, and sidewall 13b is opposed to the field plate electrode 30 across the first interlayer insulating layer 45. The lower surface 13c is connected to the sidewalls 13a and 13b and is in contact with the field plate insulating layer 40 in the -Z direction. Furthermore, in the semiconductor device 100 of this embodiment, a vertex 70 facing the -Z direction is formed near the center of the lower surface 13c. Vertex 70 is the lowest point or minimum value in the -Z direction on the lower surface 13c.

[0051] Next, through Figure 2 The structural features of the field plate insulation layer 40 are described.

[0052] The field plate insulating layer 40 has a first insulating layer 41 connected to the n-type drift layer 20, a second insulating layer 42 disposed between the first insulating layer 41 and the field plate electrode 30, and a third insulating layer 43 disposed between the second insulating layer 42 and the field plate electrode 30. The second insulating layer 42 is located between the first insulating layer 41 and the third insulating layer 43, so the field plate insulating layer 40 has a three-layer structure.

[0053] Furthermore, generally speaking, sharp vertices 70 tend to concentrate the electric field due to the abrupt change in electric field. Therefore, it is desirable for the vertex 70 to be positioned near the center in the X direction of the field plate insulating layer 40. For example, if the vertex 70 is formed at a location adjacent to the side 13a, the electric field tends to concentrate near the lower end of the thin gate insulating layer 44 in the X direction. Thus, to prevent the electric field from concentrating in the thin insulating layer, the vertex 70 may also be adjacent to the second insulating layer 42.

[0054] (Manufacturing method of semiconductor device 100)

[0055] Next, refer to Figures 3 to 16 The manufacturing process of the semiconductor device 100 of this embodiment will be described. Figures 3 to 16 This is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to this embodiment.

[0056] First, such as Figure 3 As shown, an n-type drift layer 20 is formed on top of the n-type drain layer 21. Furthermore, the n-type drain layer 21 has a higher n-type impurity concentration than the n-type drift layer. The n-type impurity concentration of the n-type drain layer 21 is, for example, 1 × 10⁻⁶. 17 cm －3 Above 5×10 17 cm －3 the following.

[0057] Next, as Figure 4 As shown, multiple trenches U extending in the -Z direction are formed from the upper surface of the n-type drift layer 20 into the n-type drift layer 20 by means of reactive ion etching (RIE).

[0058] Next, as Figure 5 As shown, a field plate insulating layer 40 is formed by sequentially forming a first insulating layer 41, a second insulating layer 42, and a third insulating layer 43 on the entire inner surface of the upper surface including the n-type drift layer 20 and the side and bottom surfaces of the trench U. The field plate insulating layer 40 consists of three layers of insulating films with different etching rates in wet etching that are connected to each other.

[0059] Specifically, compared to the first insulating layer 41 and the third insulating layer 43, the second insulating layer 42 is composed of an insulating film with a faster etching rate in wet etching.

[0060] For example, as insulating films with slow etching rates, SiN (Silicon Nitride) films, D-SiN (Dual Frequency Silicon Nitride) films, SInSiN (Semi Insulated Silicon Nitride) films, and SiON (Silicon Oxynitride) films, which are semi-insulating silicon nitride films, are used in the first insulating layer 41 and the third insulating layer 43. Additionally, D-SiN is a SiN film formed using plasma CVD with plasmas at two frequencies.

[0061] Compared to silicon oxide films that can be deposited using conventional CVD (Chemical Vapor Deposition) methods, silicon nitride films such as SiN, D-SiN, and SInSiN have a denser structure and exhibit slower etching rates when wet-etched.

[0062] That is, the second insulating layer 42 is a silicon oxide film, and the first insulating layer 41 and the third insulating layer 43 are silicon nitride films. In addition, in the second insulating layer 42, as an insulating film with a fast wet etching rate, a silicon oxide film containing phosphorus and boron (Boron Phosphorus Silicon Glass: BPSG) can also be used, for example.

[0063] The formation sequence of the above-mentioned insulating film is, for example, forming the second insulating layer 42 after forming the first insulating layer 41, and finally forming the third insulating layer 43.

[0064] The first to third insulating layers are not limited to the above-described embodiments, and can be formed from a film having the characteristic that the wet etching rate of the first insulating layer 41 and the third insulating layer 43 is slower than the etching rate of the second insulating layer 42.

[0065] Next, the field plate electrode 30 is formed. For example... Figure 6 As shown, the conductive layer 30a is formed on the upper surface, i.e., the first surface 40a, of the field plate insulating layer 40 by CVD in a manner that embeds it in the trench U. The conductive layer 30a is, for example, polycrystalline silicon, and as conductive impurities, it contains, for example, phosphorus and boron.

[0066] Next, as Figure 7 As shown, the conductive layer 30a is removed by RIE in such a way that a portion remains in the trench U, forming the field plate electrode 30.

[0067] Next, the field plate insulating layer 40 is selectively etched using wet etching, causing it to recede from the upper surface of the n-type drift layer 20 in the -Z direction, thus exposing the upper surface of the n-type drift layer 20. Furthermore, by performing etching, such as... Figure 8 As shown, a groove 60 is formed at the upper end of the field plate insulating layer 40 within the trench U. The groove 60 is formed at the upper end of the field plate insulating layer 40 in the Z direction. The groove 60 is disposed inside the trench U, and is located in the X direction between the field plate electrode 30 and the n-type drift layer 20, facing each other.

[0068] In this embodiment, the desired shape of the groove 60 is formed by utilizing the different etching rates during wet etching of the first to third insulating layers constituting the field plate insulating layer 40. That is, the field plate insulating layer 40 is composed of three layers and has the characteristic that the etching rate of the second insulating layer 42 is faster during wet etching compared to the first insulating layer 41 and the third insulating layer 43. Therefore, the etching of the second insulating layer 42 is performed more quickly.

[0069] Furthermore, by using an etchant selective for polysilicon, the field plate insulating layer 40 is selectively etched without etching the field plate electrode 30. Moreover, an etchant with a faster etching rate for the second insulating layer 42 compared to the first insulating layer 41 and the third insulating layer 43 is used. When the second insulating layer 42 is a silicon oxide film and the first insulating layer 41 and the third insulating layer 43 are silicon nitride films, an etchant with a fast etching rate for silicon oxide films, such as hydrofluoric acid, can be used. For example, if the hydrofluoric acid concentration is 37% and the temperature is 65 degrees Celsius, the etching rate for the silicon oxide film is approximately 45 nm / sec, and the etching rate for the silicon nitride film is approximately 3 nm / sec. Thus, the etching rate ratio can be adjusted according to the concentration and temperature. Additionally, when the first insulating layer 41 and the third insulating layer 43 are SiON films, the etching rate can be slowed down by increasing the nitrogen ratio.

[0070] Figure 9 It shows the result of Figure 8 Part B is enclosed by the dotted line. For example... Figure 9 As shown, a trench 60 for forming the gate electrode 13 is formed on the upper end of the field plate insulating layer 40 by wet etching. The trench 60 has an upper surface 41a of a first insulating layer 41, an upper surface 42a of a second insulating layer 42, and an upper surface 43a of a third insulating layer 43.

[0071] according to Figure 9 The upper surface 42a of the second insulating layer 42 is located in the -Z direction closer than the upper surface 41a of the first insulating layer 41 and the upper surface 43a of the third insulating layer 43. At this time, the n-type drift layer 20 is exposed on the sidewall of the trench U.

[0072] Next, the upper surface of the n-type drift layer 20, the side surface of the n-type drift layer 20 exposed on the sidewall of the trench U, and the upper and side surfaces of the field plate electrode 30 are oxidized through a heat-based oxidation process. For example... Figure 10 As shown, a new gate insulating layer 44 is formed, covering the upper surface of the n-type drift layer 20 and the side surface of the n-type drift layer 20 exposed on the sidewall of the trench U, and a first interlayer insulating layer 45 is formed, covering the upper part of the field plate electrode 30. At this time, the upper surface of the field plate insulating layer 40 is also oxidized.

[0073] In addition, during the formation of the first interlayer insulating layer 45, a portion of the field plate electrode 30 is oxidized, leaving a narrower upper end portion 30c of the field plate electrode.

[0074] Next, as Figure 11 As shown, a conductive layer 13a is formed by CVD by embedding it into the n-type drift layer 20 and the trench portion 60 of the trench U. This conductive layer 13a contains polycrystalline silicon. The conductive layer 13a may contain conductive impurities such as phosphorus or boron.

[0075] Next, as Figure 12 As shown, the conductive layer 13a is etched to form the gate electrode 13 on the field plate insulating layer 40. At this time, the conductive layer 13a is etched back until the first interlayer insulating layer 45 is exposed. The gate electrode 13 is formed between the upper end portion 30c of the field plate electrode and the n-type drift layer 20. A pair of gate electrodes 13 are arranged side-by-side, sandwiching the upper end portion 30c of the field plate electrode.

[0076] Next, as Figure 13 As shown, a p-type substrate layer 24 is formed on top of the n-type drift layer 20. For example, p-type impurities are ion-implanted into the upper surface of the n-type drift layer 20, and then activated by heat treatment. The p-type impurities diffuse to a specified depth during the heat treatment process.

[0077] Next, an n-type source layer 26 is formed on top of the p-type substrate layer 24. The n-type source layer 26 faces the upper end of the gate electrode 13 in the X direction, separated by the gate insulating layer 44. The n-type source layer 26 is formed, for example, by selectively ion implanting n-type impurities from the upper surface of the p-type substrate layer 24 and performing heat treatment to activate it. The lower end of the n-type source layer 26 in the -Z direction overlaps with the upper end of the gate electrode 13 in the X direction.

[0078] Next, a p-type contact layer 25 is formed on top of the p-type substrate layer 24. The p-type contact layer 25 is formed, for example, by selectively ion implanting p-type impurities from the upper surface of the p-type substrate layer 24 and activating it by performing heat treatment. The p-type contact layer 25 is arranged side by side with the n-type source layer 26 in the X direction.

[0079] Next, as Figure 14 As shown, an insulating layer 46a covering the trench U is formed on the gate electrode 13, the field plate electrode 30, the n-type source layer 26, and the p-type base layer 24. Then, as... Figure 15 As shown, a portion of the insulating layer 46a on the n-type source layer 26 and the p-type base layer 24, as well as a portion of the gate insulating layer 44, are removed to form a second interlayer insulating layer 46.

[0080] Next, as Figure 16 As shown, a source electrode 14 is formed on the upper part of the n-type source layer 26 and the p-type contact layer 25.

[0081] Furthermore, a drain electrode 10 is formed under the n-type drain layer 21. Through the above processes, a manufacturing process is achieved. Figure 1 The semiconductor device 100 shown.

[0082] [First Comparative Example]

[0083] Next, Figure 17 This is a schematic cross-sectional view of the semiconductor device 200 of the first comparative example.

[0084] Compared to the semiconductor device 100 of the first embodiment, the semiconductor device 200 has a different cross-sectional shape for the gate electrode 15. Furthermore, the field plate insulating layer 48 is composed of a single layer. Alternatively, the field plate insulating layer 48 may be a double layer.

[0085] By amplifying the Figure 17 The part C enclosed by the dashed line Figure 18 The structure of the gate electrode 15 of the semiconductor device 200 will be described.

[0086] The gate electrode 15 of the semiconductor device 200 has a sidewall 15b that is connected to the field plate electrode 30 through a first interlayer insulating layer 45, and a sidewall 15a that is connected to a portion of the n-type drift layer 20, the p-type base layer 24 and the n-type source layer 26 through a gate insulating layer 44.

[0087] In the semiconductor device 200, the vertex 70 in the -Z direction formed on the lower surface 15c of the gate electrode 15 is located at the connection between the sidewall 15a and the lower surface 15c.

[0088] Figure 18 The cross-sectional structure of the gate electrode of the semiconductor device 200 shown is, for example, formed in the portion of the field plate electrode 30 that is led out onto the surface of the drift layer 20 at the boundary region between the element region and the terminal region. When the field plate electrode 30 is etched by RIE, the portion of the field plate electrode 30 that is led out onto the surface of the drift layer 20 is protected in the terminal region using a photoresist or the like. In this state, when the field plate insulating layer 48 is etched by RIE, it is believed that residues of the photoresist applied in the terminal region have an impact.

[0089] In the first comparative example, a field plate insulating layer 48 consisting of one or two layers is used. Alternatively, the field plate insulating layer 48 may be any of the first to third insulating layers used in the first embodiment.

[0090] Figure 19 A schematic cross-sectional view of the first comparative example is shown after the field plate insulating layer 48 has been retreated in the -Z direction by wet etching. Figure 19 As shown, the exposed sidewall of the n-type drift layer 20 in the trench U is deeper in the -Z direction than the exposed sidewall of the opposing field electrode 30 in the X direction. As previously mentioned, this is the effect of resist residue on the etching of the RIE. In other words, the etching of the insulating layer 48 along the sidewall of the field electrode 30, which is near the resist residue, proceeds slowly, while the etching of the insulating layer 48 along the sidewall of the trench U proceeds easily. As a result, the cross-sectional shape of the gate electrode buried in the trench 61 is different.

[0091] For the reasons mentioned above, such as Figure 18As shown, compared to the first embodiment, the semiconductor device 200 has a structure in which the sharp vertex 70 of the gate electrode 15 is formed along the sidewall 15a. This structure causes electric field concentration near the extremely thin insulating layer such as the gate insulating layer 44, which cannot ensure sufficient insulation withstand voltage and increases the risk of product damage.

[0092] [Effects of the First Embodiment]

[0093] According to the first embodiment, the field plate insulating layer 40 is easily etched in the center in the X direction. Therefore, it is difficult to form sharp vertices 70 in the -Z direction of the sidewalls 13a and 13b of the gate electrode 13.

[0094] Furthermore, in the semiconductor device 100 of the first embodiment, even if a sharp vertex 70 is formed at the lower end of the gate electrode 13 along the central portion of the field plate insulating layer 40, it is possible to ensure that the vertex 70 of the gate electrode 13, which generates a concentrated electric field, is in line with n. － The thickness of the field plate insulation layer between the drift layers is thicker than that of the first comparative example.

[0095] As described in detail above, in the semiconductor device 100 of the first embodiment, the position of the vertex 70, which is prone to electric field concentration, can be controlled, and the voltage withstand voltage reduction can be prevented.

[0096] While embodiments of the invention have been described, they are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are also included in the scope of the invention as described in the claims and its equivalents.

[0097] Explanation of reference numerals in the attached figures

[0098] 10 Drain electrode

[0099] 13, 15 Gate electrodes

[0100] 14 Source Electrode

[0101] 20 n-type drift layer

[0102] 21 n-type drain layer

[0103] 24 p-type basal layer

[0104] 25 p-type contact layer

[0105] 26 n-type source layer

[0106] 30, 30a field plate electrodes

[0107] 30C field plate electrode upper end

[0108] 40 3-layer field plate insulation layer

[0109] 41 First Insulation Layer

[0110] 42 Second Insulation Layer

[0111] 43 Third Insulation Layer

[0112] 44 Gate insulating layer

[0113] 45 First interlayer insulation layer

[0114] 46 Second interlayer insulation layer

[0115] 48 1-layer field plate insulation layer

[0116] 60 and 61 grooves

[0117] 13a and 13b sidewalls

[0118] 13c lower surface

[0119] 15a, 15b sidewalls

[0120] 15c lower surface

[0121] 70 vertices

Claims

1. A semiconductor device, characterized by comprising: having: a first electrode; a second electrode; a first semiconductor layer of a first conductivity type provided between the first electrode and the second electrode and electrically connected to the first electrode; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type provided between the second semiconductor layer and the second electrode and electrically connected to the second electrode; a field plate electrode extending in a first direction from the first semiconductor layer toward the second semiconductor layer in the first semiconductor layer; a field plate insulating layer provided between the first semiconductor layer and the field plate electrode; a gate electrode having a first side surface opposite the second semiconductor layer, a second side surface opposite the first side surface, and a first surface connected to the first side surface and the second side surface and in contact with the field plate insulating layer, the first surface having an apex projecting in a direction opposite the first direction at a position away from the first side surface and the second side surface; a first interlayer insulating layer provided between the field plate electrode and the gate electrode; and a second interlayer insulating layer provided between the gate electrode and the second electrode.

2. The semiconductor device according to claim 1, wherein the field plate insulating layer has: a first insulating layer in contact with the first semiconductor layer; a second insulating layer provided between the first insulating layer and the field plate electrode; and a third insulating layer provided between the second insulating layer and the field plate electrode.

3. The semiconductor device according to claim 2, wherein the apex is a lowermost point of the first surface and is in contact with the second insulating layer.

4. The semiconductor device according to claim 2, wherein the first insulating layer and the third insulating layer are silicon nitride films, and the second insulating layer is a silicon oxide film.

5. The semiconductor device according to claim 2, wherein the first insulating layer and the third insulating layer have an etching rate in a first etching process slower than an etching rate of the second insulating layer in the first etching process.

6. The semiconductor device according to claim 1, further comprising a fourth semiconductor layer of the first conductivity type having a higher impurity concentration than the first semiconductor layer between the first semiconductor layer and the first electrode.

7. The semiconductor device according to claim 1, further comprising a fifth semiconductor layer of the second conductivity type having a higher impurity concentration than the second semiconductor layer between the second semiconductor layer and the second electrode. including the steps of: forming a trench extending from a second surface of a first semiconductor layer of a first conductivity type having a first surface on which a first electrode is provided and a second surface on which a second electrode is provided toward the first electrode; forming a first insulating layer so as to cover a side wall of the trench; forming a second insulating layer having an etching rate based on wet etching faster than the first insulating layer on the first insulating layer; forming a third insulating layer having an etching rate based on the wet etching slower than the second insulating layer on the second insulating layer; and ​ ​ ​ ​ ​ ​ ​ 8. A method for manufacturing a semiconductor device, characterized by ​ ​ ​ ​ ​ a field plate electrode is embedded in the trench across the third insulating layer; by the wet etching, the upper end of each of the first insulating layer, the second insulating layer, and the third insulating layer is made to be distanced from the second surface in a direction opposite to the first direction, and a part of the side wall of the trench and a part of the field plate electrode are exposed; a part of the exposed side wall of the trench and the exposed part of the field plate electrode are oxidized; and a gate electrode is formed on the upper end of each of the first insulating layer, the second insulating layer, and the third insulating layer.

9. The method of manufacturing a semiconductor device according to claim 8, wherein the first insulating layer and the third insulating layer are silicon nitride films, and the second insulating layer is a silicon oxide film.

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