Semiconductor device and manufacturing method

Abstract

The invention provides a semiconductor device and a method of forming the semiconductor device. A semiconductor device includes a first termination trench at a first edge region and a second termination trench at a second edge region. A first active trench extends from the first termination trench toward the second termination trench and terminates in a first tip region that is separated from the second termination trench by a termination mesa region. A second active trench extends from the second termination trench toward the first termination trench and terminates in a second tip region that is separated from the first termination trench by the termination mesa region. A first gate contact trench is connected to the first termination trench within the first edge region. A coupling trench is located at the third edge region and connected to the second termination trench, the coupling trench including a corner portion coupling the coupling trench to the first gate contact trench.

Description

Technical Field

[0001] This disclosure relates generally to electronic devices, and more specifically to semiconductor device structures and methods of forming semiconductor devices. Background Technology

[0002] As the size of semiconductor devices, such as shielded-gate trench metal-oxide-semiconductor (MOSFET) devices, shrinks, it becomes increasingly difficult to integrate additional shielding contact structures within the MOSFET cell topology to achieve reduced shielding electrode resistance without adversely affecting other MOSFET characteristics. Low shielding resistance is required to provide MOSFETs with low gate transition, good unclamped inductive switching (UIS) performance, and high operating efficiency. For the device to function properly, structures and methods are needed that contribute to reducing shielding resistance without adversely affecting the device's breakdown voltage. Summary of the Invention

[0003] In a first aspect, a semiconductor device is provided, comprising: a semiconductor material region. The semiconductor material region includes: a top side; an active mesa region; a terminating mesa region; a cross mesa region; a first edge region at the top side; a second edge region at the top side opposite to the first edge region; and a third edge region at the top side extending between the first edge region and the second edge region. The semiconductor device further includes: a first terminating trench located within the first edge region; a second terminating trench located within the second edge region and coupled to the first terminating trench; a first active trench extending from the first terminating trench toward the second terminating trench and terminating at a first tip region, the first tip region being separated from the second terminating trench by the terminating mesa region; a second active trench extending from the second terminating trench toward the first terminating trench, separating from the first active trench by the active mesa region, and terminating at a second tip region, the second tip region being separated from the first terminating trench by the terminating mesa region; and a first gate contact trench, the first gate... A gate contact trench is coupled to a first termination trench within a first edge region; a coupling trench is located within a third edge region, coupled to a second termination trench, and includes a corner portion coupling the coupling trench to the first gate contact trench, the corner portion being separated from the first termination trench by a cross-plate region; a shielding electrode is located within the coupling trench; a shielding dielectric is located within the coupling trench, insulating the shielding electrode from the semiconductor material region; a gate electrode is located within the coupling trench; a gate dielectric is located within the coupling trench, insulating the gate electrode from the semiconductor material region; and an inter-electrode dielectric is located within the inter-electrode dielectric, insulating the gate electrode from the shielding electrode.

[0004] In a second aspect, a semiconductor device is provided, the semiconductor device comprising: a semiconductor material region, the semiconductor material region including: a top side; an active mesa region; a terminating mesa region; a cross mesa region; a first edge region at the top side; a second edge region at the top side opposite to the first edge region; and a third edge region at the top side extending between the first edge region and the second edge region. The semiconductor device further includes a first termination trench located within a first edge region; a second termination trench located within a second edge region and coupled to the first termination trench; a first active trench extending from the first termination trench toward the second termination trench and terminating at a first tip region, the first tip region being separated from the second termination trench by a termination mesa region; a second active trench extending from the second termination trench toward the first termination trench, intersecting with the first active trench, being separated from the first active trench by an active mesa region, and terminating at a second tip region, the second tip region being separated from the first termination trench by a termination mesa region; and a first gate contact trench coupled to the first termination trench within the first edge region. A coupling trench, located within a third edge region, coupled to a second termination trench and including a corner portion coupling the coupling trench to a first gate contact trench, the corner portion being separated from the first termination trench by a cross-mesa region; a shielding electrode, located within the coupling trench; a shielding dielectric, located within the coupling trench, insulating the shielding electrode from a semiconductor material region; a gate electrode, located within the coupling trench, including a first side adjacent to the termination mesa region and a second side opposite to the first side; a gate dielectric, located within the coupling trench, insulating the first side of the gate electrode from the cross-mesa region, wherein the shielding dielectric insulates the second side of the gate electrode from the semiconductor material region; and an inter-electrode dielectric, the inter-electrode dielectric insulating the gate electrode from the shielding electrode.

[0005] Thirdly, a method for providing a semiconductor device is provided, the method comprising: providing a semiconductor material region; providing a first termination trench located within the semiconductor material region; providing a second termination trench located within the semiconductor region and coupled to the first termination trench, wherein the first termination trench and the second termination trench provide an active region; providing an active trench located within the active region; providing a coupling trench located within the semiconductor material region and outside the active region; and providing a shielding conductor located within the coupling trench, the active trench, the first termination trench, and the second termination trench; and providing... A gate conductor is provided, located within a coupling trench, an active trench, a first termination trench, and a second termination trench; a shielding contact trench is provided, coupled to the first termination trench; a shielding contact via is provided, located within the shielding contact trench, outside the active region, and coupled to the shielding conductor; a gate contact trench is provided, coupled to the first termination trench; and a gate contact via is provided, located within the gate contact trench and coupled to the gate conductor; wherein: the gate conductor is a continuous and uninterrupted conductor within the active region; and the coupling trench couples the active region to the gate contact trench. Attached Figure Description

[0006] Figure 1 A top partial plan view illustrating an example cell topography of a semiconductor device according to this specification is shown;

[0007] Figure 2 Examples are given according to this specification. Figure 1 A magnified top view of section 2A mentioned above;

[0008] Figure 3 Examples are given according to this specification. Figure 1 A magnified top view of section 3A mentioned above;

[0009] Figure 4 Examples along Figure 2 A partial cross-sectional view of a semiconductor device with an example cell topography taken from reference line 4A-4A;

[0010] Figure 5 Examples along Figure 3 A partial cross-sectional view of a semiconductor device with an example cell topography taken from reference line 5A-5A;

[0011] Figure 6 A top partial plan view illustrating an example cell topography of a semiconductor device according to this specification is shown;

[0012] Figure 7 A top partial plan view illustrating an example cell topography of a semiconductor device according to this specification is shown;

[0013] Figure 8 Examples along Figure 6 A partial cross-sectional view of an example shielding contact trench taken from reference line 8A-8A;

[0014] Figure 9 Examples along Figure 7 A partial cross-sectional view of an example shielding contact trench taken from reference line 9A-9A;

[0015] Figure 10 A top partial plan view illustrating an example cell topography of a semiconductor device according to this specification is shown;

[0016] Figure 11 A top partial plan view illustrating an example cell topography of a semiconductor device according to this specification is shown;

[0017] Figure 12 A top partial plan view illustrating an example cell topography of a semiconductor device according to this specification is shown; and

[0018] Figure 13 A partial cross-sectional view of an example semiconductor device according to this specification is shown.

[0019] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. These examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0020] To keep the illustrations simple and clear, the components in the figures may not be drawn to scale, and the same reference numerals in different figures indicate the same components. Additionally, for the sake of brevity, descriptions and details of well-known steps and components have been omitted.

[0021] For clarity of the accompanying drawings, certain regions of the device structure, such as doped or dielectric regions, trenches, or contacts, may be illustrated as having generally straight edges and corners with precise angles. However, those skilled in the art will understand that the edges of such regions may not typically be straight and the corners may not have precise angles due to the diffusion and activation of dopants or the formation of layers.

[0022] Although semiconductor devices are interpreted herein as having certain N-type conductive regions and certain P-type conductive regions, those skilled in the art will understand that the conductivity type can be reversed, and that, in accordance with this specification, any necessary reversal of voltage polarity, transistor type, and / or current direction can also be taken into account.

[0023] Furthermore, the terminology used herein is for the purpose of describing particular examples only and is not intended to limit this disclosure. As used herein, the singular form is intended to also include the plural form unless otherwise expressly indicated in the context.

[0024] As used herein, “current-carrying electrode” refers to a component within a device that carries current through the device, such as the source or drain of a MOS transistor, the emitter or collector of a bipolar transistor, or the cathode or anode of a diode, and “control electrode” refers to a component within a device that controls the current flowing through the device, such as the gate of a MOS transistor or the base of a bipolar transistor.

[0025] Additionally, when used in conjunction with a semiconductor region, wafer, or substrate, the term "master surface" refers to the surface of a semiconductor region, wafer, or substrate that forms an interface with another material such as a dielectric, insulator, conductor, or polycrystalline semiconductor. The master surface can have a morphology that varies along the x, y, and z directions.

[0026] Furthermore, the structure of the present invention can be embodied in a cellular base design (where the main area consists of multiple different and separate cellular or strip-shaped areas) or a single base design (where the main area is a single area formed by an elongated pattern, generally in the form of a serpentine pattern or a central portion with connecting appendages). However, for ease of understanding, one embodiment of this specification will be described throughout as a cellular base design. It should be understood that this specification covers both cellular base designs and single base designs.

[0027] When used in this specification, the terms “comprising,” “including,” “having,” and / or “containing” are open-ended terms that specify the presence of the stated features, numbers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or groups thereof.

[0028] The term "or" refers to any one or more items in a list connected by "or". For example, "x or y" refers to any element in the three-element group {(x),(y),(x,y)}. Similarly, "x, y or z" refers to any element in the seven-element group {(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}.

[0029] Although the terms “first,” “second,” etc., may be used herein to describe various components, elements, regions, layers, and / or segments, these components, elements, regions, layers, and / or segments should not be limited by these terms. These terms are used only to distinguish one component, element, region, layer, and / or segment from another component, element, region, layer, and / or segment. Therefore, without departing from the teachings of this invention, for example, the first component, first element, first region, first layer, and / or first segment discussed below may be referred to as a second component, second element, second region, second layer, and / or second segment.

[0030] Those skilled in the art will understand that the phrases “during,” “at the same time,” and “when” used herein in relation to circuit operation do not precisely refer to an action occurring immediately after the initiation of the action, but rather to a possible small but reasonable delay, such as a propagation delay, between the responses triggered by the initial action. Additionally, the term “at the same time” means that an action occurs at least for a period of time during the duration of the initiation of the action.

[0031] The terms “about,” “approximately,” or “basically” are used to indicate that the value of a component is expected to be close to the declared value or position. However, it is well known in the art that there are always some small deviations that prevent the value or position from being exactly the declared value or position.

[0032] Unless otherwise specified, the phrases “above” or “on” as used herein include the orientation, placement, or relationship in which the specified element may be in direct or indirect physical contact.

[0033] Unless otherwise specified, as used herein, the phrase “overlapping with” includes the orientation, placement, or relationship in which the specified elements can at least partially or completely coincide or align on the same or different planes.

[0034] It should also be understood that the examples exemplified and described below may have examples lacking any elements not expressly disclosed herein, and / or may be implemented in the absence of any elements not expressly disclosed herein. Detailed Implementation

[0035] Insulated-gate field-effect transistors (IGFETs), such as metal-oxide-semiconductor field-effect transistors (MOSFETs), are used in many power switching applications, such as DC-DC converters. In a typical MOSFET, the gate electrode provides turn-on and turn-off control by applying an appropriate gate voltage. For example, in an N-type enhancement-mode MOSFET, turn-on occurs when a conductive N-type inversion layer (i.e., the channel region) is formed in the P-type body region in response to the application of a positive gate voltage exceeding its intrinsic threshold voltage. The inversion layer connects the N-type source region to the N-type drain region and allows majority carrier conduction between these regions.

[0036] There exists a class of MOSFET devices known as trench MOSFETs. In a trench MOSFET, the gate electrode is formed in a trench extending downward (e.g., vertically downward) from the main surface of a semiconductor material such as silicon. Current flow in a trench MOSFET is primarily vertical (e.g., in the N-type conductivity doped drift region), and therefore, device cells can be packaged more densely. Packaging several device cells together increases current carrying capacity and reduces the on-resistance of the device.

[0037] Device cells may, for example, include a trench containing a gate electrode and an adjacent semiconductor mesa containing the drain, drift region, source, body, and channel region of the device. An example trench MOSFET device may comprise an array of hundreds or thousands of device cells (each including a trench and an adjacent mesa). Device cells may be referred to herein as trench-mesa cells because each device cell geometrically comprises a trench structure and a mesa structure (or two half-mesas).

[0038] Trench MOSFET devices may also include a shielding electrode formed in the trench below the gate electrode and insulated from the gate electrode by one or more dielectrics. In some examples, the shielding electrode may be coupled to the source electrode of the device. The shielding electrode has several advantages, including promoting a higher doping concentration in the drift region, and provides a shielding effect that can improve switching capability and other performance parameters. However, the shielding electrode may require low shielding resistance to provide low gate transition, good unclamped inductive switching (UIS) performance, and higher efficiency, among other things.

[0039] In some applications, such as motor drive applications, device robustness, including the ability to withstand short bursts of high current, has become increasingly important. Because high shielding resistance at device edges leads to high current integration (UIS), there is a need to provide structures and methods with low shielding resistance at device edges to meet increasingly stringent performance requirements.

[0040] Current trench MOSFET termination structures for medium-voltage devices (e.g., voltages between approximately 30 volts and approximately 100 volts) have shown improved breakdown voltage (BV). DSS While this approach offers performance advantages, it doesn't yet support low shielding resistance at the device edges without other structural changes. Such structural changes could include additional shielding feeds, which can be up to 30 micrometers wide and must completely surround the entire device edge. Unfortunately, this approach leads to an undesirable increase in die size or other device parameter degradation.

[0041] One type of termination structure used in trench MOSFET devices is called a gate-terminated trench (GTT) structure. This GTT structure uses a connected trench termination design, which helps reduce the effects of electric field buildup under blocking or reverse bias conditions. Some GTT designs have shown improvements in supporting high-current UIS, but at least in medium-voltage devices (e.g., voltages between approximately 30 volts and approximately 100 volts), the BV... DSS This aspect also exhibits unacceptable degradation. Therefore, it is necessary to address BV. DSS This kind of deterioration in structure and method.

[0042] Generally, this example relates to semiconductor device structures and methods for fabricating semiconductor devices (such as shielded gate trench MOSFET devices) with improved manufacturability and performance. In some examples, methods for addressing the BV in a GTT structure using an arched termination design are described. DSS Structures and methods for addressing performance issues. Examples include GTT-type cell topologies with staggered or offset comb-shaped active trenches, arched termination designs, and coupling trenches. The coupling trenches connect to one side of the cell topology and include a surrounding top trench that connects to a gate contact trench on the opposite side of the cell topology. The coupling trenches may also form additional termination trenches to promote design flexibility. In some examples, gate connections may be provided on the opposite side of the cell topology to reduce gate resistance.

[0043] In some examples, shielding electrode connections are also facilitated on opposite edges or opposite sides of the cell topology, which reduces shielding resistance. In some examples, for a given cell topology length, the structure of the present invention reduces the shielding resistance by approximately half. Shielding electrode connections are provided without interrupting the connections between active gate trenches and the gate electrode connections (which are outside the region of the topology forming source metal contacts) compared to previous cell topologies. Furthermore, this specification provides shielding electrode contacts within the region of the topology forming source metal contacts. Examples of providing additional shielding contacts within the cell topology to further improve shielding resistance performance are also described. The cell topology also facilitates gate connections from one side or opposite sides or both sides. In some examples, a gate silicide structure can be used to offset any increase in gate resistance.

[0044] In one example, the semiconductor device includes a semiconductor material region comprising a top side, an active mesa region, a terminating mesa region, a cross mesa region, a first edge region at the top side, a second edge region at the top side opposite to the first edge region, and a third edge region at the top side extending between the first and second edge regions. A first terminating trench is located within the first edge region, and a second terminating trench is located within the second edge region and coupled to the first terminating trench. A first active trench extends from the first terminating trench toward the second terminating trench and terminates at a first tip region, which is separated from the second terminating trench by the terminating mesa region. A second active trench extends from the second terminating trench toward the first terminating trench, is separated from the first active trench by the active mesa region, and terminates at a second tip region, which is separated from the first terminating trench by the terminating mesa region. A first gate contact trench is coupled to the first terminating trench within the first edge region. A coupling trench is located within the third edge region, coupled to the second terminating trench, and includes a corner portion coupling the coupling trench to the first gate contact trench. The cross-plate area separates the corner portion from the first termination trench. The shielding electrode is located within the coupling trench, and the shielding dielectric is located within the coupling trench, insulating the shielding electrode from the semiconductor material region. The gate electrode is located within the coupling trench, and the gate dielectric is located within the coupling trench, insulating the gate electrode from the semiconductor material region. The inter-electrode dielectric insulates the gate electrode from the shielding electrode.

[0045] In one example, a semiconductor device includes a semiconductor material region comprising a top side, an active mesa region, a terminating mesa region, a cross-mesa region, a first edge region at the top side, a second edge region at the top side opposite to the first edge region, and a third edge region at the top side extending between the first and second edge regions. A first terminating trench is located within the first edge region, and a second terminating trench is located within the second edge region and coupled to the first terminating trench. A first active trench extends from the first terminating trench toward the second terminating trench and terminates at a first tip region, which is separated from the second terminating trench by the terminating mesa region. A second active trench extends from the second terminating trench toward the first terminating trench, intersects with the first active trench, is separated from the first active trench by the active mesa region, and terminates at a second tip region, which is separated from the first terminating trench by the terminating mesa region. A first gate contact trench is coupled to the first terminating trench within the first edge region. A coupling trench is located within the third edge region and coupled to the second terminating trench. The coupling trench includes a corner portion coupling the coupling trench to a first gate contact trench. The corner portion is separated from the first termination trench by a cross-mesa region. A shielding electrode is located in the coupling trench, and a shielding dielectric is located in the coupling trench and insulates the shielding electrode from the semiconductor material region. A gate electrode is located in the coupling trench and includes a first side adjacent to the termination mesa region and a second side opposite to the first side. A gate dielectric is located in the coupling trench and insulates the first side of the gate electrode from the cross-mesa region. The shielding dielectric insulates the second side of the gate electrode from the semiconductor material region. An inter-electrode dielectric insulates the gate electrode from the shielding electrode.

[0046] In one example, a method of manufacturing a semiconductor device may include: providing a semiconductor material region; providing a first termination trench located within the semiconductor material region; and providing a second termination trench located within the semiconductor region and coupled to the first termination trench, wherein the first and second termination trenches define an active region. The method includes: providing an active trench located within the active region; and providing a coupling trench located within the semiconductor material region and outside the active region. The method includes: providing a shielding conductor located within the coupling trench, the active trench, the first termination trench, and the second termination trench. The method includes: providing a gate conductor located within the coupling trench, the active trench, the first termination trench, and the second termination trench. The method includes: providing a shielding contact trench coupled to the first termination trench; and providing a shielding contact via located within the shielding contact trench, outside the active region, and coupled to the shielding conductor. The method includes: providing a gate contact trench coupled to a first terminating trench; and providing a gate contact via located within the gate contact trench and coupled to a gate conductor. The gate conductor is a continuous and uninterrupted conductor within an active region, and the coupling trench couples the active region to the gate contact trench. In another example, the method includes: providing an active region without any shielding contact vias.

[0047] In some examples, the semiconductor device includes a second gate contact trench coupled to a second termination trench within a second edge region and a first shield contact trench coupled to a first termination trench within a first edge region. In some examples, the first shield contact trench is parallel to the first gate contact trench. In some examples, the first shield contact trench is perpendicular to and intersects the first gate contact trench. In some examples, in a top plan view, the second gate contact trench is laterally offset relative to the first gate contact trench.

[0048] Other examples are included in this disclosure. Such examples can be seen in the drawings, the claims, and / or the description of this disclosure.

[0049] Figure 1 A partial top plan view of the cell topography 100 of the semiconductor device 10 according to this specification is shown. Figure 2 Examples Figure 1 The enlarged plan view of the top part of section 2A of the unit morphology 100 mentioned in the document, and Figure 3 Examples Figure 1 The enlarged plan view of the top part of section 3A of the unit morphology 100 mentioned in the document. Figure 4 Examples along Figure 2A partial cross-sectional view of a portion of the semiconductor device 10, taken along reference lines 4A-4A, and Figure 5 Examples along Figure 3 A partial cross-sectional view of another portion of the semiconductor device 10, taken along reference lines 5A-5A. References are used in the following description. Figures 1 to 5 .

[0050] Cell topology 100 may also be referred to as device layout, GTT cell topology, or cell layout, and semiconductor device 10 may also be referred to as semiconductor component, electronic device structure, or electronic component. In some examples, cell topology 100 is suitable for medium-voltage devices, such as 30-volt to 100-volt shielded gate trench MOSFET devices. However, the structures and methods described herein are relevant to shielded gate devices requiring low shielding resistance. Figure 1 In the top plan view, semiconductor device 10 conductors 44A and 44B are illustrated with dashed lines to better illustrate the structure below. Figure 1 , Figure 2 and Figure 3 The crosshairs in the diagram illustrate a top view of the gate conductor 28. In some examples, the gate conductor 28 in cell topology 100 is a continuous conductor without interruptions or breaks, which reduces gate resistance and simplifies the placement of gate contact structures (such as conductor 44B) in cell topology 100. In this example, the cell topology includes the top side 18 of the semiconductor device 10 (see, for example...). Figure 4 and Figure 5 The edge region 101 at the top side 18, the edge region 102 opposite to the edge region 101 at the top side 18, and the edge region 103 extending between the edge region 101 and the edge region 102. The edge region 101 may be an example of a first edge region or an upper edge region, the edge region 102 may be an example of a second edge region or a lower edge region, and the edge region 103 may be an example of a third edge region or an outer edge region.

[0051] According to this specification, semiconductor device 10 is configured to maintain breakdown voltage (BV) by adding coupling trench 22C. DSSSimultaneously, multiple shielding contact trenches 210 provide reduced shielding electrode resistance. These coupling trenches include corner portions 22CA coupled to gate contact trenches 280 located within edge regions 101 of the cell topology 100. The coupling trenches 22C are also configured to reduce shielding resistance at the edge regions of the semiconductor device 10 by providing additional shielding electrode channels. The semiconductor device 10 is shown as an N-channel MOSFET device; however, it should be understood that the structures and methods described herein can also be used for other types of semiconductor devices, such as insulated-gate bipolar transistor (IGBT) devices. In other examples, the semiconductor device 10 can be a P-channel MOSFET device by reversing the conductivity types of the various regions described below.

[0052] The element morphology 100 is illustrated as a partial element, and can be represented by... Figure 1 The cell continues to the right side to obtain the desired number of active trenches to provide a complete cell. In some examples, a second coupling trench may be added to the right side of cell topology 100. The second coupling trench may be a mirror image of coupling trench 22C, or may be vertically flipped so that the corner portion (e.g., corner portion 22CA) is close to the bottom side of cell topology 100. In one example, Figure 1 Some cells can be copied and flipped 180 degrees, and combined with the illustrated partial cells to provide a complete cell. As is known to those skilled in the art, cell morphology 100 is copied multiple times as part of a photomask set or mask group to provide the desired cell density for semiconductor device 10. In some examples, cell morphology is provided on or as part of semiconductor device 10 using photolithographic patterning techniques such as patterned photoresist and etching processes.

[0053] In this example, the unit topography 100 includes a trench region 22, which may include active trenches 22A, active trenches 22B, one or more coupling trenches 22C, a top terminating trench 22D, and a bottom terminating trench 22D'. In some examples, the trench region 22 is a continuous region, wherein the active trenches 22A, active trenches 22B, coupling trenches 22C, top terminating trenches 22D, and bottom terminating trenches 22D' are all connected to form a continuous trench structure. In this example, the top terminating trench 22D is located within the edge region 101, the bottom terminating trench 22D' is located within the edge region 102, and the coupling trenches 22C are located within the edge region 103. The active trench 22A is laterally separated from the active trench 22B through the active platform region 16A, and the tip regions 222 of the active trench 22A and the active trench 22B are separated from the top termination trench 22D and the bottom termination trench 22D' through the termination platform region 16B, respectively.

[0054] In some examples, conventional photo-patterning and etching techniques can be used to pattern the semiconductor material region 11 extending from the top side 18 (see [reference]). Figure 4 and Figure 5 A trench region 22 is provided within the semiconductor material region 11. When the semiconductor material region 11 comprises silicon, the trench region 22 may be provided using fluorine etching chemistry or similar chemistry known to those skilled in the art. In some examples, active trenches 22A and 22B, as well as coupling trench 22C, may have widths ranging from about 200 nanometers to about 2 micrometers. In some examples, the width is about 600 nanometers. In some examples, coupling trench 22C may have a width ranging from about 300 nanometers to about 3 micrometers. In some examples, the width of coupling trench 22C is greater than the widths of active trenches 22A and 22B.

[0055] Termination trench 22D can be an example of a first termination trench, and bottom termination trench 22D' can be an example of a second termination trench. Active trench 22A can be an example of a first active trench extending from the first termination trench toward the second termination trench. Active trench 22B can be an example of a second active trench extending from the second termination trench toward the first termination trench and separated from the first active trench through active platform region 16A.

[0056] In some examples, active trench 22A branches or extends from the top of trench 22D in a downward direction, and active trench 22B branches or extends from the bottom of trench 22D' in an upward direction. It should be understood that the terms downward and upward are used to aid this specification, but other terms describing orientation, such as first and second, or left and right (e.g., if cell morphology 100 is rotated 90 degrees), may be used.

[0057] In some examples, active trenches 22A and 22B extend in opposite directions relative to each other and are provided in an interleaved configuration, wherein active trenches 22A are coupled together by a top-terminal trench 22D and active trenches 22B are coupled together by a bottom-terminal trench 22D'. In some examples, the upper portion of cell profile 100 is offset relative to the lower portion of cell profile 100. For example, the gate contact trench 280 and shield contact trench 210 at the top side of cell profile 100 are not aligned with the gate contact trench 280 and shield contact trench 210 at the bottom side of cell profile 100. In other examples, the upper portion of cell profile 100 is not offset relative to the lower portion of cell profile 100. In some examples, active trenches 22A can be interposed between a pair of active trenches 22B, or active trenches 22B can be interposed between a pair of active trenches 22A. In this example, one of the active trenches 22A is set as the leftmost active trench or the left outermost active trench. In some examples, the active trench 22B is set as the rightmost active trench or the right outermost active trench of the cell topology 100. In this example, the active mesa region 16A separates the active trenches 22A and 22B.

[0058] In some examples, the top termination trench 22D and the bottom termination trench 22D' include an arched termination structure 51 adjacent to the tip regions 222 of the active trenches 22A and 22B. In some examples, the active trenches 22A and 22B may include, or be referred to as, shielded gate trench regions or elongated strip trench regions, and the top termination trench region 22D and the bottom termination region 22D' may include, or be referred to as termination trench regions, termination regions, or GTT regions. In this example, the arched termination structure 51 includes a concave structure or an inwardly rounded arch, and the tip region 222 includes a convex structure or an outwardly rounded arch. In this example, the termination mesa region 16B separates the tip region 222 from the arched termination structure 51. In some examples, in Figure 1 In the top plan view, the arched termination structure 51 in the top termination groove 22D is laterally offset relative to the arched termination structure 51 in the bottom termination groove 22D'.

[0059] like Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5As illustrated, active trenches 22A and 22B include a shielding dielectric 24, a shielding electrode 21, an inter-electrode dielectric 27, a gate dielectric 26, an upper trench dielectric 240, and a gate electrode 28. Furthermore, terminating trenches 22D and terminating trench 22D' include a shielding dielectric 24, a shielding electrode 21, an inter-electrode dielectric 27, an upper trench dielectric 240, and a gate electrode 28. In some examples, terminating trenches 22D and terminating trench 22D' include a gate dielectric 26 adjacent to the side of terminating trenches 22D and terminating trench 22D' near the active trenches 22A and 22B. In this example, terminating trenches 22D and 22D' include an upper trench dielectric 240 along the outer edge of cell topology 100, which includes a gate contact trench 280 and a shielding contact trench 210. According to this specification, the upper trench dielectric 240 is thicker than the shielding dielectric 24. The upper trench dielectric 240 is configured to provide a lower gate-to-drain capacitance.

[0060] Cell topology 100 also includes a gate contact trench 280 and a shield contact trench 210 located on the top and bottom sides of the cell topology 100. In this example, the gate contact trench 280 and the shield contact trench are generally parallel to each other and do not intersect. In this way, a lower shielding resistance can be provided compared to previous devices that use a single shield contact trench in the central portion of the topology. The gate contact trench 280 is coupled to the gate electrode 28 via a gate contact via 280A, and the shield contact trench 210 is coupled to the shield electrode 21 via a shield contact via 210A. More specifically, the gate contact via 280A and the shield contact via 210A couple the gate electrode 28 and the shield electrode 21 to conductors 44B and 44B, respectively. According to this specification, on the same side edge of the cell topology, the gate electrode 28 is continuous from the active trench 22A, the active trench 22B, and the terminating trenches 22D and 22D' to the gate contact trench 280. Furthermore, in the termination trenches 22D and 22D', the shielding electrode 21 is connected to the shielding contact trench 210 and extends below the gate electrode 28. Although the gate electrode 28 and the shielding electrode 28 are referred to as multiple electrodes, it should be understood that the gate electrode 28 and the shielding electrode 21 in the semiconductor device 10 can each be a single, uninterrupted, continuous conductive structure. In this example, the gate contact trench 280 has a longer length than the shielding contact trench 210, such that the conductor 44A can be conveniently coupled to both the shielding contact trench 210 and the source region 33 of the semiconductor device 10 via the conductive via 43. Furthermore, the conductor 44B can be conveniently coupled to the gate contact trench 280, which, in the top plan view, are located above the conductor 44A on the top side of the cell topology 100 and below the conductor 44A on the bottom side.

[0061] In some examples, the inner portion or active region of cell topology 100 between terminating trench 22D and terminating trench 22D' may not have shielded contact vias 210A. More specifically, in some examples, the only shielded contact trenches 210 or shielded contact vias 210A in cell topology 100 and semiconductor device 10 are those shielded contact trenches 210 or shielded contact vias 210A outside or outside the boundary defined by the top terminating trench 22D and the bottom terminating trench 22D'. In this way, the gate electrode 28 can be a continuous or uninterrupted structure inside or within the boundary defined by the top terminating trench 22D and the bottom terminating trench 22D'. Figure 1 An example of this configuration is illustrated below. In some examples, this reduces any impact on the gate resistance. In other examples, as will be described later, an additional shielding contact via 210A may be placed in the active region between the termination trench 22D and the termination trench 22D' or within the coupling trench 22C.

[0062] Termination trench 22D includes a corner portion 22DA, which is adjacent to the corner portion 22CA of coupling trench 22C and separated by a cross-mesa region 16C. At the location where corner portion 22DA couples with gate contact trench 280, the inner edge of the corner portion is spaced apart from the outer edge of corner portion 22DA by a distance 161. Experiments have shown that this distance 161 is a factor affecting the BV of semiconductor device 10. DSS Design variables. In some examples, distance 161 is greater than 600 nm. In some examples, distance 161 is greater than 700 nm. In some examples, distance 161 is greater than 800 nm. In some examples, distance 161 is greater than 900 nm. In some examples, distance 161 is greater than 1000 nm. In some examples, distance 161 is in the range of about 800 nm to about 1000 nm. In some examples, the width of the cross trench region 16C is different from the width of the active mesa region 16A and is generally wider than the width of the active mesa region. In some examples, in the top plan view, the sidewall 2801 of the gate contact trench 280 extending between the outer edge of the terminating trench 22D and the inner edge of the coupling trench 22C includes a straight, linear, or non-curved shape.

[0063] According to this instruction manual and reference Figure 1 and Figure 4 The coupling trench 22C provides an additional shielding electrode 21 portion or flow channel at the outer edge of the cell topology 100. In this way, the coupling trench 22C is configured to reduce the shielding resistance at the outer edge of the semiconductor device 10, which, experimentally, has been shown to improve device performance, including maintaining good BV. DSSWhile improving performance, the high-current UIS capability is also enhanced. Furthermore, experiments have shown that the cell topology 100 provides a semiconductor device 10 with lower resistance in its packaged form, and this, together with the improved high-current UIS capability, improves performance in motor control applications, including motor control applications. Additionally, the corner portion 22CA is configured to maintain the charge balance in the termination region of the semiconductor device 10, which helps maintain or improve BV. DSS performance.

[0064] refer to Figure 4 and Figure 5 In some examples, the semiconductor device 10 includes a semiconductor material region 11, which may also include or be referred to as a semiconductor material body, semiconductor workpiece, semiconductor region, or semiconductor material. In some examples, the semiconductor material region 11 includes silicon. In other examples, the semiconductor material region 11 or a portion thereof may include other semiconductor materials, including but not limited to silicon-germanium, silicon-germanium-carbon, carbon-doped silicon, silicon carbide, gallium nitride, or other related or equivalent materials known to those skilled in the art.

[0065] like Figure 4 and Figure 5 As illustrated, in some examples, the semiconductor material region 11 may include a substrate 12 (such as an N-type silicon substrate) and a semiconductor region 14 adjacent to the substrate 12. The substrate 12 may also be referred to as a semiconductor substrate or a starting substrate, and the semiconductor region 14 may also be referred to as a semiconductor layer or an extended drain region. In some examples, the substrate 12 has a resistivity ranging from about 0.0005 ohm-cm to about 0.005 ohm-cm. For example, the substrate 12 may be doped with phosphorus, arsenic, or antimony. In the illustrated examples, the substrate 12 provides a drain region, a drain contact, or a first current-carrying contact for the semiconductor device 10. The semiconductor material region 11 includes a main surface 18 and a main surface 19 opposite to the main surface 18. The main surface 18 may also be referred to as a front side or a top side, and the main surface 19 may also be referred to as a back side or a bottom side.

[0066] In some examples, semiconductor epitaxial growth techniques can be used to form semiconductor region 14. Alternatively, semiconductor doping and diffusion techniques can be used to form semiconductor region 14. In an example suitable for a 50-volt device, semiconductor region 14 may include N-type conductivity and approximately 1.0 x 10⁻⁶ volts. 16 Atoms per cubic centimeter to approximately 5.0 x 10⁻⁶ 17 The doping concentration is atoms per cubic centimeter, and the thickness can range from about 3 micrometers to about 5 micrometers. The doping concentration and thickness of semiconductor region 14 can be determined based on the desired drain-source breakdown voltage (BV) of semiconductor device 10. DSSThe value may be increased or decreased depending on the rating. In some examples, semiconductor region 14 may include a gradient dopant distribution. In an alternative example, the conductivity type of substrate 12 may be opposite to that of semiconductor region 14 to form, for example, an IGBT semiconductor device.

[0067] The shielding dielectric 24 can be one or more dielectric or insulating materials. In some examples, the shielding dielectric 24 can be a thermal oxide layer of about 0.1 micrometers to about 1.5 micrometers. In some examples, the shielding dielectric 24 can be multiple layers of similar or different materials, such as thermally deposited dielectrics or insulating materials. The thickness of the shielding dielectric will vary depending on the required BV of the device. DSS And the changes, BV DSS The higher the density, the thicker the required layers. According to some examples, the upper trench dielectric 240 is thicker than the shielding dielectric 24 and the inter-electrode dielectric 27. The upper trench dielectric 240 can be one or more dielectric or insulating materials. In some examples, the upper trench dielectric 240 can be a thermal oxide layer of about 0.2 micrometers to about 2 micrometers. In some examples, the upper trench dielectric 240 can be multiple layers of similar or different materials, such as thermally and deposited dielectrics or insulating materials.

[0068] The gate dielectric 26 and the inter-electrode dielectric 27 may comprise oxides, nitrides, tantalum pentoxide, titanium dioxide, barium strontium titanate, high-k dielectric materials, combinations thereof, or other related or equivalent materials known to those skilled in the art. In some examples, the gate dielectric 26 and the inter-electrode dielectric 27 may be silicon oxide. In some examples, the gate dielectric 26 may have a thickness from about 0.02 micrometers to about 0.1 micrometers, and the inter-electrode dielectric 27 may have a thickness greater than that of the gate dielectric 26. In some examples, the dielectric 24 may have a thickness greater than that of the gate dielectric 26 and the inter-electrode dielectric 27. According to some examples, the upper trench dielectric 240 is thicker than the shielding dielectric 24 and the inter-electrode dielectric 27.

[0069] In some examples, the gate electrode 28 and the shield electrode 21 comprise a doped polycrystalline semiconductor material, such as doped polycrystalline silicon. In some examples, an N-type conductive dopant material may be used to dope the polycrystalline silicon. In some examples, a metal, silicide, or other conductor may be included as part of the gate electrode 28 or the shield electrode 21.

[0070] like Figure 4 and Figure 5As further illustrated, the semiconductor device 10 includes a body region 31 extending inward from the main surface 18 into a semiconductor material region 11 (e.g., into a semiconductor region 14), the body region being adjacent to active trenches 22A and 22B. The body region 31 may also include, or be referred to as, a doped region or base region. The body region 31 may have a conductivity type opposite to that of the semiconductor region 14. For example, when the semiconductor region 14 includes N-type conductivity, the body region 31 includes P-type conductivity. The body region 31 includes a dopant concentration suitable for forming inversion layers that serve as channel regions of the semiconductor device 10. In some examples, the body region 31 may extend from the main surface 18 to a depth of about 0.3 micrometers to about 1.5 micrometers. Doping techniques such as ion implantation and annealing can be used to form the body region 31. In some examples, the body region 31 is a single, continuous, interconnected region. In other examples, the body region 31 may be multiple regions including separated regions.

[0071] The semiconductor device 10 may further include a doped region 33 located within the body region 31 in the active mesa region 16A. In some examples, the doped region 33 may optionally be included in the active mesa region 16A within the body region 31 and in a portion of the cross-mesa region 16C adjacent to the active trench 22A. In some examples, the doped region 33 is not included adjacent to the coupling trench 22C. In some examples, the doped region 33 is not included in the body region 31 in the terminating mesa region 16B, therefore the terminating mesa region 16B has no doped region 33. The doped region 33 may also be referred to as a source region, a current-carrying region, or a current-conducting region. When the body region 31 includes P-type conductivity, the doped region 33 includes N-type conductivity and may be formed using, for example, a phosphorus or arsenic dopant source. In some examples, an ion implantation doping process may be used to form the doped region 33 within the body region 31. The doped region 33 may extend from the main surface 18 to a depth of, for example, about 0.2 micrometers to about 0.5 micrometers.

[0072] In some examples, the semiconductor device 10 further includes an interlayer dielectric (ILD) 41 over the active gate electrode 28A, over the coupling gate electrode 28B, and over the cross gate electrode 28C. In some examples, the interlayer dielectric 41 comprises silicon oxide, such as doped or undoped deposited silicon oxide. In some examples, the interlayer dielectric 41 may comprise a deposited silicon oxide layer doped with phosphorus or boron and phosphorus and an undoped oxide layer. In some examples, the interlayer dielectric 41 may have a thickness of about 0.25 micrometers to about 1.0 micrometer. In some examples, the interlayer dielectric 41 may be planarized to provide a more uniform surface topography, which improves manufacturability.

[0073] In some examples, the semiconductor device 10 also includes a body contact region 36 within the body region 31. The body contact region 36 may also be referred to as a doped region, an enhanced region, or a contact region. In some examples, the body contact region 36 may include P-type conductivity and is configured to provide a lower contact resistance with the body region 31. The body contact region 36 may be formed using ion implantation (e.g., using boron) and annealing techniques.

[0074] In some examples, the semiconductor device 10 also includes a conductive region 43 configured to provide electrical contact with the doped region 33 and the body region 31 via a body contact region 36. An active gate electrode 28A, a coupled gate electrode 28B, and a cross-gate electrode 28C may be connected to one or more gate contact trenches 280, and an active shielding electrode 21A, a coupled shielding electrode 21B, and a cross-shielding electrode 21C may be connected to one or more shielding contact trenches 210. In some examples, the conductive region 43 includes a conductive plug or plug structure. In some examples, the conductive region 43 may include a conductive barrier structure or liner and a conductive filler material. In some examples, the barrier structure may include a metal / metal-nitride configuration, such as titanium / titanium nitride or other related or equivalent materials known to those skilled in the art. In other examples, the barrier structure may also include a metal silicide structure. In some examples, the conductive filler material includes tungsten. In some examples, the conductive region 43 may be planarized to provide a more uniform surface morphology.

[0075] In some examples, conductors 44A and 44B may be formed adjacent to the main surface 18 (in Figure 1 (shown in the diagram), and conductor 46 may be formed adjacent to the main surface 19. Conductors 44A and 44B may also be referred to as top metal or top conductor, and conductor 46 may also be referred to as bottom conductor or back metal. Conductors 44A, 44B, and 46 may be configured to provide electrical connections between various units of the semiconductor device 10 and next-level components. In some examples, conductors 44A and 44B comprise titanium / titanium nitride / aluminum copper or other related or equivalent materials known to those skilled in the art and are configured as source electrodes or terminals. In some examples, conductor 46 comprises a solderable metal structure, such as titanium nickel silver, chromium nickel gold, or other related or equivalent materials known to those skilled in the art and configured as drain electrodes or terminals. In some examples, an additional passivation layer (not shown) may be formed adjacent to conductors 44A and 44B. In some examples, a shielding electrode 21 may be connected to conductor 44A such that the shielding electrode 21 is configured to be at the same potential as the doped region 33 when the semiconductor device 10 is in use. In other examples, shielding electrode 21 may be configured to be independently biased or partially coupled to gate contact trench 280.

[0076] In one example, the semiconductor device 10 can be operated as follows. If conductor 44A and shielding electrode 21 are at a potential of zero volts V... S In the following operation, the gate electrode 28 will receive a 10-volt control voltage V. G It is greater than the conduction threshold of semiconductor device 10, and the drain electrode (or output terminal) 46 will be at a drain potential V less than 2.0 volts. D Next operation. V G and V S The value will cause the body region 31 to reverse the adjacent gate electrode 28 to form a channel region, which will electrically connect the doped region 33 to the semiconductor region 14 in the active mesa region 16A. Device current I DS The current will flow out of conductor 46 and be guided through semiconductor region 14, channel region, and doped region 33 to conductor 44B. In some examples, I DS Approximately 10.0 amperes. To switch semiconductor device 10 to the off state, a control voltage V less than the semiconductor's conductivity threshold is applied. G This control voltage will remove the channel region, and I DS No more current will flow through semiconductor device 10. According to this specification, the configuration of semiconductor device 10 as described herein achieves improved UIS performance due to the structural properties of the cell morphology 100 including coupling trench 22C, which reduces the shielding resistance at the outer edge of semiconductor device 10. Furthermore, experiments have shown that the corner portion 22CA of coupling trench 22 provides improved BV through charge balancing techniques. DSS performance.

[0077] Figure 6 A top partial plan view of an example cell topography 200 of a semiconductor device (such as semiconductor device 10) according to this specification is shown. In this example, Figure 6 The upper left portion of cell shape 200 is shown as an example. Figure 6 The unit morphology 200 is structurally similar to Figure 1 The cell morphology 100 has some similarities, and these similarities will not be repeated here. In this example, a shielding contact trench 211 extends between a pair of gate contact trenches 280, and a shielding contact via 211A extends through the gate electrode 28 to contact the shielding electrode 21 below the gate electrode 28. The shielding contact trench 211 is generally perpendicular to the gate contact trenches 280 and is generally aligned with the corner portion 22CA of the coupling trench 22C. In this example, the shielding contact via dielectric 211B insulates the shielding contact via 211A from the gate electrode 28. In some examples, portions of the gate electrode 28 extend above and below the shielding contact via dielectric 211B, such that the gate electrode 28 is continuous and uninterrupted within the shielding contact trench 211.

[0078] In some examples, the only shielding contact trenches 211 or shielding contact vias 211A in the cell topology 200 and semiconductor device 10 are those shielding contact trenches 211 or shielding contact vias 211A outside or beyond the boundary defined by the top terminating trench 22D and the bottom terminating trench 22D'. In this way, the gate electrode 28 can be a continuous or uninterrupted structure inside or within the boundary defined by the top terminating trench 22D and the bottom terminating trench 22D'. Furthermore, conductor 44A can be used to facilitate contact with the shielding contact vias 211A.

[0079] In some examples, cell topology 200 includes one or more shielded contact vias in the active region or within coupling trench 22C. In some examples, cell topology 200 may also include vias in coupling trench 22C or in active trench 22B (or as in...). Figure 8 Shielded contact vias 211A within the tip region 222 of one or more active trenches (shown as active trenches 22A), these shielded contact vias are insulated from the gate electrode 28 via a shielded contact via dielectric 211B. Other types of shielded contacts may be used, such as those in one or more active trenches 22B (or as shown in the diagram). Figure 8 A shielded contact via 213A is shown within the tip region 222 of the active trench 22A. In this example, the shielded contact via 213A may be insulated from the gate electrode 28 by a thicker shielding dielectric 24. The combination of the shielded contact via 213A and the shielding dielectric 24 provides an outwardly flared shielded contact via structure, wherein the tip region 222 is wider than the rest of the active trench 22B. In some examples, the shielded contact via 212A may be placed within the active trench 22B (or as shown in the example). Figure 8 The tip region 222 of one or more active trenches (shown as active trench 22A) is within this active trench. In this example, shielded contact via 212A is insulated from the gate electrode 28 by shielding dielectric 24. Shielded contact via 212A is narrower than shielded contact via 213A, such that the corresponding tip region 222 has the same width over the remainder of the active trench 22B. It should be understood that any shielded contact via described herein can be used in any combination with any cell morphology described herein, depending on the desired device characteristics. In some examples, shielded contact vias 211A, 212A, and 213A are coupled to conductor 44A. The use of additional shielded contact vias as described herein further reduces the shielding resistance in the semiconductor device 10.

[0080] Figure 7 A top partial plan view of an example cell topography 300 of a semiconductor device (such as semiconductor device 10) according to this specification is shown. In this example, Figure 7 The upper left portion of unit shape 300 is shown as an example. Figure 7 The unit morphology 300 is structurally similar to Figure 1 Unit morphology 100 and Figure 6 The cell topology 200 has some similarities, and these similarities will not be repeated here. In this example, cell topology 300 includes one or more shielded contact vias in the active region or in the coupling trench 22C. For example, cell topology 300 includes one or more shielded contact vias 211A placed in the tip region 222 of the active trench 22B or in the coupling trench 22C, which further reduces the shielding resistance in the semiconductor device 10.

[0081] Figure 8 Examples along Figure 6 The reference lines 8A-8A show a partial cross-sectional view of an example shielded contact trench 211. In this example, a portion of the shielded electrode 21 is disposed near the top side 18 of the semiconductor material region 11 between portions of the gate electrode 28. A shielded contact via dielectric 211B insulates this portion of the shielded electrode 21 from these portions of the gate electrode 28. In some examples, the shielded contact dielectric 211B may resemble the inter-electrode dielectric 27. In some examples, the shielded contact via 211A extends through ILD 41 to couple to the shielded electrode 21. In other examples, the shielded contact via 211A may extend between these portions of the gate electrode 28 and may be coupled to the shielded electrode 21 below the bottom side of the gate electrode 28. In this example, the shielded contact trench 211 is outside the terminating trench 22D and outside the active region of the semiconductor device 10.

[0082] Figure 9 Examples along Figure 7 The reference lines 9A-9A show a partial cross-sectional view of an example shielded contact trench 210. In this example, a portion of the shielded electrode 21 is close to the top side 18 of the semiconductor material region 11, where it terminates outside the trench 22D at the top. In some examples, the shielded contact via 210A extends through the ILD 41 to couple to the shielded electrode 21. In other examples, the shielded contact via 210A may extend through the upper trench dielectric 240 and may couple to the shielded electrode 21 below the bottom side of the gate electrode 28. In this example, the shielded contact via 210A is outside the terminating trench 22D and outside the active region of the semiconductor device 10.

[0083] Figure 10 A top partial plan view of an example cell topography 400 of a semiconductor device (such as semiconductor device 10) according to this specification is shown. In this example, Figure 10 The lower left portion of cell shape 400 is shown as an example. Figure 10 The unit morphology 400 is structurally similar to Figure 1 Unit morphology 100 and Figure 6 The cell topology 200 has some similarities, and these similarities will not be repeated here. In this example, cell topology 400 includes one or more shielded contact vias in the active region or within the coupling trench 22C. For example, cell topology 400 includes one or more shielded contact vias in the active region of the cell topology or within the coupling trench 22C. In some examples, shielded contact vias 211A, 212A, or 213A as described above may be within the active trench 22A or the coupling trench 22C, which further reduces the shielding resistance in the semiconductor device 10.

[0084] Figure 11 A top partial plan view of an example cell topography 500 of a semiconductor device (such as semiconductor device 10) according to this specification is shown. In this example, Figure 11 The lower left portion of cell shape 500 is shown as an example. Figure 9 The unit morphology 500 is structurally similar to Figure 1 Unit morphology 100 Figure 6 Unit morphology 200 and Figure 7 Cell topology 300 shares some similarities, and these similarities will not be repeated here. In this example, cell topology 500 includes one or more shielded contact vias in the active region or within the coupling trench 22C. In some examples, shielded contact vias 211A, as previously described, may be within the active trench 22A or the coupling trench 22C, which further reduces the shielding resistance in the semiconductor device 10. Similar to cell topology 200, cell topology 500 uses a shielded contact trench 211 extending between a pair of gate contact trenches 280 and a shielded contact via 211A extending through the gate electrode 28 to contact the shielded electrode 21 below the gate electrode 28. The shielded contact trench 211 is generally perpendicular to the gate contact trench 280.

[0085] Figure 12 A top partial plan view of an example cell topography 600 of a semiconductor device (such as semiconductor device 10) according to this specification is shown. In this example, Figure 12 The upper left portion of cell shape 600 is shown as an example. Figure 12 The unit morphology 600 is structurally similar to Figure 1 The cell morphology 100 has some similarities, and these similarities will not be repeated here. In this example, the sidewall 2802 of the gate contact trench 280 coupled to the coupling trench 22C includes a curved, arched, or non-linear shape, which in some examples is configured to control the electric field spread in the semiconductor device 10 to improve BV. DSS performance.

[0086] Figure 13A partial cross-sectional view of an example semiconductor device 10A according to this specification is shown. Figure 13 The semiconductor device 10A is structurally similar to Figure 4 The semiconductor device 10 has some similarities, and these similarities will not be repeated here. In this example, the semiconductor device 10A includes a gate silicide 282 located above the gate electrode 28. In some examples, the gate silicide 282 may include cobalt silicide or other silicide materials known to those skilled in the art. In this example, in an embodiment using an additional shielded contact via with the coupling trench 22C according to this specification, the gate silicide 282 may be used to reduce gate resistance. In other embodiments, a shielding silicide 218 may also be disposed above the shielding electrode 21 to further reduce shielding resistance. The shielding silicide 218 may include cobalt silicide or other materials known to those skilled in the art.

[0087] Generally, this example relates to semiconductor device structures and methods for fabricating semiconductor devices (such as shielded gate trench MOSFET devices) with improved manufacturability and performance. In some examples, methods for addressing the BV in a GTT structure using an arched termination design are described. DSS Structures and methods for addressing performance issues. Examples include GTT-type cell topologies with staggered or offset comb-shaped active trenches, arched termination designs, and coupling trenches. The coupling trenches connect to one side of the cell topology and include a surrounding top trench that connects to a gate contact trench on the opposite side of the cell topology. The coupling trenches may also form additional termination trenches to promote design flexibility. In some examples, gate connections may be provided on the opposite side of the cell topology to reduce gate resistance.

[0088] In some examples, shielding electrode connections are also facilitated on opposite edges or opposite sides of the cell topography, which reduces shielding resistance. In some examples, for a given cell topography length, the inventive structure reduces the shielding resistance by approximately half. Examples of providing additional shielding contacts within the cell topography to further improve shielding resistance performance are also described. The cell topography also facilitates gate connections from one or opposite sides or both sides. In some examples, a gate silicide structure can be used to offset any increase in gate resistance.

[0089] From all the foregoing, those skilled in the art will recognize that a semiconductor device may include a semiconductor material region, a first termination trench located within the semiconductor material region, and a second termination trench located within the semiconductor region and coupled to the first termination trench, wherein the first and second termination trenches define an active region. An active trench is located within the active region, and a coupling trench is located within the semiconductor material region and outside the active region. A shielding conductor is located within the coupling trench, the active trench, the first termination trench, and the second termination trench. A gate conductor is located within the coupling trench, the active trench, the first termination trench, and the second termination trench. A shielding contact trench is coupled to the first termination trench, and a shielding contact via is located within the shielding contact trench, outside the active region, and coupled to the shielding conductor. A gate contact trench is coupled to the first termination trench, and a gate contact via is located within the gate contact trench and coupled to the gate conductor. The gate conductor is a continuous and uninterrupted conductor within the active region, and the coupling trench couples the active region to the gate contact trench. In another example, the active region has no shielding contact vias.

[0090] Based on all the foregoing, those skilled in the art will determine that a method of manufacturing a semiconductor device includes: providing a semiconductor material region including a top side, an active mesa region, a terminating mesa region, a cross mesa region, a first edge region at the top side, a second edge region at the top side opposite to the first edge region, and a third edge region at the top side extending between the first edge region and the second edge region. The method further includes: providing a trench region extending into the semiconductor material region, the trench region including: a first terminating trench located within the first edge region; a second terminating trench located within the second edge region and coupled to the first terminating trench; a first active trench extending from the first terminating trench toward the second terminating trench and terminating at a first tip region, the first tip region being separated from the second terminating trench by a terminating mesa region; and a second active trench extending from the second terminating trench toward the second terminating trench. A stop trench extends toward a first terminating trench, separates from the first active trench through an active mesa region, and terminates at a second tip region, which is separated from the first terminating trench through the terminating mesa region; a first gate contact trench is coupled to the first terminating trench within a first edge region; and a coupling trench is located within a third edge region, coupled to the second terminating trench, and includes a corner portion coupling the coupling trench to the first gate contact trench, the corner portion being separated from the first terminating trench through a cross-mesa region. The method includes: providing a shielding electrode located within a coupling trench. The method includes: providing a shielding dielectric located within the coupling trench, insulating the shielding electrode from a semiconductor material region. The method includes: providing a gate electrode located within the coupling trench. The method includes: providing a gate dielectric located within the coupling trench, insulating the gate electrode from a semiconductor material region. The method includes: providing an inter-electrode dielectric that insulates the gate electrode from the shielding electrode.

[0091] In another example, the method may include: providing a second gate contact trench coupled to a second terminating trench within a second edge region and laterally offset relative to a first gate contact trench in a top plan view. In another example, the method may include: providing a first shielding contact trench coupled to a first terminating trench within a first edge region. In yet another example, the method may include: providing a second shielding contact trench coupled to a second terminating trench within a second edge region.

[0092] In summary, structures and methods for semiconductor devices with improved manufacturability and performance have been described. More specifically, the BV in the GTT structure using a trench-terminated design with interconnects is addressed. DSSStructures and methods for addressing performance issues. Examples include GTT-type cell topologies with staggered or offset comb-shaped active trenches, arched termination designs, and coupling trenches. The coupling trenches connect to one side of the cell topology and include a surrounding top trench that connects to a gate contact trench on the opposite side of the cell topology. The coupling trenches may also form additional termination trenches to promote design flexibility. In some examples, gate connections may be provided on the opposite side of the cell topology to reduce gate resistance.

[0093] In some examples, shielding electrode connections are also facilitated on opposite edges or opposite sides of the cell topology, which reduces shielding resistance. In some examples, for a given cell topology length, the structure of the present invention reduces the shielding resistance by approximately half. The shielding connections described herein are provided without interrupting the connections between active gate trenches and gate contacts (which are outside the region of the topology forming source metal contacts) compared to previous cell topologies. Furthermore, this specification provides shielding contacts within the region of the topology forming source metal contacts. Examples of providing additional shielding contacts within the cell topology to further improve shielding resistance performance are also described. The cell topology also facilitates gate connections from one or opposite sides or both sides. In some examples, a gate silicide structure may be used to offset any increase in gate resistance.

[0094] It should be understood that the different examples described herein can be combined with any other examples described herein to obtain different implementation schemes.

[0095] Although the subject matter of the invention has been described in conjunction with specific preferred examples, the foregoing figures and description are merely illustrative examples of the subject matter and should not be construed as limiting the scope of the invention. It will be apparent to those skilled in the art that many alternatives and variations will be readily apparent. For example, the conductivity type of each region can be reversed. Furthermore, other IV-IV semiconductor materials besides SiC, such as SiGe or SiGeC, can be used. Additionally, other compound semiconductor materials can be used. Moreover, the structures and methods described herein can be used for higher voltage devices (e.g., greater than 100 volts) or lower voltage devices (e.g., less than 30 volts). Furthermore, instead of being connected to a gate contact trench, or in addition to being connected to a gate contact trench, the coupling trench can also be connected to a shield contact trench.

[0096] As reflected in the claims below, various aspects of the invention may have fewer features than all the features of a single example disclosed above. Therefore, the claims set forth below are hereby expressly incorporated into this detailed description, wherein each claim represents an independent example of the invention. Furthermore, although some examples described herein include some features included in other examples but not all of those features, those skilled in the art will understand that combinations of features from different examples are intended to fall within the scope of the invention and to form different examples.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a semiconductor material region comprising: a top side; an active mesa region; a termination mesa region; a cross-mesa region; a first edge region at the top side; a second edge region at the top side, opposite the first edge region; and a third edge region at the top side, extending between the first edge region and the second edge region; a first termination trench within the first edge region; a second termination trench within the second edge region and coupled to the first termination trench; a first active trench extending from the first termination trench towards the second termination trench and terminating in a first tip region separated from the second termination trench by the termination mesa region; a second active trench extending from the second termination trench towards the first termination trench, separated from the first active trench by the active mesa region, and terminating in a second tip region separated from the first termination trench by the termination mesa region; a first gate contact trench coupled to the first termination trench within the first edge region; a coupling trench within the third edge region, coupled to the second termination trench, and comprising a corner portion coupling the coupling trench to the first gate contact trench, the corner portion separated from the first termination trench by the cross-mesa region; a shield electrode within the coupling trench; a shield dielectric within the coupling trench insulating the shield electrode from the semiconductor material region; a gate electrode within the coupling trench; a gate dielectric within the coupling trench insulating the gate electrode from the semiconductor material region; and an inter-electrode dielectric insulating the gate electrode from the shield electrode.

2. The semiconductor device of claim 1, wherein the semiconductor device further comprises: a second gate contact trench coupled to the second termination trench within the second edge region; and a first shield contact trench within the first edge region, outside the first termination trench, and coupled to the shield electrode.

3. The semiconductor device of claim 2, wherein: the first shield contact trench is parallel to the first gate contact trench.

4. The semiconductor device of claim 2, wherein: the first shield contact trench is perpendicular to and intersects the first gate contact trench.

5. The semiconductor device of claim 2, wherein: in a top plan view, the second gate contact trench is laterally offset relative to the first gate contact trench.

6. The semiconductor device of claim 2, wherein the semiconductor device further comprises: a second shield contact trench located outside the second termination trench within the second edge region, laterally offset relative to the first shield contact trench in a top plan view, and coupled to the shield electrode.

7. The semiconductor device of claim 1, wherein the corner portion comprises an arcuate shape in a top plan view.

8. The semiconductor device of claim 1, wherein the semiconductor device further comprises: a shield contact via located within the coupling trench; and a gate silicide located on the gate electrode in the coupling trench.

9. The semiconductor device of claim 1, wherein: the cross-tread region comprises a cross-tread width between the corner portion of the coupling trench and the first termination trench at the first gate contact trench; and the cross-tread width is greater than about 600 nanometers.

10. The semiconductor device of claim 1, wherein: the first gate contact trench comprises a sidewall extending between the corner portion of the coupling trench and the first termination trench.

11. The semiconductor device of claim 10, wherein: the sidewall comprises a linear shape in a top plan view.

12. The semiconductor device of claim 10, wherein: the sidewall comprises a non-linear shape in a top plan view.

13. The semiconductor device of claim 1, wherein: the first termination trench comprises an arcuate termination structure proximate the first tip region of the first active trench.

14. A semiconductor device, characterized by comprising: the semiconductor device comprises: a semiconductor material region comprising: a top side; an active-tread region; a termination-tread region; a cross-tread region; a first edge region at the top side; a second edge region at the top side, opposite the first edge region; and a third edge region at the top side, extending between the first edge region and the second edge region; a first termination trench located within the first edge region; a second termination trench located within the second edge region and coupled to the first termination trench; a first active trench extending from the first termination trench toward the second termination trench and terminating at a first tip region, the first tip region separated from the second termination trench by the termination-tread region; a second active trench extending from the second termination trench toward the first termination trench, interleaved with the first active trench, separated from the first active trench by the active-tread region, and terminating at a second tip region, the second tip region separated from the first termination trench by the termination-tread region; a first gate contact trench coupled to the first termination trench within the first edge region; a coupling trench within the third edge region, coupled to the second termination trench, and including a corner portion coupling the coupling trench to the first gate contact trench, the corner portion separated from the first termination trench by the cross-tuck region; a shield electrode in the coupling trench; a shield dielectric in the coupling trench insulating the shield electrode from the semiconductor material region; a gate electrode in the coupling trench and including a first side adjacent the termination tuck region and a second side opposite the first side; a gate dielectric in the coupling trench insulating the first side of the gate electrode from the cross-tuck region, wherein the shield dielectric insulates the second side of the gate electrode from the semiconductor material region; and an electrode-to-electrode dielectric insulating the gate electrode from the shield electrode.

15. The semiconductor device of claim 14, wherein: the shield electrode and the gate electrode are within the first termination trench, the second termination trench, the first active trench, and the second active trench.

16. The semiconductor device of claim 14, wherein the semiconductor device further comprises: a second gate contact trench coupled to the second termination trench within the second edge region and laterally offset relative to the first gate contact trench in a top plan view; and a first shield contact trench coupled to the first termination trench within the first edge region.

17. The semiconductor device of claim 14, wherein: the first termination trench includes a first arched termination structure proximate the first tip region of the first active trench; the second termination trench includes a second arched termination structure proximate the second tip region of the second active trench; the first tip region and the second tip region include outwardly rounded arches in a top plan view; the first arched termination structure and the second arched termination structure include inwardly rounded arches in the top plan view; and the first arched termination structure is laterally offset relative to the second arched termination structure in the top plan view.

18. The semiconductor device of claim 14, wherein: the cross-tuck region includes a cross-tuck width between the corner portion of the coupling trench and the first termination trench at the first gate contact trench; the cross-tuck width is greater than about 800 nanometers; the first gate contact trench includes a sidewall extending between the corner portion of the coupling trench and the first termination trench; and the sidewall includes a linear shape in a top plan view. the method comprises:

19. A method of providing a semiconductor device, characterized by, providing a semiconductor material region; providing a first termination trench within the semiconductor material region; ​ a second termination trench is provided, the second termination trench being located within the semiconductor region and coupled to the first termination trench, wherein the first termination trench and the second termination trench provide an active region; an active trench is provided, the active trench being located within the active region; a coupling trench is provided, the coupling trench being located within the semiconductor material region and outside of the active region; a shield conductor is provided, the shield conductor being located within the coupling trench, the active trench, the first termination trench, and the second termination trench; a gate conductor is provided, the gate conductor being located within the coupling trench, the active trench, the first termination trench, and the second termination trench; a shield contact trench is provided, the shield contact trench being coupled to the first termination trench; a shield contact via is provided, the shield contact via being located within the shield contact trench, outside of the active region, and coupled to the shield conductor; a gate contact trench is provided, the gate contact trench being coupled to the first termination trench; and a gate contact via is provided, the gate contact via being located within the gate contact trench and coupled to the gate conductor; wherein: the gate conductor is a continuous and uninterrupted conductor within the active region; and the coupling trench couples the active region to the gate contact trench.

20. The method of claim 19, wherein: the active region is free of any shield contact via.

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