Semiconductor substrate, semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor substrate, a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. The semiconductor base body comprises a substrate and a mask, and the substrate is provided with a plurality of cellular areas; the mask covers the substrate and is provided with a plurality of injection windows, and the injection windows correspond to the cellular areas; the ratio of the opening area of the injection window to the area of the corresponding cellular region is an opening area proportion, and the opening area proportions of the injection windows in at least part of the cellular regions are different. The semiconductor substrate, the semiconductor device and the preparation method of the semiconductor substrate and the semiconductor device are used for forming differentiated doping concentrations in a cellular region, and process simplification, cost reduction and reliability improvement are achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor substrate, a semiconductor device and a preparation method thereof. BACKGROUND

[0002] In many application fields such as new energy, semiconductor devices need to have a wide safe operating area (SOA) to ensure system efficiency and operation safety. To improve the safe operating area of semiconductor devices, a cell region with different threshold voltages is usually designed inside the chip to realize staged turn-on or turn-off during the turn-on or turn-off process of the device.

[0003] In the prior art, to realize regional control of threshold voltage, when performing P-type ion implantation, a multi-step implantation process or a precise alignment method between two layers of masks is generally used to form P-type ions with different doping concentrations in different regions of the substrate, thereby adjusting the distribution of threshold voltage.

[0004] However, the above scheme has a complex process, which is difficult to meet the production requirements of high reliability and low cost. SUMMARY

[0005] Embodiments of the present application provide a semiconductor substrate, a semiconductor device and a preparation method thereof, to form differential doping concentrations in cell regions, realize process simplification, cost reduction and reliability improvement.

[0006] In a first aspect, the present application provides a semiconductor substrate, comprising:

[0007] a substrate, the substrate having a plurality of cell regions;

[0008] a mask covering the substrate, the mask being provided with a plurality of implantation windows corresponding to the cell regions;

[0009] The ratio of the opening area of the implantation window to the area of the corresponding cell region is the opening area ratio, and the opening area ratios of the implantation windows in at least part of the cell regions are different.

[0010] As an optional implementation, the opening area ratio is greater than or equal to 0.5 and less than or equal to 1.

[0011] As an optional implementation, the plurality of cell regions includes a first cell region and a second cell region;

[0012] The opening area ratio of the implantation window corresponding to the first cell region is different from the opening area ratio of the implantation window corresponding to the second cell region;

[0013] The first cell region and the second cell region are arranged side by side, or the first cell region is annularly arranged at the side of the second cell region.

[0014] As an optional implementation, the injection window comprises a sub-window, and the substrate is provided with a groove towards the side of the mask;

[0015] The sub-window and the groove are arranged at an angle.

[0016] As an optional implementation, the number of the sub-windows is multiple, and at least part of the sub-windows are arranged at intervals along a first direction;

[0017] The number of the grooves is multiple, and the grooves are arranged at intervals along a second direction, and the first direction and the second direction are arranged at an angle.

[0018] As an optional implementation, along the first direction, the average distance between two adjacent sub-windows is greater than or equal to 0.2 μm and less than or equal to 1 μm;

[0019] And / or, along the direction perpendicular to the extension direction of the sub-window, the average width of the sub-window is greater than or equal to 0.2 μm and less than or equal to 3 μm;

[0020] And / or, along the second direction, the average distance between two adjacent grooves is greater than or equal to 0.6 μm and less than or equal to 6 μm;

[0021] And / or, along the direction perpendicular to the extension direction of the groove, the average width of the groove is greater than or equal to 0.2 μm and less than or equal to 2 μm;

[0022] And / or, along the thickness direction of the substrate, the average depth of the groove is greater than or equal to 1 μm and less than or equal to 10 μm.

[0023] In a second aspect, the application provides a semiconductor device, comprising a substrate and a P-type semiconductor layer arranged in layers;

[0024] The P-type semiconductor layer has multiple distribution regions, and the doping concentration of P-type ions in at least part of the distribution regions is different.

[0025] In a third aspect, the application provides a semiconductor device preparation method, which is used for preparing the semiconductor device of any one of the above semiconductor substrates, and the method comprises:

[0026] Forming a photoresist layer on the surface of the substrate, and the substrate and the photoresist layer form an initial semiconductor substrate;

[0027] Multiple trenches are formed on the initial semiconductor substrate, and the depth of the trenches is greater than the thickness of the photoresist layer;

[0028] An injection window is formed on the photoresist layer, and the photoresist layer forms a mask;

[0029] P-type ions are implanted into the substrate through the mask;

[0030] Annealing is performed to allow the P-type ions to diffuse.

[0031] As an optional implementation, the P-type ions include boron ions, wherein the implantation dose of the boron ions is greater than or equal to 5E12 cm⁻¹. -2 Less than or equal to 2E14cm -2 .

[0032] As an optional implementation, the annealing temperature is greater than or equal to 1000°C and less than or equal to 1200°C;

[0033] And / or, the annealing time is greater than or equal to 30 minutes and less than or equal to 300 minutes.

[0034] The semiconductor substrate, semiconductor device, and fabrication method provided in this application include a semiconductor substrate and a mask. The substrate has multiple cell regions. The mask covers the substrate and has multiple injection windows, which correspond to the cell regions. The ratio of the opening area of ​​the injection window to the area of ​​the corresponding cell region is the opening area percentage. The opening area percentage of the injection window is different in at least a portion of the cell regions.

[0035] By setting implantation windows with different opening area ratios in different cell regions, after P-type ion implantation, regions with larger opening area ratios have more P-type ions entering the substrate, resulting in a higher average doping concentration in these regions; regions with smaller opening area ratios have fewer impurity ions entering, resulting in a lower average doping concentration in these regions. This allows multiple regions with different P-type doping concentrations to be formed on the substrate.

[0036] These P-type impurity regions with varying concentrations can optimize the switching characteristics of semiconductor devices and effectively expand the safe operating area (SOA) of semiconductor devices.

[0037] The semiconductor substrate, semiconductor device, and fabrication method provided in this application can form multiple regions with different P-type impurity concentrations by setting implantation windows with different opening area ratios, requiring only one mask and one P-type ion implantation process. This simplifies the processing technology, reduces manufacturing costs, eliminates alignment errors when using multiple masks, improves parameter consistency, and helps meet the production requirements of high reliability and low cost. Attached Figure Description

[0038] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0039] Figure 1 This is a schematic diagram of the structure of the substrate in the semiconductor matrix provided in the embodiments of this application;

[0040] Figure 2 This is a schematic diagram of a semiconductor substrate with a mask covering the substrate, provided in an embodiment of this application.

[0041] Figure 3 This is another schematic diagram of a semiconductor substrate with a mask covering the substrate, provided in an embodiment of this application.

[0042] Figure 4 This is a schematic flowchart of a semiconductor device fabrication method provided in an embodiment of this application.

[0043] Explanation of reference numerals in the attached figures:

[0044] 100. Substrate;

[0045] 110. Cellular region;

[0046] 111. First cell region;

[0047] 112. Second cell region;

[0048] 120. Trench;

[0049] 200. Mask;

[0050] 210. Injection window;

[0051] 211. Sub-window.

[0052] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the embodiments of this application.

[0054] In the embodiments of this application, the terms "upper," "lower," "inner," "middle," "outer," "front," and "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are mainly for better describing the embodiments of this application and their implementations, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation. Furthermore, some of the above terms may be used to indicate other meanings besides orientation or positional relationship; for example, the term "upper" may also be used in some cases to indicate a certain dependency or connection relationship. For those skilled in the art, the specific meaning of these terms in the embodiments of this application can be understood according to the specific circumstances.

[0055] Furthermore, the terms "set up," "connect," and "fix" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0056] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the present application described herein can be implemented, for example, in orders other than those illustrated or described herein.

[0057] In this application, the terms "exemplarily" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplarily" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0058] In applications such as industrial frequency conversion equipment, new energy, rail transportation, and aerospace, semiconductor devices are required to have a wide safe operating area (SOA) to ensure system efficiency and operational safety.

[0059] To expand the safe operating area of ​​semiconductor devices, cell regions with different threshold voltages are usually designed inside the device. When the device is turned on or off, cells with different threshold voltages switch on and off in sequence, thereby optimizing the switching characteristics.

[0060] To achieve regional control of the threshold voltage, some techniques involve changing the spacing between the P-type ion-doped region and the polysilicon gate during P-type ion implantation of the substrate. This utilizes the diffusion effect to create differences in the P-type ion doping concentration in different regions, thereby adjusting the threshold voltage. However, this method relies on the precise alignment of the two photomasks, resulting in a complex process that is susceptible to photomask misalignment, leading to poor parameter consistency.

[0061] Some related techniques indirectly affect the threshold voltage by adjusting the spacing between the contact holes and the trench gate, thereby altering the impurity diffusion path. However, this method is also limited by the photomask alignment accuracy and has limited control over doping uniformity.

[0062] Some related technologies achieve threshold voltage differences by creating concentration gradients in different regions through multiple p-type ion implantation and annealing steps. However, multi-step processes significantly increase manufacturing costs and process complexity, and thermal preheating between steps may affect device performance.

[0063] Therefore, while the above-mentioned solutions can achieve regional control of the threshold voltage, they generally suffer from complex processes and cannot meet the production requirements of high reliability and low cost.

[0064] In view of the above, embodiments of this application provide a semiconductor substrate, a semiconductor device and a method for fabricating the same, wherein the semiconductor substrate includes a substrate and a mask, the substrate having multiple cell regions; the mask covers the substrate, the mask having multiple injection windows, the injection windows corresponding to the cell regions, the ratio of the opening area of ​​the injection window to the area of ​​the corresponding cell region being the opening area percentage, and the opening area percentage of the injection windows in at least a portion of the cell regions being different.

[0065] By setting implantation windows with different opening area ratios in different cell regions, after P-type ion implantation, more P-type ions enter the substrate in the region with a larger opening area ratio, resulting in a higher average doping concentration in that region; while fewer impurity ions enter the region with a smaller opening area ratio, resulting in a lower average doping concentration in that region. This allows multiple regions with different P-type doping concentrations to be formed on the substrate.

[0066] These P-type impurity regions with varying concentrations, when interacting with structures such as the gate, create different threshold voltages. As a result, when the chip is turned on or off, low-threshold cells turn on first and then off, while high-threshold cells turn on last and turn off first. This smooths the switching waveform, reduces instantaneous peak power and thermal stress, and effectively widens the safe operating area (SOA) of the semiconductor device.

[0067] Specifically, this application can form multiple regions with different doping concentrations of P-type impurities by setting implantation windows with different opening area ratios, using only one mask and one P-type ion implantation process. This simplifies the processing technology, reduces manufacturing costs, eliminates alignment errors when using multi-layer masks, improves parameter consistency, and helps meet the production requirements of high reliability and low cost.

[0068] The technical solution of this application will be described in detail below with reference to the accompanying drawings and specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0069] Combination Figures 1 to 3 As shown, a first aspect of this application provides a semiconductor substrate, including a substrate 100. The substrate 100 serves as the physical basis and carrier of a semiconductor device.

[0070] The semiconductor substrate also includes a mask 200, which covers the substrate 100. In the ion implantation process, the mask 200 acts as a selective barrier layer to distinguish between the parts of the substrate 100 surface that need to be exposed to receive impurity ion implantation and the parts that need to be protected, ensuring that impurities are only introduced to the locations specified in the design, thereby constructing different functional units on the semiconductor device.

[0071] The mask 200 has multiple implantation windows 210. The implantation windows 210 are openings on the mask 200, serving as channels for impurity ions to enter the substrate 100. The shape and size of the implantation windows 210 determine the two-dimensional planar shape and distribution of the doped regions in the underlying substrate 100. The arrangement of multiple implantation windows 210 allows for the parallel fabrication of multiple identical or functionally similar units on the same semiconductor substrate, forming the basis for constructing a multi-cell parallel structure for semiconductor devices.

[0072] It should be noted that the material of the substrate 100 is not limited in the embodiments of this application. For example, the substrate 100 may include a silicon substrate and a silicon-germanium substrate.

[0073] The substrate 100 has multiple cellular regions 110.

[0074] Understandably, semiconductor devices (such as MOSFET chips or IGBT chips) are composed of a large number of tiny cell units. A single cell can only handle a limited amount of current. By connecting thousands or even tens of thousands of cells in parallel, a large current can be shared, thus achieving the device's high current handling capability.

[0075] Each cell region 110 is formed by a multi-cell structure, which can evenly distribute current and heat, avoid current concentration, and thus enhance the robustness and burn-out resistance of the device.

[0076] The injection window 210 corresponds to the cell region 110. The injection window 210 of the mask 200 has a spatial correspondence with the cell of the semiconductor device. According to the actual application requirements, different area ratios of the injection window 210 in each cell region 110 can be flexibly set to independently and precisely control the threshold voltage of each cell region 110. The required threshold voltage distribution can be planned on the semiconductor device to achieve better electrical and thermal performance.

[0077] The ratio of the opening area of ​​the injection window 210 to the area of ​​the corresponding cell region 110 is the opening area percentage, and the opening area percentage of the injection window 210 is different in at least a portion of the cell regions 110.

[0078] Understandably, during ion implantation, P-type ions bombard the entire surface of substrate 100 uniformly. Due to the shielding effect of mask 200, P-type ions can only enter substrate 100 through implantation window 210. For regions with the same opening area ratio, the opportunity to be exposed to ion bombardment per unit area is equal. Therefore, under the same process conditions, the number of impurity ions received per unit area in these regions is similar, and the average doping concentration formed in these cellular regions 110 is also similar.

[0079] When the implantation window 210 above different cell regions 110 has a different opening area ratio, the region with a larger opening area ratio has a larger proportion of its surface area open. Under the same ion bombardment, this region can accommodate more impurity ions per unit area. For the region with a smaller opening area ratio, its surface has a smaller proportion of open areas, resulting in fewer impurity ions that can be accommodated per unit area.

[0080] Therefore, by controlling the difference in the opening area ratio of the implantation window 210, one cell region 110 can obtain a lower (or higher) implantation dose per unit area than the other cell region 110, and the difference in implantation dose will be directly converted into a difference in doping concentration.

[0081] Regions with higher received doses have higher average doping concentrations, while regions with lower received doses have lower average doping concentrations. This creates a P-type impurity region with a doping concentration gradient within the device.

[0082] It should be noted that the opening area ratio of the injection window 210 can be configured according to the specific device performance requirements.

[0083] Different doping concentrations of P-type regions will generate different threshold voltages after interacting with the gate structure above them. Regions with high doping concentration have low threshold voltages, while regions with low doping concentration have high threshold voltages.

[0084] When the chip is turned on or off, low-threshold cells are turned on first and then off, while high-threshold cells are turned on last and then off first. This smooths the switching waveform, reduces instantaneous peak power and thermal stress, and thus effectively widens the safe operating area (SOA) of the semiconductor device.

[0085] Compared to traditional complex processes that require multiple ion implantations, multiple annealings, or multiple masks 200, the semiconductor substrate provided in this application embodiment completes the doping steps for all cell regions 110 in the same photolithography and ion implantation process. This ensures extremely high consistency between cells of the same type (with the same window area), avoids deviations introduced by batch processing, and eliminates the need for multiple alignments and implantations. Multiple regions with different P-type doping concentrations can be formed on the substrate 100, reducing process complexity and helping to reduce manufacturing costs and production cycles.

[0086] It should be noted that the mask 200 can be formed from a layer of photoresist disposed on the surface of the substrate 100. The mask 200, also known as a photomask, can be formed by opening an injection window 210 at a specific position on the photoresist.

[0087] In some embodiments, the percentage of the opening area is greater than or equal to 0.5 and less than or equal to 1.

[0088] For example, the ratio of the opening area of ​​the injection window 210 to the area of ​​the corresponding cell region 110 can be 0.5, 0.6, 0.7, 0.8, 0.9, 1, or any range between two values.

[0089] By setting the opening area ratio within the above range, it is possible to ensure that a sufficient amount of impurity ions are implanted into the substrate to form an effective and uniform P-type body region within the cell region 110.

[0090] In practice, the proportion of the opening area can be adjusted according to actual needs to achieve a doping concentration gradient between different cell regions 110.

[0091] In some embodiments, the plurality of cell regions 110 include a first cell region 111 and a second cell region 112. The proportion of the opening area of ​​the injection window 210 corresponding to the first cell region 111 is different from the proportion of the opening area of ​​the injection window 210 corresponding to the second cell region 112.

[0092] It should be noted that the first cell region 111 and the second cell region 112 in the embodiments of this application are merely illustrative examples used to clearly illustrate the basic principles of the present invention. In other optional embodiments of this application, the number of multiple cell regions 110 is not limited to two, and can be extended to three or more cell regions 110.

[0093] In these three or more cell regions 110, at least two cell regions 110 correspond to injection windows 210 with different opening area ratios. By configuring various different opening area ratios, a more refined or complex threshold voltage gradient distribution can be formed, thereby adapting to the specific requirements of different application scenarios for switching characteristics, safe operating area, and reliability.

[0094] Combination Figure 2 As shown, for example, the first cell region 111 and the second cell region 112 are arranged side by side.

[0095] Specifically, there may be multiple first cell regions 111 and multiple second cell regions 112, and the first cell regions 111 and the second cell regions 112 may be arranged alternately. The direction of arrangement may be consistent with the first direction.

[0096] For example, for the first cell region 111, the opening area of ​​the injection window 210 can be smaller than the opening area of ​​the injection window 210 corresponding to the second cell region 112.

[0097] This arrangement of the first cell region 111 and the second cell region 112 enables the current to be uniformly distributed at the microscale during the switching process, effectively preventing local concentration of current and heat, suppressing the formation of hot spots, thereby optimizing the switching waveform and improving the overall robustness and durability of the semiconductor device.

[0098] Combination Figure 3 As shown, for example, the first cell region 111 is arranged around the periphery of the second cell region 112.

[0099] During the switching process, since there are differences in electric field, current density and heat dissipation conditions between the edge region and the center region of a semiconductor device, a sequential switching process from the center to the edge (or from the edge to the center) can be formed by setting different threshold voltages.

[0100] For example, the proportion of the opening area of ​​the injection window 210 corresponding to the first cell region 111 can be smaller than the proportion of the opening area of ​​the injection window 210 corresponding to the second cell region 112.

[0101] When the device is turned off, the second cell region 112, which has a high threshold voltage located in the center, will turn off first. At this time, the first cell region 111, which has a low threshold voltage located on the periphery, will remain on, providing a buffer path for rapidly changing current.

[0102] This sequential turn-off process from the inside out makes the current drop more gradual, effectively suppressing voltage overshoot and current oscillations generated during the turn-off process.

[0103] Of course, depending on actual needs, the proportion of the opening area of ​​the injection window 210 corresponding to the first cell region 111 can also be set to be greater than the proportion of the opening area of ​​the injection window 210 corresponding to the second cell region 112. This application embodiment does not impose any restrictions on this.

[0104] It should be noted that the arrangement of the various cell regions 110 with different opening area ratios of the injection window 210 within the semiconductor device is not limited to the two forms listed in the foregoing embodiments. Specifically, the multiple cell regions 110 can be arranged in any other suitable topological layout according to actual electrical performance requirements (e.g., specific current propagation paths, thermal distribution management, or switching stress buffering requirements), such as checkerboard distribution, concentric ring distribution, fan-shaped distribution, or any combination thereof.

[0105] In some embodiments, the implantation window 210 includes sub-windows 211. There are multiple sub-windows 211. In the substrate 100 at the implantation window 210, cell doping is not achieved through a single large opening, but rather through a set of small windows.

[0106] Within a larger cell region 110, multiple dispersed sub-windows 211 are used for implantation, which can avoid the doping inhomogeneity caused by the implantation shadow effect at the edge of a single large window or the uneven lateral diffusion of impurities during subsequent annealing, thus ensuring the uniformity of electrical properties within the cell region 110.

[0107] The substrate 100 has a trench 120 on the side facing the mask 200, and there are multiple trenches 120.

[0108] Trench 120 is a three-dimensional structure extending into the substrate 100, with its sidewalls and bottom used to form the gate and electric field termination region of the device. The three-dimensional structure of trench 120 helps to optimize the electric field distribution inside the device, thereby improving the breakdown voltage.

[0109] Compared to planar devices, the trench 120 structure allows for smaller and denser cells, thereby significantly reducing the on-resistance of the device and improving switching speed and current handling capability.

[0110] The extension direction of the sub-window 211 has an angle with the extension direction of the trench 120, which can achieve the overlap of the doped region and the trench 120, so that the impurities can be more evenly distributed in the substrate 100 on both sides of the trench 120, rather than concentrated on one side of the trench 120 or excessively diffused along the direction of the trench 120, thereby achieving more precise control of the doped region.

[0111] For example, the angle between the extension direction of the sub-window 211 and the extension direction of the groove 120 is 90°. That is, the extension direction of the sub-window 211 is perpendicular to the extension direction of the groove 120.

[0112] When the extension direction of the sub-window 211 is perpendicular to the extension direction of the trench 120, it helps to disrupt the incident direction of ions, making the ions more evenly distributed, thereby improving the uniformity of doping.

[0113] Combination Figure 2 and Figure 3 As shown, in some embodiments, at least a portion of the sub-windows 211 are spaced apart along the first direction X. This orderly arrangement of the sub-windows 211 facilitates more controlled and uniform lateral diffusion of impurities from these discrete point sources during subsequent annealing, ultimately forming a continuous P-type impurity region.

[0114] Multiple trenches 120 are spaced apart along the second direction Y. The parallel and spaced trenches 120 help to form a uniform electric field distribution in the terminal region of the semiconductor device, maximizing the breakdown voltage of the device.

[0115] There is an angle between the first direction X and the second direction Y. Specifically, the first direction X and the second direction Y are set perpendicularly.

[0116] When the first direction X and the second direction Y are perpendicular, the sub-windows 211 array arranged along the first direction X can span each groove 120 in a more uniform manner, ensuring that both sides of the extension direction of each groove 120 can be covered by a similar number of symmetrically distributed sub-windows 211, thereby obtaining an extremely symmetrical and uniform P-type impurity region.

[0117] It should be noted that, in combination Figure 3 As shown, in the case where the first cell region 111 is arranged around the periphery of the second cell region 112, among the sub-windows 211 located within the first cell region 111, A number of sub-windows 211 will be located on one side of the second cell region 112 along the second direction Y, B number of sub-windows 211 will be located on the other side of the second cell region 112 along the second direction Y, C number of sub-windows 211 will be located on one side of the second cell region 112 along the first direction X, and D number of sub-windows 211 will be located on the other side of the second cell region 112 along the first direction X.

[0118] Sub-windows 211 of type A, type C, and type D are distributed at intervals along the first direction X; sub-windows 211 of type B, type C, and type D are also distributed at intervals along the first direction X.

[0119] The number of sub-windows 211 in part A and the number of sub-windows 211 in part B are distributed along the second direction Y.

[0120] In some embodiments, along the first direction X, the average spacing between two adjacent sub-windows 211 is greater than or equal to 0.2 μm and less than or equal to 1 μm.

[0121] For example, the average spacing between two adjacent sub-windows 211 can be 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1μm, or any range between two values.

[0122] By setting the average spacing between two adjacent sub-windows 211 to less than or equal to 1 μm, excessive spacing can be avoided, ensuring that impurities can diffuse laterally sufficiently to form a complete and continuous P-type impurity region.

[0123] By setting the average spacing between two adjacent sub-windows 211 to be greater than or equal to 0.2 μm, it has good adaptability to process capabilities.

[0124] Specifically, by controlling the average spacing range between two adjacent sub-windows 211, it helps to balance the diffusion and distribution uniformity of impurities, and helps to form an ideal doping profile, thereby optimizing the threshold voltage and breakdown voltage.

[0125] In some embodiments, the average width of the sub-window 211 is greater than or equal to 0.2 μm and less than or equal to 3 μm in a direction perpendicular to the extension direction of the sub-window 211.

[0126] For example, the average width of the sub-window 211 can be 0.2μm, 0.5μm, 0.8μm, 1μm, 1.2μm, 1.5μm, 1.8μm, 2μm, 2.2μm, 2.5μm, 2.8μm, 3μm, or any range between two values.

[0127] Setting the average width of sub-window 211 to less than or equal to 3 μm helps maintain fine-grained characteristics of implantation and diffusion. Simultaneously, it helps avoid forming excessively deep doped junctions below a single sub-window 211, facilitating the formation of shallow junctions and meeting the semiconductor device's requirement for controlling short-channel effects.

[0128] By setting the average width of sub-window 211 to be greater than or equal to 0.2 μm, it has good adaptability to process capabilities and avoids excessive dimensional fluctuations.

[0129] It should be noted that the opening area ratio of different injection windows 210 can be controlled by adjusting the width of the sub-window 211. For example, for an injection window 210 with a larger opening area ratio, the width of its sub-window 211 can be wider. For an injection window 210 with a smaller opening area ratio, the width of its sub-window 211 can be smaller.

[0130] In some embodiments, along the second direction Y, the average spacing between two adjacent trenches 120 is greater than or equal to 0.6 μm and less than or equal to 6 μm.

[0131] For example, the average spacing between two adjacent grooves 120 can be 0.6μm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, or any range between two values.

[0132] By controlling the average spacing between two adjacent trenches 120, more trenches 120 can be accommodated per unit area, thereby reducing the specific on-resistance of the device and helping to ensure sufficient space to withstand the widening of the depletion region and maintain the required breakdown voltage.

[0133] In some embodiments, the average width of the groove 120 is greater than or equal to 0.2 μm and less than or equal to 2 μm in a direction perpendicular to the extension direction of the groove 120.

[0134] For example, the average width of the groove 120 can be 0.2μm, 0.4μm, 0.6μm, 0.8μm, 1μm, 1.2μm, 1.4μm, 1.6μm, 1.8μm, 2μm, or any range between two values.

[0135] By controlling the average width of the trench 120, the electric field distribution inside the device is optimized, and the electric field is prevented from being excessively concentrated at the corners of the trench 120. At the same time, it helps to avoid the wide trench 120 unnecessarily occupying the area of ​​the substrate 100, thereby increasing the cell density and reducing the on-resistance.

[0136] In some embodiments, the average depth of the trench 120 along the thickness direction of the substrate 100 is greater than or equal to 1 μm and less than or equal to 10 μm.

[0137] For example, the average depth of the trench 120 can be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, or any range between two values.

[0138] By controlling the average depth of the trench 120, it is helpful to ensure that the sidewalls of the trench 120 form sufficiently long vertical channels to provide a large conduction current, while avoiding the trench 120 from being too deep and causing defects.

[0139] In summary, the semiconductor substrate provided in this application embodiment can form a P-type doped region with a doping concentration gradient in a single and highly consistent manner in the semiconductor substrate by setting implantation windows 210 with different opening area ratios on a single-layer mask 200 and by a single P-type ion implantation.

[0140] These regions impart different threshold voltages to the cells inside the semiconductor device, enabling cells with different thresholds to be turned on and off sequentially during the switching process. This smooths the current waveform, suppresses local hot spots, optimizes switching characteristics, and effectively widens the safe operating area.

[0141] Meanwhile, this solution also helps to eliminate errors introduced by the multi-layer mask 200 alignment process and simplifies the complex multi-step process into one step, which helps to improve device reliability, parameter consistency and reduce manufacturing costs.

[0142] A second aspect of this application provides a semiconductor device including a substrate 100 and a P-type semiconductor layer stacked together. The P-type semiconductor layer has multiple distribution regions, and at least a portion of the distribution regions have different doping concentrations of P-type ions.

[0143] The semiconductor device provided in this application can achieve different threshold voltage distributions by constructing multiple distribution regions with different P-type ion doping concentrations in the P-type semiconductor layer. This enables the device to achieve sequential current switching on and off during dynamic operation, thereby greatly smoothing the switching waveform, suppressing the concentration of electrothermal stress, significantly improving the switching robustness of the device, and fundamentally expanding its safe operating area (SOA).

[0144] Specifically, the semiconductor also includes an N-type layer, an isolation dielectric layer, and a metal layer stacked sequentially.

[0145] For example, the structure of a semiconductor device can be fabricated and applied to the manufacture of a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT).

[0146] The aforementioned MOSFET or IGBT chips can be supplied as standalone, unpackaged semiconductor dies and can be directly used in system-in-package or module integration. Furthermore, the semiconductor dies can also be packaged using existing packaging processes to form complete discrete device products or power modules in package formats such as TO-220, D²PAK, and TO-247.

[0147] Combination Figure 4 As shown, a third aspect of this application provides a method for fabricating a semiconductor device, used to fabricate the semiconductor device provided in any of the above embodiments using the semiconductor substrate provided in any of the above embodiments. The method includes:

[0148] S101. A photoresist layer is formed on the surface of a substrate, and the substrate and the photoresist layer form an initial semiconductor substrate;

[0149] S102. Multiple trenches are formed on the initial semiconductor substrate, and the depth of the trenches is greater than the thickness of the photoresist layer.

[0150] S103. An injection window is opened on the photoresist layer, and the photoresist layer forms a mask;

[0151] S104. P-type ions are implanted into the substrate through a mask;

[0152] S105, annealing treatment, to allow P-type ions to diffuse.

[0153] The semiconductor substrate has been described in detail in the above embodiments and will not be repeated here.

[0154] After the injection window 210 is opened on the photoresist layer, the substrate 100 and the photoresist layer form a semiconductor substrate, wherein the photoresist layer forms a mask 200 for the semiconductor substrate.

[0155] Specifically, an N-type floating zone single-crystal silicon substrate can be selected, with its main crystal plane being the (100) crystal plane, and the resistivity of the substrate can be selected from 20Ω·cm to 200Ω·cm depending on the voltage rating of the target semiconductor device.

[0156] A silicon dioxide layer with a thickness between 5000 Å and 10000 Å is deposited on the surface of a silicon substrate using a chemical vapor deposition process to serve as a hard mask 200 for subsequent etching.

[0157] The first photolithography and etching process is performed, using a composite mask 200 consisting of a silicon dioxide layer and a photoresist layer to etch the semiconductor substrate, forming multiple trenches 120. After etching, the remaining silicon dioxide mask 200 layer is removed.

[0158] A silicon dioxide layer is grown on the sidewalls and bottom surface of trench 120 using a thermal oxidation process to serve as the gate dielectric layer. Subsequently, polysilicon is filled into trench 120 using a chemical vapor deposition process to form the gate. Finally, the polysilicon outside trench 120 is removed using a chemical mechanical polishing process, ensuring that the polysilicon remains only inside trench 120.

[0159] A P-type bulk lithography process is performed, using the photoresist layer as a mask 200 for boron ion implantation. Due to the difference in the proportion of the opening area of ​​the implantation window 210 of the mask 200, the average unit area dose of boron ions implanted into the first cell region 111 of the silicon substrate is different from the average unit area dose of boron ions implanted into the second cell region 112 of the silicon substrate.

[0160] High-temperature annealing activates and diffuses the implanted boron ions, forming a continuous P-type semiconductor layer. Within the P-type semiconductor layer, the boron ion concentration is relatively uniform within the same cell region 110, but the boron ion concentration differs between the first cell region 111 and the second cell region 112.

[0161] Perform N-type source implantation, such as implanting arsenic ions, at a dose ranging from 5E14 cm⁻² to 1E16 cm⁻², and anneal to activate the impurities at a temperature ranging from 800°C to 1000°C.

[0162] A silicon dioxide layer with a thickness of 0.5 μm to 3 μm is generated using a chemical vapor deposition process to serve as an interlayer isolation dielectric layer. Subsequently, contact holes are formed in the isolation dielectric layer using photolithography and etching processes to expose part of the contact area between the N-type source and the P-type body region.

[0163] A front-side metallization layer is deposited. For example, a Ti / TiN layer can be deposited first, followed by tungsten deposition and contact hole filling via a etch-back process. Subsequently, an aluminum layer with a thickness of 3 μm to 8 μm is deposited as the main interconnect metal. Finally, a polyimide (PI) layer is coated as a surface passivation layer and patterned.

[0164] The back side of the wafer is thinned by grinding to a thickness ranging from 60 μm to 200 μm. Subsequently, backside ion implantation is performed to form a buffer layer and a collector layer, followed by annealing to activate the implanted impurities. Finally, a metal layer with a thickness of 0.5 μm to 2 μm is deposited on the back side to form the collector.

[0165] The above fabrication method yields an IGBT chip with a wide safe operating area (SOA). Due to the different area ratios of the injection windows 210 in the P-type body mask 200, the doping concentration of the P-type body region in the first cell region 111 differs from that in the second cell region 112, resulting in different threshold voltages for the first cell region 111 and the second cell region 112. This structure allows cells with different threshold voltages to sequentially turn on or off during device turn-on or turn-off, thereby optimizing the switching waveform, significantly improving the switching characteristics of the semiconductor device, and widening its safe operating area (SOA).

[0166] In some embodiments, the P-type ion includes boron ions, and the implantation dose of boron ions is greater than or equal to 5E12 cm⁻¹. -2 Less than or equal to 2E14 cm -2 .

[0167] By controlling the boron ion implanter within the range of 5E12 cm⁻² to 2E14 cm⁻², it was ensured that the P-type body region could form an effective conductive channel and maintain a reasonable threshold voltage.

[0168] In some embodiments, the annealing temperature is greater than or equal to 1000°C and less than or equal to 1200°C.

[0169] Annealing temperature can determine the activation rate and diffusion rate of impurity atoms.

[0170] Annealing at a temperature greater than or equal to 1000℃ ensures sufficient impurity activation and lattice repair; at the same time, annealing at a temperature less than or equal to 1200℃ avoids excessive diffusion of impurities due to excessively high temperatures.

[0171] Annealing time of 30 minutes or more can ensure uniform diffusion and solidification; annealing time of 300 minutes or less can prevent excessive diffusion of impurities.

[0172] Finally, it should be noted that those skilled in the art, upon considering the specification and practicing the application disclosed herein, will readily conceive of other embodiments of the present application. The embodiments of this application are intended to cover any variations, uses, or adaptations of the embodiments of this application that follow the general principles of the embodiments of this application and include common knowledge or customary technical means in the art not disclosed in the embodiments of this application. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the embodiments of this application are indicated by the following claims.

[0173] It should be understood that the embodiments of this application are not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from their scope. The scope of the embodiments of this application is limited only by the appended claims.

Claims

1. A semiconductor substrate, characterized by, The application relates to a substrate (100) having a plurality of cell regions (110); a mask (200) covering the substrate (100), the mask (200) being provided with a plurality of implantation windows (210) corresponding to the cell regions (110); a ratio of an opening area of the implantation window (210) to an area of the corresponding cell region (110) is an opening area ratio, and the opening area ratios of the implantation windows (210) in at least part of the cell regions (110) are different. The opening area ratio is greater than or equal to 0.5 and less than or equal to 1. The plurality of cell regions (110) include a first cell region (111) and a second cell region (112); the opening area ratio of the implantation window (210) corresponding to the first cell region (111) is different from the opening area ratio of the implantation window (210) corresponding to the second cell region (112); and the first cell region (111) and the second cell region (112) are arranged side by side or the first cell region (111) is arranged around the second cell region (112). The implantation window (210) includes a sub-window (211), and the substrate (100) is provided with a groove (120) on a side facing the mask (200); the extension direction of the sub-window (211) and the extension direction of the groove (120) form an included angle.

2. The semiconductor substrate of claim 1, wherein The number of the sub-windows (211) is a plurality, and at least part of the sub-windows (211) are distributed in a first direction; 3. The semiconductor substrate of claim 2, wherein The number of the grooves (120) is a plurality, and the plurality of grooves (120) are distributed in a second direction, and the first direction and the second direction form an included angle. In the first direction, the average distance between two adjacent sub-windows (211) is greater than or equal to 0.2 mu m and less than or equal to 1 mu m; In a direction perpendicular to the extension direction of the sub-window (211), the average width of the sub-window (211) is greater than or equal to 0.2 mu m and less than or equal to 3 mu m; 4. The semiconductor substrate according to any one of claims 1 to 3, characterized by In the second direction, the average distance between two adjacent grooves (120) is greater than or equal to 0.6 mu m and less than or equal to 6 mu m; In a direction perpendicular to the extension direction of the groove (120), the average width of the groove (120) is greater than or equal to 0.2 mu m and less than or equal to 2 mu m; 5. The semiconductor substrate of claim 4, wherein In the thickness direction of the substrate (100), the average depth of the groove (120) is greater than or equal to 1 mu m and less than or equal to 10 mu m. The application relates to a substrate (100) and a P-type semiconductor layer arranged in a stack; 6. The semiconductor substrate of claim 5, wherein The P-type semiconductor layer has a plurality of impurity distribution regions, and the doping concentration of P-type ions in at least part of the impurity distribution regions is different. The method comprises: ​ ​ ​ 7. A semiconductor device, characterized by comprising: ​ ​ 8. A method for manufacturing a semiconductor device using the semiconductor substrate according to any one of claims 1 to 6, for manufacturing the semiconductor device according to claim 7, characterized by, ​ forming a photoresist layer on a surface of a substrate (100), the substrate (100) and the photoresist layer forming an initial semiconductor base; forming a plurality of grooves (120) on the initial semiconductor base, the grooves (120) having a depth greater than a thickness of the photoresist layer; forming an implantation window (210) on the photoresist layer, the photoresist layer forming a mask (200); implanting P-type ions into the substrate (100) through the mask (200); annealing to diffuse the P-type ions.

9. The method of fabricating a semiconductor device according to claim 8, wherein The P-type ions include boron ions, and the boron ions have an implantation dose greater than or equal to 5E12 cm -2 and less than or equal to 2E14 cm -2 .

10. The method of claim 8, wherein The annealing is performed at a temperature greater than or equal to 1000℃ and less than or equal to 1200℃. And / or, the annealing is performed for a time greater than or equal to 30 minutes and less than or equal to 300 minutes.

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