Semiconductor device

Abstract

Embodiments relate to a semiconductor device. According to one embodiment, a semiconductor device includes: a substrate having a first surface; a semiconductor layer disposed on the first surface of the substrate; the field plate electrodes are arranged in the semiconductor layer and are positioned at the vertexes of a triangle in a plane parallel to the first plane; and a gate electrode which is located between the plurality of field plate electrodes in a plane parallel to the first surface, has a hexagonal pattern surrounding the periphery of one of the field plate electrodes, and has six side surfaces around the one of the field plate electrodes, the semiconductor layer has first side surfaces, which are six equivalent crystal surfaces respectively facing the six side surfaces of the gate electrode.

Description

[0001] [Related Application]

[0002] This application enjoys priority based on Japanese Patent Application No. 2024-154024 (filed on September 6, 2024). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] The implementation involves a semiconductor device. Background Technology

[0004] A power semiconductor device with a trench gate formed in a honeycomb pattern between multiple columnar field plate electrodes arranged in the densest possible filling manner is proposed. Summary of the Invention

[0005] According to an embodiment, a semiconductor device includes: a substrate having a first surface; a semiconductor layer disposed on the first surface of the substrate; a plurality of field plates electrodes disposed within the semiconductor layer, located at the vertices of a triangle in a plane parallel to the first surface; and a gate electrode located between the plurality of field plates electrodes in a plane parallel to the first surface, wherein the pattern surrounding one of the field plates electrodes is hexagonal, and the field plate electrode has six side surfaces around the one field plate electrode, and the semiconductor layer has six equivalent crystal planes, i.e., first side surfaces, respectively opposite to the six side surfaces of the gate electrode.

[0006] According to this embodiment, a semiconductor device capable of improving performance can be provided. Attached Figure Description

[0007] Figure 1 This is a schematic top view of the semiconductor device according to the embodiment.

[0008] Figure 2 yes Figure 1 AA section view in the image.

[0009] Figure 3 This is a schematic top view of a semiconductor device as a variation of the embodiment. Detailed Implementation

[0010] Hereinafter, embodiments will be described with reference to the accompanying drawings. Furthermore, in each drawing, the same reference numerals are used to denote the same structures.

[0011] Figure 1 This is a schematic top view showing the configuration of the main components in the semiconductor device 1 of the embodiment. Figure 2 yes Figure 1 AA section view. In Figure 1 In the middle, the following was omitted. Figure 2 The diagram shows the second electrode 32 and the insulating layer 63.

[0012] like Figure 2 As shown, the semiconductor device 1 of the embodiment includes a first electrode 31, a second electrode 32, a substrate 10, and a semiconductor layer 20. The substrate 10 and the semiconductor layer 20 are disposed between the first electrode 31 and the second electrode 32. In this specification, the direction from the first electrode 31 toward the second electrode 32 is defined as upward or above, and the direction from the second electrode 32 toward the first electrode 31 is defined as downward or below.

[0013] The substrate 10 has a first surface 11 and a second surface 12 located on the opposite side of the first surface 11. The second surface 12 is in contact with the first electrode 31 and is electrically connected to the first electrode 31.

[0014] A semiconductor layer 20 is disposed on the first surface 11 of the substrate 10. In this embodiment, the first conductivity type in the semiconductor layer 20 is defined as n-type and the second conductivity type as p-type, but it is also possible to define the first conductivity type as p-type and the second conductivity type as n-type.

[0015] The semiconductor layer 20 has an n-type first semiconductor portion 21 disposed on a first surface 11 of the substrate 10, a p-type second semiconductor portion 22 disposed on the first semiconductor portion 21, and an n-type third semiconductor portion 23 disposed on the second semiconductor portion 22. The n-type impurity concentration of the third semiconductor portion 23 is higher than that of the first semiconductor portion 21.

[0016] The second electrode 32 is disposed on the semiconductor layer 20. The third semiconductor portion 23 is connected to and electrically connected to the second electrode 32. In addition, a portion 22A of the second semiconductor portion 22 adjacent to the third semiconductor portion 23 is connected to the second electrode 32.

[0017] The semiconductor device 1 in this embodiment, for example, has a vertically oriented MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure. In the MOSFET, the first electrode 31 functions as the drain electrode, the second electrode 32 functions as the source electrode, the first semiconductor portion 21 functions as the drift layer, the second semiconductor portion 22 functions as the substrate layer, the third semiconductor portion 23 functions as the source layer, and the substrate 10 functions as the n-type drain layer with a higher n-type impurity concentration than the first semiconductor portion 21.

[0018] Alternatively, the semiconductor device in this embodiment may also have a vertical IGBT (Insulated Gate Bipolar Transistor) structure. In the IGBT, the first electrode 31 functions as the collector electrode, the second electrode 32 functions as the emitter electrode, the first semiconductor portion 21 functions as the drift layer, the second semiconductor portion 22 functions as the substrate layer, the third semiconductor portion 23 functions as the emitter layer, and the substrate 10 functions as the p-type collector layer. In the IGBT, a buffer layer with a higher n-type impurity concentration than the n-type impurity concentration in the first semiconductor portion 21 may also be provided between the substrate 10 (collector layer) and the first semiconductor portion 21 (drift layer).

[0019] The semiconductor device 1 in the embodiment also includes a gate electrode 50 and a gate insulating film 61.

[0020] The gate electrode 50 extends downward from the upper surface of the semiconductor layer 20 located on the side of the second electrode 32, and is located within the semiconductor layer 20. The gate electrode 50 is disposed within a trench t formed in the semiconductor layer 20, separated by a gate insulating film 61. The lower end of the gate electrode 50 is located within the first semiconductor portion 21, which is lower than the pn junction of the second semiconductor portion 22 and the first semiconductor portion 21. As a material for the gate electrode 50, conductive polysilicon can be used, for example.

[0021] A gate insulating film 61 is disposed between the gate electrode 50 and the semiconductor layer 20. The side surface 50A of the gate electrode 50 is opposed to the second semiconductor portion 22 through the gate insulating film 61.

[0022] The semiconductor device 1 of the embodiment also includes a field plate electrode 40 and a field insulating film 62.

[0023] Field plate electrodes 40 extend downward from the upper surface of semiconductor layer 20 and are located within semiconductor layer 20. Multiple columnar field plate electrodes 40 are disposed within semiconductor layer 20, separated by a field insulating film 62. Each field plate electrode 40 is disposed within a hole h formed in semiconductor layer 20, separated by the field insulating film 62. The field insulating film 62 is disposed between the field plate electrode 40 and semiconductor layer 20.

[0024] The field electrode 40 does not reach the substrate 10. The lower end of the field electrode 40 is located within the first semiconductor section 21. The depth of the hole h where the field electrode 40 is disposed from the upper surface of the semiconductor layer 20 is greater than the depth of the trench t where the gate electrode 50 is disposed from the upper surface of the semiconductor layer 20. The shortest distance between the lower end of the field electrode 40 and the first electrode 31 is shorter than the shortest distance between the lower end of the gate electrode 50 and the first electrode 31. As a material for the field electrode 40, conductive polycrystalline silicon can be used, for example.

[0025] The semiconductor device 1 in this embodiment also includes an insulating layer 63. The insulating layer 63 is disposed between the upper surface of the gate electrode 50 and the second electrode 32.

[0026] If a first potential (e.g., a positive potential) is applied to the first electrode 31, a second potential lower than the first potential (e.g., a ground potential) is applied to the second electrode 32, and a gate voltage above a threshold value is applied to the gate electrode 50, an n-type channel is formed in the region of the second semiconductor section 22 opposite to the side surface 50A of the gate electrode 50. Current flows between the first electrode 31 and the second electrode 32 via the substrate 10, the first semiconductor section 21, the channel, and the third semiconductor section 23, and the semiconductor device 1 becomes conductive.

[0027] In the off state of the semiconductor device 1, where a voltage above a threshold is stopped being applied to the gate electrode 50, the depletion layer extends from the pn junction of the second semiconductor section 22 and the first semiconductor section 21 and the boundary between the field insulating film 62 and the first semiconductor section 21, thereby maintaining the withstand voltage of the semiconductor device 1.

[0028] For example, the upper part of the field plate electrode 40 is connected to the second electrode 32, and the field plate electrode 40 is electrically connected to the second electrode 32. Alternatively, the field plate electrode 40 can also be electrically connected to the gate electrode 50. In the off state, such a field plate electrode 40 makes the electric field distribution of the first semiconductor section 21 (drift layer) smooth, thereby increasing the withstand voltage of the semiconductor device 1.

[0029] like Figure 1 As shown, in a plane parallel to the first surface 11 of the substrate 10 (viewed from above), multiple triangles (equilateral triangles in this example) are virtually represented by double-dotted lines, arranged without gaps between each other. Multiple field plate electrodes 40 are arranged such that they are located at the vertices of the triangles. Thus, the gate electrode 50 can be arranged in a honeycomb pattern between the multiple field plate electrodes 40 arranged in the densest possible configuration. This structure reduces on-resistance compared to a structure in which the gate electrode 50 is arranged in a grid pattern between multiple field plate electrodes 40 arranged in a square lattice.

[0030] The gate electrode 50 is located among a plurality of field plate electrodes 40 in a plane parallel to the first surface 11 of the substrate 10 (viewed from above), and surrounds one field plate electrode 40 with a hexagonal (regular hexagon in this example) pattern. The planar pattern of the gate electrode 50 is a honeycomb pattern of repeating hexagonal patterns. The gate electrode 50 has six sides 50A around one field plate electrode 40. In the plane parallel to the first surface 11 of the substrate 10, the gate electrode 50 has an intersection portion 51 and extension portions 52 extending from the intersection portion 51 in three different directions. Three extension portions 52 are arranged around the intersection portion 51 at approximately 120° intervals.

[0031] When viewed from above, the semiconductor layer 20 located inside the hexagonal gate electrode 50 has six equivalent crystal planes, namely first side surfaces 20A, which are respectively opposite to the six side surfaces 50A of the gate electrode 50. The first side surfaces 20A correspond to the sidewalls of the trench t in which the gate electrode 50 is disposed. The first side surfaces 20A include the region in the second semiconductor section 22 that forms the channel and the third semiconductor section 23 that includes the region that forms the main path of current in the on-state.

[0032] The substrate 10 has a cubic crystal structure, such as a silicon substrate. The first surface 11 of the substrate 10 is a (111) plane. The semiconductor layer 20 is a silicon layer epitaxially grown on the (111) plane of the substrate 10. Therefore, in the semiconductor layer 20, the surface parallel to the first surface 11 of the substrate 10 is the (111) plane. In addition, the six first side surfaces 20A of the semiconductor layer 20 located inside the hexagonal gate electrode 50 when viewed from above are surfaces perpendicular to the (111) plane, and are crystallographically equivalent {110} planes due to the symmetry of the crystal lattice. Crystallographically equivalent surfaces are those in which the arrangement of atoms and the spacing between atoms are the same.

[0033] Typically, a silicon layer is formed on the (100) facet of a silicon substrate. In this case, when viewed from above, two of the six sides of the silicon layer, which face the six sides of the gate electrode formed by a honeycomb pattern composed of multiple regular hexagons, are {100} faces, and four are {470} faces. With such a mixture of high Miller index faces on the six sides of the silicon layer, deviations in characteristics due to differences in channel mobility and threshold due to facet orientation are likely to occur.

[0034] According to this embodiment, in the semiconductor layer 20 located inside the hexagonal gate electrode 50 when viewed from above, all six first side surfaces 20A that are respectively opposite to the six side surfaces 50A of the gate electrode are equivalent crystal planes, thereby reducing the deviation of channel mobility and threshold in the six first side surfaces 20A.

[0035] The gate insulating film 61 is, for example, a silicon oxide film, which can be formed by thermal oxidation after the trench t is formed in the semiconductor layer 20. According to this embodiment, the first sidewall 20A of the semiconductor layer 20, which serves as the sidewall of the trench t, ​​becomes an equivalent crystal plane in all directions extending from the trench t when viewed from above. Therefore, the deviation in the growth rate of the silicon oxide films in the six first sidewalls 20A can be reduced, and the deviation in the thickness of the gate insulating film 61 located between the first sidewalls 20A and the sidewall 50A of the gate electrode 50 can be reduced. This, in turn, reduces threshold deviations, etc.

[0036] Furthermore, the third surface 20C of the semiconductor layer 20 forming the bottom surface of the trench t is parallel to the first surface 11 of the substrate 10 and is a (111) surface. In silicon, the growth rate of the silicon oxide film on the (110) surface is the same as that on the (111) surface. Therefore, the deviation between the thickness of the gate insulating film 61 located between the first side surface 20A and the side surface 50A of the gate electrode 50 and the thickness of the gate insulating film 61 located between the third surface 20C and the lower end of the gate electrode 50 can be reduced. As a result, the gate insulating film 61 is less prone to local insulation failure, and the withstand voltage can be improved.

[0037] In this embodiment, the field plate electrode 40 extends in a columnar shape within the semiconductor layer 20 in a direction parallel to the

[111] direction. Figure 1 In the example shown, a field plate electrode 40 is a hexagonal prism with six sides 40A. The semiconductor layer 20 surrounding one field plate electrode 40, when viewed from above, has six equivalent crystal planes, namely second sides 20B, which are respectively opposed to the six sides 40A of the field plate electrode 40. These six second sides 20B are planes perpendicular to the (111) plane (first plane 11) of the substrate 10, and are equivalent to {110} planes.

[0038] The field insulating film 62 is, for example, a silicon oxide film, which can be formed by thermal oxidation after the hexagonal holes h are formed in the semiconductor layer 20. According to this embodiment, the six second sidewalls 20B of the semiconductor layer 20, which serve as the sidewalls of the holes h, become equivalent crystal planes. Therefore, the deviation in the growth rate of the silicon oxide film in the six second sidewalls 20B can be reduced, and the deviation in the film thickness of the field insulating film 62 located between the second sidewalls 20B and the sidewalls 40A of the field electrode 40 can be reduced. As a result, the field insulating film 62 is less prone to localized insulation failure, and its withstand voltage can be improved.

[0039] Furthermore, the fourth surface 20D of the semiconductor layer 20 constituting the bottom surface of the hole h is parallel to the first surface 11 of the substrate 10 and is a (111) surface. As described above, in silicon, the growth rate of the silicon oxide film on the (110) surface is the same as that on the (111) surface. Therefore, the deviation between the thickness of the field insulating film 62 located between the second side surface 20B and the side surface 40A of the field plate electrode 40 and the thickness of the field insulating film 62 located between the fourth surface 20D and the lower end of the field plate electrode 40 can be reduced. As a result, the field insulating film 62 is less prone to local insulation failure, and the withstand voltage can be improved.

[0040] The trench t that forms the gate electrode 50 can be formed on the semiconductor layer 20, for example, by a reactive ion etching (RIE) method. In this case, the depth of the intersection point where the extensions of the trenches extending in three different directions intersect when viewed from above is deeper than the depth of the trench extensions. Therefore, the lower end of the intersection point 51 of the gate electrode 50 is located below the lower end of the extension 52.

[0041] Between a field plate electrode 40 and a hexagonal gate electrode 50 surrounding the field plate electrode 40 (viewed from above), the shortest distance between the center of the field plate electrode 40 (viewed from above) and the center of the intersection 51 of the gate electrode 50 (viewed from above) is longer than the shortest distance between the center of the field plate electrode 40 and the extension 52 of the gate electrode 50. Due to this difference in distance, the electric field from the field plate electrode 40 is less likely to affect the intersection 51 of the gate electrode 50 compared to the extension 52. By positioning the lower end of the intersection 51 of the gate electrode 50 below the lower end of the extension 52, the electric field from the field plate electrode 40 can more easily act on the lower end of the intersection 51 of the gate electrode 50, thus mitigating the electric field concentration at the lower end of the intersection 51 of the gate electrode 50.

[0042] Field plate electrode 40 can also be as follows Figure 3 As shown, it is cylindrical. The shape of the hole h for arranging the field plate electrode 40 when viewed from above is circular.

[0043] The substrate 10 is not limited to a silicon substrate; for example, a gallium nitride (GaN) substrate can also be used. In this case, by forming a GaN layer as a semiconductor layer 20 on the c-surface of the GaN substrate, which serves as the first surface 11 of the substrate 10, the surface orientation of the first side surface 20A and the second side surface 20B of the semiconductor layer 20 can be aligned with the equivalent m-surface. Alternatively, using a silicon carbide (SiC) substrate as the substrate 10, forming a SiC layer as a semiconductor layer 20 on the c-surface of the SiC substrate can also achieve the same effect.

[0044] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0045] [Explanation of reference numerals in the attached figures]

[0046] 1… Semiconductor device, 10… Substrate, 11… First surface, 12… Second surface, 20… Semiconductor layer, 20A… First side surface, 20B… Second side surface, 20C… Third surface, 20D… Fourth surface, 21… First semiconductor section, 22… Second semiconductor section, 23… Third semiconductor section, 31… First electrode, 32… Second electrode, 40… Field plate electrode, 40A… Side surface of field plate electrode, 50… Gate electrode, 50A… Side surface of gate electrode, 51… Intersection, 52… Extension, 61… Gate insulating film, 62… Field insulating film, 63… Insulating layer, h… Hole, t… Trench.

Claims

1. A semiconductor device comprising: a substrate having a first surface; a semiconductor layer provided on the first surface of the substrate; a plurality of field plate electrodes provided in the semiconductor layer, located at vertices of a triangle in a plane parallel to the first surface; and a gate electrode located between the plurality of field plate electrodes in the plane parallel to the first surface, a pattern surrounding one of the field plate electrodes being a hexagon having six sides around the one field plate electrode, the semiconductor layer having six equivalent crystal planes, i.e., first side surfaces, respectively opposing the six sides of the gate electrode.

2. The semiconductor device according to claim 1, wherein the substrate is a silicon substrate, the semiconductor layer is a silicon layer, the first surface is a (111) surface, and the six first side surfaces are {110} surfaces.

3. The semiconductor device according to claim 2, wherein the field plate electrodes extend in the semiconductor layer along a direction parallel to a [111] direction.

4. The semiconductor device according to claim 1, wherein the one field plate electrode is a hexagonal prism having six sides, and the semiconductor layer has six equivalent crystal planes, i.e., second side surfaces, respectively opposing the six sides of the field plate electrode.

5. The semiconductor device according to claim 4, wherein the substrate is a silicon substrate, the semiconductor layer is a silicon layer, the first surface is a (111) surface, and the six second side surfaces are {110} surfaces.

6. The semiconductor device according to claim 1, wherein the gate electrode has a cross point portion and extension portions extending from the cross point portion to different three directions, respectively, and a lower end of the cross point portion is located at a position lower than lower ends of the extension portions.

7. The semiconductor device according to claim 1, further comprising a first electrode and a second electrode, wherein the substrate and the semiconductor layer are provided between the first electrode and the second electrode.

8. The semiconductor device according to claim 7, wherein the substrate has a second surface located on an opposite side of the first surface and in contact with the first electrode.

9. The semiconductor device according to claim 1, wherein the semiconductor layer has: a first semiconductor portion of a first conductivity type provided on the first surface of the substrate; a second semiconductor portion of a second conductivity type provided on the first semiconductor portion; and a third semiconductor portion of the first conductivity type provided on the second semiconductor portion, and a first conductivity type impurity concentration of the third semiconductor portion is higher than a first conductivity type impurity concentration of the first semiconductor portion.

10. The semiconductor device according to claim 9, wherein the substrate is of the first conductivity type.

11. The semiconductor device according to claim 9, wherein the substrate is of the second conductivity type.

12. The semiconductor device according to claim 9, wherein the field plate electrodes do not reach the substrate, and lower ends of the field plate electrodes are located in the first semiconductor portion.

13. The semiconductor device according to claim 7, wherein a shortest distance between a lower end of the field plate electrode and the first electrode is shorter than a shortest distance between a lower end of the gate electrode and the first electrode.

14. The semiconductor device according to claim 7, wherein the semiconductor layer has: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ a first semiconductor portion of a first conductivity type provided on the first surface of the substrate; a second semiconductor portion of a second conductivity type provided on the first semiconductor portion; and a third semiconductor portion of the first conductivity type provided on the second semiconductor portion, the first conductivity type impurity concentration of the third semiconductor portion is higher than the first conductivity type impurity concentration of the first semiconductor portion.

15. The semiconductor device according to claim 14, the third semiconductor portion is in contact with the second electrode.

16. The semiconductor device according to claim 14, the substrate is of the first conductivity type.

17. The semiconductor device according to claim 14, the substrate is of the second conductivity type.

18. The semiconductor device according to claim 14, the field plate electrode does not reach the substrate, a lower end of the field plate electrode is positioned within the first semiconductor portion.

19. The semiconductor device according to claim 14, a shortest distance between a lower end of the field plate electrode and the first electrode is shorter than a shortest distance between a lower end of the gate electrode and the first electrode.

20. The semiconductor device according to claim 7, the field plate electrode is in contact with the second electrode.

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