Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention discloses a semiconductor device and a manufacturing method of the semiconductor device. A first dielectric layer of the device covers a partial region of a first surface of a substrate; the gate structure covers the first dielectric layer; the first side walls cover the two sides of the gate structure and are located on the first dielectric layer; the second side wall covers the first side wall and the two sides of the first dielectric layer, and is in contact with the first surface of the substrate. The first dielectric layer can be used for wrapping and covering the bottom of the gate structure so as to reduce the situation that etching liquid makes contact with the gate structure through the substrate and damages the gate structure, the second side wall covers the first side wall and the two sides of the first dielectric layer, and the second side wall can cover and protect the interface between the first side wall and the first dielectric layer. Therefore, an etching solution is prevented from entering and damaging a gate structure through an interface between the first side wall and the first dielectric layer, the protection effect of the side wall on the gate structure is further improved, and the device yield is further improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and a manufacturing method of the semiconductor device. BACKGROUND

[0002] In the preparation process of a semiconductor device, a current gate etching process usually needs to introduce a side wall to protect the gate structure. Especially in the preparation of a semiconductor device with a node below 28nm, a High-k material (HK layer) is introduced as the bottom layer of the gate structure, and the side wall is used to protect the HK layer of the gate structure. The protection effect of the side wall on the HK layer directly affects the process effect of subsequent processes such as ion implantation and material deposition in the preparation of the semiconductor device, and thus affects the production yield of the semiconductor device.

[0003] The existing gate etching process in the preparation of a semiconductor device has insufficient wrapping of the HK layer by the side wall, which causes the etching solution used in the subsequent process to damage the HK layer, resulting in a decrease in the yield of the device. SUMMARY

[0004] To solve the above technical problems, the present application provides a semiconductor device and a manufacturing method of the semiconductor device.

[0005] To solve the above problems, the present application provides a first technical solution: providing a semiconductor device, comprising a substrate, a first dielectric layer, a gate structure, a first side wall and a second side wall; the first dielectric layer covers part of the first surface of the substrate; the gate structure covers the first dielectric layer; the first side wall covers both sides of the gate structure and is located on the first dielectric layer; the second side wall covers both sides of the first side wall and the first dielectric layer and is in contact with the first surface of the substrate.

[0006] Optionally, the first side wall is in contact with the first dielectric layer to form a first contact surface, the second side wall is in contact with the first surface of the substrate to form a second contact surface, and the first contact surface and the second contact surface are not in the same plane.

[0007] Optionally, the substrate has a boss protruding from the first surface, the first dielectric layer covers the boss, and the gate structure and the first side wall cover the first dielectric layer on the boss.

[0008] Optionally, the second side wall covers both sides of the first side wall, the first dielectric layer and the boss.

[0009] Optionally, the substrate further includes a substrate body disposed around the protrusion, the contact surface of the second sidewall in contact with the substrate body forms a second contact surface, the contact surface of the first sidewall in contact with the first dielectric layer forms a first contact surface, the substrate has a second surface disposed opposite to the first surface, and the second contact surface is closer to the second surface than the first contact surface.

[0010] Optionally, the gate structure includes a high dielectric constant layer that covers the first dielectric layer.

[0011] Optionally, the substrate has ion-doped regions on both sides near the gate structure.

[0012] To address the aforementioned problems, this application provides a second technical solution: a method for manufacturing a semiconductor device, comprising: providing a substrate; forming a first dielectric layer covering a first surface of the substrate; forming a gate structure covering the first dielectric layer; forming a first sidewall covering both sides of the gate structure, the first sidewall being located on the first dielectric layer; and forming a second sidewall covering both sides of the first sidewall and the first dielectric layer, the second sidewall being in contact with the first surface of the substrate.

[0013] Optionally, after the step of forming a first sidewall covering both sides of the gate structure, wherein the first sidewall is located on the first dielectric layer, the manufacturing method further includes: removing the first dielectric layer and a portion of the substrate located outside the coverage area of ​​the first sidewall and the gate structure, so that the substrate forms a boss; the step of forming a second sidewall covering both sides of the first sidewall and the first dielectric layer, wherein the second sidewall is in contact with a first surface of the substrate, includes: forming a second sidewall covering both sides of the first sidewall and the first dielectric layer, wherein the second sidewall is in contact with a substrate body surrounding the outside of the boss.

[0014] Optionally, when removing the substrate located outside the coverage area of ​​the first sidewall and the gate structure, the amount of substrate removed is less than or equal to 10 Å.

[0015] Optionally, after the step of forming a first sidewall covering both sides of the gate structure, wherein the first sidewall is located on the first dielectric layer, the manufacturing method further includes: performing a first dose of ion implantation on both sides of the first dielectric layer near the gate structure.

[0016] Optionally, after the step of removing the first dielectric layer and part of the substrate located outside the coverage area of ​​the first sidewall and the gate structure to form a boss on the substrate, the manufacturing method further includes performing a second dose of ion implantation on both sides of the substrate near the gate structure.

[0017] This application provides a semiconductor device and a method for manufacturing the semiconductor device. The device includes a substrate, a first dielectric layer, a gate structure, a first sidewall, and a second sidewall. The first dielectric layer covers a portion of a first surface of the substrate. The gate structure covers the first dielectric layer. The first sidewall covers both sides of the gate structure and is located on the first dielectric layer. The second sidewall covers both sides of the first sidewall and the first dielectric layer and is in contact with the first surface of the substrate. The first dielectric layer can be used to wrap and cover the bottom of the gate structure to reduce the contact between the etching solution and the gate structure through the substrate and damage to the gate structure. Since the second sidewall covers both sides of the first sidewall and the first dielectric layer, the second sidewall can cover and protect the interface between the first sidewall and the first dielectric layer to reduce the entry of the etching solution through the interface between the first sidewall and the first dielectric layer and damage to the gate structure, further improving the protective effect of the sidewall on the gate structure, thereby improving the device yield. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a schematic diagram of the structure of an embodiment of the semiconductor device provided in this application; Figure 2 This is a schematic flowchart of an embodiment of the semiconductor device manufacturing method provided in this application; Figure 3 This is a schematic diagram of the structure provided in this application for forming bosses that are respectively connected to the gate structure and the first sidewall; Figure 4 This is a schematic diagram of the structure of the semiconductor device forming the gate structure and the first sidewall provided in this application; Figure 5 This is a schematic diagram of the structure of the semiconductor device forming the second sidewall provided in this application.

[0019] Wherein, 10 is the substrate; 11 is the boss; 12 is the substrate body; 20 is the gate structure; 30 is the first sidewall; 40 is the second sidewall; 50 is the first dielectric layer; and 60 is the isolation structure. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0022] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0023] This application first provides a semiconductor device. For example... Figure 1 As shown, Figure 1 This is a schematic diagram of a semiconductor device according to an embodiment of the present application. In this embodiment, the semiconductor device includes a substrate 10, a gate structure 20, a first sidewall 30, a second sidewall 40, and a first dielectric layer 50.

[0024] A first dielectric layer 50 covers a portion of the first surface of the substrate 10. A gate structure 20 covers the first dielectric layer 50. A first sidewall 30 covers both sides of the gate structure 20 and is located on the first dielectric layer 50. A second sidewall 40 covers both sides of the first sidewall 30 and the first dielectric layer 50, and is in contact with the first surface of the substrate 10.

[0025] A gate structure 20 is disposed on the substrate 10 of the semiconductor device. The gate structure 20 can be, but is not limited to, a metal gate structure. For example, the gate structure 20 includes, but is not limited to, an interface oxide layer, a high dielectric constant layer, a barrier layer, a work function metal layer, a metal filling layer, or a mask layer. A first dielectric layer 50 covers a portion of the first surface of the substrate 10. The first surface of the substrate 10 is a plane on the side of the substrate 10 closest to the gate structure 20. A first sidewall 30 covers both sides of the gate structure 20 and is located on the first dielectric layer 50. One end of the first sidewall 30 covers the sidewall of the gate structure 20 away from the first dielectric layer 50, and the other end of the first sidewall 30 extends to and contacts the first dielectric layer 50. That is, both the first sidewall 30 and the gate structure 20 are located on the first dielectric layer 50, and a portion of the first dielectric layer 50 is located between the first sidewall 30 and the substrate 10.

[0026] The second sidewall 40 covers both sides of the first sidewall 30 and the first dielectric layer 50, and one side of the second sidewall 40 contacts the first surface of the substrate 10. In a possible embodiment, the second sidewall 40 and the first dielectric layer 50 enclose an upward-opening enclosing space, within which the sidewalls and bottom of the gate structure 20 are located, and the first sidewall 30 is located. The top of the gate structure 20 is exposed through the opening in the enclosing space to allow the gate structure 20 to be led out. The first sidewall 30 contacts the first dielectric layer 50 to form a first contact surface, and the second sidewall 40 contacts the first surface of the substrate 10 to form a second contact surface. The substrate 10 has a second surface opposite to the first surface, and the second contact surface of the second sidewall 40 contacting the substrate 10 is closer to the second surface than the first contact surface of the first sidewall 30 contacting the first dielectric layer 50.

[0027] In this embodiment, the first dielectric layer 50 covers a portion of the first surface of the substrate 10; the gate structure 20 covers the first dielectric layer 50; the first sidewall 30 covers both sides of the gate structure 20 and is located on the first dielectric layer 50; the second sidewall 40 covers both sides of the first sidewall 30 and the first dielectric layer 50, and is in contact with the first surface of the substrate 10. The first dielectric layer 50 can be used to wrap and cover the bottom of the gate structure 20 to prevent the etching solution from contacting and damaging the gate structure 20. Since the second sidewall 40 covers both sides of the first sidewall 30 and the first dielectric layer 50, and the second contact surface of the second sidewall 40 is closer to the second surface than the first contact surface of the first sidewall 30, the second sidewall 40 can cover and protect the interface between the first sidewall 30 and the first dielectric layer 50, thereby reducing the entry of the etching solution through the interface between the first sidewall 30 and the first dielectric layer 50 and damaging the gate structure 20, further improving the protective effect of the sidewall on the gate structure 20, and thus improving the device yield.

[0028] In one embodiment, the first contact surface of the first sidewall 30 and the second contact surface of the second sidewall 40 are not on the same plane.

[0029] Specifically, the second sidewall 40 extends to and contacts the first surface of the substrate 10, and the contact surface of the second sidewall 40 with the first surface of the substrate 10 is the second contact surface. The first sidewall 30 covers the sidewall of the gate structure, and the first sidewall 30 contacts the side of the first dielectric layer 50 away from the substrate 10, and the contact surface of the first sidewall 30 with the side of the first dielectric layer away from the substrate 10 is the first contact surface. The first contact surface and the second contact surface do not coincide, or the first contact surface and the second contact surface are parallel, or the second contact surface is closer to the second surface of the substrate 10 relative to the first contact surface.

[0030] Therefore, in the semiconductor device of this embodiment, there is a height difference between the first contact surface of the first sidewall 30 and the second contact surface of the second sidewall 40. When the semiconductor device is subsequently processed with an etching solution, the second sidewall 40 can cover and protect the interface between the first sidewall 30 and the first dielectric layer 50. The etching solution is less likely to enter through the substrate 10 and damage the gate structure 20, which can effectively improve the protection effect of the sidewall on the gate structure 20, thereby improving the device yield.

[0031] In one embodiment, the substrate 10 has a boss 11 protruding from a first surface, a first dielectric layer 50 covering the boss 11, and a gate structure 20 and a first sidewall 30 covering the first dielectric layer 50 on the boss 11.

[0032] Specifically, a boss 11 protrudes from the first surface of the substrate 10, and a first dielectric layer 50 covers the boss 11. The cross-section of the first dielectric layer 50 is the same as the cross-section of the protruding area of ​​the boss 11. A gate structure 20 covers the middle region of the first dielectric layer 50, and a first sidewall 30 covers the sidewall of the gate structure 20. The first contact surface of the first sidewall 30 and the gate structure 20 together cover the surface of the first dielectric layer 50 away from the substrate 10.

[0033] Optionally, the second sidewall 40 covers both sides of the first sidewall 30, the first medium layer 50, and the boss 11.

[0034] The second sidewall 40 covers the first side surface of the first sidewall 30, and the second side surface of the first sidewall 30 covers the gate structure 20. The second sidewall 40 contacts the first surface of the substrate 10 on the side offset from the boss 11 to cover the sidewall of the first dielectric layer 50 and the sidewall of the boss 11, and to protect the interface between the first sidewall 30 and the first dielectric layer 50, and the interface between the first dielectric layer 50 and the boss 11.

[0035] Therefore, the second sidewall 40 can simultaneously cover and protect the interface between the first sidewall 30 and the first dielectric layer 50, as well as the interface between the first dielectric layer 50 and the boss 11, so as to reduce or prevent the etching solution from entering and damaging the gate structure 20 through the interface between the first sidewall 30 and the first dielectric layer 50 and the interface between the first dielectric layer 50 and the boss 11, thereby further improving the protection effect of the sidewall on the gate structure 20 and thus improving the device yield.

[0036] Furthermore, the substrate 10 also includes a substrate body 12 disposed around the boss 11, the contact surface of the second sidewall 40 in contact with the substrate body 12 forms a second contact surface, the contact surface of the first sidewall 30 in contact with the first dielectric layer 50 forms a first contact surface, the substrate 10 has a second surface disposed opposite to the first surface, and the second contact surface of the second sidewall 40 is closer to the second surface than the first contact surface of the first sidewall 30.

[0037] Specifically, the substrate 10 includes a substrate body 12 and a boss 11. The boss 11 is formed by protruding from one side of the first surface of the substrate body 12, and the substrate body 12 is disposed around the boss 11. A portion of the first dielectric layer 50 is located between the first sidewall 30 and the boss 11, and the second sidewall 40 is in contact with the substrate body 12 on one side of the boss 11.

[0038] The second contact surface of the second sidewall 40 is closer to the second surface than the first contact surface of the first sidewall 30. That is, the second sidewall 40 extends and covers part of the substrate 10, and the second sidewall 40 can simultaneously cover and protect the first sidewall 30, the first dielectric layer 50, and the side of the boss 11.

[0039] Therefore, in this embodiment, the semiconductor device is configured such that the second contact surface of the second sidewall 40 that contacts the substrate body 12 is closer to the second surface of the substrate 10 than the first contact surface of the first sidewall 30 that contacts the first dielectric layer 50. This allows the second sidewall 40 to cover the interface between the first sidewall 30 and the first dielectric layer 50, thereby improving the protection effect of the second sidewall 40 on the gate structure 20 and improving the device yield.

[0040] Furthermore, the first dielectric layer 50 of the semiconductor device is located between the protrusion 11 and the gate structure 20. The first dielectric layer 50 may be, but is not limited to, a silicon oxide dielectric layer. The first dielectric layer 50 is used to reduce the entry of etching solution through the interface between the first sidewall 30 and the protrusion 11 of the substrate 10 and damage the gate structure 20, thereby improving the protective effect of the sidewall on the gate structure 20 and improving the device yield.

[0041] In one embodiment, the gate structure 20 includes a high dielectric constant layer that covers the first dielectric layer 50.

[0042] Specifically, the high-k dielectric layer of the gate structure serves as the gate dielectric, used to collaboratively regulate the threshold voltage to ensure device drive capability and reliability. In the prior art, both the second sidewall 40 and the first sidewall 30 only cover the sidewalls of the gate structure 20. When wet etching is required in subsequent manufacturing processes, the etching solution can enter the gate structure 20 through the interface between the second sidewall 40 and the first dielectric layer 50 and damage the high-k dielectric layer. This can lead to problems such as leakage current spikes and threshold voltage runaway in semiconductor devices, affecting device yield and reliability.

[0043] In this embodiment, the first dielectric layer 50 can be used to cover the bottom of the gate structure 20 to reduce the contact between the etching solution with certain properties and the gate structure 20 through the substrate 10. Since the second sidewall 40 covers both sides of the first sidewall 30 and the first dielectric layer 50, the second sidewall 40 can cover and protect the interface between the first sidewall 30 and the first dielectric layer 50, further reducing the entry of the etching solution through the interface between the first sidewall 30 and the first dielectric layer 50 and damaging the high dielectric constant layer, further improving the protection effect of the sidewall on the high dielectric constant layer, and thus improving the device yield.

[0044] In one embodiment, the substrate 10 has ion-doped regions on both sides near the gate structure 20.

[0045] Specifically, the ion-doped region can be, but is not limited to, forming the P-type or N-type source / drain region of the substrate 10. Depending on the process requirements of the semiconductor device, the thickness of the sidewalls, etc., the above-mentioned ion-doped region can be formed by one or more ion implantations. The concentration distribution of implanted ions, junction depth, etc., can be selected according to requirements and are not specifically limited here.

[0046] This application also provides a method for manufacturing a semiconductor device, which can be used to manufacture semiconductor devices as described in any of the above embodiments. Figure 2 As shown, Figure 2 This is a schematic flowchart of an embodiment of the semiconductor device manufacturing method provided in this application. Figure 2 As shown, the manufacturing method of this embodiment includes the following steps: Step S1: Provide substrate 10.

[0047] Specifically, a substrate 10 is provided, which serves as a mechanical support and process platform for subsequent process devices and packaging. In possible embodiments, the substrate 10 may have multiple active regions and isolation structures 60, which isolate the multiple active regions to improve electrical performance.

[0048] Step S2: Form a first dielectric layer 50 covering the first surface of the substrate 10.

[0049] The first dielectric layer 50 covers the first surface of the substrate 10, and the first dielectric layer 50 may be, but is not limited to, a silicon oxide dielectric layer.

[0050] Step S3: Form a gate structure 20 covering the first dielectric layer 50.

[0051] A gate structure 20 is formed covering the first dielectric layer 50. The gate structure 20 may be, but is not limited to, a metal gate, which is formed by stacking multiple layers, such as an interface oxide layer, a high dielectric constant layer, a barrier layer, a work function metal layer, a metal filling layer, or a mask layer.

[0052] Step S4: Form a first sidewall 30 covering both sides of the gate structure 20, the first sidewall 30 being located on the first dielectric layer 50.

[0053] After the gate structure 20 is formed, a first sidewall 30 is formed covering both sides of the gate structure 20. The first sidewall 30 extends along the height direction on the substrate 10, with one side of the first sidewall 30 extending to the top of the gate structure 20 and the other side extending to the tail of the gate structure 20 and contacting the first dielectric layer 50. The first sidewall 30 and the first dielectric layer 50 are in contact to form a first contact surface. The first sidewall 30 and the gate structure 20 are located on the first dielectric layer 50.

[0054] Step S5: Form a second sidewall 40 covering both sides of the first sidewall 30 and the first dielectric layer 50, the second sidewall 40 being in contact with the first surface of the substrate 10.

[0055] After the first sidewall 30 is formed, a second sidewall 40 is formed covering the first sidewall 30 and the first dielectric layer 50. The second sidewall 40 extends along the height direction on the substrate 10. One side of the second sidewall 40 covers the first sidewall 30, and the other side of the second sidewall 40 covers the first dielectric layer 50 and contacts the first surface of the substrate 10. The contact between the second sidewall 40 and the first surface of the substrate 10 forms a second contact surface, which is closer to the second surface of the substrate 10 than the first contact surface.

[0056] Therefore, the manufacturing method of this embodiment provides a substrate 10, forms a first dielectric layer 50 covering the substrate 10, the first dielectric layer 50 covering a portion of the first surface of the substrate 10; forms a gate structure 20 covering the first dielectric layer 50; forms a first sidewall 30 covering both sides of the gate structure 20, the first sidewall 30 being located on the first dielectric layer 50; and forms a second sidewall 40 covering both sides of the first sidewall 30 and the first dielectric layer 50, the second sidewall 40 being in contact with the first surface of the substrate 10, so that the second sidewall 40 can be used to cover and protect the interface between the first sidewall 30 and the first dielectric layer 50, thereby reducing the entry of etching solution through the interface between the first sidewall 30 and the first dielectric layer 50 and damaging the gate structure 20, further improving the protective effect of the sidewall on the gate structure 20, and thus improving the device yield.

[0057] In one embodiment, after step S4, the manufacturing method further includes: removing the first dielectric layer 50 and a portion of the substrate 10 outside the coverage area of ​​the first sidewall 30 and the gate structure 20, so that the substrate 10 forms a boss 11. Step S5 further includes: forming a second sidewall 40 covering both sides of the first sidewall 30 and the first dielectric layer 50, and the second sidewall 40 contacting the substrate body 12 surrounding the outside of the boss 11.

[0058] Specifically, such as Figure 3 As shown, Figure 3 This is a schematic diagram of the structure provided in this application for forming protrusions that are respectively connected to the gate structure and the first sidewall. In this embodiment, by using the first sidewall 30 and the gate structure 20 as masks, the first dielectric layer 50 and part of the substrate 10 outside the coverage area of ​​the first sidewall 30 and the gate structure 20 are removed using dry etching, wet etching, or other processing methods. This results in a protrusion 11 being formed on the substrate 10 below the first sidewall 30 and the gate structure 20, with a first dielectric layer 50 between the protrusion 11 and the first sidewall 30 and the gate structure 20. At this time, the first dielectric layer 50 is used to form an enclosing space with the second sidewall 40, and the gate structure 20 is located within the enclosing space to achieve coverage and protection of the gate structure 20.

[0059] Optionally, the removal of the first dielectric layer 50 and part of the substrate 10 outside the coverage area of ​​the first sidewall 30 and the gate structure 20 may further include controlling the amount of substrate 10 removed to be less than or equal to 10 Å.

[0060] Specifically, such as Figure 4 As shown, Figure 4 This is a schematic diagram of the semiconductor device forming the gate structure and the first sidewall provided in this application. Figure 4In this configuration, the first dielectric layer 50 covers the substrate, and the gate structure 20 and the first sidewall 30 are disposed on the first dielectric layer 50. At this time, the first sidewall 30 and the gate structure 20 can be used as masks, and etching gases or liquids suitable for the substrate 10 and the first dielectric layer 50 can be selected for etching to remove the first dielectric layer 50 and the substrate 10 located outside the first sidewall 30 and the gate structure 20, thus obtaining the desired result. Figure 3 The substrate structure shown has a boss 11.

[0061] When removing the substrate 10, the amount of substrate 10 removed can be controlled to be less than or equal to 10 Å by controlling the concentration and time of the etching gas or liquid. Therefore, by limiting the amount of substrate 10 removed to within 10 Å, this application enables the second sidewall 40 to extend precisely to a position closer to the second surface of the substrate 10, ensuring the protective effect of the second sidewall 40 between the first dielectric layer 50 and the boss 11, while ensuring that the thickness of the substrate 10 is sufficient to provide support for subsequent processes, thereby improving device yield.

[0062] Optionally, after step S4, the manufacturing method of this embodiment further includes performing a first dose of ion implantation on both sides of the first dielectric layer 50 near the gate structure 20.

[0063] Specifically, after forming the first sidewall 30, a first dose of ion implantation is performed on both sides of the first dielectric layer 50 near the gate structure 20. The first sidewall 30 serves as an insulating dielectric layer to isolate the gate structure 20 from the implanted dopant ions, preventing direct electrical contact between the gate structure 20 and the dopant ions. Furthermore, during ion implantation, the first dielectric layer 50 protects the substrate 10, reducing damage to the substrate 10 during ion implantation, thereby reducing the energy required for the first dose of ion implantation, improving the reliability of the first dose of ion implantation, and ultimately improving device yield.

[0064] In one possible implementation, by performing a first dose of ion implantation on both sides of the first dielectric layer 50, ion-doped regions can be formed on both sides of the substrate 10 corresponding to the gate structure 20, so that the ion-doped regions serve as P-type source / drain regions or N-type source / drain regions of the substrate 10.

[0065] In another possible implementation, depending on the requirements of the semiconductor device performance for sidewall thickness, two ion implantation operations can be performed to form ion-doped regions on both sides of the substrate 10 corresponding to the gate structure 20.

[0066] Specifically, after the step of removing the first dielectric layer 50 and part of the substrate 10 outside the coverage area of ​​the first sidewall 30 and the gate structure 20 to form the protrusion 11 on the substrate 10, the manufacturing method of this embodiment further includes performing a second dose of ion implantation on both sides of the substrate 10 near the gate structure 20.

[0067] The ions implanted into the substrate 10 are used to change the electrical properties of local areas of the substrate 10. The ions selected vary depending on the type of substrate. When the conductive charge carrier is electron, the implanted ions are usually N-type impurities that provide electrons; when the conductive charge carrier is hole, the implanted ions are usually P-type impurities that provide holes. No specific restrictions are placed on the type of ions, doping concentration, or implantation depth for the first and second implantations.

[0068] Therefore, the manufacturing method of this embodiment first performs a first dose of ion implantation on both sides of the first dielectric layer 50 to protect the substrate 10 through the first dielectric layer 50 and reduce the damage to the substrate 10 caused by the first dose of ion implantation. Then, a second dose of ion implantation is performed on both sides of the substrate 10 near the gate structure 20. Since the first dose of ions has already been implanted, less energy is required to form the ion-doped region during the second ion implantation, further reducing the damage to the substrate 10 caused by the first dose of ion implantation. That is, this embodiment protects the substrate 10 from the first ion implantation by the first dielectric layer 50 and reduces the doping energy of each ion implantation by segmented ion implantation, which can effectively reduce the degree of damage to the substrate 10 during the ion implantation process, thereby improving the reliability of the substrate 10.

[0069] Furthermore, in step S5, the manufacturing method may further include: depositing a second sidewall 40 covering the first sidewall 30 on the substrate 10; etching the second sidewall 40 so that the second sidewall 40 extends along the height direction of the gate structure 20 and covers both sides of the first dielectric layer 50 and the boss 11.

[0070] like Figure 5 As shown, Figure 5 This is a schematic diagram of the semiconductor device forming the second sidewall provided in this application. After depositing the second sidewall 40 covering the first sidewall 30 on the substrate 10, the second sidewall 40 is further etched to remove the second sidewalls 40 on both sides of the boss 11 and to remove the second sidewall 40 covering the top of the gate structure 20, thereby forming the second sidewall 40 extending along the height direction of the gate structure 20, thus obtaining the... Figure 1 The structure of the second sidewall 40 shown is designed to ensure that the second sidewall 40 covers the sidewalls of the first sidewall 30, the first medium layer 50, and the boss 11 while reducing the impact of the second sidewall 40 on other parts.

[0071] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate; a first dielectric layer covering a portion of a first surface of the substrate; a gate structure covering the first dielectric layer; a first sidewall covering both sides of the gate structure and located on the first dielectric layer; a second sidewall covering both sides of the first sidewall and the first dielectric layer and contacting the first surface of the substrate.

2. The semiconductor device of claim 1, wherein: the first sidewall contacts the first dielectric layer to form a first contact surface, the second sidewall contacts the first surface of the substrate to form a second contact surface, and the first contact surface and the second contact surface are not in the same plane.

3. The semiconductor device of claim 1, wherein: the substrate has a bump protruding from the first surface, the first dielectric layer covers the bump, and the gate structure and the first sidewall cover the first dielectric layer on the bump.

4. The semiconductor device of claim 3, wherein: the second sidewall covers both sides of the first sidewall, the first dielectric layer, and the bump.

5. The semiconductor device of claim 3, wherein the substrate further comprises a substrate body disposed around the bump, a contact surface of the second sidewall contacting the substrate body forms a second contact surface, a contact surface of the first sidewall contacting the first dielectric layer forms a first contact surface, the substrate has a second surface disposed opposite to the first surface, and the second contact surface is closer to the second surface than the first contact surface.

6. The semiconductor device of claim 1, wherein the gate structure comprises a high dielectric constant layer, and the high dielectric constant layer covers the first dielectric layer.

7. The semiconductor device of claim 1, wherein the substrate has ion-doped regions near both sides of the gate structure.

8. A method of manufacturing a semiconductor device, characterized by The semiconductor device comprises: providing a substrate; forming a first dielectric layer covering a first surface of the substrate; forming a gate structure covering the first dielectric layer; forming a first sidewall covering both sides of the gate structure, the first sidewall being located on the first dielectric layer; forming a second sidewall covering both sides of the first sidewall and the first dielectric layer, the second sidewall contacting the first surface of the substrate.

9. The production method according to claim 8, wherein The semiconductor device further comprises: after the step of forming the first sidewall covering both sides of the gate structure, the first sidewall being located on the first dielectric layer, the manufacturing method further comprises: removing the first dielectric layer and a portion of the substrate outside a covered area of the first sidewall and the gate structure, so that the substrate forms a bump; the step of forming the second sidewall covering both sides of the first sidewall and the first dielectric layer, the second sidewall contacting the first surface of the substrate, comprises:

10. The manufacturing method according to claim 9, wherein forming the second sidewall covering both sides of the first sidewall and the first dielectric layer, and the second sidewall contacting a substrate body disposed around the outside of the bump.

11. The manufacturing method according to claim 9, wherein when removing the substrate outside the covered area of the first sidewall and the gate structure, the amount of the substrate removed is less than or equal to 10 Å. the semiconductor device further comprises: after the step of forming the first sidewall covering both sides of the gate structure, the first sidewall being located on the first dielectric layer, the manufacturing method further comprises: performing a first dose of ion implantation on both sides of the first dielectric layer near the gate structure.

12. The manufacturing method according to claim 11, wherein After the step of removing the first dielectric layer and part of the substrate outside the covered area of the first sidewall and the gate structure to form a mesa of the substrate, the manufacturing method further comprises: performing a second dose of ion implantation on both sides of the substrate near the gate structure.

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