Decoupling capacitor in semiconductor device and method of forming same

Abstract

The invention relates to a decoupling capacitor in a semiconductor device and a method of forming the same. The semiconductor device includes a buried semiconductor layer (110) disposed over a substrate and having a first conductivity type, an epitaxial layer (112) disposed over the buried semiconductor layer and having an opposite second conductivity type, a deep trench isolation structure (120) extending through the epitaxial layer, the buried semiconductor layer and into the substrate, and a capacitor (122 / 132) disposed over the substrate. The capacitor interfaces with the deep trench isolation structure and is electrically coupled to the buried semiconductor layer.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Indian Provisional Patent Application No. 202441067471, filed on September 6, 2024, which is hereby incorporated by reference in its entirety. Technical Field

[0003] This disclosure generally relates to integrated semiconductor devices, and more specifically, to integrated capacitors. Background Technology

[0004] Decoupling capacitors are used in semiconductor devices containing integrated circuits to prevent electrical power transfer by decoupling one part of the semiconductor device from another. Decoupling capacitors help stabilize the power supply and reduce electrical noise in the semiconductor device. Generally, decoupling capacitors are placed near the power supply. In some semiconductor devices, two distinct power supplies may be used. Decoupling capacitors can be used to isolate these two power supplies. Summary of the Invention

[0005] This document discloses a semiconductor device. The semiconductor device includes a buried semiconductor layer disposed above a substrate and having a first conductivity type, an epitaxial layer disposed above the buried semiconductor layer and having a second conductivity type, an epitaxial layer disposed above the buried semiconductor layer and having the opposite second conductivity type, a trench isolation structure extending through the epitaxial layer, the buried semiconductor layer and into the substrate, and a capacitor disposed above the substrate. The capacitor interfaces with the trench isolation structure and is electrically coupled to the buried semiconductor layer.

[0006] This document also discloses an electronic device comprising: a buried semiconductor layer having a first conductivity type disposed above a semiconductor substrate; a semiconductor layer having an opposite second conductivity type disposed above the buried semiconductor layer; and a trench extending through the semiconductor layers to at least the buried semiconductor layer. The electronic device further comprises a doped region disposed within the semiconductor layer and along the sidewalls of the trench. The doped region extends to at least the buried semiconductor layer and has the first conductivity type. The electronic device further comprises a capacitor. The capacitor comprises a doped well forming a plate of the capacitor. The doped well is disposed within the semiconductor layer and has the first conductivity type. The doped well interfaces with the trench and the doped region and is electrically coupled to the buried semiconductor layer through the doped region.

[0007] This document also discloses a method for forming an integrated circuit. The method includes forming a trench through a first semiconductor layer having a first conductivity type to a second semiconductor layer having an opposite second conductivity type. The method further includes forming a doped region having a second conductivity type within the first semiconductor layer, such that the doped region intersects with the sidewalls of the trench. The method further includes forming a conductive layer over the doped region, such that the doped region forms a first plate of a capacitor, and the conductive layer forms a second plate of the capacitor.

[0008] Unless otherwise expressly indicated herein, the foregoing features and elements can be combined in any combination without exclusivity. The operation of these features and elements, and the disclosed examples, will become more apparent from the following description and accompanying drawings. Attached Figure Description

[0009] Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale. While the drawings illustrate various examples employing the principles described herein, they do not limit the scope of the claims.

[0010] Figure 1A , 1B The diagram 1C illustrates a view of the decoupling capacitors for an integrated circuit based on various examples.

[0011] Figure 2A and 2B The diagram shows a view of the decoupling capacitors for the integrated circuits in various examples.

[0012] Figure 3A and 3B The diagram shows a view of the decoupling capacitors for the integrated circuits in various examples.

[0013] Figure 4 Drawing based on Figures 1A to 1C , Figure 2A and 2B as well as Figure 3A and 3B The flowchart shows the method of forming a decoupling capacitor using the device and various examples associated therewith. Detailed Implementation

[0014] The following detailed description is presented for illustrative and not restrictive purposes. Benefits, advantages, and / or solutions to problems may be described with reference to various examples. Detailed descriptions utilize various examples and refer to the accompanying drawings illustrating the various examples described herein. The diagrams, descriptions, and examples are described in sufficient detail to practice this disclosure. It should be understood that the connecting lines shown in the various diagrams are intended to represent exemplary functional relationships and / or physical couplings between various elements, but other relationships and / or couplings are possible while remaining within the scope of this disclosure. It should be further understood that the various diagrams may not be drawn to scale in order to simplify and clarify the detailed descriptions herein. Furthermore, it should be understood that the descriptions and examples contained herein may permit the practice of other examples with logical, chemical, and / or mechanical changes without departing from the spirit and scope of this disclosure. For example, the steps described in the method and process description may be performed in a different order, additional process steps may be added, and / or process steps may be removed, while remaining within the scope of this disclosure.

[0015] Any reference to a singular item and / or instance may include multiple items and / or instances, and any reference to more than one item and / or instance may include a singular item and / or instance. Similarly, unless otherwise stated, a reference to “a / an” or “described” may include one or more of the referenced items. Any reference to the words and / or phrases of connection, coupling, fixing, attachment, or similar terms may include partial, complete, temporary, removable, permanent, or other connection options. Any reference to the phrase of contact may include minimal contact or reduced contact. All scopes used herein may include the upper and lower limits of the scopes disclosed herein, including ratio limits. The stated values ​​may include at least the variations expected within the scope of practicing this disclosure and will be understood and accepted as values ​​included within 10% of the stated values. Similarly, the use of “approximately,” “about,” “substantially,” or other similar terms indicates a quantity that is close to the stated value and still achieves the stated or desired result and / or performs the stated or desired function, and may refer to a quantity within 10% of the stated value.

[0016] The detailed description of the accompanying drawings and illustrations includes reference numerals that may be repeated across multiple instances. The repetition of reference numerals is intended for simplicity and clarity of description and is not intended to establish or define a relationship between the different instances described herein. The examples and descriptions provided herein are intended to be illustrative and do not limit the scope beyond the claims. For example, the use of the terms “above” and “over” may indicate that a first feature is formed in direct contact with a second feature, or may indicate a relationship where there is no direct contact between the first and second features, such as when an additional feature is formed between the first and second features. For instance, “above” can be used to indicate direct contact between the two, and “over” can be used to indicate direct contact or separation by one or more intermediate layers.

[0017] Spatial relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “upward,” “downward,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used herein for ease of discussion and are not intended to limit the orientation of various components, systems, devices, apparatuses, or other features. Therefore, it should be understood and appreciated that the use of spatial relative terms for different orientation practices remains within the scope of this disclosure.

[0018] Decoupling capacitors can be used in integrated circuit devices, including integrated circuit devices with more than one power supply. In various instances, one or more decoupling capacitors can be used at up to about 15% to about 20% of the die size of a given integrated circuit. A baseline process can form the decoupling capacitors adjacent to but not interfaced with a scribe line area of ​​the integrated circuit device. In other words, a gap (e.g., lateral spacing) is typically present between the scribe line area and the decoupling capacitor. Furthermore, the width of the decoupling capacitor formed using the baseline process is designed to be about 5 to about 6 times its length. That is, the extension of the decoupling capacitor in the die area (e.g., the active circuitry area) (e.g., along the width) is about 5 to about 6 times greater than its extension along the edge of the scribe line area (e.g., along the length). Thus, the baseline process designs decoupling capacitors with an aspect ratio of about 1:5 to about 1:6. In addition, the baseline decoupling capacitor may include multiple fingers (e.g., connections, contacts, etc.) to provide a connection between the base plate and the substrate potential, which extends through a break or opening in the top plate of the decoupling capacitor (providing a low equivalent series resistance connection), thereby using significant die space for a given capacitance.

[0019] This document discloses decoupling capacitors that, compared to baseline decoupling capacitors, utilize less die space without adversely affecting the equivalent series resistance (ESR) of the decoupling capacitor. In various instances, the decoupling capacitors consistent with this disclosure may be formed adjacent to and interface with a scribe line structure of an integrated circuit. In some instances, the decoupling capacitor may be partially formed above a portion of an isolation structure (e.g., a deep trench isolation structure) within the scribe line region. In various instances, interface with the scribe line region, and more specifically with the buried layer of the scribe line region, provides a direct connection from the base plate to the substrate potential through the buried layer. This direct connection eliminates the need for fingers or multiple contacts to connect to the base plate through an opening (or break) in the top plate, thereby reducing the die area consumed by the decoupling capacitor. Furthermore, the length of the decoupling capacitor described herein that extends along the scribe line region is at least 10 times the width of the capacitor extending laterally into the die region away from the scribe line region. In various instances, the aspect ratio (sometimes referred to as "width-to-length ratio") can range from about 20:1 to about 60:1, and in some cases from about 35:1 to about 45:1. Finally, the architecture of the decoupling capacitor disclosed herein ensures good electrical connection and good ESR values ​​between the base plate and the top plate (including between the base plate and the buried layer) without the need for additional verification checks during the manufacturing process. While these examples can be expected to provide the benefits described, the invention does not claim specific results unless expressly stated in the particular claims.

[0020] Now for reference Figures 1A to 1C The diagram illustrates a top view and a cross-sectional view of the integrated circuit 100 according to various aspects of this disclosure. Figure 1A This is a top view of an integrated circuit 100 including a scribing region 102, a die region 104, and a decoupling capacitor 106 extending along the scribing region 102. Figure 1B A close-up top view of a portion of an integrated circuit 100, including a portion of a decoupling capacitor 106. Figure 1C This is a schematic cross-sectional view of an integrated circuit including decoupling capacitor 106. In various instances, integrated circuit 100 may be a single circuit or part of a larger circuit. For example, integrated circuit 100 may be part of a larger integrated circuit using two distinct power supplies. Decoupling capacitor 106 provides electrical isolation between the two distinct power supplies to reduce electrical noise.

[0021] refer to Figure 1A This illustrates a portion of integrated circuit 100, including a scribed region 102 that separates integrated circuit 100 containing a first power supply from another integrated circuit having a second unique power supply. Figure 1AAs shown, a scribing region 102 (e.g., a scribing seal) extends around the outer periphery of the integrated circuit 100, which includes a surrounding die region 104. The scribing region 102 is adjacent to a scribing path (e.g., a space, not shown) between adjacent dies on a semiconductor wafer (e.g., a semiconductor substrate). This scribing path can be used to separate the die region during the semiconductor wafer dicing process. The die region 104 refers to the area on the semiconductor wafer containing components of an integrated circuit (e.g., integrated circuit 100). In various instances, the die region 104 may contain any number and / or type of semiconductor components (e.g., functional and non-functional components) forming the integrated circuit, such as transistors, resistors, capacitors, interconnect structures, logic circuit systems, analog circuit systems, memory, or other similar components. For simplicity and clarity, the integrated circuit 100 is shown as a die region surrounded by the scribing region 102. However, this disclosure is not limited to any number of integrated circuits, scribing regions, and / or die regions.

[0022] like Figure 1A and 1C As shown, the scribe region 102 includes a portion of the deep well 118 extending around the outer periphery of the integrated circuit 100 (e.g., within the scribe region 102). In various embodiments, the deep well 118 may be concentric with the scribe region 102. In various embodiments, the deep well 118 may be associated with the substrate potential of the integrated circuit 100, as further described below.

[0023] A decoupling capacitor 106 is disposed along the edge of the scribe region 102, including placement above the deep well 118. The decoupling capacitor 106 has a first length L1 (e.g., along the edge of the scribe region 102, e.g., along the y-axis) and a first width W1 (e.g., along the x-axis into the die region 104) and an aspect ratio L1 / W1. As shown, the first length L1 is substantially greater than the first width W1. In various instances, the aspect ratio may range from about 20:1 to about 60:1, and in some cases from about 35:1 to about 45:1. The relatively large aspect ratio of the decoupling capacitor 106, combined with its placement above the deep well 118, provides good connectivity through the underlying layer (e.g., the first buried layer 110 described below) to the substrate potential (e.g., ground, 0V), reduces the overall die size, and ensures good equivalent series resistance (ESR) for the decoupling capacitor 106.

[0024] For reference Figure 1B , Figure 1AAn enlarged top view of a portion of the decoupling capacitor 106, marked in center, is shown extending along the edge of the dashed region 102, encompassing an area extending above the deep well 118. Additionally, a base plate contact 140a, a top plate contact 140b, and a top plate 132 are shown. The base plate contacts 140a and 140b are positioned above the laterally spaced sides of the decoupling capacitor 106. In various other embodiments, the orientation and arrangement of the base plate contacts 140a and 140b may differ from those illustrated. As will be described in further detail below, the base plate of the decoupling capacitor 106 is electrically coupled to the base plate contacts 140a, and the top plate of the decoupling capacitor 106 is electrically coupled to the top plate contacts 140b (e.g., voltage potential, VDD, etc.).

[0025] For reference Figure 1C Showing the integrated circuit 100 along Figure 1B The cross-section of line A-A'. Integrated circuit 100 includes a semiconductor substrate 108, a first buried layer 110, a second semiconductor layer 112, a second buried layer 114, a doped semiconductor layer 116, a deep well 118, a deep isolation structure 120, a shallow well 122, a shallow isolation structure 124, a contact region 126, a contact region 128, a dielectric layer 130, a top plate 132, a sidewall spacer 134, a dielectric pad 136, a first interlayer dielectric (ILD) layer 138, a contact 140, a first metal layer 142, a second ILD layer 144, a via 146, a second metal layer 148, and a third ILD layer 150.

[0026] Semiconductor substrate 108 may comprise a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or any other suitable substrate. For example, semiconductor substrate 108 may be or comprise a bulk silicon wafer. In various instances, semiconductor substrate 108 may comprise dielectric materials, epitaxially grown materials, and / or any other materials and / or layers thereto to which the processes described herein may be performed. For example, semiconductor substrate 108 may comprise one or more epitaxially grown layers disposed on a semiconductor substrate (e.g., a silicon substrate).

[0027] A first buried layer 110 (e.g., a first buried semiconductor layer) is disposed over a semiconductor substrate 108 and has a first conductivity type. In various embodiments, at least a portion of the first buried layer 110 may be part of a scribing region 102. For example, the first buried layer 110 may include a first portion 110a and a second portion 110b, wherein the first portion 110a is part of the scribing region 102 and the second portion 110b extends within a bare die region 104. Furthermore, the first buried layer 110 has a first voltage potential. In various embodiments, the first voltage potential may be a device voltage potential (e.g., ground). In various embodiments, the first buried layer 110 may include one or more semiconductor layers, such as silicon (Si), germanium (Ge), or silicon-germanium (SiGe), or combinations thereof. In various embodiments, the dopant used may be one or more n-type dopants or one or more p-type dopants. In various embodiments, the n-type dopant may be arsenic (Ar), phosphorus (P), antimony (Sb), or combinations thereof. In various examples, the p-type dopant may be boron (B), indium (In), or a combination thereof. In various examples, the first buried layer 110 may be an n-type buried semiconductor layer.

[0028] A semiconductor layer 112 (e.g., an epitaxial layer) is disposed above the first buried layer 110. In various embodiments, the semiconductor layer 112 may comprise one or more semiconductor layers. In various embodiments, the semiconductor layer 112 may have a second conductivity type opposite to the first conductivity type. For example, when the first buried layer 110 is doped with one or more n-type dopants, the semiconductor layer 112 may be doped with one or more p-type dopants. In another embodiment, when the first buried layer 110 is doped with one or more p-type dopants, the semiconductor layer 112 may be doped with one or more n-type dopants. In various embodiments, the semiconductor layer 112 may be epitaxially grown. In various embodiments, the semiconductor layer 112 may also be referred to as a doped region. In various embodiments, the semiconductor layer 112 may be a p-type semiconductor layer.

[0029] A second buried layer 114 (e.g., a second buried semiconductor layer) is disposed above semiconductor layer 112. The second buried layer 114 may comprise one or more semiconductor layers. In various embodiments, the second buried layer 114 may be epitaxially grown. In various embodiments, the second buried layer 114 may have a second conductivity type. For example, when semiconductor layer 112 is doped with one or more p-type dopants, the second buried layer 114 may be doped with one or more p-type dopants. In various embodiments, the dopant concentration of semiconductor layer 112 may be greater than the dopant concentration of the second buried layer. In various embodiments, the second buried layer 114 may also be referred to as doped region 112.

[0030] A doped semiconductor layer 116 is disposed above the second buried layer 114. In various embodiments, the doped semiconductor layer 116 may comprise one or more semiconductor layers. In various embodiments, the doped semiconductor layer 116 may have a second conductivity type. In various embodiments, the doped semiconductor layer 116 may be doped with the same type of dopant as the type used in the second buried layer 114. For example, when the second buried layer 114 is doped with one or more p-type dopants, the doped semiconductor layer 116 may be doped with one or more p-type dopants. In various embodiments, the doped semiconductor layer 116 may be epitaxially grown. In various embodiments, the doped semiconductor layer 116 may have a higher concentration of dopant than the second buried layer 114.

[0031] A deep well 118 (comprising a first portion 118a and a second portion 118b) extends through a first buried layer 110, a semiconductor layer 112, a second buried layer 114, and a doped semiconductor layer 116. As shown, in some embodiments, the deep well 118 terminates within the first buried layer 110, such that the deep well 118 does not extend completely through the first buried layer 110. In various embodiments, the deep well 118 has a first conductivity type and may be or contain a semiconductor material similar to the first buried layer 110, the semiconductor layer 112, the second buried layer 114, and / or the doped semiconductor layer 116. In various embodiments, the dopant used may be one or more n-type dopants or one or more p-type dopants. In various embodiments, the deep well 118 may be referred to as a doped region.

[0032] A deep isolation structure 120 (e.g., a deep trench isolation structure, a trench) extends through a deep well 118, a first buried layer 110 (comprising a first portion 110a and a second portion 110b), and may further extend into a semiconductor substrate 108, as shown. In various embodiments, the first portion 110a and the second portion 110b may be electrically isolated and may each be at different potentials. In various embodiments, the deep isolation structure 120 may be a deep trench isolation structure and is thus formed within a trench extending through various semiconductor layers. The deep isolation structure 120 electrically isolates (or conductively isolates) the decoupling capacitor 106 from the scribing region 102. In various embodiments, the deep isolation structure 120 may be disposed within the scribing region 102. In various embodiments, the deep isolation structure 120 may extend around the periphery of the integrated circuit 100. In various embodiments, such as Figure 1C As shown, a first portion 118a of the deep well 118 may interface with a first sidewall of the deep isolation structure 120, and a second portion 118b of the deep well 118 may interface with a corresponding second sidewall of the deep isolation structure 120.

[0033] In various examples, the deep isolation structure 120 may include dielectric trench sidewall liner and trench filling material. The trench sidewall liner may include one or more dielectric (insulating) materials, such as silicon oxide, silicon nitride, silicon oxynitride, and / or combinations thereof. The filling material may include polycrystalline silicon (sometimes referred to as polycrystalline or polycrystalline), doped polycrystalline silicon, amorphous silicon, dielectric material, one or more conductive metals, and / or combinations thereof. The deep isolation structure 120 may be formed using various processes. For example, the trench may be formed through the deep well 118, the first buried layer 110, and into the semiconductor substrate 108. A deep trench oxide may then be formed along the exposed sidewall surfaces of the trench, and a deep trench filling material may be used to fill the remaining space between the sidewall surfaces of the deep trench oxide liner in the trench.

[0034] As described below, the decoupling capacitor 106 may include a shallow well 122 (sometimes referred to as a shallow doped well or doped region) serving as a base, a top plate 132 serving as a top plate, and a portion of a dielectric layer 130 therebetween serving as an insulating material for the capacitor. In this respect, the shallow well 122 forms the base of the decoupling capacitor 106 and has a first width W1 and a first length L1. Figure 1A (As shown in the diagram). A shallow well 122 is disposed in a doped semiconductor layer 116 and extends over a portion of a second buried layer 114, a deep well 118 (e.g., a second portion 118b), and a deep isolation structure 120. In various embodiments, as shown, the shallow well 122 may interface (e.g., contact, physical contact, adjacency, etc.) with the deep well 118 and the deep isolation structure 120 and form an ohmic connection with said deep well and deep isolation structure. Additionally, as... Figure 1C As shown, in some instances, the shallow well 122 may extend within the scribing region 102 and be positioned (or formed) above a portion of the deep isolation structure 120. Furthermore, in various instances, the shallow well 122 may be electrically coupled to the first buried layer 110 via the deep well 118. The direct connection between the shallow well 122 and the deep well 118 along a first length L1 of the decoupling capacitor 106 provides the decoupling capacitor 106 with an electrical connection through the first buried layer 110 to a first voltage line (e.g., ground, substrate potential). The electrical connection from the shallow well 122 (e.g., the base plate) to the first voltage line reduces the die space used by the decoupling capacitor 106 (e.g., within die region 104) by removing multiple fingers (e.g., contacts) used during the baseline process to provide a voltage connection through the top plate 132 to the base plate. In other words, unlike some baseline solutions, the decoupling capacitor 106 has a continuous top plate (e.g., top plate 132) that lacks fingers (or interdigitated fingers) that would otherwise require a larger die area. Therefore, the decoupling capacitor 106 occupies less space (e.g., die area) than the baseline process.

[0035] In various embodiments, the shallow well 122 has a first conductivity type and may be or contain a semiconductor material similar to that of the deep well 118. In various embodiments, the dopant used may be one or more n-type dopants or one or more p-type dopants. Therefore, in some embodiments, when the deep well 118 is doped with an n-type dopant, the shallow well 122 may be doped with an n-type dopant (e.g., an n-type doped well characteristic), and in these embodiments, it may be referred to as an n-type well. Similarly, when the deep well 118 is doped with a p-type dopant, the shallow well 122 may be doped with a p-type dopant, and in these embodiments, it may be referred to as a p-type well.

[0036] In various embodiments, a shallow well 122 may be formed after the deep well 118 and the deep isolation structure 120 are formed. In various embodiments, one or more etching processes may be used to remove portions of the deep well 118 and the deep isolation structure 120. The shallow well 122 may then be formed over the second buried layer 114 and the remaining portions of the deep well 118 and the deep isolation structure 120. In various embodiments, process parameters may be adjusted to form the shallow well 122 over the deep well 118 and the deep isolation structure 120. In various embodiments, one or more planarization processes may be performed to planarize the top surface of the shallow well 122. In various embodiments, the one or more planarization processes may include etching, chemical mechanical polishing (CMP), or combinations thereof.

[0037] A shallow isolation structure 124 is disposed above the doped semiconductor layer 116, the deep well 118, the deep isolation structure 120, and the shallow well 122. The shallow isolation structure 124 provides electrical isolation between the decoupling capacitor 106 and other portions of the integrated circuit 100. In various embodiments, the shallow isolation structure 124 may comprise a shallow trench isolation (STI) structure. In various embodiments, the shallow isolation structure 124 may comprise a dielectric material providing electrical isolation, such as silicon oxide, silicon nitride, silicon oxynitride, and / or combinations thereof.

[0038] Contact regions 126a and 126b are disposed above the deep well 118 and the shallow well 122. In various embodiments, contact regions 126a and 126b may interface with the deep well 118 and / or the shallow well 122 (e.g., contact, physical contact, adjacency, etc.). Contact regions 126a and 126b have a first conductivity type. In various embodiments, the dopant used may be one or more n-type dopants or one or more p-type dopants. In various embodiments, contact regions 126a and 126b may have a higher concentration of the dopant used than the deep well 118 and / or the shallow well 122. In various embodiments, contact region 126a may provide an electrical connection to the shallow well 122 (e.g., the base plate) of the decoupling capacitor 106. In various other embodiments, contact regions 126a and 126b may be discontinuous, such that contact regions 126a and 126b are not a continuous region. In other instances, contact regions 126a and 126b may be a continuous region. In various instances, contact region 126a may be surrounded by a shallow well 122. In various instances, contact region 126a has higher conductivity than the shallow well 122.

[0039] Contact region 128a is disposed over deep isolation structure 120, and contact region 128b is disposed over doped semiconductor layer 116. In various embodiments, contact region 128a provides an ohmic connection to deep isolation structure 120, and contact region 128b provides an ohmic connection to doped semiconductor layer 116. When the filler material is a doped semiconductor (e.g., p-type polysilicon), contact region 128a has the same conductivity type as the filler material of deep isolation structure 120, while contact region 128b has the same conductivity type as doped semiconductor layer 116, e.g., p-type. In some other embodiments, the filler material and / or doped semiconductor layer 116 may be an n-type dopant. In various embodiments, contact region 128a has a higher concentration of the dopant used than deep isolation structure 120, and contact region 128b has a higher concentration of the dopant used than doped semiconductor layer 116. In embodiments where deep isolation structure includes metal filler, contact region 128a may be omitted.

[0040] A dielectric layer 130 is disposed over the shallow well 122 and may be formed during the formation of the gate oxide associated with various transistors in the die region 104. The dielectric layer 130 is shown extending over the shallow isolation structure 124, contact region 126, and contact region 128, while in some instances, the dielectric layer 130 is removed due to the formation of sidewall spacers 134. As described above, the portion of the dielectric layer 130 disposed between the shallow well 122 (e.g., a bottom plate) and the top plate 132 (e.g., a top plate) provides a capacitor dielectric for the decoupling capacitor 106. Throughout this disclosure, the term silicon oxide encompasses materials such as silicon monoxide (SiO) and / or silicon dioxide (SiO2) and / or a non-stoichiometric mixture of both. In some instances, the dielectric layer 130 is a thermally grown silicon oxide layer. In some other instances, the dielectric layer 130 may comprise localized oxidation of silicon oxide (LOCOS). In various instances, dielectric layer 130 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon oxide-based materials (such as phosphosilicate glass (PSG) or tetraethyl orthosilicate (TEOS) oxide), polytetrafluoroethylene, a high-k dielectric layer, any other dielectric material, or any combination thereof.

[0041] A top plate 132 is disposed above the dielectric layer 130, including a portion of the shallow well 122 (e.g., a base plate). As described above, the top plate 132 forms the top plate of the decoupling capacitor 106. In some embodiments, as shown, the top plate 132 has a second width W2 smaller than a first width W1 of the shallow well 122. The first width W1 defines the die space used by the decoupling capacitor 106, and the second width W2 of the top plate 132 defines the effective width (or capacitance width) of the decoupling capacitor 106. Figure 1C As shown, the top plate 132 is a continuous material layer because there are no openings in the top plate 132 to provide electrical connections (e.g., contacts) to the shallow well 122. Furthermore, the top plate 132 is shown to be laterally spaced from the deep isolation structure 120. In various embodiments, the top plate 132 may be spaced from the deep isolation structure 120 and laterally spaced relative to the top surface of the shallow well 122. These embodiments reduce the area occupied by the decoupling capacitor 106 within the die region (e.g., die region 104) without adversely affecting the ESR of the decoupling capacitor 106. Additionally, the absence of breaks in the top plate 132 used by the baseline process reduces capacitive interference caused by breaks.

[0042] In various examples, top plate 132 may comprise polycrystalline silicon. For example, top plate 132 may be a polycrystalline silicon structure comprising at least one polycrystalline silicon layer. In other examples, top plate 132 may comprise other metals and metal alloys. For example, top plate 132 may comprise metal alloys such as titanium nitride (TiN), tantalum nitride (TaN), and / or combinations thereof. In other examples, top plate 132 may comprise copper (Cu), tungsten (W), and / or aluminum (Al). In various examples, top plate 132 has a material composition different from that of shallow well 122. For example, shallow well 122 may be a doped region formed in a semiconductor layer (e.g., a silicon and / or germanium epitaxial layer), while top plate 132 comprises polycrystalline silicon (or the metals and / or metal alloys described above). In various examples, top plate 132 may also be referred to as a conductive layer.

[0043] Sidewall spacers 134 are disposed along the sidewalls of the top plate 132. Sidewall spacers 134 (sometimes referred to as dielectric spacers) may comprise one or more layers of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride and / or silicon oxynitride), or combinations thereof. Sidewall spacers 134 may be formed using any known process, such as chemical vapor deposition (CVD) and / or physical vapor deposition (PVD). In various instances, a dielectric material may be formed over the integrated circuit 100 and subsequently etched to form the sidewall spacers 134.

[0044] Dielectric pad 136 is disposed over top plate 132, sidewall spacers 134, and dielectric layer 130. Dielectric pad 136 may comprise one or more layers of dielectric material comprising oxide and / or nitride materials, such as silicon oxide and / or silicon nitride. Dielectric pad 136 may serve as a silicide barrier layer associated with the formation of electrical components in die region 104 and may be removed over contact regions 126a, 126b, 128a, 128b to allow the formation of a silicide layer (not shown) over these regions.

[0045] A first interlayer dielectric (ILD) layer 138 is disposed above the dielectric pad 136. The first ILD layer 138 may be a single dielectric layer or may comprise multiple dielectric layers of the same or different dielectric materials. In various examples, the first ILD layer 138 may comprise silicon nitride, silicon oxide-based materials (e.g., phosphosilicate glass (PSG), borosilicate glass (BPSG), or tetraethyl orthosilicate (TEOS) oxide), polytetrafluoroethylene, etc.

[0046] Contact 140 includes a bottom plate contact 140a and a top plate contact 140b. The bottom plate contact 140a provides a conductive connection to the shallow well 122 (e.g., a bottom plate), and the top plate contact 140b provides a conductive connection to the top plate 132. In various embodiments, other contacts 140 provide additional electrical and structural connections at the same layer as contacts 140a and 140b. In this respect, contacts 140 are positioned to pass through the first ILD layer 138, the dielectric pad 136, and / or the dielectric layer 130, and to fall on (and conductively contact) contact areas 126 and 128 and the top plate 132. In various embodiments, a silicide layer (not shown) may be formed over the contact areas 126 and 128 before the contacts 140 are formed on the contact areas. Each contact 140 may include (i) one or more metal barrier layers and / or adhesive layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc. or combinations thereof) conformally formed in a corresponding opening in the first ILD layer 138; and (ii) a filler metal (e.g., aluminum (Al), copper (Cu), tungsten (W), etc. or combinations thereof) above and / or on one or more metal barrier layers and / or adhesive layers.

[0047] A first metal layer 142 is disposed above and on the contact 140 (and is structurally connected to the contact). In various embodiments, a portion of the first metal layer 142 disposed in the die region 104 is further electrically connected to the contact 140, the bottom plate contact 140a, and the top plate contact 140b. In various embodiments, the first metal layer 142 comprises multiple metal lines or multiple portions. Each portion of the first metal layer 142 may comprise one or more metal barrier layers and / or adhesive layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or combinations thereof), and a bulk metal (e.g., aluminum (Al), copper (Cu), etc., or combinations thereof) above and / or on the one or more metal barrier layers and / or adhesive layers.

[0048] A second ILD layer 144 is disposed over the first metal layer 142 and the first ILD layer 138. The second ILD layer 144 may contain a material similar to the first ILD layer 138. A via 146 is disposed through the second ILD layer 144 and on the first metal layer 142 (and structurally connected to the first metal layer). Some of the vias 146 in the die region 104 are further electrically connected to portions of the first metal layer 142 in the die region 104. The vias 146 may contain a material similar to that of the contacts 140. A second metal layer 148 is disposed over the second ILD layer 144 and the vias 146. The second metal layer 148 may contain a material similar to that of the first metal layer 142.

[0049] A third ILD layer 150 is disposed above the second metal layer 148 and the second ILD layer 144. The third ILD layer 150 may contain a material similar to the first ILD layer 138. The second metal layer 148 is disposed above the second ILD layer 144 and the via 146. Additional ILD layers, vias, and metal layers may be formed above the integrated circuit as desired.

[0050] In various embodiments, portions of the first metal layer 142, via 146, and second metal layer 148 disposed in the die region 104 may be part of the interconnect structure of the integrated circuit 100. In other words, portions of the first metal layer 142, via 146, and second metal layer 148 disposed in the die region 104 may provide electrical connections to various functional components of the integrated circuit 100. In various embodiments, portions of the first metal layer 142, via 146, and second metal layer 148 disposed in the scribing region 102 may be part of a dummy interconnect structure. In this respect, such a dummy interconnect structure can prevent and / or reduce damage to the die region 104 during subsequent semiconductor wafer dicing processes.

[0051] Therefore, the decoupling capacitor 106 disclosed herein can be positioned adjacent to the scribing region 102, and in some instances, at least partially positioned within the scribing region. This allows the decoupling capacitor 106 to occupy a significantly smaller space within the die region 104 than the baseline process. In this respect, a deep well 118 (e.g., second portion 118b) disposed along the edge of the scribing region 102 provides an electrical connection between the base plate of the decoupling capacitor 106 (e.g., shallow well 122) and the first buried layer 110 (e.g., second portion 110b). More specifically, the direct connection between the shallow well 122 and the deep well 118 along a first length L1 of the decoupling capacitor 106 provides the decoupling capacitor 106 with an electrical connection through the first buried layer 110 to a first voltage line (e.g., ground, substrate potential). This electrical connection between the shallow well 122 (e.g., the base plate) and the first voltage line allows the top plate (e.g., top plate 132) of the decoupling capacitor 106 to be formed from a continuous (e.g., non-interdigitated or non-finger-shaped) layer of material, since it is no longer necessary to form an opening through the top plate to provide a voltage connection to the base plate as in the baseline process. Therefore, compared to the baseline process, the decoupling capacitor 106 can be configured to extend significantly further along the scribing region 102 (e.g., length or y-direction) than it extends into the die region 104 (e.g., width or x-direction). In various examples, the aspect ratio (length to width ratio) can range from about 20:1 to about 60:1, and in some examples from about 35:1 to about 45:1. This significantly reduces the space occupied by the decoupling capacitor 106 within the die region 104 without adversely affecting the ESR of the decoupling capacitor 106. Furthermore, the absence of a break (or opening) through the top plate 132 reduces and / or prevents capacitive interference caused by a break (or opening) in the top plate that can be used by the baseline process.

[0052] For reference Figure 2A and 2B This demonstrates an integrated circuit 200 according to various aspects of this disclosure. Figure 2A This is an enlarged top view of integrated circuit 200, and Figure 2B For integrated circuit 200 along Figure 2AA schematic cross-sectional view of line A-A'. Integrated circuit 200 includes components similar to those of integrated circuit 100, including scribing region 202, die region 204, decoupling capacitor 206, semiconductor substrate 208, first buried layer 210 (including first portion 210a and second portion 210b), semiconductor layer 212, second buried layer 214, doped semiconductor layer 216, first deep well 218 (including first portion 218a and second portion 218b), deep isolation structure 220, shallow well 222, STI structure 224, and contact. Regions 226a to 226c, contact regions 228a to 228c, dielectric layer 230, top plate 232, sidewall spacer 234, dielectric pad 236, first interlayer dielectric (ILD) layer 238, contact 240 (including first bottom plate contact 240a, top plate contact 240b and second bottom plate contact 240c), first metal layer 242, second ILD layer 244, through hole 246, second metal layer 248 and third ILD layer 250, the description of which will not be repeated below.

[0053] In this respect, decoupling capacitor 206 functions similarly to decoupling capacitor 106, but is wider (e.g., along the x-axis). The larger width of decoupling capacitor 206 increases the effective capacitance without adversely affecting its equivalent series resistance (ESR). Effective capacitance is increased by increasing the width of both the shallow well 222 (e.g., the bottom plate) and the top plate 232. ESR is maintained by providing electrical connections between the shallow well 222 and the first buried layer 210 on both sides of the shallow well 222 (e.g., in the positive x-direction and the negative x-direction) and by providing an electrical connection to the top plate 232 near its centerline.

[0054] In this respect, the decoupling capacitor 206 includes a first portion 206a and a second portion 206b. As shown, the first portion 206a of the decoupling capacitor 206 is depicted to the "left side" (e.g., in the negative x direction) of the top plate contact 240b, and the second portion 206b of the decoupling capacitor 206 is depicted to the "right side" (e.g., in the positive x direction) of the top plate contact 240b. Similar to... Figure 1C The decoupling capacitor 106, the first part 206a and the second part 206b of the decoupling capacitor 206 include a shallow well 222 forming a base plate, a top plate 232 forming a top plate, and a portion of the dielectric layer 230 disposed between the shallow well 222 and the top plate 232 forming an insulator of the capacitor.

[0055] In some instances, the first portion 206a and / or the second portion 206b may be similar to the decoupling capacitor 106 (e.g., size / dimension and assembly). For example, the first portion 206a and / or the second portion 206b may extend a first length L1 (e.g., along the edge of the scribed region 302 (e.g., along the y-axis)), similar to what has been described above. Figure 1A The decoupling capacitor 106 is shown. Furthermore, as... Figure 1B As shown, decoupling capacitor 206 has a third width W3, which is approximately twice the size of the first width W1 (e.g., the width W1 of decoupling capacitor 106). For example, a first portion 206a may have the first width W1 and a second portion 206b may have the first width W1, such that the total width of the decoupling capacitor is the third width W3. Even if decoupling capacitor 206 has a larger total width (e.g., the third width W3) than the first capacitor 106 (e.g., the first width W1), the first length L1 may still be substantially greater than the third width W3. In various examples, the ratio (aspect ratio) of the first length L1 to the third width W3 relative to decoupling capacitor 206 may be from about 10:1 to about 30:1, and in some examples from about 15:1 to about 25:1.

[0056] The integrated circuit 200 further includes a second deep well 252, a third isolation structure 254, a contact region 226c, and a contact region 228c. The second deep well 252 and the third isolation structure 254 may be similar to the first deep well 218 and the deep isolation structure 220, respectively. The contact region 226c is disposed above the shallow well 222 and the second deep well 252, and is similar to contact regions 226a and 226b. The contact region 228c is disposed above the third isolation structure 254, and is similar to contact regions 228a and 228b.

[0057] As shown, in various examples, the shallow trap 222 extends from the deep isolation structure 220 to the third isolation structure 254. Furthermore, a first end of the shallow trap 222 (e.g., within the first portion 206a) is positioned above a portion of the first deep trap 218 (e.g., the second portion 218b) and the deep isolation structure 220, and an opposing second end of the shallow trap 222 (e.g., within the second portion 206b) is positioned above a portion of the second deep trap 252 and the third isolation structure 254. As described below, an electrical connection between the shallow trap 222 and the first buried layer 210 is formed on both sides of the shallow trap 222 (e.g., in the positive x-direction and the negative x-direction) via the first deep trap 218 and the second deep trap 252.

[0058] Figure 2A and 2BThe decoupling capacitor 206 shown uses less space than the baseline decoupling capacitor, where the ESR difference is small or negligible. The shallow well 222 (e.g., the base plate) has two connections to a first voltage (e.g., ground) via a first deep well 218 and a second deep well 252 to a first buried layer 210. The top plate 232 has a connection to a second voltage (e.g., VDD) via top plate contacts 240b. Figure 2B As shown, the top plate contact 240b may be positioned above the top plate 232 and electrically coupled to the top plate at a point between the deep isolation structure 220 and the third isolation structure 254. In various embodiments, the top plate contact 240b may be approximately equidistant from the deep isolation structure 220 and the third isolation structure 254. In other embodiments, the top plate contact 240b may be closer to one of the deep isolation structure 220 or the third isolation structure 254.

[0059] Therefore, the decoupling capacitor 206 disclosed herein provides electrical connection to the first buried layer 210 via a shallow well 222, a first deep well 218, and a second deep well 252. The top plate 132 can then provide one or more electrical connections along its centerline for the first portion 206a and the second portion 206b of the decoupling capacitor 206. The decoupling capacitor 206 can use a smaller die space than the baseline decoupling capacitor because there are no openings in the top plate 232 to provide connection to the shallow well 122. Furthermore, the architecture of the decoupling capacitor 206 disclosed herein ensures a good electrical connection between the shallow well 222 and the first buried layer 210 with minimal impact on ESR, without requiring additional verification checks during manufacturing.

[0060] For reference Figure 3A and 3B This demonstrates an integrated circuit 300 according to various aspects of this disclosure. Figure 3A This is a top view of integrated circuit 300, and Figure 3B For integrated circuit 300 along Figure 3AA schematic cross-sectional view of line A-A'. Integrated circuit 300 includes components similar to those of integrated circuit 100, including scribing region 302, bare die region 304, decoupling capacitor 306, semiconductor substrate 308, first buried layer 310 (including first portion 310a and second portion 310b), semiconductor layer 312, second buried layer 314, doped semiconductor layer 316, deep well 318 (including first portion 318a and second portion 318b), deep isolation structure 320, shallow well 322, and shallow isolation structure 3. 24, contact areas 326a, 326b, contact areas 328a, 328b, dielectric layer 330, top plate 332, sidewall spacer 334, dielectric pad 336, first interlayer dielectric (ILD) layer 338, contact 340 (including bottom plate contact 340a and top plate contact 340b), first metal layer 342, second ILD layer 344, through hole 346, second metal layer 348 and third ILD layer 350, the description of which will not be repeated below.

[0061] Integrated circuit 300 further includes a metal-insulator-metal (MIM) capacitor 356 disposed above decoupling capacitor 306. MIM capacitor 356 may include portions of a first metal layer 342, a second ILD layer 344, and a second metal layer 348. MIM capacitor 356 provides capacitance in parallel with decoupling capacitor 306 and increases the total available capacitance. In various embodiments, the total capacitance may increase by approximately 5% to approximately 10% compared to a baseline process.

[0062] As described above, the top plate 332 of the decoupling capacitor 306 can be formed of a continuous (e.g., non-interdigitated or non-finger-shaped) layer of material because there is no longer a need to form an opening through the top plate to provide a voltage connection to the bottom plate, as in the baseline process. This is because the direct connection between the shallow well 322 (e.g., the bottom plate) and the deep well 318 (e.g., the second portion 318b) provides the decoupling capacitor 306 with an electrical connection to a first voltage line (e.g., ground, substrate potential) through the first buried layer 310 (e.g., the second portion 110b). Therefore, the decoupling capacitor 306 may not have an opening and / or contacts extending through the top plate 332. This lack of openings and / or contacts provides additional space (e.g., space) for forming a MIM capacitor 356 above the decoupling capacitor 306. The MIM capacitor 356 operates in parallel with the decoupling capacitor 306 to increase the total capacitance while using a smaller die space than the baseline decoupling capacitor.

[0063] For reference Figure 4The diagram illustrates a flowchart of a method 400 for forming a decoupling capacitor according to various embodiments of the present disclosure. At step 402, a deep trench isolation structure is formed through a semiconductor layer to at least a buried semiconductor layer. At step 404, a doped well is formed in a semiconductor layer adjacent to the deep trench isolation structure, the doped well interfacing with the deep trench isolation structure. At step 406, a conductive layer is formed over the doped well, wherein the doped well forms a first plate of the capacitor, and the conductive layer forms a second plate of the capacitor.

[0064] This document discloses decoupling capacitors for integrated circuits that use less die space and have virtually no impact on ESR compared to baseline decoupling capacitors. The decoupling capacitors disclosed herein are formed adjacent to a scribe region of the integrated circuit, and in some instances, are formed above the scribe region, thereby providing good connectivity to the substrate potential. The decoupling capacitor includes a base plate (e.g., a shallow well) formed above and in direct contact with a deep well and isolation structure. The deep well provides good electrical connectivity of the base plate to a buried semiconductor layer (e.g., substrate potential). The top plate of the capacitor is formed as a single continuous material above the base plate without breaks. This combination reduces the die space used by the decoupling capacitor while having virtually no impact on its ESR. In various instances, multiple decoupling capacitors may be arranged adjacent to each other. In various instances, a MIM capacitor may be formed above the decoupling capacitor to increase the total capacitance.

[0065] Finally, it should be understood that any of the concepts described above may be used alone or in combination with any or all of the other concepts described above. Although various examples have been disclosed and described, it should be understood, recognized, and / or anticipated that certain modifications will fall within the scope of this disclosure. Therefore, the description is not intended to be exhaustive or to limit the principles described or illustrated herein to any precise form. In light of the foregoing teachings, many modifications and variations are possible.

Claims

1. An integrated circuit comprising: a buried semiconductor layer disposed above a substrate and having a first conductivity type; an epitaxial layer disposed above the buried semiconductor layer and having an opposite second conductivity type; a deep trench isolation structure extending through the epitaxial layer, the buried semiconductor layer, and into the substrate; and a capacitor disposed above the substrate, the capacitor interfacing with the deep trench isolation structure and electrically coupled to the buried semiconductor layer.

2. The integrated circuit of claim 1, wherein the capacitor includes a first plate electrically coupled to the buried semiconductor layer and interfacing with the deep trench isolation structure.

3. The integrated circuit of claim 2, further comprising: a first doped region disposed within the epitaxial layer along a sidewall of the deep trench isolation structure, the first doped region extending from the first plate of the capacitor to the buried semiconductor layer.

4. The integrated circuit of claim 3, further comprising: a second doped region disposed within the epitaxial layer adjacent to the first doped region, the first doped region having the first conductivity type and the second doped region having the second conductivity type.

5. The integrated circuit of claim 2, wherein the capacitor further includes a second plate electrically isolated from the buried semiconductor layer and laterally spaced apart from the deep trench isolation structure relative to a top surface of the first plate.

6. The integrated circuit of claim 5, wherein the first plate has a different material composition than the second plate.

7. The integrated circuit of claim 5, wherein the first plate of the capacitor includes a shallow doped well disposed within the epitaxial layer and the second plate of the capacitor includes a polysilicon structure disposed above the first plate.

8. The integrated circuit of claim 1, wherein the deep trench isolation structure is disposed within a scribe line region of the substrate.

9. The integrated circuit of claim 1, wherein the buried semiconductor layer is an n-type buried semiconductor layer, and wherein the capacitor includes an n-type doped well forming a plate of the capacitor, the n-type doped well disposed within the epitaxial layer and electrically coupled to the n-type buried semiconductor layer.

10. The integrated circuit of claim 1, wherein the capacitor includes a first doped feature forming a plate of the capacitor, the first doped feature electrically coupled to the buried semiconductor layer and having the first conductivity type, the integrated circuit further comprising: a second doped feature at least partially surrounded by the first doped feature and having a higher electrical conductivity than the first doped feature; and a contact electrically coupled to the second doped feature.

11. The integrated circuit of claim 1, wherein the capacitor has a length and a width, wherein a ratio of the length to the width is in a range of about 20: 1 to about 40:

1. ​ ​ 12. The integrated circuit of claim 1, wherein the deep trench isolation structure is a first deep trench isolation structure, and the integrated circuit further comprises: a second deep trench isolation structure disposed over the substrate and extending through the buried semiconductor layer, wherein a plate of the capacitor extends from the first deep trench isolation structure to the second deep trench isolation structure.

13. An electronic device comprising: a buried semiconductor layer having a first conductivity type disposed over a semiconductor substrate; a semiconductor layer having an opposite second conductivity type disposed over the buried semiconductor layer; a trench extending through the semiconductor layer to at least the buried semiconductor layer; a doped region disposed within the semiconductor layer along a sidewall of the trench, the doped region extending to at least the buried semiconductor layer and having the first conductivity type; and a capacitor including a doped well forming a plate of the capacitor, the doped well disposed within the semiconductor layer and having the first conductivity type, the doped well interfacing with the trench and the doped region, wherein the doped well is electrically conductively coupled to the buried semiconductor layer through the doped region.

14. The electronic device of claim 13, wherein the doped well is a first plate of the capacitor, and wherein the capacitor further includes: a dielectric layer disposed between the doped well and the polysilicon layer, the device further comprising: a polysilicon layer forming a second plate of the capacitor, the polysilicon layer disposed over the doped well; a first contact disposed through the dielectric layer and electrically conductively coupled to the doped well; and a second contact electrically conductively coupled to the polysilicon layer.

15. The electronic device of claim 14, wherein the trench is disposed within a scribe region of the semiconductor substrate.

16. The electronic device of claim 14, the device further comprising: a first metal layer including a plurality of metal lines disposed over the polysilicon layer and electrically coupled to the first contact and the second contact; and a second metal layer including a plurality of metal lines disposed over the first metal layer.

17. The electronic device of claim 16, wherein the capacitor is a first capacitor, and wherein the plurality of metal lines form a second capacitor electrically connected in parallel with the first capacitor.

18. A method of forming an integrated circuit, comprising: forming a trench through a first semiconductor layer having a first conductivity type to a second semiconductor layer having an opposite second conductivity type; forming a doped region having the second conductivity type within the first semiconductor layer, the doped region intersecting a sidewall of the trench; forming an electrically conductive layer over the doped region, wherein the doped region forms a first plate of a capacitor and the electrically conductive layer forms a second plate of the capacitor.

19. The method of claim 18, further comprising forming a doped region in the first semiconductor layer and the second semiconductor layer, wherein the doped region is electrically conductively coupled to the second semiconductor layer through the doped region. ​ ​ ​ ​ 20. The method of claim 18 wherein forming the trench through the first semiconductor layer includes forming a layer of material through the first semiconductor layer, the layer of material including a dielectric material or a conductive material.

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