High-performance power device and preparation method
By introducing trench cell structure and shielding structure into SiC MOSFET devices, combined with Schottky diodes, the problems of gate oxide reliability and bipolar degradation are solved, the on-resistance is optimized, and the performance of the device under high voltage and high frequency conditions is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-12
- Publication Date
- 2026-03-10
AI Technical Summary
SiC MOSFET devices suffer from gate oxide reliability issues, bipolar degradation, and limited on-resistance development, making it difficult to meet the requirements of high-voltage and high-frequency operating conditions.
A trench-type cell structure is adopted, including a shielding trench, a shielding metal body, and a P-type shielding layer. Combined with a Schottky diode, the electric field at the bottom of the gate trench is reduced through the shielding structure, the conductivity path is increased, and the on-resistance of the device is optimized.
It improves gate oxide reliability, suppresses bipolar degradation, reduces on-resistance, and enhances the device's surge immunity under high current.
Smart Images
Figure CN121645974A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor devices, and in particular to a high-performance power device and its fabrication method. Background Technology
[0002] With increasing application demands, power discrete semiconductor devices such as MOSFETs and IGBTs are gradually developing towards higher power density. To further meet the requirements of higher voltage and high frequency operating conditions, SiC, with its excellent material properties, is gradually increasing its market share in the power semiconductor market. However, SiC MOSFET devices have some defects that urgently need to be optimized: 1. Gate oxide reliability issues: One of the advantages of SiC materials compared to Si devices is that the critical breakdown electric field is significantly improved. However, since both use SiO2 materials as the gate dielectric, the gate oxide of SiC MOSFETs is subjected to a high electric field, which makes reliability issues stand out.
[0003] 2. Bipolar degradation: When the body diode of a SiC MOSFET is turned on, the injection of minority carriers (holes) into the N-drift region causes reliability problems. Factors such as lattice quality, temperature, and dynamic stress can exacerbate this problem.
[0004] 3. Limited development of on-resistance: In pursuit of high efficiency, SiC devices need to gradually shrink the smallest unit size to achieve higher current density, but this also leads to higher on-resistance. Summary of the Invention
[0005] To address the aforementioned problems and technical requirements, the inventors have proposed a high-performance power device and its fabrication method. The technical solution of this invention is as follows: A high-performance power device includes a semiconductor substrate of a first conductivity type and an active region fabricated in the central region of the semiconductor substrate; the active region includes a plurality of trench cells arranged in parallel. For any trench cell, including a trench grid structure and a shielding structure, the shielding structure includes a shielding trench disposed on one side of the trench grid structure, a shielding metal body filled in the shielding trench, and a second conductivity type shielding layer located below the shielding trench, wherein the second conductivity type shielding layer traverses the active region and contacts the shielding metal body. The shielding metal body is isolated from the trench gate structure through the semiconductor substrate. The shielding metal body is in Schottky contact with the semiconductor substrate and in contact with the first electrode metal above the semiconductor substrate used to form the first electrode. A first conductivity type doped region is provided below the trench gate structure. The first conductivity type doped region penetrates the second conductivity type shielding layer and contacts the semiconductor substrate above and below the second conductivity type shielding layer.
[0006] A further technical solution is that the shielding structure further includes a second conductivity type doped region, which is located on the side of the shielding trench away from the trench gate structure; The second conductivity type doped region is in contact with the second conductivity type shielding layer and in ohmic contact with the first electrode metal above the semiconductor substrate used to form the first electrode; The second type of conductivity doped region is in ohmic contact with the shielding metal body, or is isolated from the shielding metal body through an isolation oxide layer.
[0007] A further technical solution is that the isolation oxide layer includes a sidewall oxide layer disposed on the inner sidewall of the shielding trench near the second conductivity type doped region, and the second conductivity type doped region is isolated from the shielding metal through the sidewall oxide layer; The isolation oxide layer also includes a bottom oxide layer disposed at the bottom of the shielding trench. The bottom oxide layer extends from one corner of the shielding trench near the doped region of the second conductivity type to another corner of the shielding trench and does not completely cover the bottom of the shielding trench.
[0008] A further technical solution is that the trench gate structure includes a gate trench, a gate oxide layer, and a gate polysilicon. The gate polysilicon is filled in the gate trench and is insulated from the inner wall of the gate trench by the gate oxide layer. The gate polysilicon is in ohmic contact with the second electrode metal above the semiconductor substrate for forming the second electrode.
[0009] A further technical solution is that the depth of the shielding trench is greater than the depth of the gate trench.
[0010] A further technical solution is that the doping concentration of the second conductivity type doped region is greater than the doping concentration of the second conductivity type shielding layer; Both the second conductivity type shielding layer and the first conductivity type doped region are disposed in the first conductivity type epitaxial layer of the semiconductor substrate, and the doping concentration of the first conductivity type doped region is greater than the doping concentration of the first conductivity type epitaxial layer.
[0011] A further technical solution is that a second conductivity type base region is provided on both sides of the gate trench, and a first conductivity type source region is provided in each second conductivity type base region; The second conductivity type base region and the first conductivity type source region are in contact with the corresponding outer wall of the gate trench; the junction depth of the first conductivity type source region is not greater than the junction depth of the second conductivity type base region; the first conductivity type source region is in ohmic contact with the first electrode metal above the semiconductor substrate used to form the first electrode.
[0012] A method for fabricating a high-performance power device, comprising: A substrate of a first conductivity type is provided, and a front-side cell process is performed on the front side of the substrate corresponding to the active region. The front-side cell process includes fabricating a semiconductor substrate based on the substrate and fabricating a plurality of parallel-distributed trench cells, wherein... For any trench cell, including a trench grid structure and a shielding structure, the shielding structure includes a shielding trench disposed on one side of the trench grid structure, a shielding metal body filled in the shielding trench, and a second conductivity type shielding layer located below the shielding trench, wherein the second conductivity type shielding layer traverses the active region and contacts the shielding metal body. The shielding metal body is isolated from the trench gate structure through the semiconductor substrate. The shielding metal body is in Schottky contact with the semiconductor substrate and in contact with the first electrode metal above the semiconductor substrate used to form the first electrode. A first conductivity type doped region is provided below the trench gate structure. The first conductivity type doped region penetrates the second conductivity type shielding layer and contacts the semiconductor substrate above and below the second conductivity shielding layer.
[0013] A further technical solution is that the frontal cell process includes: A first epitaxial layer is grown on the front side of the substrate. A second conductivity type shielding layer that traverses the active region and a first conductivity type doped region that penetrates the second conductivity type shielding layer are prepared in the first epitaxial layer. A first pre-doped region of the second conductivity type is prepared above the second conductivity type shielding layer. A second epitaxial layer is grown on a first epitaxial layer. The first epitaxial layer, the second epitaxial layer, and the substrate form a semiconductor substrate. A second conductivity type pre-base region traversing the active region is prepared in the second epitaxial layer, and a first conductivity type pre-source region traversing the active region is prepared in the second conductivity type pre-base region. A second pre-doped region of a second conductivity type is prepared within the second epitaxial layer. The second pre-doped region of the second conductivity type is located above the first pre-doped region of the second conductivity type and is connected to the first pre-doped region of the second conductivity type to form a doped region of the second conductivity type.
[0014] A further technical solution is that the frontal cell process includes: A trench gate structure, a source region of the first conductivity type, and a base region of the second conductivity type were fabricated. A shielding trench is etched on the front side of a semiconductor substrate, and a thermal oxide layer is grown. The thermal oxide layer on the front side of the semiconductor substrate is etched to prepare an insulating layer covering the trench gate structure. The thermal oxide layer in the shielding trench is etched to remove the thermal oxide layer near the inner sidewall of the trench grid structure and part of the thermal oxide layer at the bottom of the shielding trench, so as to form the sidewall oxide layer and the bottom oxide layer, or the thermal oxide layer on the inner wall of the shielding trench is completely etched away. Metal is deposited in the aforementioned shielding trench to form a shielding metal body, and a front metal layer is deposited on top of the semiconductor substrate. The front metal layer includes a first electrode metal and a second electrode metal.
[0015] For N-type power devices, the first conductivity type refers to N-type and the second conductivity type refers to P-type; for P-type power devices, the first conductivity type and the second conductivity type refer to the opposite types as those for N-type devices.
[0016] The beneficial technical effects of this invention are: 1. Improve gate oxide reliability: The power device provided by the present invention is equipped with a shielding structure, which together with the shielding metal body, the P-type shielding layer and the P-type doped region to achieve the shielding effect, effectively reducing the peak electric field at the bottom of the gate trench and improving the reliability of the gate oxide.
[0017] 2. Suppressing bipolar degradation: The shielding metal body in the shielding structure makes contact with the Schottky contact of the N-type epitaxial layer (drift region) in the semiconductor substrate, so that the device integrates a Schottky diode. The Schottky diode suppresses the conduction of the body diode when the device is turned off, thereby suppressing bipolar degradation.
[0018] 3. Improved current carrying capacity: After the integrated Schottky diode is turned on, if the device has a large freewheeling current, the PN junction formed by the P-type shielding layer and the drift region below will be further turned on. The P-type shielding layer injects holes into the drift region. Both electrons and holes participate in conduction, resulting in conduction modulation, which significantly reduces the on-state voltage drop VF of the parasitic diode, thereby improving the device's surge resistance under high current.
[0019] 4. Optimized On-Resistance: The N-type doped region penetrating the P-type shielding layer serves as the current path for forward conduction of the device. Its doping concentration is greater than that of the epitaxial layer, which reduces the on-resistance of the device. Furthermore, this invention employs a trench gate structure, which, compared to a planar gate structure, avoids parasitic JFET resistance. Simultaneously, the pitch is easier to reduce, providing higher current density and lower on-resistance. Attached Figure Description
[0020] Figure 1 This is a cross-sectional schematic diagram of an embodiment of the high-performance power device provided by the present invention.
[0021] Figure 2 This is a cross-sectional schematic diagram of another embodiment of the high-performance power device provided by the present invention.
[0022] Figure 3 This is a schematic diagram of the electronic current path when the high-performance power device provided by the present invention is turned on.
[0023] Figure 4 This is a schematic diagram of the electronic current path when the high-performance power device provided by the present invention is turned off.
[0024] Figure 5 This is a schematic diagram of the high-performance power device provided by the present invention, in which the device is turned off and the current carrier path is downloaded in a high current state.
[0025] Figure 6 This is a schematic diagram of the device being turned off and the current carrier path being downloaded in a high-current state in another embodiment of the high-performance power device provided by the present invention.
[0026] Figures 7-17 This is a cross-sectional view of the process steps in the fabrication of high-performance power devices, wherein... Figure 7 This is a cross-sectional view of one embodiment of the present invention after the first epitaxial layer has been prepared.
[0027] Figure 8 This is a cross-sectional view of one embodiment of the present invention after the first pre-doped region of the P-type is prepared.
[0028] Figure 9 This is a cross-sectional view of one embodiment of the second epitaxial layer prepared according to the present invention.
[0029] Figure 10 This is a cross-sectional view of one embodiment of the P-type doped region prepared according to the present invention.
[0030] Figure 11 This is a cross-sectional view of one embodiment of the present invention after polysilicon is deposited on the second epitaxial layer.
[0031] Figure 12 This is a cross-sectional view of one embodiment of the trench grid structure prepared according to the present invention.
[0032] Figure 13 This is a cross-sectional view of one embodiment of the thermally oxidized layer prepared according to the present invention.
[0033] Figure 14 This is a cross-sectional view of one embodiment of the present invention after thermal oxide layer etching.
[0034] Figure 15 This is a cross-sectional view of another embodiment of the present invention after thermal oxide layer etching.
[0035] Figure 16 This is a cross-sectional view of one embodiment of the preparation of the third electrode metal according to the present invention.
[0036] Figure 17 This is a cross-sectional view of another embodiment of the preparation of the third electrode metal according to the present invention.
[0037] Figure label: 1-Substrate, 2-N-type epitaxial layer, 3-Shielding trench, 4-Shielding metal body, 5-P-type shielding layer, 6-Gate trench, 7-Gate oxide layer, 8-Gate polysilicon, 9-First electrode metal, 10-N-type doped region, 11-P-type doped region, 12-Sidewall oxide layer, 13-Trench bottom oxide layer, 14-Insulating layer, 15-P-type base region, 16-N-type source region, 17-First epitaxial layer, 18-P-type first pre-doped region, 19-Second epitaxial layer, 20-P-type pre-base region, 21-N-type pre-source region, 22-Thermal oxide layer. Detailed Implementation
[0038] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.
[0039] To improve gate oxide reliability, optimize on-resistance, suppress bipolar degradation, and enhance surge protection, this invention provides a high-performance power device, taking N-type as an example, comprising an N-type semiconductor substrate and an active region fabricated in the central region of the semiconductor substrate; the active region includes a plurality of trench cells arranged in parallel. For any trench cell, including a trench grid structure and a shielding structure, the shielding structure includes a shielding trench 3 disposed on one side of the trench grid structure, a shielding metal body 4 filled in the shielding trench 3, and a P-type shielding layer 5 located below the shielding trench 3, wherein the P-type shielding layer 5 traverses the active region and contacts the shielding metal body 4. The shielding metal body 4 is isolated from the gate trench 6 through the semiconductor substrate. The shielding metal body 4 is in Schottky contact with the semiconductor substrate and in contact with the first electrode metal above the semiconductor substrate used to form the first electrode. An N-type doped region 10 is provided below the trench gate structure. The N-type doped region 10 penetrates the P-type shielding layer 5 and contacts the semiconductor substrate above and below the P-type shielding layer 5.
[0040] Specifically, a power device generally includes an active region located in the central area of a semiconductor substrate and a termination protection zone surrounding the active region. The specific functions and distribution of the active region and the termination protection zone can be consistent with existing technologies. The semiconductor substrate can be made of commonly used materials, such as silicon substrates or SiC substrates, to meet application requirements.
[0041] The semiconductor substrate has a front side and a corresponding back side. In one embodiment of the present invention, the semiconductor substrate is made of SiC, and the semiconductor substrate includes an N-type substrate 1 and an N-type epitaxial layer 2 (also referred to as a drift region) located on the N-type substrate 1. The P-type shielding layer 5 and the N-type doped region 10 are both disposed in the N-type epitaxial layer 2.
[0042] The trench gate structure includes a gate trench 6, a gate oxide layer 7, and a gate polysilicon 8. The gate polysilicon 8 fills the gate trench 6 and is insulated from the inner wall of the gate trench 6 by the gate oxide layer 7. The gate polysilicon 8 makes an ohmic contact with the second electrode metal above the semiconductor substrate, which is used to form the second electrode. In the shielding structure, the P-type shielding layer 5 can be electrically connected to the first electrode potential through the shielding metal body 4. The shielding metal body 4 and the P-type shielding layer 5 together shield the electric field at the trench gate structure during withstand voltage, thereby reducing the electric field strength at the trench gate structure and improving the reliability of the gate oxide layer. The trench depth of the shielding trench 3 is greater than the trench depth of the gate trench 6 to achieve a better shielding effect. The N-type doped region 10 serves as the current path when the device is forward-biased, such as... Figure 3 As shown, the electron current enters the N-type epitaxial layer 2 above the N-type doped region 10 through the gate inversion channel, and then passes through the N-type doped region 10 to enter the N-type epitaxial layer 2 below the N-type doped region 10. In this embodiment, the N-type doped region 10 is located directly below the gate trench 6, and the doping concentration of the N-type doped region 10 is greater than the doping concentration of the N-type epitaxial layer 2, so as to reduce the electron path resistance and further optimize the on-resistance of the device.
[0043] like Figure 1 As shown, the shielding metal body 4 makes Schottky contact with the semiconductor substrate, specifically with the N-type epitaxial layer 2 on the right side of the shielding metal body 4, to integrate the Schottky diode into the device. The shielding metal body 4 is in contact with the first electrode metal 9, forming the positive electrode of the Schottky diode, and the N-type epitaxial layer 2 forms the negative electrode of the Schottky diode. Figure 4 As shown, since the barrier of a Schottky junction is smaller than that of a PN junction, the integrated Schottky diode can suppress the conduction freewheeling current of the body diode when the device is turned off, thereby suppressing bipolar degradation.
[0044] Typically, a third metal electrode (not shown in the figure) is also disposed on the back side of the N-type substrate 1. The power device can be formed as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). For a MOSFET device, the first electrode is the source, the second electrode is the gate, and the third electrode is the drain; for an IGBT device, the first electrode is the emitter, the second electrode is the gate, and the third electrode is the collector.
[0045] Furthermore, the shielding structure also includes a P-type doped region 11, which is located on the side of the shielding trench 3 away from the gate trench 6. The P-type doped region 11 is in contact with the P-type shielding layer 5 and has an ohmic contact with the first electrode metal 9 above the semiconductor substrate used to form the first electrode. In this embodiment, the junction depth of the P-type doped region 11 is less than the trench depth of the shielding trench 3. The P-type doped region 11 is in contact with the P-type shielding layer 5, and the shielding trench 3 can extend downward into the P-type shielding layer 5. The doping concentration of the P-type doped region 11 is greater than the doping concentration of the P-type shielding region 5, which can further help improve the electric field shielding effect and also serve to electrically connect the P-type shielding layer 5 to the first electrode.
[0046] In one embodiment of the present invention, the P-type doped region 11 is isolated from the shielding metal body 4 by an isolation oxide layer. The isolation oxide layer includes a sidewall oxide layer 12 disposed on the inner sidewall of the shielding trench 3 near the P-type doped region 11, and the P-type doped region 11 is isolated from the shielding metal body 4 by the sidewall oxide layer 12; the isolation oxide layer also includes a bottom oxide layer 13 disposed at the bottom of the shielding trench 3, the bottom oxide layer 13 extending from one corner of the shielding trench 3 near the P-type doped region 11 to another corner of the shielding trench 3, and not completely covering the bottom of the shielding trench 13, so that the P-type shielding layer 5 is electrically connected to the shielding metal body 4, ensuring the shielding effect and enabling the integrated Schottky diode to conduct and trigger the PN junction formed between the P-type shielding layer 5 and the N-type epitaxial layer 2. The isolation oxide layer aims to prevent the P-type doped region 11 from being electrically connected to the N-type epitaxial layer 2 through the shielding metal body 4 and to reduce the contact area between the shielding metal body 4 and the P-type shielding layer 5, thereby further suppressing the conduction of parasitic diodes and reducing the risk of bipolar degradation.
[0047] like Figure 5As shown, after the integrated Schottky diode is turned on, if the device's freewheeling current is large, the PN junction formed by the P-type doped region 11, the P-type shielding layer 5, and the underlying N-type epitaxial layer 2 will further conduct under high current conditions. The P-type shielding layer 5 injects holes into the N-type epitaxial layer 2. Both electrons and holes participate in conduction, resulting in conductivity modulation, which significantly reduces the forward voltage drop VF of the body diode, thereby improving the device's surge resistance under high current. This achieves the effect of suppressing body diode conduction and bipolar degradation under low current conditions through the Schottky diode, and triggering the PN junction formed by the P-type shielding layer 5 and the underlying N-type epitaxial layer 2 under high current conditions through the Schottky diode, reducing the forward voltage drop and causing the body diode to conduct, thus improving the high current carrying capacity.
[0048] In another embodiment of the present invention, such as Figure 2 As shown, the shielding metal body 4 within the shielding trench 3 is in ohmic contact with the P-type doped region 11. The P-type doped region 11 can form a PN junction with the N-type epitaxial layer 2 through the shielding metal body 4, the P-type shielding layer 5, and the shielding metal body 4. Since the P-type doped region 11 is electrically connected to the P-type shielding layer 5 through the shielding metal body 4, and further electrically connected to the N-type epitaxial layer 2, the conductive path and area are increased. Figure 6 As shown, under high current conditions, it can provide a stronger conductivity modulation effect and a lower on-state voltage drop, and the current carrying capacity will be further enhanced compared with the previous embodiment.
[0049] Furthermore, an insulating layer 14 covering the trench gate structure is provided above the semiconductor substrate corresponding to the trench gate structure to isolate the gate polysilicon 8 from the first electrode metal 9. P-type base regions 15 are provided on both sides of the gate trench 6, and an N-type source region 16 is provided in each P-type base region 15. The P-type base region 15 and the N-type source region 16 are in contact with the corresponding outer sidewall of the gate trench 6; the junction depth of the N-type source region 16 is not greater than the junction depth of the P-type base region 15; the N-type source region 16 is in ohmic contact with the first electrode metal 9 above the semiconductor substrate used to form the first electrode.
[0050] Regarding the aforementioned high-performance power device, this invention provides a method for fabricating the high-performance power device, the method comprising: An N-type substrate 1 is provided, and a front-side cell process is performed on the front side of the substrate corresponding to the active region. The front-side cell process includes fabricating a semiconductor substrate based on the substrate and fabricating a plurality of parallel-distributed trench cells within the semiconductor substrate. For any trench cell, including a trench grid structure and a shielding structure, the shielding structure includes a shielding trench 3 disposed on one side of the trench grid structure, a shielding metal body 4 filled in the shielding trench 3, and a P-type shielding layer 5 located below the shielding trench 3, wherein the P-type shielding layer 5 traverses the active region and contacts the shielding metal body 4. The shielding metal body 4 is isolated from the trench gate structure through the semiconductor substrate. The shielding metal body 4 is in Schottky contact with the semiconductor substrate and in contact with the first electrode metal 9 above the semiconductor substrate used to form the first electrode. An N-type doped region 10 is provided below the trench gate structure. The N-type doped region 10 penetrates the P-type shielding layer 5 and contacts the semiconductor substrate above and below the P-type shielding layer 5.
[0051] Generally, the front cell process is performed first on the front side of substrate 1, and then the back cell process is performed on the back side of substrate 1. The front cell process includes: A first epitaxial layer 17 is grown on the front side of the substrate. A P-type shielding layer that traverses the active region and an N-type doped region 10 that penetrates the P-type shielding layer 5 are prepared in the first epitaxial layer 17. A first P-type pre-doped region 18 is prepared above the P-type shielding layer 5. A second epitaxial layer 19 is grown on the first epitaxial layer. The first epitaxial layer 17, the second epitaxial layer 19 and the substrate 1 form a semiconductor substrate. A P-type pre-base region 20 traversing the active region is prepared in the second epitaxial layer 19 and an N-type pre-source region 21 traversing the active region is prepared in the P-type pre-base region 20. A second P-type pre-doped region is prepared in the second epitaxial layer 19. The second P-type pre-doped region is located above the first P-type pre-doped region 18 and is connected to the first P-type pre-doped region 18 to form a P-type doped region 11.
[0052] Furthermore, a trench gate structure, an N-type source region 16, and a P-type base region 15 were fabricated. A shielding trench 3 is etched on the front side of a semiconductor substrate, and a thermal oxide layer 22 is grown. The thermal oxide layer 22 on the front side of the semiconductor substrate is etched to prepare an insulating layer 14 covering the trench gate structure. The thermal oxide layer in the shielding trench 3 is etched to remove the thermal oxide layer 22 near the inner sidewall of the trench grid structure and part of the thermal oxide layer 22 at the bottom of the shielding trench 3, so as to form the sidewall oxide layer 12 and the bottom oxide layer 13, or the thermal oxide layer 22 on the inner wall of the shielding trench 3 is completely etched away. Metal is deposited in the aforementioned shielding trench 3 to form a shielding metal body 4, and a front metal layer is deposited above the semiconductor substrate. The front metal layer includes a first electrode metal 9 and a second electrode metal.
[0053] Specifically, Figures 7 to 17 The process steps of the above-mentioned power device fabrication method are illustrated using a MOSFET-type device. The following section combines... Figures 7 to 17 The process steps of the above power device fabrication method are explained in detail: Please refer to Figure 7-8 A SiC substrate 1 is provided, and a first epitaxial layer 17 is grown on the substrate 1. The first epitaxial layer has an N-type conductivity. A P-type shielding layer 5 is prepared in the first epitaxial layer 17 by ion implantation, traversing the active region. An implantation region for an N-type doped region 10 is defined using a first mask, and an N-type doped region 10 is implanted into the P-type shielding layer 5, penetrating the P-type shielding layer 5. An implantation region for a first P-type pre-doped region 18 is defined using a second mask, and a first P-type pre-doped region 18 is prepared in the first epitaxial layer 17, as shown below. Figure 8 As shown, the first pre-doped region 18 of the P-type has a first epitaxial layer 17 that extends vertically downward to the P-type shielding layer 5 and contacts the P-type shielding layer 5.
[0054] Please refer to Figure 9 A second epitaxial layer 19 is grown on the first epitaxial layer 17. The conductivity type of the second epitaxial layer is N-type, and the doping concentration is the same as that of the first epitaxial layer 17. The second epitaxial layer 19 and the first epitaxial layer 17 form the N-type epitaxial layer 2. The substrate 1, the first epitaxial layer 17 and the second epitaxial layer 19 form the semiconductor substrate.
[0055] Please refer to Figure 10 A P-type pre-doped region 20 traversing the active region is prepared within the second epitaxial layer 19, and an N-type pre-doped source region 21 traversing the active region is prepared within the P-type pre-doped region 20. The junction depth of the N-type pre-doped source region 21 is less than the junction depth of the P-type pre-doped region 20. An implantation region for the P-type second pre-doped region is defined using a second mask, and a P-type second pre-doped region is prepared within the second epitaxial layer 19. The P-type second pre-doped region is located above the P-type first pre-doped region 18 and is integrally connected to the P-type first pre-doped region 18 to form a P-type doped region 11.
[0056] Please refer to Figure 11-12 A gate trench 6 is etched onto the second epitaxial layer 19 using a third mask. The gate trench 6 penetrates the P-type pre-base region 20 and the N-type pre-source region 21. The P-type pre-base region 20 and the N-type pre-source region 21 on both sides of the gate trench 6 form a P-type base region 15 and an N-type source region 16. A trench gate thermal oxide layer is grown on the second epitaxial layer 19, and polysilicon is deposited. The trench gate thermal oxide layer and polysilicon on the surface of the second epitaxial layer 19 are then etched away to prepare the gate oxide layer 7 and the gate polysilicon 8, thus completing the fabrication of the trench gate structure.
[0057] Please refer to Figure 13A shielding trench 3 is obtained by etching the front side of the semiconductor substrate and the front side of the N-type epitaxial layer 19 using a fourth mask, a thermal oxide layer 22 is grown, and the thermal oxide layer 22 in the front side of the semiconductor substrate and the shielding trench 3 is etched using a fifth mask.
[0058] Please refer to Figure 14 In one embodiment of the present invention, when etching the thermal oxide layer 22 using the fifth mask, the etching process includes etching the thermal oxide layer 22 on the front side of the semiconductor substrate to prepare an insulating layer 14 covering the trench gate structure, etching the thermal oxide layer 22 within the shielding trench 3, and etching away a portion of the thermal oxide layer 22 near the inner sidewall of the trench gate structure and at the bottom of the shielding trench 3 to form a sidewall oxide layer 12 and a bottom oxide layer 13. The specific forms of the sidewall oxide layer 12 and the bottom oxide layer 13 are consistent with those described above.
[0059] Please refer to Figure 15 In another embodiment of the present invention, when etching the thermal oxide layer 22 using the fifth mask, the process includes etching the thermal oxide layer 22 on the front side of the semiconductor substrate to prepare an insulating layer 14 covering the trench gate structure, and completely etching away the thermal oxide layer 22 on the inner wall of the shielding trench 3.
[0060] In one embodiment of the present invention, Figure 14 Metal is deposited within the shielding trench 3 to form a shielding metal body 4. The shielding metal body 4 is in Schottky contact with the semiconductor substrate and isolated from the P-type doped region 11. Simultaneously, a front-side metal layer is deposited above the semiconductor substrate. This front-side metal layer includes a first electrode metal 9 and a second electrode metal (not shown in the figure). The first electrode metal 9 is in contact with the shielding metal body 4 and has a 16-ohm contact with the P-type doped region 11 and the N-type source region 16. The second electrode metal has an 8-ohm contact with the gate polysilicon. Subsequently, a back-side process is performed, depositing metal on the back side of the semiconductor substrate, i.e., the back side of substrate 1, to form a third electrode metal. This third electrode metal has an ohm contact with substrate 1 to form a third electrode (not shown in the figure), thus forming... Figure 16 The structure shown.
[0061] In another embodiment of the invention, Figure 15Metal is deposited within the shielding trench 3 to form a shielding metal body 4. The shielding metal body 4 makes a Schottky contact with the semiconductor substrate and an 11-ohm contact with the P-type doped region 11. Simultaneously, a front-side metal layer is deposited above the semiconductor substrate. This front-side metal layer includes a first electrode metal 9 and a second electrode metal (not shown in the figure). The first electrode metal 9 makes contact with the shielding metal body 4 and a 16-ohm contact with the P-type doped region 11 and the N-type source region 11. The second electrode metal makes an 8-ohm contact with the gate polysilicon. Subsequently, a back-side process is performed, depositing metal on the back side of the semiconductor substrate, i.e., the back side of substrate 1, to form a third electrode metal (not shown in the figure). This third electrode metal makes an ohm contact with substrate 1 to form a third electrode, thereby forming... Figure 17 The structure shown.
[0062] In the description of this specification, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0063] The use of terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., refers to a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example, which is included in at least one embodiment / mode or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.
[0064] In the description of this application, if terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" appear, these terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0065] It should be noted that, in this application, unless otherwise explicitly specified and limited, the use of descriptions such as "above" or "below" the second feature indicates that the first and second features are in direct contact, or indirect contact via an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. Similarly, "below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.
[0066] The above descriptions are merely preferred embodiments of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations that can be directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.
Claims
1. A high performance power device, characterized by, A semiconductor substrate of a first conductivity type and an active region formed in a central region of the semiconductor substrate; the active region includes a plurality of parallelly arranged trench cells; For any trench cell, a gate trench structure and a shielding structure are included, the shielding structure includes a shielding trench arranged at one side of the gate trench structure, a shielding metal body filled in the shielding trench, and a shielding layer of a second conductivity type arranged below the shielding trench, wherein the shielding layer of the second conductivity type traverses the active region and contacts the shielding metal body; The shielding metal body is isolated from the gate trench structure by the semiconductor substrate, and the shielding metal body is in Schottky contact with the semiconductor substrate and in ohmic contact with a first electrode metal arranged above the semiconductor substrate for forming a first electrode; A doped region of the first conductivity type is arranged below the gate trench structure, the doped region of the first conductivity type penetrates the shielding layer of the second conductivity type and contacts the semiconductor substrate above and below the shielding layer of the second conductivity type.
2. A high performance power device according to claim 1, wherein, The shielding structure further includes a doped region of the second conductivity type, which is arranged at a side of the shielding trench away from the gate trench structure; The doped region of the second conductivity type contacts the shielding layer of the second conductivity type and is in ohmic contact with a first electrode metal arranged above the semiconductor substrate for forming a first electrode; The doped region of the second conductivity type is in ohmic contact with the shielding metal body or is isolated from the shielding metal body by an isolation oxide layer.
3. A high performance power device according to claim 2, wherein, The isolation oxide layer includes a sidewall oxide layer arranged on the sidewall of the shielding trench close to the doped region of the second conductivity type, and the doped region of the second conductivity type is isolated from the shielding metal body by the sidewall oxide layer; The isolation oxide layer further includes a bottom oxide layer arranged on the bottom of the shielding trench, the bottom oxide layer extends from a corner of the shielding trench close to the doped region of the second conductivity type to another corner of the shielding trench, and does not completely cover the bottom of the shielding trench.
4. The high performance power device of claim 1, wherein, The gate trench structure includes a gate trench, a gate oxide layer, and a gate polysilicon, the gate polysilicon is filled in the gate trench and is insulated and isolated from the inner wall of the gate trench by the gate oxide layer, and the gate polysilicon is in ohmic contact with a second electrode metal arranged above the semiconductor substrate for forming a second electrode.
5. A high performance power device according to claim 4, wherein, The depth of the shielding trench is greater than the depth of the gate trench.
6. The high performance power device of claim 1, wherein, The doping concentration of the doped region of the second conductivity type is greater than the doping concentration of the shielding layer of the second conductivity type; The shielding layer of the second conductivity type and the doped region of the first conductivity type are arranged in a first conductivity type epitaxial layer of the semiconductor substrate, and the doping concentration of the doped region of the first conductivity type is greater than the doping concentration of the first conductivity type epitaxial layer.
7. A high performance power device according to claim 2, wherein, Second conductivity type base regions are arranged on both sides of the gate trench, and a first conductivity type source region is arranged in each second conductivity type base region; The second conductivity type base regions and the first conductivity type source regions contact the corresponding outer sidewalls of the gate trench, the junction depth of the first conductivity type source region is not greater than the junction depth of the second conductivity type base region, and the first conductivity type source region is in ohmic contact with a first electrode metal arranged above the semiconductor substrate for forming a first electrode.
8. A method of fabricating a high performance power device, characterized by, A method for manufacturing the power device of any one of claims 1-7, the method for manufacturing the high-performance power device includes: The first conductive type substrate is provided, and a front surface cell process is performed on the front surface of the substrate corresponding to the active region, the front surface cell process including preparing a semiconductor substrate based on the substrate and preparing a plurality of parallelly distributed trench type cells, wherein, For any trench type cell, a trench gate structure and a shielding structure are included, the shielding structure including a shielding trench arranged on one side of the trench gate structure, a shielding metal body filled in the shielding trench, and a second conductive type shielding layer below the shielding trench, wherein the second conductive type shielding layer traverses the active region and is in contact with the shielding metal body; The shielding metal body is isolated from the trench gate structure by the semiconductor substrate, and the shielding metal body is in Schottky contact with the semiconductor substrate and in contact with the first electrode metal above the semiconductor substrate for forming a first electrode; A first conductive type doped region is arranged below the trench gate structure, the first conductive type doped region penetrating the second conductive type shielding layer and being in contact with the semiconductor substrate above and below the second conductive type shielding layer.
9. The method of claim 9, wherein the high performance power device is a high electron mobility transistor (HEMT) or a metal-oxide-semiconductor field-effect transistor (MOSFET). The front surface cell process includes: growing a first epitaxial layer on the front surface of the substrate, preparing a second conductive type shielding layer traversing the active region in the first epitaxial layer, and a first conductive type doped region penetrating the second conductive type shielding layer, and preparing a second conductive type first preliminary doped region above the second conductive type shielding layer; growing a second epitaxial layer on the first epitaxial layer, the first epitaxial layer, the second epitaxial layer and the substrate forming a semiconductor substrate, preparing a second conductive type preliminary base region traversing the active region in the second epitaxial layer, and preparing a first conductive type preliminary source region traversing the active region in the second conductive type preliminary base region; preparing a second conductive type second preliminary doped region in the second epitaxial layer, the second conductive type second preliminary doped region being above the second conductive type first preliminary doped region and being integrated with the second conductive type first preliminary doped region to form a second conductive type doped region.
10. The method of claim 9, wherein the high performance power device is a high electron mobility transistor (HEMT) or a metal-oxide-semiconductor field-effect transistor (MOSFET). The front surface cell process includes: preparing a trench gate structure, a first conductive type source region and a second conductive type base region; etching a shielding trench on the front surface of the semiconductor substrate, and growing a thermal oxide layer, etching the thermal oxide layer on the front surface of the semiconductor substrate to prepare an insulating layer covering the trench gate structure; etching the thermal oxide layer in the shielding trench, etching and removing the thermal oxide layer near the inner wall of the shielding trench and part of the thermal oxide layer at the bottom of the shielding trench to form a side wall oxide layer and a bottom oxide layer, or completely etching and removing the thermal oxide layer in the inner wall of the shielding trench; depositing a metal in the above shielding trench to form a shielding metal body, and depositing a front surface metal layer above the semiconductor substrate, the front surface metal layer including a first electrode metal and a second electrode metal.