Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, and forming an isolation structure, a drift region and a body region in the substrate; forming a high-voltage gate oxide layer in the high-voltage device region; forming a medium-voltage gate oxide layer in the medium-voltage device region, and forming a groove in the isolation structure of the high-voltage device region; forming a gate material layer; and patterning the gate material layer to form a gate and a field plate located in the groove. While the medium-voltage gate oxide layer is formed in the medium-voltage device region, the grooves are formed in the isolation structures on the two sides of the gate region of the high-voltage device region, the field plates are formed in the grooves while the gate is formed, only the mask plate for forming the medium-voltage gate oxide layer and the mask plate for forming the gate need to be revised, the influence on the process is small, and the yield is high. The process is simple, the cost is low, the electric field of the drift region can be optimized, the breakdown voltage and the on-resistance of the high-voltage device are improved, and the device performance is optimized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuits, and in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] In HV (High Voltage) platform technology, HV MOS (High Voltage Metal Oxide Semiconductor) and CMOS (Complementary Metal Oxide Semiconductor) are integrated in the same chip. The HV MOS has the characteristics of high voltage and large current of discrete devices, and also absorbs the advantages of high-density intelligent logic control of low-voltage integrated circuits. A single chip can realize the functions that originally required multiple chips, greatly reducing the area, reducing the cost, improving the energy efficiency, and meeting the development direction of modern power electronic devices, i.e., miniaturization, intelligentization, and low energy consumption.

[0003] Breakdown voltage and on-resistance are key parameters for measuring HV MOS devices. Therefore, under the condition of obtaining the same breakdown voltage, the on-resistance should be reduced as much as possible to improve the competitiveness of the product.

[0004] The most common HV MOS device is isolated by STI (Shallow Trench Isolation), and the STI formed by the CMOS process is used as the field plate dielectric layer of the HV MOS device. Since the process of the STI is shared with the CMOS device, the parameters of the STI process cannot be arbitrarily changed to optimize the breakdown voltage and on-resistance of the HV MOS device. SUMMARY

[0005] The present application provides a semiconductor device and a manufacturing method thereof. A recess is formed in the isolation structure of the high-voltage device region while forming the medium-voltage gate oxide layer, so that a field plate is formed in the recess. The process is simple, the manufacturing cost is low, and the device performance can be optimized.

[0006] To solve the above technical problems, according to a first aspect of the present application, a manufacturing method of a semiconductor device is provided, comprising the following steps:

[0007] A substrate is provided, which includes at least a high-voltage device region and a medium-voltage device region. A plurality of isolation structures, two drift regions, and a body region surrounding the two drift regions are formed in the substrate in the high-voltage device region and the medium-voltage device region, respectively. The region between the two drift regions is used as a gate region for forming a gate;

[0008] A high-voltage gate oxide layer is formed on the substrate in the gate region of the high-voltage device region.

[0009] forming a layer of medium voltage gate oxide material over the substrate, leaving the layer of medium voltage gate oxide material in the gate region of the medium voltage device region as a medium voltage gate oxide layer, and removing the layer of medium voltage gate oxide material in the remaining areas while forming a recess in the isolation structure on both sides of the gate region of the high voltage device region;

[0010] forming a gate material layer, the gate material layer filling the recess and covering the high voltage gate oxide layer, the medium voltage gate oxide layer, the substrate and the isolation structure; and

[0011] patterning the gate material layer to form a gate on the high voltage gate oxide layer and the medium voltage gate oxide layer and a field plate in the recess on both sides of the gate of the high voltage device region.

[0012] Optionally, the method of removing the layer of medium voltage gate oxide material in the remaining areas while forming a recess in the isolation structure on both sides of the gate region of the high voltage device region comprises:

[0013] forming a first patterned photoresist layer, the first patterned photoresist layer exposing the layer of medium voltage gate oxide material in the drift region and the body region of the high voltage device region and the medium voltage device region and part of the isolation structure on both sides of the gate region of the high voltage device region;

[0014] using the first patterned photoresist layer as a mask, etching the exposed layer of medium voltage gate oxide material and the isolation structure until the layer of medium voltage gate oxide material is removed and the recess is formed in the isolation structure; and

[0015] removing the first patterned photoresist layer.

[0016] Optionally, the depth of the recess is 15% to 35% of the depth of the isolation structure in which the recess is formed, and the width of the recess is 20% to 30% of the width of the isolation structure in which the recess is formed.

[0017] Optionally, the depth of the recess is 300A to 600A, and the width of the recess is 300nm to 400nm.

[0018] Optionally, the method of patterning the gate material layer to form a gate on the high voltage gate oxide layer and the medium voltage gate oxide layer and a field plate in the recess on both sides of the gate of the high voltage device region comprises:

[0019] forming a second patterned photoresist layer covering the gate material layer on the high-voltage gate oxide layer and the middle-voltage gate oxide layer and the gate material layer in the recess on both sides of the high-voltage gate oxide layer;

[0020] forming the gate and the field plate by etching the exposed gate material layer with the second patterned photoresist layer as a mask; and

[0021] removing the second patterned photoresist layer.

[0022] Optionally, the field plate is also located on the isolation structure where the recess is located.

[0023] Optionally, the gate and the field plate have a spacing therebetween; or the gate and the field plate are connected.

[0024] To solve the above technical problems, according to a second aspect of the present application, a semiconductor device is also provided, which is manufactured by the manufacturing method of the semiconductor device as described above, and the semiconductor device comprises:

[0025] a substrate, the substrate comprising at least a high-voltage device region and a middle-voltage device region, the substrate of the high-voltage device region and the middle-voltage device region each comprising a plurality of isolation structures, two drift regions and a body region surrounding the two drift regions, a region between the two drift regions being a gate region for forming a gate; the isolation structures on both sides of the gate region of the high-voltage device region each comprising a recess;

[0026] a high-voltage gate oxide layer on the substrate of the gate region of the high-voltage device region;

[0027] a middle-voltage gate oxide layer on the substrate of the gate region of the middle-voltage device region;

[0028] a gate on the high-voltage gate oxide layer and the middle-voltage gate oxide layer; and

[0029] a field plate in the recess on both sides of the gate of the high-voltage device region.

[0030] Optionally, the field plate is also located on the isolation structure where the recess is located.

[0031] Optionally, the gate and the field plate have a spacing therebetween; or the gate and the field plate are connected.

[0032] The semiconductor device and the manufacturing method thereof provided by the application include the following steps: providing a substrate, the substrate including at least a high-voltage device area and a medium-voltage device area; forming a plurality of isolation structures, two drift areas and a body area surrounding the two drift areas in the substrate in the high-voltage device area and the medium-voltage device area respectively, and the area between the two drift areas is used as a gate area for forming a gate; forming a high-voltage gate oxide layer on the substrate in the gate area of the high-voltage device area; forming a medium-voltage gate oxide material layer on the substrate, reserving the medium-voltage gate oxide material layer in the gate area of the medium-voltage device area as a medium-voltage gate oxide layer, removing the medium-voltage gate oxide material layer in the remaining area, and forming a groove in the isolation structure on both sides of the gate area of the high-voltage device area at the same time; forming a gate material layer, the gate material layer fills the groove and covers the high-voltage gate oxide layer, the medium-voltage gate oxide layer, the substrate and the isolation structure; and patterning the gate material layer to form a gate on the high-voltage gate oxide layer and the medium-voltage gate oxide layer and a field plate in the groove on both sides of the gate of the high-voltage device area. The application forms a medium-voltage gate oxide layer in the medium-voltage device area, forms a groove in the isolation structure on both sides of the gate area of the high-voltage device area at the same time, and then forms a field plate in the groove of the high-voltage device area at the same time of forming a gate, only the mask for forming the medium-voltage gate oxide layer and the mask for forming the gate need to be modified, the process is less affected, the process is simple, the cost is low, the field plate formed in the groove can optimize the electric field of the drift area, improve the breakdown voltage and on-resistance of the high-voltage device, and optimize the device performance.

[0033] In addition, the field plate is formed in the groove, and a space is formed between the gate and the field plate, so that the gate and the field plate can be applied with voltages separately, the working voltage range of the gate is larger, and the voltage adjustment capability is better.

[0034] In addition, the field plate is also located on the isolation structure where the groove is located, and the gate can be connected with the field plate, so that the mask for forming the gate does not need to be modified, thereby saving the cost. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 is a structural schematic diagram after forming a medium-voltage gate oxide material layer in the related art.

[0036] Figure 2 is a structural schematic diagram after forming a first patterned photoresist layer in the related art.

[0037] Figure 3 is a structural schematic diagram after removing the medium-voltage gate oxide material layer in the high-voltage device area in the related art.

[0038] Figure 4is a structural schematic diagram of a structure after a gate material layer is formed in the related art.

[0039] Figure 5 is a structural schematic diagram of a structure after a gate and a field plate are formed in the related art.

[0040] Figure 6 is a structural schematic diagram of a structure after a source / drain end and a substrate end are formed in the related art.

[0041] Figure 7 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application.

[0042] Figure 8 is a structural schematic diagram of a structure after a middle-voltage gate oxide material layer is formed according to an embodiment of the present application.

[0043] Figure 9 is a structural schematic diagram of a structure after a first patterned photoresist layer is formed according to an embodiment of the present application.

[0044] Figure 10 is a structural schematic diagram of a structure after a recess is formed according to an embodiment of the present application.

[0045] Figure 11 is a structural schematic diagram of a structure after a gate material layer is formed according to an embodiment of the present application.

[0046] Figure 12 is a structural schematic diagram of a structure after a gate and a field plate are formed according to an embodiment of the present application.

[0047] Figure 13 is a structural schematic diagram of a structure after a source / drain end and a substrate end are formed according to an embodiment of the present application.

[0048] Figure 14 is a structural schematic diagram of a structure after a gate and a field plate are formed according to another embodiment of the present application.

[0049] Figure 15 is a structural schematic diagram of a structure after a source / drain end and a substrate end are formed according to another embodiment of the present application.

[0050] Legend of reference numerals:

[0051] Figures 1 to 6 10 - substrate; 11 - isolation structure; 12 - drift region; 13 - body region; 14 - high-voltage gate oxide layer; 15 - middle-voltage gate oxide material layer; 16 - first patterned photoresist layer; 17 - gate material layer; 18 - gate; 19 - field plate; 20 - source / drain end; 21 - substrate end.

[0052] Figures 8 to 15Fig. 2 is a schematic diagram of a structure after forming a high-voltage gate oxide layer in the prior art. As shown in Fig. 2, a substrate 10 is provided, which includes at least a high-voltage device region and a medium-voltage device region, a high-voltage gate oxide layer 14 is formed on the substrate 10 in the high-voltage device region, and a medium-voltage gate oxide layer 15 is formed on the substrate 10 in the medium-voltage device region. DETAILED DESCRIPTION

[0053] Figure 1 Fig. 3 is a schematic diagram of a structure after forming a medium-voltage gate oxide layer in the prior art. As shown in Fig. 3, the medium-voltage gate oxide layer 15 is formed on the substrate 10 in the medium-voltage device region, and the medium-voltage gate oxide layer 15 covers the gate region, the drift region and the body region in the medium-voltage device region, and covers the drift region 12 and the body region 13 in the high-voltage device region. Figure 1 DETAILED DESCRIPTION Figure 1 Figure 1 As shown in Fig. 1, a substrate 10 is provided, which includes at least a high-voltage device region and a medium-voltage device region, a plurality of isolation structures 11 are formed in the substrate 10 in the high-voltage device region and the medium-voltage device region, respectively, a drift region 12 and a body region 13 are formed in the substrate 10 by ion implantation, and the region between the two drift regions 12 is a gate region for forming a gate electrode.

[0054] As shown in Fig. 2, a high-voltage gate oxide layer 14 is formed on the substrate 10 in the gate region of the high-voltage device region. For example, a high-voltage gate oxide material layer is first formed, which covers the substrate 10 in the high-voltage device region and the medium-voltage device region, and then all of the high-voltage gate material layer except that in the gate region of the high-voltage device region is removed, and the high-voltage gate material layer in the gate region of the high-voltage device region serves as the high-voltage gate oxide layer 14. Figure 1 As shown in Fig. 3, a medium-voltage gate oxide layer 15 is formed on the substrate 10 in the medium-voltage device region, which covers the gate region, the drift region and the body region in the medium-voltage device region, and covers the drift region 12 and the body region 13 in the high-voltage device region.

[0055] As shown in Fig. 4, a first patterned photoresist layer 16 is formed, which exposes the medium-voltage gate oxide layer 15 in the drift region 12 and the body region 13 of the high-voltage device region, and also exposes the medium-voltage gate oxide layer 15 in the drift region and the body region of the medium-voltage device region.

[0056] Figure 2 As shown in Fig. 5, a gate material layer 17 is formed on the substrate 10 in the gate region of the high-voltage device region and the medium-voltage device region, and the gate material layer 17 covers the medium-voltage gate oxide layer 15 in the gate region of the high-voltage device region and the medium-voltage device region.

[0057] As shown in Fig. 6, a gate electrode 18 is formed on the substrate 10 in the gate region of the high-voltage device region and the medium-voltage device region, and the gate electrode 18 covers the medium-voltage gate oxide layer 15 in the gate region of the high-voltage device region and the medium-voltage device region. Figure 3 ​​As shown in Fig. 4, a second patterned photoresist layer is formed on the gate material layer 17. The gate material layer 17 is patterned by using the second patterned photoresist layer as a mask to form a gate 18 on the high-voltage gate oxide layer 14 and the medium-voltage gate oxide layer, and a field plate 19 on part of the isolation structure 11 on both sides of the gate 18 in the high-voltage device region. The gate 18 is connected to the field plate 19.

[0058] Then, referring to Fig. 5, Figure 4 As shown in Fig. 6, a gate material layer 17 is formed, which covers the high-voltage gate oxide layer 14, the medium-voltage gate oxide layer, the substrate 10 and the isolation structure 11, i.e. covers all regions on the substrate 10.

[0059] Next, referring to Fig. 7, Figure 4 With Figure 5 As shown in Fig. 4, a second patterned photoresist layer is formed on the gate material layer 17. The gate material layer 17 is patterned by using the second patterned photoresist layer as a mask to form a gate 18 on the high-voltage gate oxide layer 14 and the medium-voltage gate oxide layer, and a field plate 19 on part of the isolation structure 11 on both sides of the gate 18 in the high-voltage device region. The gate 18 is connected to the field plate 19.

[0060] Then, referring to Fig. 5, Figure 6 As shown in Fig. 7, a source / drain 20 is formed in the drift region 12, and a substrate end 21 is formed in the body region 13.

[0061] As described in the background, since the isolation structure 11 in the high-voltage device region is formed together with the isolation structure of the CMOS device on the same substrate 10, the process parameters of the isolation structure 11 cannot be changed at will to optimize the breakdown voltage and on-resistance of the high-voltage device.

[0062] The solution to this problem is to add a field plate in the isolation structure 11 by etching to optimize the electric field in the drift region, so as to optimize the breakdown voltage and on-resistance of the high-voltage device. However, the process of introducing a field plate in the isolation structure 11 is relatively complex, which increases the production cost and process complexity and reduces the competitiveness of the product.

[0063] To solve the above problems, it is found through research that the isolation structure 11 on both sides of the gate region can be etched when the medium-voltage gate oxide material layer 15 in the high-voltage device region is removed (i.e. the medium-voltage gate oxide layer is formed in the medium-voltage device region), i.e. a field plate can be introduced in the isolation structure 11. This can reduce the process complexity and cost, and only the mask used when forming the patterned photoresist layer 16 needs to be changed, which has a small impact on the process.

[0064] Further research shows that the application provides a semiconductor device manufacturing method, comprising: providing a substrate, the substrate comprising at least a high-voltage device region and a medium-voltage device region, forming a plurality of isolation structures, two drift regions and a body region surrounding the two drift regions in the substrate of the high-voltage device region and the medium-voltage device region respectively, and the region between the two drift regions as a gate region for forming a gate; forming a high-voltage gate oxide layer on the substrate of the gate region of the high-voltage device region; forming a medium-voltage gate oxide material layer on the substrate, retaining the medium-voltage gate oxide material layer of the gate region of the medium-voltage device region as a medium-voltage gate oxide layer, removing the medium-voltage gate oxide material layer in the remaining region, and forming a groove in the isolation structure on both sides of the gate region of the high-voltage device region at the same time; forming a gate material layer, the gate material layer fills the groove and covers the high-voltage gate oxide layer, the medium-voltage gate oxide layer, the substrate and the isolation structure; and patterning the gate material layer to form a gate on the high-voltage gate oxide layer and the medium-voltage gate oxide layer and a field plate in the groove on both sides of the gate of the high-voltage device region.

[0065] Correspondingly, the application also provides a semiconductor device, comprising: a substrate, the substrate comprising at least a high-voltage device region and a medium-voltage device region, a plurality of isolation structures, two drift regions and a body region surrounding the two drift regions are formed in the substrate of the high-voltage device region and the medium-voltage device region respectively, and the region between the two drift regions as a gate region for forming a gate; a high-voltage gate oxide layer on the substrate of the gate region of the high-voltage device region; a medium-voltage gate oxide layer on the substrate of the gate region of the medium-voltage device region; a gate on the high-voltage gate oxide layer and the medium-voltage gate oxide layer respectively; and a field plate in the groove on both sides of the gate of the high-voltage device region.

[0066] The semiconductor device and its manufacturing method provided by the application form a medium-voltage gate oxide layer in the medium-voltage device region at the same time as forming a groove in the isolation structure on both sides of the gate region of the high-voltage device region, then form a field plate in the groove of the high-voltage device region at the same time as forming a gate, only need to modify the mask for forming the medium-voltage gate oxide layer and the mask for forming the gate, the impact on the process is relatively small, and the process is simple, low cost, and the field plate formed in the groove can optimize the drift region electric field, improve the breakdown voltage and on-resistance of the high-voltage device, and optimize the device performance.

[0067] For purposes of the USPTO, the phrase "AUSN, advantage, and features of the present application" in this disclosure is intended to supply a clear description of the purposes, advantages, and features of the present application. The following detailed description is presented in connection with the appended drawings. It is to be understood that the various embodiments of the application are merely illustrative of the principles of the application. It is intended that the scope of the application be defined by the claims appended hereto, not by the specification. In the drawings, like numbers refer to like elements throughout the several views, unless otherwise indicated. Additionally, the use of "about" in connection with a given value means that the value is within a range of acceptable manufacturing tolerances for the given value.

[0068] As used in this application, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. As used in this application, the term "or" is generally employed in its sense of "and / or" unless the content clearly dictates otherwise. As used in this application, the term "at least one" is generally employed in its sense of "one or more" unless the content clearly dictates otherwise. As used in this application, the term "at least two" is generally employed in its sense of "two or more" unless the content clearly dictates otherwise. In addition, the terms "first," "second," "third," etc. are used merely as labels, and are not intended to suggest or imply relative importance or a quantity of indicia there to which the labels are applied; thus, "first" can be understood to imply a quantity of at least one, unless the content clearly dictates otherwise.

[0069] Figure 7 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application. As shown in Figure 7 The method for manufacturing a semiconductor device according to an embodiment of the present application includes the following steps:

[0070] S1: providing a substrate, the substrate including at least a high-voltage device region and a medium-voltage device region, forming a plurality of isolation structures, two drift regions, and a body region surrounding the two drift regions in the substrate in the high-voltage device region and the medium-voltage device region, respectively, and a region between the two drift regions as a gate region for forming a gate;

[0071] S2: forming a high-voltage gate oxide layer on the substrate in the gate region of the high-voltage device region;

[0072] S3: forming a medium-voltage gate oxide material layer on the substrate, retaining the medium-voltage gate oxide material layer in the gate region of the medium-voltage device region as a medium-voltage gate oxide layer, removing the medium-voltage gate oxide material layer in the remaining regions, and forming a groove in the isolation structure on both sides of the gate region of the high-voltage device region;

[0073] S4: Forming a gate material layer, the gate material layer filling the trench and covering the high-voltage gate oxide layer, the medium-voltage gate oxide layer, the substrate, and the isolation structure; and

[0074] S5: Pattern the gate material layer to form a gate located on the high-voltage gate oxide layer and the medium-voltage gate oxide layer, and a field plate located in the groove on both sides of the gate in the high-voltage device region.

[0075] Figures 8 to 13 This is a schematic diagram illustrating the structural steps of a semiconductor device fabrication method according to an embodiment of this application. Next, we will combine... Figure 7 , Figures 8 to 13 A method for fabricating a semiconductor device according to an embodiment of this application will be described in detail.

[0076] In step S1, please refer to Figure 8 As shown, a substrate 100 is provided, the substrate 100 including at least a high voltage device region and a medium voltage device region, a plurality of isolation structures 110, two drift regions 120 and a body region 130 surrounding the two drift regions 120 are formed in the substrate 100 in the high voltage device region and the medium voltage device region respectively, and the region between the two drift regions 120 serves as a gate region for forming a gate.

[0077] The substrate 100 can be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon-carbon substrate, indium arsenide (InAs) substrate, gallium arsenide (GaAs) substrate, indium phosphide (InP) substrate, or other III / V compound semiconductor substrates. It can also be a silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), or germanium-on-insulator (GeOI) substrate, etc. The substrate 100 can also be implanted with certain dopant particles to change the electrical parameters according to design requirements. In this embodiment, the substrate 100 is a silicon substrate.

[0078] The substrate 100 includes at least a high-voltage device region and a medium-voltage device region. The high-voltage device region is used to form high-voltage devices, and the medium-voltage device region is used to form medium-voltage devices, but is not limited to these. The substrate 100 may also include a low-voltage device region for forming low-voltage devices, and may also include other regions.

[0079] Figure 8 Only the high-voltage device area is shown. The device structures of the medium-voltage device area and the low-voltage device area can be the same as those of the high-voltage device area. Refer to [the relevant documentation / reference]. Figure 8 The structure shown.

[0080] In an embodiment of the present application, a plurality of isolation structures 110 are first formed in the substrate 100, which are used to isolate the drift regions and the body region or the body region and other regions formed subsequently in the substrate 100. The isolation structure 110 is, for example, a shallow trench isolation structure. An exemplary method for forming the shallow trench isolation structure includes: first forming an oxide layer and a nitride layer on the substrate 100, and forming a patterned photoresist layer on the nitride layer; then taking the patterned photoresist layer as a mask to etch the nitride layer, the oxide layer and the substrate 100 to form a shallow trench in the substrate 100; then filling an isolation material in the shallow trench, which fills the shallow trench and covers the nitride layer; then planarizing the isolation material to expose the nitride layer; and then removing the nitride layer and the oxide layer to form the shallow trench isolation structure. The upper surface of the shallow trench isolation structure thus formed is higher than the upper surface of the substrate 100, as shown in Figure 8 Fig. 1, but of course is not limited thereto. The upper surface of the isolation structure 110 can also be flush with the upper surface of the substrate 100.

[0081] Then, the substrate 100 is ion implanted in sequence to form the drift regions 120 and the body region 130 in the substrate 100. For example, first select the region between two adjacent isolation structures 110 as the region for pre-forming the gate, which is referred to as the gate region hereinafter, and then select the regions on both sides of the gate region and adjacent to only one isolation structure as the regions for pre-forming the source and the drain to form two drift regions 120 by ion implantation, one of which is the source and the other is the drain, and then perform ion implantation on the outer sides of the two drift regions 120 to form the body region 130, which is spaced apart from the drift regions 120 by the isolation structure 110 and is used as the lead-out of the substrate 100. In an embodiment, the substrate 100 is a P-type substrate, the drift regions 120 are N-type drift regions, and the body region 130 is a P-type body region, but of course is not limited thereto.

[0082] It can be understood that the isolation structures 110 can be formed in the substrate 100 in the high-voltage device region and the medium-voltage device region at the same time, and then the drift regions 120 and the body region 130 can be formed in the substrate 100 in the high-voltage device region and the medium-voltage device region, respectively.

[0083] In step S2, please continue to refer to Figure 8 Fig. 1, a high-voltage gate oxide layer 140 is formed on the substrate 100 in the gate region of the high-voltage device region.

[0084] In one embodiment, a high-voltage gate oxide layer (not shown) is first formed on the substrate 100, the high-voltage gate oxide layer covering the high-voltage device region and the medium-voltage device region; then, a patterned photoresist layer is formed on the high-voltage gate oxide layer, the patterned photoresist layer covering the substrate 100 of the gate region of the high-voltage device region, exposing the remaining areas; next, using the patterned photoresist layer as a mask, the high-voltage gate oxide layer is etched until the substrate 100 is exposed, and a high-voltage gate oxide layer 140 is formed on the substrate 100 of the gate region of the high-voltage device region; then, the patterned photoresist layer is removed.

[0085] The high-voltage gate oxide layer can be formed using a thermal oxidation process. The material of the high-voltage gate oxide layer includes, but is not limited to, silicon oxide. The thickness of the high-voltage gate oxide layer is determined by the required thickness of the gate oxide layer in the high-voltage device region.

[0086] In step S3, please refer to Figures 8 to 10 As shown, a medium-voltage gate oxide layer 150 is formed on the substrate 100. The medium-voltage gate oxide layer 150 of the gate region of the medium-voltage device region is retained as a medium-voltage gate oxide layer, and the medium-voltage gate oxide layer 150 of the remaining regions is removed. Meanwhile, a groove 170 is formed in the isolation structure 110 on both sides of the gate region of the high-voltage device region.

[0087] In one embodiment of this application, please refer to... Figure 8 As shown, a medium-voltage gate oxide layer 150 is formed on the substrate 100. The medium-voltage gate oxide layer 150 covers the drift region 120 and the body region 130 of the high-voltage device region, and also covers the gate region, the drift region, and the body region of the medium-voltage device region. The medium-voltage gate oxide layer 150 can be formed using a thermal oxidation process, and the thickness of the medium-voltage gate oxide layer 150 is determined by the required thickness of the gate oxide layer in the medium-voltage device region.

[0088] When the medium-voltage gate oxide layer 150 is formed by thermal oxidation, since the high-voltage gate oxide layer 140 has already been formed on the gate region of the high-voltage device region, silicon consumption and the growth of the new oxide layer are extremely slow and the thickness remains almost unchanged. Therefore, it will not affect the high-voltage gate oxide layer 140.

[0089] Then, please refer to Figure 9As shown, a first patterned photoresist layer 160 is formed, which exposes the high-voltage device region and the medium-voltage device region's drift region 120 and body region 130's medium-voltage gate oxide material layer 150, and part of the isolation structure 110 on both sides of the high-voltage device region's gate region. In this embodiment, a first photoresist layer is formed on the substrate 100, and a first mask is used to expose and develop the first photoresist layer, thereby forming the first patterned photoresist layer 160.

[0090] Compared with the first patterned photoresist layer 16 in Figure 2 , the first patterned photoresist layer 160 in this embodiment exposes part of the isolation structure 110 on both sides of the high-voltage device region's gate region, so only the first mask needs to be improved.

[0091] Next, as shown in Figure 10 , the exposed medium-voltage gate oxide material layer 150 and isolation structure 110 are etched using the first patterned photoresist layer 160 as a mask, until the medium-voltage gate oxide material layer 150 is removed and the groove 170 is formed in the isolation structure 110. That is, the exposed medium-voltage gate oxide material layer 150 is removed, a medium-voltage gate oxide layer is formed in the medium-voltage device region's gate region, and a groove 170 is formed in the isolation structure 110 on both sides of the high-voltage device region's gate region.

[0092] In this embodiment, a medium-voltage gate oxide layer is formed in the medium-voltage device region, and a groove 170 is formed in the isolation structure 110 on both sides of the high-voltage device region's gate region, without the need for a separate etching process to form the groove 170 in the isolation structure 110, and only the first mask used to form the medium-voltage gate oxide layer needs to be improved, which has a relatively small impact on the process and is simple and low-cost.

[0093] The first patterned photoresist layer 160 is then removed. For example, a gray etching process or a wet etching process can be used to remove the first patterned photoresist layer 160.

[0094] In one embodiment, a wet etching process can be used to etch the medium-voltage gate oxide material layer 150 and the isolation structure 110. In another embodiment, a dry etching process combined with a wet etching process can be used to etch the medium-voltage gate oxide material layer 150 and the isolation structure 110.

[0095] In an embodiment of the present application, the depth of the recess 170 is 15% to 35% of the depth of the isolation structure 110 where the recess 170 is located, and the width of the recess 170 is 20% to 30% of the width of the isolation structure 110 where the recess 170 is located. For example, the depth of the recess 170 is 300A to 600A, and the width of the recess 170 is 300 nm to 400 nm, but the present application is not limited to this example. Here, the isolation structure 110 is the isolation structure where the recess 170 is located.

[0096] When the substrate 100 further includes a low-voltage device region, after the formation of the medium-voltage gate oxide layer and the recess 170, a low-voltage gate oxide layer is further formed. The low-voltage gate oxide layer can be formed by a thermal oxidation process, and the thickness of the low-voltage gate oxide layer is determined by the thickness of the gate oxide layer required by the low-voltage device region. Since the low-voltage gate oxide layer is relatively thin, the formation of the low-voltage gate oxide layer will not affect the gate oxide layers in the high-voltage device region and the low-voltage device region. The thickness of the high-voltage gate oxide layer 140 is greater than the thickness of the medium-voltage gate oxide layer, and the thickness of the medium-voltage gate oxide layer is greater than the thickness of the low-voltage gate oxide layer. The materials of the high-voltage gate oxide layer 140, the medium-voltage gate oxide layer, and the low-voltage gate oxide layer can be the same or different.

[0097] In step S4, as shown in Figure 11 , a gate material layer 180 is formed, which fills the recess 170 and covers the high-voltage gate oxide layer 140, the medium-voltage gate oxide layer, the substrate 100, and the isolation structure 110.

[0098] The gate material layer 180 fills the recess 170 and covers the substrate 100. The gate material layer 180 can be formed by any suitable process or a combination thereof, such as a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. The material of the gate material layer 180 is, for example, polysilicon.

[0099] In step S5, as shown in Figure 11 and Figure 12 , the gate material layer 180 is patterned to form a gate 190 located on the high-voltage gate oxide layer 140 and the medium-voltage gate oxide layer, and a field plate 200 located in the recess 170 on both sides of the gate 190 in the high-voltage device region.

[0100] In one embodiment of this application, the field plate 200 may be located only within the recess 170. A gap exists between the gate 190 and the field plate 200. Exemplarily, firstly, a photoresist layer is formed on the gate material layer 180. The photoresist layer is then exposed and developed using a second mask to form a second patterned photoresist layer. This second patterned photoresist layer covers the gate material layer 180 on the high-voltage gate oxide layer 140 and the medium-voltage gate oxide layer, as well as the gate material layer 180 within the recess 170 on both sides of the high-voltage gate oxide layer 140. Next, using the second patterned photoresist layer as a mask, the exposed gate material layer 180 is etched to form the gate 190 and the field plate 200.

[0101] and Figure 5 Compared to the field plate 19 shown, in this embodiment, the field plate 200 is located within the recess 170 of the isolation structure 110. Figure 5 Compared to the high-voltage device shown, the field plate 200 formed in the groove 170 in this embodiment can optimize the electric field in the drift region, improve the breakdown voltage and on-resistance of the high-voltage device, and optimize the device performance.

[0102] With formation Figure 5 Compared to the second mask used, in this embodiment, the second mask needs to be modified to expose the isolation structure 110 between the gate 190 and the groove 170, thereby forming the gate 190 and the field plate 200 spaced apart.

[0103] In another embodiment of this application, please refer to Figure 12 As shown, the field plate 200 can also be located on the isolation structure 110 where the groove 170 is located, that is, the field plate 200 is located in the groove 170 on both sides of the gate 190 in the high-voltage device region and on the isolation structure 110 where the groove 170 is located. There is still a gap between the gate 190 and the field plate 200. The field plate 200 can be located on a part of the isolation structure 110 where the groove 170 is located (i.e., the part of the part close to the groove 170), or it can be located on all areas of the isolation structure 110 except for the gap area between it and the gate 190.

[0104] Please refer to Figure 13 As shown, after forming the gate 190 and the field plate 200, the method further includes: forming a source / drain terminal 210 in the drift region 120 and forming a substrate terminal 220 in the body region 130.

[0105] The application forms a recess 170 in the isolation structure 110 on both sides of the gate region of the high-voltage device region while forming the medium-voltage gate oxide layer in the medium-voltage device region, and then forms the field plate 200 in the recess 170 of the high-voltage device region while forming the gate 190, which only needs to modify the mask for forming the medium-voltage gate oxide layer (i.e. the first mask mentioned above) and the mask for forming the gate (i.e. the second mask mentioned above), has less impact on the process, and the process is simple, low in cost, and the field plate 200 formed in the recess 170 can optimize the electric field of the drift region, improve the breakdown voltage and on-resistance of the high-voltage device, and optimize the device performance.

[0106] In the embodiment, the field plate 200 is formed in the recess 170 (or formed in the recess 170 and on the part of the isolation structure 110 where the recess 170 is located), and a space is formed between the gate 190 and the field plate 200, so that the gate 190 and the field plate 200 can be separately applied with voltage, so that the working voltage range of the gate 190 is larger, and the voltage adjustment capability is better.

[0107] Figure 14 is a structural schematic diagram after forming the gate and the field plate provided by another embodiment of the application, Figure 15 is a structural schematic diagram after forming the source / drain and the substrate provided by another embodiment of the application. Please refer to Figure 14 and Figure 15 It is shown that the difference between the embodiment and the previous embodiment is that, in the embodiment, the gate 190 and the field plate 200 are connected.

[0108] Please refer to Figure 11 and 14 It is shown that first, a photoresist layer is formed on the gate material layer 180, the photoresist layer is exposed and developed by using a second mask, a second patterned photoresist layer is formed, and the second patterned photoresist layer covers the high-voltage gate oxide layer 140, the medium-voltage gate oxide layer, and the gate material layer 180 on part of the isolation structure 110 on both sides of the high-voltage gate oxide layer 140. Then, the exposed gate material layer 180 is etched by taking the second patterned photoresist layer as a mask, the gate 190 and the field plate 200 are formed, the gate 190 and the field plate 200 are connected, and the field plate 200 is located in the recess 170 and covers the isolation structure 110 where the recess 170 is located.

[0109] The field plate 200 is located in the isolation structure 110 where the recess 170 is located, and can be located on the part of the isolation structure 110 close to the gate 190 (as shown in Figure 15 , or can be located on all regions of the isolation structure 110.

[0110] In this embodiment, the second mask plate does not need to be changed, and cost can be saved.

[0111] This embodiment mainly illustrates the difference from the previous embodiment, and the same parts can be referred to the previous embodiment.

[0112] Please refer to Figure 15 As shown in FIG. 1, after forming the gate 190 and the field plate 200, the method further includes: forming a source / drain end 210 in the drift region 120 and forming a substrate end 220 in the body region 130.

[0113] The method for manufacturing a semiconductor device provided by the present application includes the following steps: providing a substrate 100, the substrate 100 at least including a high-voltage device region and a medium-voltage device region; forming a plurality of isolation structures 110, two drift regions 120 and a body region 130 surrounding the two drift regions 110 in the substrate 100 of the high-voltage device region and the medium-voltage device region, and the region between the two drift regions 120 being a gate region for forming a gate; forming a high-voltage gate oxide layer 140 on the substrate 100 of the gate region of the high-voltage device region; forming a medium-voltage gate oxide material layer 150 on the substrate 100, retaining the medium-voltage gate oxide material layer 150 of the gate region of the medium-voltage device region as a medium-voltage gate oxide layer, removing the medium-voltage gate oxide material layer in the remaining region, and forming a groove 170 in the isolation structure 110 on both sides of the gate region of the high-voltage device region; forming a gate material layer 180, the gate material layer 180 filling the groove 170 and covering the high-voltage gate oxide layer 140, the medium-voltage gate oxide layer, the substrate 100 and the isolation structure 110; and patterning the gate material layer 180 to form a gate 190 on the high-voltage gate oxide layer 140 and the medium-voltage gate oxide layer and a field plate 200 in the groove 170 on both sides of the gate 190 of the high-voltage device region. In the method provided by the present application, the medium-voltage gate oxide layer is formed in the medium-voltage device region, and the groove 170 is formed in the isolation structure 110 on both sides of the gate region of the high-voltage device region, then the gate 190 is formed, and the field plate 200 is formed in the groove 170 of the high-voltage device region. Only the mask plate for forming the medium-voltage gate oxide layer and the mask plate for forming the gate need to be changed, which has little effect on the process, and the process is simple, low in cost, and the field plate 200 formed in the groove 170 can optimize the electric field of the drift region, improve the breakdown voltage and on-resistance of the high-voltage device, and optimize the performance of the device.

[0114] In addition, the field plate 200 is formed in the groove 170, and a space is formed between the gate 190 and the field plate 200, so that the gate 190 and the field plate 200 can be applied with voltages separately, the working voltage range of the gate 190 is larger, and the voltage adjustment capability is better.

[0115] In addition, the field plate 200 is located on the isolation structure 110 where the groove 170 is located, and the gate 190 can be connected with the field plate 200, so that the mask used to form the gate 200 does not need to be modified, thereby saving cost.

[0116] Correspondingly, the application further provides a semiconductor device manufactured by the manufacturing method of the semiconductor device. Figure 13 With Figure 15 As shown in the figure, the semiconductor device provided by the embodiment comprises:

[0117] a substrate 100, wherein the substrate 100 comprises at least a high-voltage device area and a medium-voltage device area, and a plurality of isolation structures 110, two drift regions 120 and a body region 130 surrounding the two drift regions 120 are formed in the substrate 100 of the high-voltage device area and the medium-voltage device area respectively, and a region between the two drift regions 120 is used as a gate region for forming a gate; a groove 170 is formed in the isolation structure 110 on both sides of the gate region of the high-voltage device area;

[0118] a high-voltage gate oxide layer 140 located on the substrate 100 of the gate region of the high-voltage device area;

[0119] a medium-voltage gate oxide layer located on the substrate 100 of the gate region of the medium-voltage device area;

[0120] a gate 190 located on the high-voltage gate oxide layer 140 and the medium-voltage gate oxide layer respectively; and

[0121] a field plate 200 located in the groove 170 on both sides of the gate 190 of the high-voltage device area.

[0122] In the embodiment of the application, as shown in the figure, the field plate 200 is located on the isolation structure 110 where the groove 170 is located, and a space is formed between the gate 190 and the field plate 200. Figure 13 As shown in the figure, the field plate 200 is located on the isolation structure 110 where the groove 170 is located, and a space is formed between the gate 190 and the field plate 200. The field plate 200 can be located on a part of the isolation structure 110 where the groove 170 is located (i.e. a part close to the groove 170), or can be located on all regions of the isolation structure 110 except the space between the gate 190 and the field plate 200.

[0123] In the embodiment of the application, as shown in the figure, the field plate 200 is located on the isolation structure 110 where the groove 170 is located, and a space is formed between the gate 190 and the field plate 200. Figure 15As shown, the field plate 200 is also located on the isolation structure 110 where the groove 170 is located, and the gate 190 is connected with the field plate 200. The field plate 200 can be located on the part of the isolation structure 110 where the groove 170 is located, close to the gate 190 (as shown), or can be located on the whole area of the isolation structure 110. Figure 15 As shown, the field plate 200 is also located on the isolation structure 110 where the groove 170 is located, and the gate 190 is connected with the field plate 200. The field plate 200 can be located on the part of the isolation structure 110 where the groove 170 is located, close to the gate 190 (as shown), or can be located on the whole area of the isolation structure 110.

[0124] In an embodiment of the present application, the gate 190 and the field plate 200 are made of the same material.

[0125] In summary, the semiconductor device and the manufacturing method thereof provided by the present application provide a substrate, which comprises at least a high-voltage device region and a medium-voltage device region, a plurality of isolation structures, two drift regions and a body region surrounding the two drift regions are formed in the substrate in the high-voltage device region and the medium-voltage device region respectively, and the region between the two drift regions is used as a gate region for forming a gate; a high-voltage gate oxide layer is formed on the substrate in the gate region of the high-voltage device region; a medium-voltage gate oxide material layer is formed on the substrate, the medium-voltage gate oxide material layer in the gate region of the medium-voltage device region is reserved as a medium-voltage gate oxide layer, and the medium-voltage gate oxide material layer in the remaining region is removed, while a groove is formed in the isolation structure on both sides of the gate region of the high-voltage device region; a gate material layer is formed, which fills the groove and covers the high-voltage gate oxide layer, the medium-voltage gate oxide layer, the substrate and the isolation structure; and the gate material layer is patterned to form a gate on the high-voltage gate oxide layer and the medium-voltage gate oxide layer and a field plate in the groove on both sides of the gate of the high-voltage device region. In the present application, the medium-voltage gate oxide layer is formed in the medium-voltage device region, and at the same time, the groove is formed in the isolation structure on both sides of the gate region of the high-voltage device region. Then, the gate is formed, and at the same time, the field plate is formed in the groove of the high-voltage device region. Only the mask for forming the medium-voltage gate oxide layer and the mask for forming the gate need to be modified, which has little influence on the process, and the process is simple, low in cost, and can optimize the electric field of the drift region, improve the breakdown voltage and on-resistance of the high-voltage device, and optimize the performance of the device.

[0126] In addition, the field plate is formed in the groove, and a space is formed between the gate and the field plate, so that the gate and the field plate can be applied with voltages separately, which makes the working voltage range of the gate larger and the voltage adjustment capacity better.

[0127] In addition, the field plate is also located on the isolation structure where the groove is located, and the gate can be connected with the field plate, so that the mask for forming the gate does not need to be modified, thereby saving cost.

[0128] The above description is only the description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any change and modification made by the person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: providing a substrate, which comprises at least a high-voltage device region and a medium-voltage device region, forming a plurality of isolation structures, two drift regions and a body region surrounding the two drift regions in the substrate at the high-voltage device region and the medium-voltage device region respectively, and a gate region between the two drift regions for forming a gate; forming a high-voltage gate oxide layer on the substrate at the gate region of the high-voltage device region; forming a medium-voltage gate oxide material layer on the substrate, reserving the medium-voltage gate oxide material layer at the gate region of the medium-voltage device region as a medium-voltage gate oxide layer, and removing the medium-voltage gate oxide material layer in the remaining regions while forming a groove in the isolation structure on both sides of the gate region of the high-voltage device region; forming a gate material layer, which fills the groove and covers the high-voltage gate oxide layer, the medium-voltage gate oxide layer, the substrate and the isolation structure; and patterning the gate material layer to form a gate on the high-voltage gate oxide layer and the medium-voltage gate oxide layer and a field plate in the groove on both sides of the gate of the high-voltage device region.

2. The method of manufacturing a semiconductor device according to claim 1, wherein The method for removing the medium-voltage gate oxide material layer in the remaining regions while forming a groove in the isolation structure on both sides of the gate region of the high-voltage device region comprises: forming a first patterned photoresist layer, which exposes the medium-voltage gate oxide material layer of the drift region and the body region of the high-voltage device region and the medium-voltage device region and part of the isolation structure on both sides of the gate region of the high-voltage device region; using the first patterned photoresist layer as a mask, etching the exposed medium-voltage gate oxide material layer and the isolation structure until the medium-voltage gate oxide material layer is removed and the groove is formed in the isolation structure; and removing the first patterned photoresist layer.

3. The method of manufacturing a semiconductor device according to Claim 1, wherein The depth of the groove is 15% to 35% of the depth of the isolation structure where the groove is located, and the width of the groove is 20% to 30% of the width of the isolation structure where the groove is located.

4. The method of manufacturing a semiconductor device according to Claim 3, wherein The depth of the groove is 300 Å to 600 Å, and the width of the groove is 300 nm to 400 nm.

5. The method of fabricating a semiconductor device according to Claim 1, wherein The method for patterning the gate material layer to form a gate on the high-voltage gate oxide layer and the medium-voltage gate oxide layer and a field plate in the groove on both sides of the gate of the high-voltage device region comprises: forming a second patterned photoresist layer, which covers the gate material layer on the high-voltage gate oxide layer and the medium-voltage gate oxide layer and the gate material layer in the groove on both sides of the high-voltage gate oxide layer; using the second patterned photoresist layer as a mask, etching the exposed gate material layer to form the gate and the field plate; and removing the second patterned photoresist layer.

6. The method of fabricating a semiconductor device according to Claim 1, wherein The field plate is also located on the isolation structure where the groove is located.

7. The method of manufacturing a semiconductor device according to claim 6, wherein The gate and the field plate have a spacing therebetween; or the gate and the field plate are connected.

8. A semiconductor device, characterized by comprising: A semiconductor device is manufactured by using a manufacturing method of a semiconductor device as claimed in any one of claims 1 to 7, the semiconductor device comprising: a substrate, the substrate comprising at least a high-voltage device region and a medium-voltage device region, a plurality of isolation structures, two drift regions and a body region surrounding the two drift regions being formed in the substrate of the high-voltage device region and the medium-voltage device region respectively, a region between the two drift regions being a gate region for forming a gate; a recess being formed in the isolation structure on both sides of the gate region of the high-voltage device region; a high-voltage gate oxide layer being located on the substrate of the gate region of the high-voltage device region; a medium-voltage gate oxide layer being located on the substrate of the gate region of the medium-voltage device region; a gate being located on the high-voltage gate oxide layer and the medium-voltage gate oxide layer respectively; and a field plate being located in the recess on both sides of the gate of the high-voltage device region.

9. The semiconductor device of claim 8, wherein, The field plate is also located on the isolation structure where the recess is located.

10. The semiconductor device of claim 9, wherein, The gate and the field plate have a spacing therebetween; or the gate and the field plate are connected. The field plate is also located on the isolation structure where the recess is located. The gate and the field plate have a spacing therebetween; or the gate and the field plate are connected.

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