Semiconductor device

Abstract

The embodiment of the invention relates to a semiconductor device. According to an embodiment, a semiconductor device includes a semiconductor layer and a diode. The semiconductor layer includes an element region in which a semiconductor element is provided, and an outer peripheral region located around the element region along the first surface. The diode is provided on the outer peripheral region with the insulating layer interposed therebetween, and contains polycrystalline silicon. The diode includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type. The first semiconductor region includes a first extending portion extending in a first direction parallel to the first surface, and a plurality of first protruding portions protruding from the first extending portion in a second direction parallel to the first surface and perpendicular to the first direction. The second semiconductor region includes a second extending portion extending in the first direction and a plurality of second protruding portions protruding from the second extending portion in the second direction. The second semiconductor region is in contact with the first semiconductor region. The plurality of first protrusions and the plurality of second protrusions are alternately disposed in the first direction.

Description

[0001] Related Application

[0002] This application claims priority to Japanese Patent Application No. 2024-154011 (Filing date: September 6, 2024). The entire contents of the base application are incorporated herein by reference. TECHNICAL FIELD

[0003] Embodiments of the present application generally relate to semiconductor devices. BACKGROUND

[0004] There is a semiconductor device in which a diode is assembled. For this semiconductor device, there is a demand for a technology capable of miniaturizing the diode. SUMMARY

[0005] According to an embodiment, a semiconductor device includes a semiconductor layer and a diode. The semiconductor layer includes an element region in which a semiconductor element is provided, and an outer peripheral region located around the element region along a first surface. The diode is provided over the outer peripheral region with an insulating layer interposed therebetween, and contains polysilicon. The diode includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type. The first semiconductor region includes a first extension portion extending in a first direction parallel to the first surface, and a plurality of first protruding portions protruding from the first extension portion in a second direction parallel to the first surface and perpendicular to the first direction. The second semiconductor region includes a second extension portion extending in the first direction, and a plurality of second protruding portions protruding from the second extension portion in the second direction. The second semiconductor region is continuous with the first semiconductor region. The plurality of first protruding portions and the plurality of second protruding portions are alternately provided in the first direction.

[0006] According to the present embodiment, it is possible to provide a semiconductor device capable of miniaturizing a diode. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a plan view of a semiconductor device of an embodiment.

[0008] Figure 2 is a plan view of a portion II of Figure 1 is a plan view of a portion II of

[0009] Figure 3 is a III-III cross-sectional view of Figure 2

[0010] Figure 4 (a) is a plan view of a diode of a semiconductor device of a reference example. Figure 4 (b) is a plan view of a diode of a semiconductor device of a reference example. Figure 4 ​(a) is a plan view of a portion of the semiconductor device of

[0011] Figure 5 (a) is a plan view of a diode of the semiconductor device of the embodiment. Figure 5 (b) is a plan view of a diode of the semiconductor device of the embodiment. Figure 5 (a) is a plan view of a portion of the semiconductor device of

[0012] Figure 6 (a) is a plan view of a diode of the semiconductor device of the embodiment.

[0013] Figure 7 (a) is a plan view of a portion of the semiconductor device of the embodiment.

[0014] Figure 8 (a) is a plan view of a diode of the semiconductor device of the embodiment. Figure 8 (b) is a plan view of a diode of the semiconductor device of the embodiment.

[0015] Figure 9 (a) is a plan view of a diode of the semiconductor device of the embodiment.

[0016] Figure 10 (a) is a plan view of a diode of the semiconductor device of the embodiment. Figure 8 (a) is a plan view of a diode of the semiconductor device of the embodiment.

[0017] Figure 11 (a) is a plan view of a diode of the semiconductor device of the embodiment. Figure 10 (a) is a plan view of a diode of the semiconductor device of the embodiment. Figure 11 (a) is a plan view of a diode of the semiconductor device of the embodiment. Figure 10 (a) is a plan view of a diode of the semiconductor device of the embodiment. DETAILED DESCRIPTION

[0018] Hereinafter, each embodiment of the present application will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and the width of each portion, the ratio of the size between portions, and the like, are not necessarily the same as that of an actual one. Furthermore, even if the same portion is shown in different drawings, the size, the ratio, and the like, of the portion may differ from drawing to drawing. In the present application, the same portions will be given the same reference numerals, and overlapping description will be appropriately omitted.

[0019] Figure 1 (a) is a plan view of a diode of the semiconductor device of the embodiment. Figure 1 As shown in (a), the semiconductor device 1 of the embodiment includes a semiconductor layer 100 and a diode 200.

[0020] In the description of the embodiments, an XYZ orthogonal coordinate system is used. Two directions parallel to the surface of the semiconductor layer 100 and orthogonal to each other are set as the X direction (an example of the first direction) and the Y direction (an example of the second direction). The direction perpendicular to the X direction and the Y direction is set as the Z direction. In addition, for the sake of description, the direction from one surface of the semiconductor layer 100 toward the other surface is referred to as "up", and the opposite direction thereof is referred to as "down". These directions are independent of the direction of gravity.

[0021] The semiconductor layer 100 includes an element region R1 and a peripheral region R2. In the drawings, the element region R1 and the peripheral region R2 are indicated by double-dot chain lines. A semiconductor element is provided in the element region R1. The semiconductor element is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), an Insulated Gate Bipolar Transistor (IGBT), or the like. The semiconductor element can be a vertical type element in which an electrode is provided on each of the upper surface and the lower surface of the semiconductor layer. Alternatively, the semiconductor element can be a horizontal type element in which an electrode is provided only on the upper surface of the semiconductor layer.

[0022] In the illustrated example, the element region R1 includes a vertical type MOSFET or IGBT. An upper electrode 101 (first electrode) that is electrically connected to the semiconductor element is provided above the element region R1. A not-illustrated lower electrode that is electrically connected to the semiconductor element is provided below the element region R1.

[0023] The peripheral region R2 is located around the element region R1 on an X-Y plane (first plane). A diode 200 is provided above the peripheral region R2. The diode 200 can be electrically connected to the semiconductor element or can be electrically separated from the semiconductor element.

[0024] Figure 2 is a plan view that enlarges a portion II of Figure 1 Figure 3 is a III-III cross-sectional view of Figure 2

[0025] As shown in Figure 2 , the diode 200 includes a first semiconductor region 210 and a second semiconductor region 220. The first semiconductor region 210 has one of an n-type and a p-type conduction type. The second semiconductor region 220 has the other of the n-type and the p-type conduction type. In the illustrated example, the conduction type of the first semiconductor region 210 is the n-type (an example of the first conduction type), and the conduction type of the second semiconductor region 220 is the p-type (an example of the second conduction type).

[0026] ​​The first semiconductor region 210 and the second semiconductor region 220 are in contact with each other, and a pn junction is formed between the first semiconductor region 210 and the second semiconductor region 220. As Figure 3 indicated, the first semiconductor region 210 and the second semiconductor region 220 are provided on the semiconductor layer 100 via the insulating layer 105. In addition, a lower electrode 102 (second electrode) that is electrically connected to the semiconductor element of the element region R1 is provided below the semiconductor layer 100. As Figure 3 indicated, the lower electrode 102 can be provided not only in the region below the element region R1 but also in the region below the outer peripheral region R2.

[0027] As Figure 2 indicated, the first semiconductor region 210 includes a first extension 211 and a plurality of first protrusions 212. In Figure 2 , the first extension 211 and the first protrusions 212 are indicated by double-dot chain lines. The first extension 211 extends in the X direction. That is, the length of the first extension 211 in the X direction is longer than the length of the first extension 211 in the Y direction. The plurality of first protrusions 212 are separated from each other in the X direction. Each of the first protrusions 212 protrudes from the first extension 211 in the Y direction.

[0028] The second semiconductor region 220 includes a second extension 221 and a plurality of second protrusions 222. In the drawings, the second extension 221 and the second protrusions 222 are indicated by double-dot chain lines. The second extension 221 extends in the X direction. The plurality of second protrusions 222 are separated from each other in the X direction. Each of the second protrusions 222 protrudes from the second extension 221 in the Y direction. The plurality of first protrusions 212 and the plurality of second protrusions 222 are alternately arranged in the X direction.

[0029] As Figure 2 and Figure 3 indicated, the first semiconductor region 210 and the second semiconductor region 220 can be alternately provided in the Y direction. In this case, the first semiconductor region 210 includes a plurality of first protrusions 212a protruding to one side in the Y direction and a plurality of first protrusions 212b protruding to the other side in the Y direction. The first extension 211 is located between the plurality of first protrusions 212a and the plurality of first protrusions 212b.

[0030] Similarly, the second semiconductor region 220 includes a plurality of second protrusions 222a protruding to one side in the Y direction and a plurality of second protrusions 222b protruding to the other side in the Y direction. The second extension 221 is located between the plurality of second protrusions 222a and the plurality of second protrusions 222b.

[0031] The X-direction positions of each first protrusion 212a and each first protrusion 212b differ in the X-direction. When viewed from the Y-direction, the plurality of first protrusions 212a and 212b are arranged alternately in the X-direction. Similarly, the X-direction positions of each second protrusion 222a and 222b differ in the X-direction. When viewed from the Y-direction, the plurality of second protrusions 222a and 222b are arranged alternately in the X-direction.

[0032] Semiconductor layer 100 includes semiconductor materials such as silicon, silicon carbide, or gallium nitride. Upper electrode 101 includes metal materials such as aluminum, titanium, or tungsten. Insulating layer 105 includes insulating materials such as silicon oxide or silicon nitride. First semiconductor region 210 and second semiconductor region 220 include polycrystalline silicon. n-type impurities are made of arsenic, phosphorus, or antimony. P-type impurities are made of boron or aluminum. First semiconductor region 210 and second semiconductor region 220 can be formed by ion implanting n-type and p-type impurities into the polycrystalline silicon layer, respectively.

[0033] The n-type impurity concentration in the first semiconductor region 210 can be the same as or different from the p-type impurity concentration in the second semiconductor region 220. For example, p-type impurities are ion-implanted into the entire surface of the region forming the diode 200, and then n-type impurities are ion-implanted into a portion of the region. In this case, the n-type impurity concentration in the first semiconductor region 210 is higher than the p-type impurity concentration in the second semiconductor region 220. For example, the n-type impurity concentration in the first semiconductor region 210 is 6.0 × 10⁻⁶. 14 cm -3 Above and 3.0×10 16 cm -3 The p-type impurity concentration in the second semiconductor region 220 is 1.0 × 10⁻⁶. 14 cm -3 Above and 7.0×10 15 cm -3 the following.

[0034] The advantages of the implementation method will be explained.

[0035] Diodes are sometimes assembled in semiconductor devices. For example, Figure 1 As shown, a semiconductor device such as a MOSFET or IGBT is placed in the component region R1, and a diode 200 is placed on the outer peripheral region R2. In this case, the outer peripheral region R2 is an ineffective region that does not directly contribute to the operation of the semiconductor device. For the miniaturization of the semiconductor device, it is preferable that the ineffective region be small. To reduce the ineffective region, it is preferable that the diode 200 be small.

[0036] Figure 4(a) is a plan view of a diode of a semiconductor device of the reference example. Figure 4 (b) is a graph schematically showing Figure 4 (a) of the electric field intensity at the B-B line.

[0037] In Figure 4 In the diode 200r shown in (a), the first semiconductor region 210r and the second semiconductor region 220r extend in the X direction. The first semiconductor region 210r and the second semiconductor region 220r do not include a portion protruding in the Y direction. The pn junction between the first semiconductor region 210r and the second semiconductor region 220r is parallel to the X direction.

[0038] When a reverse voltage is applied to the diode 200r, a depletion layer spreads from the pn junction between the first semiconductor region 210r and the second semiconductor region 220r in the Y direction. The electric field intensity at this time is as shown in Figure 4 (b). In Figure 4 (b), the horizontal axis represents the position P in the Y direction, and the vertical axis represents the electric field intensity E. In the diode 200r of the reference example, the electric field intensity E decreases as it moves away from the pn junction.

[0039] Figure 5 (a) is a plan view of a diode of a semiconductor device of the reference example. Figure 5 (b) is a graph schematically showing Figure 5 (a) of the electric field intensity at the B-B line.

[0040] In the present embodiment, the first semiconductor region 210 includes a plurality of first protrusions 212, and the second semiconductor region 220 includes a plurality of second protrusions 222. The plurality of first protrusions 212 and the plurality of second protrusions 222 are alternately arranged in the X direction. The diode 200 includes a pn junction J1 between the first extension 211 and the second protrusion 222, a pn junction J2 between the first protrusion 212 and the second extension 221, and a pn junction J3 between the first protrusion 212 and the second protrusion 222.

[0041] When a reverse voltage is applied to the diode 200, a depletion layer spreads from the pn junctions J1 and J2 in the Y direction, and a depletion layer spreads from the pn junction J3 in the X direction. The electric field intensity at this time is as shown in Figure 5 (b). In Figure 5 (b), the horizontal axis represents the position P in the Y direction, and the vertical axis represents the electric field intensity E. According to the diode 200, the electric field intensity of the first protrusion 212 can be made substantially constant in the Y direction by the spreading of the depletion layer in the X direction from the pn junction J3.

[0042] The withstand voltage is represented by a value obtained by integrating the electric field intensity E at a position P. According to the semiconductor device of the reference example, the electric field intensity E of the diode decreases as it moves away from the pn junction. In contrast, according to the semiconductor device of the embodiment, the electric field intensity of the first protruding portion 212 and the electric field intensity of the second protruding portion 222 are substantially fixed in the Y direction. The withstand voltage of the diode 200 can be increased in correspondence with the increased amount of these electric field intensities.

[0043] In the case where the areas of the diodes are the same, according to the embodiment, the withstand voltage of the diode can be further increased compared with the reference example. Alternatively, according to the embodiment, the area of the diode required to obtain a certain withstand voltage can be reduced compared with the reference example. As a result, the ineffective area in the semiconductor device 1 can be reduced, and the semiconductor device 1 can be downsized.

[0044] Figure 6 is a plan view showing the diode of the semiconductor device of the embodiment.

[0045] Reference Figure 6 A preferred structure of the embodiment will be described. For example, the ratio (L2y / L3y) of the length L2y of one first protruding portion 212 in the Y direction with respect to the sum L3y of the length Lly of the first extending portion 211 in the Y direction and the length L2y is 0.1 or more and 0.9 or less. The larger the ratio (L2y / L3y) is, the more the proportion of the portion with high electric field intensity can be increased, and the more the withstand voltage of the diode 200 can be increased. Therefore, the ratio (L2y / L3y) is preferably 0.2 or more, and more preferably 0.3 or more. On the other hand, if the ratio (L2y / L3y) is too large, the forward voltage Vf becomes large. Therefore, the ratio (L2y / L3y) is preferably 0.8 or less, and more preferably 0.7 or less.

[0046] Similarly, the ratio (L5y / L6y) of the length L5y of one second protruding portion 222 in the Y direction with respect to the sum L6y of the length L4y of the second extending portion 221 in the Y direction and the length L5y is, for example, 0.1 or more and 0.9 or less. From the viewpoint of increasing the withstand voltage, the ratio (L5y / L6y) is preferably 0.2 or more, and more preferably 0.3 or more. In order to suppress an increase in the forward voltage Vf, the ratio (L5y / L6y) is preferably 0.8 or less, and more preferably 0.7 or less.

[0047] Specifically, the length L2y and the length L5y are designed to be 0.2 μm or more. From the viewpoint of increasing the withstand voltage, the length L2y and the length L5y are preferably 0.5 μm or more, and more preferably 1.0 μm or more.

[0048] The ratio (L5x / L2x) of the length L5x of the second protrusion 222 in the X direction to the length L2x of the first protrusion 212 in the X direction is 0.1 or more and 10 or less. It is preferable that the effective n-type impurity concentration in the first semiconductor region 210 be small in comparison with the effective p-type impurity concentration in the second semiconductor region 220, and more preferable that they be substantially the same. The "effective impurity concentration" refers to the compensated impurity concentration in the case where both n-type impurities and p-type impurities are included in a region. In the case where only one of n-type impurities or p-type impurities is included in a region, the n-type impurity concentration or the p-type impurity concentration can be regarded as the effective impurity concentration. In the case where the effective n-type impurity concentration in the first semiconductor region 210 is small in comparison with the effective p-type impurity concentration in the second semiconductor region 220, it is more preferable that the ratio (L5x / L2x) be closer to 1. Therefore, the ratio (L5x / L2x) is preferably 0.2 or more and 9 or less, and more preferably 0.3 or more and 8 or less.

[0049] The ratio (L2y / L2x) of the length L2y of the first protrusion 212 in the Y direction to the length L2x of the first protrusion 212 in the X direction is, for example, 0.1 or more and 10 or less. The shorter the length L2x, the more the number of the first protrusions 212 per unit area can be increased, and the withstand voltage of the diode 200 can be improved. In addition, the longer the length L2y, the more the proportion of the portion where the electric field is high can be increased, and the withstand voltage of the diode 200 can be improved. Therefore, the ratio (L2y / L2x) is preferably 0.2 or more, and more preferably 0.3 or more. On the other hand, if the ratio (L2y / L2x) is too large, the forward voltage Vf becomes large. Therefore, the ratio (L2y / L2x) is preferably 9 or less, and more preferably 8 or less.

[0050] Similarly, the ratio (L5y / L5x) of the length L5y of the second protrusion 222 in the Y direction to the length L5x of the second protrusion 222 in the X direction is, for example, 0.1 or more and 10 or less. From the viewpoint of improving the withstand voltage, the ratio (L5y / L5x) is preferably 0.2 or more, and more preferably 0.3 or more. In addition, in order to suppress an increase in the forward voltage Vf, the ratio (L5y / L5x) is preferably 9 or less, and more preferably 8 or less.

[0051] The embodiment of the present application is particularly suitable for a semiconductor device 1 using a semiconductor layer 100 of silicon carbide. The semiconductor layer 100 of silicon carbide is very high in cost in comparison with silicon and gallium nitride. According to the embodiment, the diode 200 can be miniaturized, and the outer peripheral region R2 can be reduced. By reducing the outer peripheral region R2, the semiconductor layer 100 can be reduced, and as a result, the cost of the semiconductor device 1 can be reduced.

[0052] (Modified Example)

[0053] Figure 7 This is a top view showing a portion of a semiconductor device representing a variation of the implementation.

[0054] exist Figure 2 as well as Figure 6 In the example shown, the position of the first protrusion 212a in the X direction is different from the position of the first protrusion 212b in the X direction. Similarly, the position of the second protrusion 222a in the X direction is different from the position of the second protrusion 222b in the X direction. Figure 7 In the example shown, the position of the first protrusion 212a in the X direction is the same as the position of the first protrusion 212b in the X direction. Similarly, the position of the second protrusion 222a in the X direction is the same as the position of the second protrusion 222b in the X direction. Thus, the positional relationship between the first protrusion 212a and the first protrusion 212b, and the positional relationship between the second protrusion 222a and the second protrusion 222b, can be appropriately changed.

[0055] (Example)

[0056] Figure 8 (a) is a top view of the semiconductor device of the embodiment. Figure 8 (b) is a bottom view of the semiconductor device of the embodiment.

[0057] The semiconductor device 2 in this embodiment includes an IGBT 110 as a semiconductor element. For example... Figure 8 As shown in (a), in the element region R1, a plurality of emitter electrodes 111 are disposed on the upper surface of the semiconductor layer 100. Figure 8 As shown in (b), a collector electrode 112 is provided on the lower surface of the semiconductor layer 100 in the element region R1 and the outer peripheral region R2.

[0058] A sensing diode 120 is also disposed above the component region R1. The sensing diode 120 is used to measure temperature. The sensing diode 120 is located between the emitter electrodes 111.

[0059] An anode electrode 121, a cathode electrode 122, and a gate pad 123 are disposed on the outer peripheral region R2. The anode electrode 121, the cathode electrode 122, and the gate pad 123 are separated from each other.

[0060] The anode electrode 121 is electrically connected to the anode side of the sensing diode 120, and the cathode electrode 122 is electrically connected to the cathode side of the sensing diode 120. Additionally, in the semiconductor device 2, the diode 200 is disposed at the same location as the cathode electrode 122. The gate pad 123 is electrically connected to the gate electrode of the IGBT 110.

[0061] Figure 9This is a circuit diagram of the semiconductor device in an embodiment.

[0062] like Figure 9 As shown, in semiconductor device 2, diode 200 is connected between the emitter electrode 111 of IGBT 110 and the cathode side of detection diode 120. Diode 200 functions as a Zener diode.

[0063] Figure 10 yes Figure 8 (a) is an enlarged plan view of the cathode electrode.

[0064] like Figure 10 As shown, the first semiconductor region 210 and the second semiconductor region 220 are disposed along the outer periphery of the cathode electrode 122. The first semiconductor region 210 and the second semiconductor region 220 are arranged alternately in a direction away from the cathode electrode 122. By disposing the first semiconductor region 210 and the second semiconductor region 220 around the cathode electrode 122, the area of ​​the pn junction between the first semiconductor region 210 and the second semiconductor region 220 can be increased. An electrode layer 230 electrically connected to the emitter electrode 111 is disposed on the outer periphery of the plurality of first semiconductor regions 210 and the plurality of second semiconductor regions 220.

[0065] Figure 11 (a) is to Figure 10 A partial XA enlarged top view. Figure 11 (b) is to Figure 10 A partial XB enlarged top view.

[0066] In some XA, such as Figure 11 As shown in (a), the first extension 211 and the second extension 221 extend in the X direction. The first protrusion 212 protrudes from the first extension 211 in the Y direction, and the second protrusion 222 protrudes from the second extension 221 in the Y direction.

[0067] In some XBs, such as Figure 11 As shown in (b), the first extension 211 and the second extension 221 extend in the Y direction. The first protrusion 212 protrudes from the first extension 211 in the X direction, and the second protrusion 222 protrudes from the second extension 221 in the X direction.

[0068] like Figure 11 (a) and Figure 11 As shown in (b), both the first semiconductor region 210 and the second semiconductor region 220 include, at any location, an extension portion extending in one direction and a protruding portion protruding from the extension portion in an orthogonal direction. This improves the voltage withstand capability of the diode 200. Alternatively, it allows for a reduction in the area of ​​the diode 200 while maintaining its voltage withstand capability. In embodiments, it is also possible to apply...Figure 7 The modified example shown is constructed to replace Figure 10 (a) and Figure 10 The construction shown in (b) is as follows.

[0069] The above embodiments of the present invention have been illustrated, but these embodiments are merely examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents. Furthermore, the above-described embodiments can be combined with each other for implementation.

Claims

1. A semiconductor device, characterized by comprising: Possessing: a semiconductor layer including an element region in which a semiconductor element is provided, and a peripheral region located around the element region along a first surface; and a diode provided over the peripheral region through an insulating layer, containing polysilicon, the diode including: a first semiconductor region of a first conductivity type including a first extension portion extending in a first direction parallel to the first surface, and a plurality of first protruding portions protruding from the first extension portion in a second direction parallel to the first surface and perpendicular to the first direction; and a second semiconductor region of a second conductivity type including a second extension portion extending in the first direction, and a plurality of second protruding portions protruding from the second extension portion in the second direction, the second semiconductor region being continuous with the first semiconductor region, the plurality of first protruding portions and the plurality of second protruding portions being alternately provided in the first direction.

2. The semiconductor device according to claim 1, wherein the first semiconductor region and the second semiconductor region are alternately provided in the second direction.

3. The semiconductor device according to claim 1, wherein a ratio of a length of the second direction of one of the plurality of first protruding portions with respect to a sum of the length of the second direction of the first extension portion and the length of the second direction of the one of the plurality of first protruding portions is 0.1 or more and 0.9 or less.

4. The semiconductor device according to claim 3, wherein the ratio is 0.3 or more and 0.7 or less.

5. The semiconductor device according to claim 1, wherein a ratio of a length of the first direction of one of the plurality of second protruding portions with respect to a length of the first direction of one of the plurality of first protruding portions is 0.1 or more and 10 or less.

6. The semiconductor device according to claim 5, wherein the ratio is 0.3 or more and 8 or less.

7. The semiconductor device according to claim 1, wherein a ratio of a length of the second direction of one of the plurality of first protruding portions with respect to a length of the first direction of the one of the plurality of first protruding portions is 0.1 or more and 10 or less.

8. The semiconductor device according to claim 7, wherein the ratio is 0.3 or more and 8 or less.

9. The semiconductor device according to claim 1, wherein a length of the second direction of one of the plurality of first protruding portions and a length of the second direction of one of the plurality of second protruding portions are 0.2 μm or more.

10. The semiconductor device according to claim 1, wherein a length of the second direction of one of the plurality of first protruding portions and a length of the second direction of one of the plurality of second protruding portions are 1.0 μm or more.

11. The semiconductor device according to claim 1, wherein the first semiconductor region includes a further plurality of first protruding portions protruding from the first extension portion in the second direction, the first extension portion is located between the plurality of first protruding portions and the further plurality of first protruding portions, the second semiconductor region includes a further plurality of second protruding portions protruding from the second extension portion in the second direction, the second extension portion is located between the plurality of second protruding portions and the further plurality of second protruding portions.

12. The semiconductor device according to claim 1, wherein the semiconductor element includes a MOSFET or an IGBT.

13. The semiconductor device according to claim 12, wherein an electrode is further provided above the outer peripheral region across the insulating layer, the diode is electrically connected between the semiconductor element and the electrode.

14. The semiconductor device according to claim 13, wherein the first semiconductor region and the second semiconductor region are provided around the electrode along a first surface perpendicular to the first direction.

15. The semiconductor device according to claim 14, wherein the first semiconductor region and the second semiconductor region are alternately provided in a direction away from the electrode.

16. The semiconductor device according to claim 1, wherein a first electrode is further provided above the element region.

17. The semiconductor device according to claim 16, wherein a second electrode is further provided below the element region.

18. The semiconductor device according to claim 17, wherein the second electrode is further provided below the outer peripheral region.

19. The semiconductor device according to claim 1, wherein The impurity concentration of the first conductivity type in the first semiconductor region is 6.0 × 10⁻⁶. 14 cm -3 Above and 3.0×10 16 cm -3 the following, The impurity concentration of the second conductivity type in the second semiconductor region is 1.0 x 10 14 cm -3 or more and 7.0 x 10 15 cm -3 or less.

20. The semiconductor device according to claim 1, wherein the semiconductor layer contains silicon carbide.

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