Semiconductor device

Abstract

A semiconductor device includes: a substrate; a bidirectional transistor, and a plurality of diode elements electrically connected to the bidirectional transistor, the bidirectional transistor includes a main channel layer, a main barrier layer, first and second gate electrodes, a first gate semiconductor layer between the main barrier layer and the first gate electrode, a second gate semiconductor layer between the main barrier layer and the second gate electrode, a first electrode between the first gate electrode and the second gate electrode, and a second electrode between the first gate electrode and the second gate electrode. A second electrode on one side of the first gate electrode; and a third electrode on one side of the second gate electrode, the plurality of diode elements electrically connecting the substrate and the first electrode, the substrate and the second electrode, and the substrate and the third electrode, respectively.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0122691, filed on September 9, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The disclosure relates to a semiconductor device. BACKGROUND

[0003] Generally, semiconductor devices are closely related to our daily life. In particular, power semiconductor devices are becoming increasingly important in various fields such as the transportation field (e.g., electric vehicles, trains, and electric rail cars), renewable energy systems (e.g., solar power generation and wind power generation), and mobile devices. Power semiconductor devices are semiconductor devices that can be used to handle high voltages or high currents, and perform functions such as power conversion and control in high-power systems and high-power electronic devices. Power semiconductor devices have the ability to handle high power and durability, allowing them to handle large amounts of current and withstand high voltages. For example, power semiconductor devices can handle voltages of several hundred to several thousand volts and currents of several tens to several thousand amperes. Power semiconductor devices can improve the efficiency of electric power by minimizing power loss. In addition, power semiconductor devices can be stably driven in environments such as high temperatures.

[0004] These power semiconductor devices can be classified by their materials, such as SiC power semiconductor devices and GaN power semiconductor devices. Instead of a conventional silicon (Si) wafer, SiC or GaN can be used to manufacture power semiconductor devices, thereby compensating for the disadvantages of silicon, which has unstable characteristics at high temperatures. SiC power semiconductor devices are resistant to high temperatures and have low power loss, making them suitable for electric vehicles, renewable energy systems, etc. GaN power semiconductor devices require high costs but are efficient in terms of speed, making them suitable for fast charging of mobile devices, etc. SUMMARY

[0005] In general, in some aspects, the disclosure is directed to a semiconductor device having stable electrical characteristics and improved reliability.

[0006] According to some embodiments, the present disclosure is directed to a semiconductor device including a substrate, a bidirectional transistor positioned on the substrate, and a plurality of diode elements electrically connected to the bidirectional transistor, and the bidirectional transistor includes a main channel layer positioned on the substrate, a main barrier layer positioned on the main channel layer and including a material having a band gap different from a band gap of the main channel layer, a first gate electrode and a second gate electrode positioned on the main barrier layer so as to be spaced apart from each other, a first gate semiconductor layer positioned between the main barrier layer and the first gate electrode, a second gate semiconductor layer positioned between the main barrier layer and the second gate electrode, a first electrode positioned between the first gate electrode and the second gate electrode and electrically connected to the main channel layer, a second electrode positioned on a side of the first gate electrode and positioned apart from the first electrode, and a third electrode positioned on a side of the second gate electrode and positioned apart from the first electrode, and the plurality of diode elements are respectively electrically connected to the substrate and the first electrode, the substrate and the second electrode, and the substrate and the third electrode.

[0007] According to some embodiments, the present disclosure is directed to a semiconductor device including a substrate, a bidirectional transistor positioned on the substrate, and a first diode element electrically connected to the bidirectional transistor, and the bidirectional transistor includes a main channel layer positioned on the substrate, a main barrier layer positioned on the main channel layer and including a material having a band gap different from a band gap of the main channel layer, a first gate electrode and a second gate electrode positioned on the main barrier layer so as to be spaced apart from each other, a first gate semiconductor layer positioned between the main barrier layer and the first gate electrode, a second gate semiconductor layer positioned between the main barrier layer and the second gate electrode, a first electrode positioned between the first gate electrode and the second gate electrode and electrically connected to the main channel layer, a second electrode positioned on a side of the first gate electrode and positioned apart from the first electrode, and a third electrode positioned on a side of the second gate electrode and positioned apart from the first electrode, and the first diode element includes a sub-channel layer positioned on the substrate, a sub-barrier layer positioned on the sub-channel layer and including a material having a band gap different from a band gap of the sub-channel layer, a sub-gate electrode positioned on the sub-barrier layer, a sub-gate semiconductor layer positioned between the sub-barrier layer and the sub-gate electrode, and a sub-source electrode and a sub-drain electrode positioned on opposite sides of the sub-gate electrode and connected to the sub-channel layer, and the sub-source electrode is connected to the sub-gate electrode and integrally formed with the first electrode.

[0008] According to some embodiments, the present disclosure is directed to a semiconductor device including: a substrate; a main channel layer positioned on the substrate; a main barrier layer positioned on the main channel layer and including a material having a different energy band gap than an energy band gap of the main channel layer; first to third gate electrodes positioned on the main barrier layer and arranged apart from each other; a protective layer positioned on the main barrier layer and covering the first to third gate electrodes; first and second electrodes, the second electrode passing through the protective layer and the main barrier layer, positioned on the main channel layer and positioned on opposite sides of the first gate electrode; third and fourth electrodes, the fourth electrode passing through the protective layer and the main barrier layer, positioned on the main channel layer and positioned on opposite sides of the third gate electrode; and a connection electrode positioned on the protective layer and connecting the second and fourth electrodes, and the second gate electrode is positioned between the second and third electrodes. BRIEF DESCRIPTION OF DRAWINGS

[0009] Example embodiments will become more fully understood from the detailed description and accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating an example of an electronic system including a semiconductor device according to some embodiments.

[0011] Figure 2 and Figure 3 is a circuit diagram illustrating an example of a semiconductor device according to some embodiments.

[0012] Figure 4 and Figure 5 is a plan view illustrating an example of a semiconductor device according to some embodiments.

[0013] Figure 6 and Figure 7 is a cross-sectional view taken along line A-A' of Figure 5 according to some embodiments.

[0014] Figure 8 is a cross-sectional view taken along line B-B' of Figure 5 according to some embodiments.

[0015] Figure 9 is a cross-sectional view taken along line C-C' of Figure 5 according to some embodiments.

[0016] Figure 10 is a cross-sectional view taken along line D-D' of Figure 5 according to some embodiments.

[0017] Figure 11 is a block diagram illustrating an example of a semiconductor device according to some embodiments and corresponds to Figure 5a cross-sectional view of line A-A' of FIG. 1.

[0018] Figure 12 is a plan view showing an example of a semiconductor device according to some embodiments and corresponds to Figure 5 a cross-sectional view of line B-B' of FIG. 1.

[0019] Figure 13 is a plan view showing an example of a semiconductor device according to some embodiments.

[0020] Figure 14 is a cross-sectional view taken along line E-E' of FIG. 1 according to some embodiments. Figure 13

[0021] Figure 15 is a plan view showing an example of a semiconductor device according to some embodiments and corresponds to Figure 13 a cross-sectional view of line E-E' of FIG. 1.

[0022] Figure 16 is a circuit diagram showing an example of a semiconductor device according to some embodiments.

[0023] Figure 17 is a plan view showing an example of a semiconductor device according to some embodiments with reference to Figure 16

[0024] Figure 18 is a circuit diagram showing an example of a semiconductor device according to some embodiments.

[0025] Figure 19 is a plan view showing an example of a semiconductor device according to some embodiments with reference to Figure 18 DETAILED DESCRIPTION

[0026] Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings.

[0027] The accompanying drawings and description are to be regarded as being in essence illustrative rather than restrictive. Throughout the specification, like reference numerals denote like elements.

[0028] Furthermore, the dimensions and thicknesses of the configurations shown in the drawings can be arbitrarily shown for the understanding and easy description, but the present disclosure is not necessarily limited thereto. In the drawings, the thicknesses of layers, films, panels, regions, and the like can be exaggerated for the sake of clarity. In addition, in the drawings, the thicknesses of some layers and regions can be exaggerated for the understanding and ease of description.

[0029] ​​​Additionally, it will be understood that when an element (such as a layer, film, region, or substrate) is referred to as being "on" another element, the element may be directly on that other element, or there may be intermediate elements present. Furthermore, when an element is referred to as being "directly on" another element, there are no intermediate elements present. Additionally, when an element is referred to as being "on" a reference portion, the element is located above or below the reference portion, and it does not necessarily mean that the element is located "above" or "on" in a direction opposite to gravity.

[0030] Furthermore, in this disclosure, unless explicitly stated otherwise, the words “comprising” and variations (such as, including) will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements.

[0031] Additionally, in this disclosure, when referring to "on a plane," it means viewing the target portion from above, while when referring to "on a cross section," it means viewing the cross section obtained by vertically cutting the target portion from the side.

[0032] Figure 1 This is a block diagram illustrating an example of an electronic system including a semiconductor device according to some embodiments. Figure 1 In this process, the electronic system may include an IC chip 20, a charger 40 electrically connected to the IC chip 20, a first terminal D1 to a third terminal D3, and a semiconductor device 10 electrically connected to the IC chip 20 and a second terminal D2, and electrically connected to the IC chip 20 and the third terminal D3.

[0033] IC chip 20 can be electrically connected to charger 40. IC chip 20 can be electrically connected via first terminal D1 to a bidirectional transistor ( Figure 2 Semiconductor device 10 (referred to as "100" in the accompanying drawings).

[0034] IC chip 20 is operable to charge or discharge charger 40. For example, IC chip 20 can receive power from charger 40. IC chip 20 can receive from charger 40 the voltage and / or current required to charge devices (or external devices) 31 and 32 connected to the second terminal D2 and / or the third terminal D3. Furthermore, IC chip 20 can transfer the power received through the second terminal D2 and / or the third terminal D3 to charger 40. Additionally, IC chip 20 is operable to charge or discharge external devices 31 and 32 connected to the second terminal D2 and / or the third terminal D3. For example, IC chip 20 can apply power received from charger 40 to the second terminal D2 and / or the third terminal D3. Furthermore, IC chip 20 can receive power from devices 31 and 32 connected to the second terminal D2 and / or the third terminal D3. IC chip 20 can transfer the power received from devices 31 and 32 connected to the second terminal D2 and / or the third terminal D3 to the second terminal D2, the third terminal D3, and / or the charger 40. IC chip 20 can apply signals to semiconductor device 10 for charging or discharging external devices 31 and 32 connected to the second terminal D2 and / or the third terminal D3 (e.g., the first gate electrode 151 and the second gate electrode 152 (see...)). Figure 4 (such as the conduction signal).

[0035] Charger 40 is electrically connected to IC chip 20. Charger 40 can supply power to IC chip 20. For example, charger 40 can supply IC chip 20 with the power required to charge devices 31, 32 connected to the second terminal D2 and / or the third terminal D3. Furthermore, charger 40 can receive power through IC chip 20. For example, charger 40 can receive power from devices 31 and 32 connected to the second terminal D2 and / or the third terminal D3 through IC chip 20.

[0036] Semiconductor device 10 can be electrically connected to IC chip 20. Semiconductor device 10 can be electrically connected to IC chip 20 via first terminal D1. In addition, semiconductor device 10 can be electrically connected to external devices 31 and 32 via second terminal D2 and third terminal D3.

[0037] In some embodiments, the semiconductor device 10 may include a bidirectional normally-off high electron mobility transistor (HEMT). For example, the semiconductor device 10 may output power applied from the charger 40 via the IC chip 20 and the first terminal D1 to the second terminal D2 and / or the third terminal D3, or it may output power applied from the second terminal D2 to the third terminal D3 and / or the first terminal D1, or it may output power applied from the third terminal D3 to the first terminal D1 and / or the second terminal D2. Therefore, external devices 31 and 32 electrically connected to the second terminal D2 and the third terminal D3 may be charged or discharged by the semiconductor device 10. However, this disclosure is not limited thereto, and the semiconductor device 10 may also be a bidirectional normally-on high electron mobility transistor.

[0038] External devices 31 and 32 can be electrically connected to the second terminal D2 and the third terminal D3. The second terminal D2 and the third terminal D3 can be terminals to which external devices 31 and 32 are connected. External devices 31 and 32 can be electrically connected to the second terminal D2 and the third terminal D3, and charge or discharge according to signals applied to the IC chip 20. As an example, the second terminal D2 and the third terminal D3 can be USB power delivery terminals or wireless charging terminals; however, this disclosure is not limited thereto. Here, USB power delivery can refer to a protocol used to supply power to a device having a USB terminal via a USB cable.

[0039] Figure 2 and Figure 3 This is a circuit diagram illustrating an example of a semiconductor device according to some embodiments. Figure 3 The diagram illustrates the current flow when the bidirectional transistor 100 and the plurality of diode elements 510, 520 and 530 are turned on.

[0040] exist Figure 2 and Figure 3 In the semiconductor device 10, a bidirectional transistor 100 and a plurality of diode elements 510, 520 and 530 electrically connected to the bidirectional transistor 100 may be included.

[0041] A bidirectional transistor 100 may include a first terminal D1, a second terminal D2, a third terminal D3, a first gate electrode G1, and a second gate electrode G2. The bidirectional transistor 100 may include a plurality of transistors 100a and 100b, each comprising some of the first terminal D1, second terminal D2, third terminal D3, first gate electrode G1, and second gate electrode G2. For example, the bidirectional transistor 100 may include a first transistor 100a and a second transistor 100b, where the first transistor 100a includes the first terminal D1, the second terminal D2, and the first gate electrode G1, and the second transistor 100b includes the first terminal D1, the third terminal D3, and the second gate electrode G2. The first transistor 100a and the second transistor 100b may share the first terminal D1.

[0042] The first transistor 100a can control the current between the first terminal D1 and the second terminal D2 according to the gate signal applied to the first gate electrode G1. For example, when a conduction signal is applied to the first gate electrode G1 of the first transistor 100a, the current can flow along... Figure 3 The first path C1 is shown. In this case, the current can flow bidirectionally between the first terminal D1 and the second terminal D2 according to the potential difference between the first terminal D1 and the second terminal D2. Furthermore, the second transistor 100b can control the current between the first terminal D1 and the third terminal D3 according to a gate signal applied to the second gate electrode G2. For example, when a conduction signal is applied to the second gate electrode G2 of the second transistor 100b, the current can flow along the path C1 as shown. Figure 3 The second path C2 shown in the diagram flows. In this case, the current can flow bidirectionally between the first terminal D1 and the third terminal D3 based on the potential difference between the first terminal D1 and the third terminal D3. Therefore, the current can flow bidirectionally in the bidirectional transistor 100 based on the potential difference between the first terminal D1 and the third terminal D3.

[0043] In some implementations, the first terminal D1 may refer to Figure 1 The electrical connection is made to the terminals of IC chip 20, and the second terminal D2 and the third terminal D3 can respectively point to... Figure 1 Electrical connection to external devices ( Figure 1 The terminals referred to by reference numerals "31" and "32" in the accompanying drawings. In some embodiments, the first terminal D1 may correspond to... Figure 5 The first electrode ( Figure 5 The reference numeral "191" in the attached figure, and the second terminal D2 may correspond to Figure 5 The second electrode ( Figure 5 The figure reference numeral "192" is used, and the third terminal D3 may correspond to... Figure 5 The third electrode ( Figure 5 (Referring to reference numeral "193" in the attached figure). Furthermore, the first gate electrode G1 may correspond to... Figure 5 The first gate electrode ( Figure 5 The figure reference numeral "151" is used in the attached drawing, and the second gate electrode G2 may correspond to... Figure 5 The second gate electrode ( Figure 5 (See attached figure "152").

[0044] Multiple diode elements 510, 520, and 530 may be electrically connected to the first terminal D1 through the third terminal D3, respectively. For example, the semiconductor device 10 may include a first diode element 510 electrically connected to the first terminal D1, a second diode element 520 electrically connected to the second terminal D2, and a third diode element 530 electrically connected to the third terminal D3.

[0045] The first diode element 510 to the third diode element 530 can be connected to the substrate 110. In other words, the first diode element 510 to the third diode element 530 can electrically connect the first terminal D1 to the third terminal D3 to the substrate 110. The first diode element 510 can electrically connect the first terminal D1 to the substrate 110, the second diode element 520 can electrically connect the second terminal D2 to the substrate 110, and the third diode element 530 can electrically connect the third terminal D3 to the substrate 110.

[0046] Each of the first diode elements 510 to the third diode element 530 may include an anode and a cathode. The anode 511 of the first diode element 510 is electrically connected to the first terminal D1 via a first node N1. The cathode 512 of the first diode element 510 is electrically connected to the substrate 110. The anode 521 of the second diode element 520 is electrically connected to the second terminal D2 via a second node N2. The cathode 522 of the second diode element 520 is electrically connected to the substrate 110. The anode 531 of the third diode element 530 is electrically connected to the third terminal D3 via a third node N3. The cathode 532 of the third diode element 530 is electrically connected to the substrate 110.

[0047] Therefore, when a predetermined voltage is applied to the first terminal D1 to the third terminal D3, the current can flow along the path shown in the figure. Figure 3 The third path C3 to the fifth path C5 shown in the diagram flow. In this case, the magnitude of the current flowing along the third path C3 to the fifth path C5 can be smaller than the magnitude of the current flowing in the first transistor 100a and / or the second transistor 100b, and a voltage with a magnitude smaller than that used for the first terminal D1 to the third terminal D3 can be applied to the substrate 110. Therefore, when the first transistor 100a and / or the second transistor 100b is turned on, a relatively small current can flow in the first diode element 510 to the third diode element 530, and a relatively small voltage can be maintained on the substrate 110. Therefore, the potential difference between the substrate 110 and the first terminal D1 to the third terminal D3 can be stably maintained, and the reliability of the bidirectional transistor 100 included in the semiconductor device 10 and operating bidirectionally can be improved.

[0048] Figure 4 This is a plan view illustrating examples of semiconductor devices according to some embodiments. Figure 4 In the semiconductor device 10, a main component region MA and a peripheral circuit region PA may be included. The main component region MA includes a bidirectional transistor 100, and the peripheral circuit region PA includes a plurality of diode elements 510, 520 and 530.

[0049] The bidirectional transistor 100 may be located in the main element region MA. For example, the bidirectional transistor 100 of the semiconductor device 10 may be a normally-off high electron mobility transistor (HEMT). However, this disclosure is not limited thereto, and the bidirectional transistor 100 of the semiconductor device 10 may be a normally-on high electron mobility transistor. In some embodiments, the main element region MA may refer to the region where the bidirectional transistor 100 is disposed.

[0050] In the main component region MA, multiple electrodes 191, 192, and 193 may be arranged spaced apart from each other. For example, the first electrode 191 to the third electrode 193 may extend in the second direction (Y direction) and be spaced apart from each other in the first direction (X direction). The first electrode 191 to the third electrode 193 may be arranged in the first direction (X direction). Additionally, in the main component region MA, multiple gate electrodes 151 and 152 may be arranged spaced apart from each other. For example, the first gate electrode 151 and the second gate electrode 152 may extend in the second direction (Y direction) and be spaced apart from each other in the first direction (X direction). The first gate electrode 151 and the second gate electrode 152 may be repeatedly arranged in the first direction (X direction).

[0051] The first electrode 191 and the second electrode 192 may be positioned on opposite sides of the first gate electrode 151 (e.g., on both sides of the first gate electrode 151), and the first electrode 191 and the third gate electrode 153 may be positioned on opposite sides of the second gate electrode 152 (e.g., on both sides of the second gate electrode 152). In other words, the first gate electrode 151 may be positioned between the first electrode 191 and the second electrode 192, and the second gate electrode 152 may be positioned between the first electrode 191 and the third electrode 193. In one example, the first element on the first side of the second element may indicate that the first element is located on the first side of the second element when in contact with the second element or when not in contact with the second element.

[0052] In some embodiments, among the plurality of electrodes 191, 192, and 193 arranged in the first direction (X direction) and the plurality of gate electrodes 151 and 152 arranged in the first direction (X direction), the first electrode 191, the second electrode 192, the third electrode 193, the first gate electrode 151, and the second gate electrode 152 may constitute a bidirectional transistor 100. In other words, the bidirectional transistor 100 may include three electrodes and two gate electrodes positioned between the electrodes. In some embodiments, the main element region MA may include a plurality of bidirectional transistors 100; however, this disclosure is not limited thereto. The plurality of bidirectional transistors 100 may be arranged in the first direction (X direction).

[0053] The peripheral circuit region PA can be located on one side of the main component region MA. For example, as Figure 4As shown, the peripheral circuit region PA can be located on one side of the main component region MA in the second direction (Y direction); however, this disclosure is not limited thereto.

[0054] The peripheral circuit region PA may include elements electrically connected to the bidirectional transistor 100. For example, a plurality of diode elements 510, 520, and 530 electrically connected to the bidirectional transistor 100 may be positioned in the peripheral circuit region PA. In some embodiments, one terminal of each of the plurality of diode elements 510, 520, and 530 may be electrically connected to the bidirectional transistor 100. The plurality of diode elements 510, 520, and 530 may be arranged in a first direction (X direction). The plurality of diode elements 510, 520, and 530 may be positioned to be spaced apart from each other in the first direction (X direction). In some embodiments, the peripheral circuit region PA may refer to the region in which the plurality of diode elements 510, 520, and 530 are disposed.

[0055] However, this disclosure is not limited thereto, and as another example, passive components (such as capacitors or inductors) or active components (such as integrated circuit (IC) chips) may be further located in the peripheral circuit region PA. As another example, shunts, voltage dividers, voltage limiters, protection elements of the bidirectional transistor 100, etc., may be further located in the peripheral circuit region PA.

[0056] In the following text, reference will be made to Figure 5 to Figure 7 Describes a bidirectional transistor in a semiconductor device.

[0057] Figure 5 This is a plan view illustrating an example of a semiconductor device according to some embodiments. Figure 6 and Figure 7 It is based on some implementation methods along Figure 5 A sectional view taken by line A-A'. Figure 6 This illustrates the state when the semiconductor device is in the off state, and Figure 7 This illustrates the state when the semiconductor device is in the ON (conduction) state. Figure 5 to Figure 7 For ease of explanation, a bidirectional transistor 100 and three diode elements 510, 520 and 530 electrically connected to the bidirectional transistor 100 are shown. In the following text, for ease of explanation, a bidirectional transistor 100 and three diode elements 510, 520 and 530 electrically connected to the bidirectional transistor 100 will be described.

[0058] exist Figure 5In this embodiment, the peripheral circuit region PA of the semiconductor device 10 may be positioned separately from the main component region MA. For example, the peripheral circuit region PA may be positioned separately from the main component region MA in a second direction (Y direction); however, this disclosure is not limited thereto. For example, the peripheral circuit region PA may be positioned separately from the main component region MA in a first direction (X direction), or it may surround the side surface of the main component region MA. Of course, various other modifications are possible. In some embodiments, the separation structure 160 may be positioned between the peripheral circuit region PA and the main component region MA; however, this disclosure is not limited thereto.

[0059] exist Figure 5 and Figure 6 In the semiconductor device 10, the bidirectional transistor 100 may include a main channel layer 132m, a main barrier layer 136m positioned on the main channel layer 132m, a first gate electrode 151 and a second gate electrode 152 positioned on the main barrier layer 136m, a first gate semiconductor layer 181 positioned between the main barrier layer 136m and the first gate electrode 151, a second gate semiconductor layer 182 positioned between the main barrier layer 136m and the second gate electrode 152, and a first electrode 191 to a third electrode 193 spaced apart from each other on the main channel layer 132m.

[0060] The main channel layer 132m can be a layer forming a channel between the first electrode 191 and the second electrode 192, and between the first electrode 191 and the third electrode 193, and a two-dimensional electron gas (2DEG) 134 can be located inside the main channel layer 132m. The two-dimensional electron gas 134 is a charge transfer model used in solid-state physics, and refers to a group of electrons that are tightly confined in two dimensions (e.g., in the XY plane) such that they can migrate freely in those two dimensions but cannot migrate in other dimensions (e.g., in the Z direction). In other words, the two-dimensional electron gas 134 can exist in three-dimensional space as a two-dimensional sheet. Such a two-dimensional electron gas 134 mainly appears in semiconductor heterojunction structures, and in the semiconductor device 10, the two-dimensional electron gas 134 can appear at the interface between the main channel layer 132m and the main barrier layer 136m. For example, the two-dimensional electron gas 134 can appear in the portion of the main channel layer 132m adjacent to the main barrier layer 136m.

[0061] The main channel layer 132m may comprise at least one material selected from group III-V materials (such as nitrides comprising Al, Ga, In, B, or combinations thereof). The main channel layer 132m may comprise a single layer or multiple layers. The main channel layer 132m may be composed of Al... x In y Ga 1-x-yN (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and x + y ≤ 1) is formed. For example, the main channel layer 132m may comprise AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof. The main channel layer 132m may be a doped layer or an undoped layer. The thickness of the main channel layer 132m may be approximately several hundred nm or less.

[0062] The main channel layer 132m can be positioned on the substrate 110, and the seed layer 121 and the buffer layer 120 can be positioned between the substrate 110 and the main channel layer 132m. The substrate 110, the seed layer 121, and the buffer layer 120 can be layers required to form the main channel layer 132m, and in some cases can be omitted. For example, when a substrate made of GaN is used as the main channel layer 132m, at least one of the substrate 110, the seed layer 121, and the buffer layer 120 can be omitted. Considering the relatively high cost of substrates made of GaN, a substrate 110 made of Si can be used to grow the main channel layer 132m containing GaN. In this case, since the lattice structure of Si is different from that of GaN, it may not be easy to grow the main channel layer 132m directly on the substrate 110. Therefore, the seed layer 121 and the buffer layer 120 can be grown on the substrate 110 first, and then the main channel layer 132m can be grown on the buffer layer 120. Additionally, at least one of the substrate 110, seed layer 121, and buffer layer 120 may be removed from the final structure of the semiconductor device 10 after the manufacturing process.

[0063] The substrate 110 may comprise a semiconductor material. For example, the substrate 110 may comprise sapphire, Si, SiC, AlN, GaN, or combinations thereof. The substrate 110 may be a silicon-on-insulator (SOI) substrate. However, the material of the substrate 110 is not limited to this, and each type of substrate commonly used can be applied. In some cases, the substrate 110 may comprise an insulating material. For example, several layers, including a main channel layer 132m, may be first formed on the semiconductor substrate, and then the semiconductor substrate may be removed and replaced with an insulating substrate.

[0064] Seed layer 121 may be directly positioned on substrate 110. However, this disclosure is not limited thereto, and other predetermined layers may be further positioned between substrate 110 and seed layer 121. Seed layer 121 is a layer used as a seed for growing buffer layer 120, and may be formed from a lattice structure to be used as a seed for buffer layer 120. Buffer layer 120 may be directly positioned on seed layer 121. However, this disclosure is not limited thereto, and other predetermined layers may be further positioned between seed layer 121 and buffer layer 120. Seed layer 121 may contain at least one material selected from group III-V materials (such as nitrides containing Al, Ga, In, B, or combinations thereof). Seed layer 121 may be made of Alx In y Ga 1-x-y N (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and x + y ≤ 1) are formed. For example, seed layer 121 may contain AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof.

[0065] A buffer layer 120 may be positioned on the seed layer 121. The buffer layer 120 may be positioned between the seed layer 121 and the main channel layer 132m. The buffer layer 120 may be a layer used to mitigate the difference in lattice constant and coefficient of thermal expansion between the seed layer 121 and the main channel layer 132m, or to prevent parasitic current (leakage current) from flowing through the main channel layer 132m. The buffer layer 120 may contain at least one material selected from group III-V materials (such as nitrides containing Al, Ga, In, B, or combinations thereof). The buffer layer 120 may be made of Al... x In y Ga 1-x-y N (where x≤1, y≤1, and x+y≤1) are formed. For example, the buffer layer 120 may contain AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof.

[0066] The buffer layer 120 of the semiconductor device 10 may include a superlattice layer 124 positioned on a seed layer 121 and a high resistivity layer 126 positioned on the superlattice layer 124. The superlattice layer 124 and the high resistivity layer 126 may be sequentially positioned on the substrate 110.

[0067] A superlattice layer 124 may be positioned on the seed layer 121. The superlattice layer 124 may be directly positioned on the seed layer 121. However, this disclosure is not limited thereto, and other predetermined layers may be further positioned between the seed layer 121 and the superlattice layer 124. The superlattice layer 124 is a layer used to mitigate the difference in lattice constant and coefficient of thermal expansion between the substrate 110 and the main channel layer 132m, thereby alleviating tensile and compressive stresses generated between the substrate 110 and the main channel layer 132m, and alleviating stress between all layers formed by growth in the final structure of the semiconductor device 10 according to the embodiment. The superlattice layer 124 may contain at least one material selected from group III-V materials (such as nitrides containing Al, Ga, In, B, or combinations thereof). The superlattice layer 124 may be made of Al x In y Ga 1-x-y N (where 0≤x≤1, 0≤y≤1, and x+y≤1) are formed, for example, the superlattice layer 124 may contain AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN or combinations thereof.

[0068] In some embodiments, the superlattice layer 124 may include multiple layers comprising different materials and stacked alternately. For example, the superlattice layer 124 may have a structure in which AlGaN layers and AlN layers are stacked alternately. In other words, AlGaN, AlN, AlGaN, AlN, AlGaN, and AlN are stacked sequentially to form the superlattice layer. The number of AlGaN and AlN layers constituting the superlattice layer 124 may vary, and the materials constituting the superlattice layer 124 may vary. As another example, the superlattice layer 124 may have a structure in which AlGaN layers and GaN layers are stacked alternately. In other words, AlGaN, GaN, AlGaN, GaN, AlGaN, and GaN are stacked sequentially to form the superlattice layer. In some embodiments, when the superlattice layer 124 comprises GaN, InN, AlGaN, AlInN, InGaN, AlN, AlInGaN, or combinations thereof, the superlattice layer 124 may have n-type semiconductor characteristics in which the concentration of electrons is greater than the concentration of holes; however, this disclosure is not limited thereto.

[0069] A high resistivity layer 126 may be positioned on the superlattice layer 124. The high resistivity layer 126 may be directly positioned on the superlattice layer 124. However, this disclosure is not limited thereto, and other predetermined layers may be further positioned between the superlattice layer 124 and the high resistivity layer 126. The high resistivity layer 126 may be positioned between the superlattice layer 124 and the main channel layer 132m. The high resistivity layer 126 is a layer used to prevent leakage current from flowing through the main channel layer 132m, thereby preventing degradation of the semiconductor device 10. The high resistivity layer 126 may comprise a material having low electrical conductivity, such that the substrate 110 and the main channel layer 132m are electrically insulated from each other. The high resistivity layer may comprise at least one material selected from group III-V materials (such as nitrides comprising Al, Ga, In, B, or combinations thereof). The high resistivity layer 126 may be made of Al x In y Ga 1-x-y N (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and x + y ≤ 1) is formed. For example, the high resistivity layer 126 may comprise AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof. The high resistivity layer 126 may comprise a single layer or multiple layers.

[0070] The main barrier layer 136m can be positioned on the main channel layer 132m. The main barrier layer 136m can be directly positioned on the main channel layer 132m. However, this disclosure is not limited to this, and other predetermined layers can be further positioned between the main channel layer 132m and the main barrier layer 136m. The regions of the main channel layer 132m superimposed on the main barrier layer 136m between the first electrode 191 and the second electrode 192, and between the first electrode 191 and the third electrode 193, can be termed drift regions. For example, a first drift region DTR1 can be positioned between the first electrode 191 and the second electrode 192, and a second drift region DTR2 can be positioned between the first electrode 191 and the third electrode 193. The first drift region DTR1 can refer to the region where carriers migrate when a potential difference occurs between the first electrode 191 and the second electrode 192. The second drift region DTR2 can refer to the region where carriers migrate when a potential difference occurs between the first electrode 191 and the third electrode 193.

[0071] The semiconductor device 10 can be turned on and off depending on whether a voltage is applied to the first gate electrode 151 and / or the second gate electrode 152 and / or the magnitude of the voltage applied to the first gate electrode 151 and / or the second gate electrode 152, thereby enabling or inhibiting the migration of charge carriers in the first drift region DTR1 and the second drift region DTR2.

[0072] The main barrier layer 136m may comprise at least one material selected from group III-V materials (such as nitrides comprising Al, Ga, In, B, or combinations thereof). x In y Ga 1-x-y N (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and x + y ≤ 1) is formed. The main barrier layer 136m may comprise GaN, InN, AlGaN, AlInN, InGaN, AlN, AlInGaN, combinations thereof, etc. The band gap of the main barrier layer 136m can be adjusted by the composition ratio of at least one of Al and In. The main barrier layer 136m may be doped with predetermined impurities. In this case, the impurity used to dope the main barrier layer 136m may be a p-type dopant capable of providing holes. For example, the impurity used to dope the main barrier layer 136m may be magnesium (Mg). By increasing or decreasing the concentration of the impurity used to dope the main barrier layer 136m, the threshold voltage, impedance, etc. of the semiconductor device 10 according to the embodiment can be adjusted.

[0073] The main barrier layer 136m may comprise a semiconductor material having properties different from those of the main channel layer 132m. At least one of the polarization characteristics, band gap, and lattice constant of the main barrier layer 136m may differ from those of the main channel layer 132m. For example, the main barrier layer 136m may comprise a material having a band gap different from that of the main channel layer 132m. In this case, the main barrier layer 136m may have a higher band gap than the main channel layer 132m, and may have a higher polarization than the main channel layer 132m. Through this main barrier layer 136m, a two-dimensional electron gas 134 can be generated in the main channel layer 132m, which has a relatively low polarization. In this respect, the main barrier layer 136m may be referred to as a channel supply layer or a two-dimensional electron gas supply layer. Two-dimensional electron gas 134 can be formed in the portion of the main channel layer 132m located below the interface between the main channel layer 132m and the main barrier layer 136m. Two-dimensional electron gas 134 can have very high electron mobility.

[0074] The main barrier layer 136m may comprise a single layer or multiple layers. When the main barrier layer 136m comprises multiple layers, the materials constituting each layer may have different band gaps. In this case, the multiple layers constituting the main barrier layer 136m may be configured such that the layers closer to the main channel layer 132m have higher band gaps.

[0075] The first gate electrode 151 and the second gate electrode 152 may be positioned on the main barrier layer 136m. In some embodiments, the first gate electrode 151 and the second gate electrode 152 may extend in a second direction (Y direction). The first gate electrode 151 and the second gate electrode 152 may be positioned spaced apart from each other in a first direction (X direction).

[0076] The first gate electrode 151 and the second gate electrode 152 may be superimposed on a portion of the main barrier layer 136m in the third direction (Z direction). The first gate electrode 151 may be superimposed on a portion of the first drift region DTR1 of the main channel layer 132m in the third direction (Z direction). The second gate electrode 152 may be superimposed on a portion of the second drift region DTR2 of the main channel layer 132m in the third direction (Z direction). The first gate electrode 151 may be positioned between the first electrode 191 and the second electrode 192, which will be described below. The first gate electrode 151 may be spaced apart from the first electrode 191 and the second electrode 192, which will be described below, in the first direction (X direction). The second gate electrode 152 may be positioned between the first electrode 191 and the third electrode 193, which will be described below, in the first direction (X direction). The second gate electrode 152 may be spaced apart from the first electrode 191 and the third electrode 193, which will be described below, in the first direction (X direction).

[0077] The first gate electrode 151 and the second gate electrode 152 can be formed simultaneously in the same process. The first gate electrode 151 and the second gate electrode 152 can be positioned in the same layer. The upper surface of the first gate electrode 151 can be positioned at substantially the same height as the upper surface of the second gate electrode 152; however, this disclosure is not limited thereto. In other words, the upper surfaces of the first gate electrode 151 and the second gate electrode 152 can be positioned at substantially the same distance from the upper surface of the substrate 110.

[0078] The first gate electrode 151 and the second gate electrode 152 may comprise conductive materials. For example, the first gate electrode 151 and the second gate electrode 152 may comprise metals, metal alloys, conductive metal nitrides, metal silicides, doped semiconductor materials, conductive metal oxides, conductive metal oxides, etc. For example, the first gate electrode 151 and the second gate electrode 152 may comprise titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (Ta The first gate electrode 151 and the second gate electrode 152 may comprise a single layer or multiple layers. The first gate electrode 151 may comprise a single layer or multiple layers.

[0079] In some embodiments, a hard mask layer positioned on the first gate electrode 151 and the second gate electrode 152 may be further included. The hard mask layer may be a hard mask used to perform patterning on a gate electrode material layer or a gate semiconductor material layer during the formation of the first gate electrode 151 and the second gate electrode 152. However, the hard mask layer may be removed depending on the etching conditions during etching on the gate electrode material layer or the cleaning conditions after etching. As an example, the hard mask layer may comprise silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0080] A first gate semiconductor layer 181 may be positioned between the main barrier layer 136m and the first gate electrode 151. A second gate semiconductor layer 182 may be positioned between the main barrier layer 136m and the second gate electrode 152. In other words, the first gate semiconductor layer 181 and the second gate semiconductor layer 182 may be positioned on the main barrier layer 136m, and the first gate electrode 151 and the second gate electrode 152 may be positioned on the first gate semiconductor layer 181 and the second gate semiconductor layer 182.

[0081] The first gate electrode 151 may have a Schottky contact or an ohmic contact with the first gate semiconductor layer 181. The first gate semiconductor layer 181 may be stacked with the first gate electrode 151 in the third direction (Z direction). In this case, the first gate semiconductor layer 181 may be completely stacked with the first gate electrode 151 in the third direction (Z direction), and the upper surface of the first gate semiconductor layer 181 may be completely covered by the first gate electrode 151. In other words, the first gate semiconductor layer 181 may have a planar shape that is substantially the same as the planar shape of the first gate electrode 151.

[0082] In some embodiments, a first gate semiconductor layer 181 may be positioned between a first electrode 191 and a second electrode 192. The first gate semiconductor layer 181 may be spaced apart from the first electrode 191 and the second electrode 192.

[0083] The second gate electrode 152 may have a Schottky contact or an ohmic contact with the second gate semiconductor layer 182. The second gate semiconductor layer 182 may be stacked with the second gate electrode 152 in the third direction (Z direction). In this case, the second gate semiconductor layer 182 may be completely stacked with the second gate electrode 152 in the third direction (Z direction), and the upper surface of the second gate semiconductor layer 182 may be completely covered by the second gate electrode 152. In other words, the second gate semiconductor layer 182 may have a planar shape that is substantially the same as the planar shape of the second gate electrode 152.

[0084] However, this disclosure is not limited thereto, and the first gate electrode 151 and the second gate electrode 152 may be positioned to cover at least a portion of the first gate semiconductor layer 181 and the second gate semiconductor layer 182.

[0085] In some embodiments, the second gate semiconductor layer 182 may be positioned between the first electrode 191 and the third electrode 193. The second gate semiconductor layer 182 may be spaced apart from the first electrode 191 and the third electrode 193.

[0086] The first gate semiconductor layer 181 and the second gate semiconductor layer 182 can be formed simultaneously in the same process. The first gate semiconductor layer 181 and the second gate semiconductor layer 182 can be located in the same layer. The upper surface of the first gate semiconductor layer 181 can be located at a height substantially the same as the upper surface of the second gate semiconductor layer 182; however, this disclosure is not limited thereto. In other words, the upper surfaces of the first gate semiconductor layer 181 and the second gate semiconductor layer 182 can be located at substantially the same distance from the upper surface of the substrate 110.

[0087] The first gate semiconductor layer 181 and the second gate semiconductor layer 182 may comprise at least one material selected from group III-V materials (such as nitrides comprising Al, Ga, In, B, or combinations thereof). The first gate semiconductor layer 181 and the second gate semiconductor layer 182 may be made of Al... x In y Ga 1-x-y N (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and x + y ≤ 1) is formed. For example, the first gate semiconductor layer 181 and the second gate semiconductor layer 182 may comprise AlN, GaN, InN, InGaN, AlGaN, AlInN, AlInGaN, or combinations thereof. The first gate semiconductor layer 181 and the second gate semiconductor layer 182 may comprise a material having a different band gap than that of the main barrier layer 136m. For example, the first gate semiconductor layer 181 and the second gate semiconductor layer 182 may comprise GaN, and the main barrier layer 136m may comprise AlGaN. The first gate semiconductor layer 181 and the second gate semiconductor layer 182 may be doped with predetermined impurities. In this case, the impurities used to dope the first gate semiconductor layer 181 and the second gate semiconductor layer 182 may be p-type dopants capable of providing holes. For example, the first gate semiconductor layer 181 and the second gate semiconductor layer 182 may comprise GaN doped with p-type impurities. In other words, the first gate semiconductor layer 181 and the second gate semiconductor layer 182 may comprise p-GaN layers. The first gate semiconductor layer 181 and the second gate semiconductor layer 182 may be a single layer or multiple layers.

[0088] A depletion region can be formed inside the main channel layer 132m via the first gate semiconductor layer 181 and the second gate semiconductor layer 182. For example, a first depletion region DPR1 can be formed inside the main channel layer 132m via the first gate semiconductor layer 181, and a second depletion region DPR2 can be formed inside the main channel layer 132m via the second gate semiconductor layer 182. The first depletion region DPR1 can be located inside the first drift region DTR1 and can have a width smaller than the width of the first drift region DTR1. The second depletion region DPR2 can be located inside the second drift region DTR2 and can have a width smaller than the width of the second drift region DTR2. Since the first gate semiconductor layer 181 and the second gate semiconductor layer 182, which have band gaps different from those of the main barrier layer 136m, are located on the main barrier layer 136m, the energy level of the portion of the main barrier layer 136m that overlaps with the first gate semiconductor layer 181 and the second gate semiconductor layer 182 can be raised.

[0089] Therefore, depletion regions DPR1 and DPR2 can be formed in the region of the main channel layer 132m that is superimposed with the first gate semiconductor layer 181 and the second gate semiconductor layer 182. Depletion regions DPR1 and DPR2 can be regions on the channel path of the main channel layer 132m where no two-dimensional electron gas 134 is formed or where the electron concentration is lower than that of other regions. In other words, depletion regions DPR1 and DPR2 can refer to regions where the flow of two-dimensional electron gas 134 in drift regions DTR1 and DTR2 is cut off. Due to the generation of depletion regions DPR1 and DPR2, no current can flow between the first electrode 191 and the second electrode 192, and between the first electrode 191 and the third electrode 193, and the channel path can be blocked. Therefore, the semiconductor device 10 can have normally-off characteristics.

[0090] In some embodiments, the semiconductor device 10 may be a normally-off high electron mobility transistor (HEMT). For example... Figure 6 As shown, in the normal state where no voltage is applied to the first gate electrode 151 and the second gate electrode 152, depletion regions DPR1 and DPR2 may exist, and the semiconductor device 10 according to the embodiment may be in a cutoff state. Figure 7As shown, when a voltage equal to or higher than a threshold voltage is applied to the first gate electrode 151 and the second gate electrode 152, the depletion regions DPR1 and DPR2 can disappear, and the two-dimensional electron gas 134 can be continuous within the drift regions DTR1 and DTR2 without being interrupted. In other words, the two-dimensional electron gas 134 can be formed as a channel path spanning the entire distance between the first electrode 191 and the second electrode 192, and between the first electrode 191 and the third electrode 193, and the semiconductor device 10 can be turned on. In summary, the semiconductor device 10 may include semiconductor layers with different polarization characteristics, and a semiconductor layer with a relatively high polarizability can induce a two-dimensional electron gas 134 in another semiconductor layer that forms a heterojunction with it. The two-dimensional electron gas 134 can be used as a channel between the first electrode 191 and the second electrode 192, and between the first electrode 191 and the third electrode 193, and the continuity or interruption of the flow of the two-dimensional electron gas 134 can be controlled by a bias voltage applied to the first gate electrode 151 and the second gate electrode 152.

[0091] Although the semiconductor device 10 has been described above as a normally-off high electron mobility transistor, this disclosure is not limited thereto. For example, the semiconductor device 10 may be a normally-on high electron mobility transistor. When the semiconductor device is a normally-on high electron mobility transistor, the first gate semiconductor layer 181 and the second gate semiconductor layer 182 may be omitted, thereby allowing the first gate electrode 151 and the second gate electrode 152 to be directly positioned on the main barrier layer 136m. In other words, the first gate electrode 151 and the second gate electrode 152 may be in contact with the main barrier layer 136m. In this structure, when no voltage is applied to the first gate electrode 151 and the second gate electrode 152, the two-dimensional electron gas 134 can be used as a channel, and current flow can occur between the first electrode 191 and the second electrode 192, and between the first electrode 191 and the third electrode 193. Furthermore, when a negative voltage is applied to the first gate electrode 151 and the second gate electrode 152, a depletion region where the flow of the two-dimensional electron gas 134 is interrupted may appear below the first gate electrode 151 and the second gate electrode 152.

[0092] The seed layer 121, superlattice layer 124, high resistivity layer 126, main channel layer 132m, main barrier layer 136m, first gate semiconductor layer 181, and second gate semiconductor layer 182 may be sequentially stacked on the substrate 110. In the semiconductor device 10, at least one of the seed layer 121, superlattice layer 124, high resistivity layer 126, main channel layer 132m, main barrier layer 136m, first gate semiconductor layer 181, and second gate semiconductor layer 182 may be omitted. The seed layer 121, superlattice layer 124, high resistivity layer 126, main channel layer 132m, main barrier layer 136m, first gate semiconductor layer 181, and second gate semiconductor layer 182 may comprise semiconductor materials based on the same material, and the material composition ratios of the respective layers may differ from each other, considering the function of each layer, the performance required by the semiconductor device 10, etc.

[0093] The semiconductor device 10 may further include a first protective layer 140 positioned on the main barrier layer 136m. The first protective layer 140 may be positioned on the main barrier layer 136m, the first gate electrode 151, and the second gate electrode 152. The first protective layer 140 may cover the upper and side surfaces of the gate electrodes 151 and 152, as well as the side surfaces of the gate semiconductor layers 181 and 182. The lower surface of the first protective layer 140 may contact the main barrier layer 136m and the gate electrodes 151 and 152. Therefore, the main barrier layer 136m, the gate semiconductor layers 181 and 182, and the gate electrodes 151 and 152 may be protected by the first protective layer 140. However, this disclosure is not limited thereto, and the gate electrodes 151 and 152 may pass through the first protective layer 140 and connect to the gate semiconductor layers 181 and 182, and the first protective layer 140 may not cover the upper surfaces of the gate electrodes 151 and 152. Furthermore, the lower surface of the first protective layer 140 may contact the gate semiconductor layers 181 and 182. The first protective layer 140 may comprise an insulating material. For example, the first protective layer 140 may comprise an oxide (such as SiO2 or Al2O3). As another example, the first protective layer 140 may comprise a nitride (such as SiN) or an oxynitride (such as SiON).

[0094] exist Figure 5 and Figure 6 In this embodiment, the first protective layer 140 comprises a single layer. However, the first protective layer 140 is not limited to this and may include multiple layers containing different materials.

[0095] The first electrode 191 to the third electrode 193 can be positioned on the main channel layer 132m. The first electrode 191 to the third electrode 193 can be in direct contact with the main channel layer 132m and can be electrically connected to the main channel layer 132m.

[0096] The first electrode 191 to the third electrode 193 may be spaced apart from each other. The first electrode 191 to the third electrode 193 may be positioned separately from each other in a first direction (X direction). The first electrode 191 to the third electrode 193 may extend in directions parallel to each other. For example, the first electrode 191 to the third electrode 193 may extend in a second direction (Y direction); however, this disclosure is not limited thereto.

[0097] Specifically, the first electrode 191 and the second electrode 192 may be positioned on opposite sides of the first gate electrode 151. The first gate electrode 151 and the first gate semiconductor layer 181 may be positioned between the first electrode 191 and the second electrode 192. The first gate electrode 151 and the first gate semiconductor layer 181 may be spaced apart from the first electrode 191 and the second electrode 192 in a first direction (X direction). For example, the first electrode 191 may be electrically connected to the main channel layer 132m on one side of the first gate electrode 151 in the first direction (X direction), and the second electrode 192 may be electrically connected to the main channel layer 132m on the other side of the first gate electrode 151 in the first direction (X direction). The first electrode 191 and the second electrode 192 may be positioned on the outer side of the first drift region DTR1 of the main channel layer 132m. The interface between the first electrode 191 and the main channel layer 132m may be an edge of the first drift region DTR1. Similarly, the interface between the second electrode 192 and the main channel layer 132m can be another edge of the first drift region DTR1. In this case, the first distance DS1 between the first electrode 191 and the first gate electrode 151 in the first direction (X direction) can be substantially equal to the second distance DS2 between the second electrode 192 and the first gate electrode 151 in the first direction (X direction).

[0098] Additionally, the first electrode 191 and the third electrode 193 may be positioned on opposite sides of the second gate electrode 152. The second gate electrode 152 and the second gate semiconductor layer 182 may be positioned between the first electrode 191 and the third electrode 193. The second gate electrode 152 and the second gate semiconductor layer 182 may be spaced apart from the first electrode 191 and the third electrode 193 in a first direction (X direction). For example, the first electrode 191 may be electrically connected to the main channel layer 132m on one side of the second gate electrode 152 in the first direction (X direction), and the third electrode 193 may be electrically connected to the main channel layer 132m on the other side of the second gate electrode 152 in the first direction (X direction). The first electrode 191 and the third electrode 193 may be positioned outside the second drift region DTR2 of the main channel layer 132m. The interface between the first electrode 191 and the main channel layer 132m may be an edge of the second drift region DTR2. Similarly, the interface between the third electrode 193 and the main channel layer 132m can be another edge of the second drift region DTR2. In this case, the third distance DS3 between the first electrode 191 and the second gate electrode 152 in the first direction (X direction) can be substantially equal to the fourth distance DS4 between the third electrode 193 and the second gate electrode 152 in the first direction (X direction). Furthermore, the third distance DS3 between the first electrode 191 and the second gate electrode 152 in the first direction (X direction) can be substantially equal to the first distance DS1 between the first electrode 191 and the first gate electrode 151 in the first direction (X direction).

[0099] However, this disclosure is not limited thereto, and the first electrode 191 to the third electrode 193 may not be positioned on the outer surface of the drift regions DTR1 and DTR2 of the main channel layer 132m. In other words, the main channel layer 132m may not be recessed, and the first electrode 191 to the third electrode 193 may be positioned on the upper surface of the main channel layer 132m.

[0100] The first electrode 191 to the third electrode 193 can penetrate the first protective layer 140 and the main barrier layer 136m, and are positioned inside a trench formed by recessing the upper surface of the main channel layer 132m. Inside the trench, the first electrode 191 to the third electrode 193 can contact the main channel layer 132m and the main barrier layer 136m. The main channel layer 132m can form the bottom surface and sidewalls of the trench, and the main barrier layer 136m can form the sidewalls of the trench. Therefore, the first electrode 191 to the third electrode 193 can contact the upper surface and side surface of the main channel layer 132m. In addition, the first electrode 191 to the third electrode 193 can contact the side surface of the main barrier layer 136m. In other words, the first electrode 191 to the third electrode 193 can cover the side surfaces of the main channel layer 132m and the main barrier layer 136m.

[0101] In some embodiments, the first electrode 191 to the third electrode 193 may cover at least a portion of the side surface of the first protective layer 140. For example, the first electrode 191 to the third electrode 193 may cover the side surface of the first protective layer 140. The upper surface of the first electrode 191 to the third electrode 193 may protrude from the upper surface of the first protective layer 140. However, this disclosure is not limited thereto, and the first electrode 191 to the third electrode 193 may cover at least a portion of the side surface of the first protective layer 140, but may not cover other portions of the side surface of the first protective layer 140. In this case, the other portions of the first protective layer 140 may be located on the upper surface of the first electrode 191 to the third electrode 193.

[0102] The first electrode 191 to the third electrode 193 may comprise a conductive material. For example, the first electrode 191 to the third electrode 193 may comprise a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, a conductive metal oxide nitride, etc. For example, the first electrode 191 to the third electrode 193 may comprise titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaC), etc. The first electrode 191 to the third electrode 193 may comprise a single layer or multiple layers. The first electrode 191 to the third electrode 193 may be in ohmic contact with the main channel layer 132m. Compared to other regions, the regions in the main channel layer 132m that are in contact with the first electrode 191 to the third electrode 193 may be doped at a relatively higher concentration.

[0103] exist Figure 6 and Figure 7 In the semiconductor device 10, the first electrode 191 to the third electrode 193 comprise a single layer, but the number of layers of the first electrode 191 to the third electrode 193 is not limited thereto. For example, the first electrode 191 to the third electrode 193 may comprise multiple electrode layers sequentially stacked in a third direction (Z direction). Referring below... Figure 11 and Figure 12 This will be described.

[0104] In some embodiments, the first electrode 191, the second electrode 192, and the first gate electrode 151 may constitute a first transistor 100a. The first electrode 191, the third electrode 193, and the second gate electrode 152 may constitute a second transistor 100b. When voltages of different magnitudes are applied to the first electrodes 191 to the third electrodes 193 of the semiconductor device 10, current may flow in the first transistor 100a and / or the second transistor 100b according to the potential difference between the first electrodes 191 and the third electrodes 193. As an example, when a first voltage is applied to the first electrode 191, and a second voltage less than the first voltage is applied to the second electrode 192 and the third electrode 193, current may flow from the first electrode 191 to the second electrode 192 and from the first electrode 191 to the third electrode 193, respectively, according to the turn-on signal for the first gate electrode 151 and the second gate electrode 152. Simultaneously, when a third voltage greater than the first voltage is applied to the second electrode 192 and the third electrode 193, according to the conduction signal for the first gate electrode 151 and the second gate electrode 152, current can flow from the second electrode 192 to the first electrode 191 and from the third electrode 193 to the first electrode 191, respectively. Therefore, when the charger ( Figure 1 Reference numeral "40" in the figure is electrically connected to the first electrode 191 and the external device ( Figure 1 When the reference numerals “31” and “32” in the figure are electrically connected to the second electrode 192 and the third electrode 193, the external device connected to the second electrode 192 can be charged or discharged according to the conduction signal for the first gate electrode 151, and the external device connected to the third electrode 193 can be charged or discharged according to the conduction signal for the second gate electrode 152.

[0105] Furthermore, the semiconductor device 10 may also include a field dispersion layer covering at least a portion of the first protective layer 140. The field dispersion layer may be positioned between the first electrode 191 and the second electrode 192, and between the first electrode 191 and the third electrode 193. The field dispersion layer may cover the first gate electrode 151 and the second gate electrode 152. The field dispersion layer may be stacked with the first gate electrode 151 and the second gate electrode 152 in the third direction (Z direction).

[0106] In some embodiments, the field dispersion layer may be electrically connected to at least one of the first electrodes 191 to the third electrodes 193. The field dispersion layer may comprise the same material as the first electrodes 191 to the third electrodes 193 and may be positioned in the same layer as the first electrodes 191 to the third electrodes 193. The field dispersion layer may be formed simultaneously with the first electrodes 191 to the third electrodes 193 in the same process. In other words, the interface between the field dispersion layer and the first electrodes 191 to the third electrodes 193 may be unclear, and the field dispersion layer may be integrally formed with the first electrodes 191 to the third electrodes 193. However, the field dispersion layer is not limited to this and may be a separate constituent element separate from the first electrodes 191 to the third electrodes 193.

[0107] As another example, the field dispersion layer may be positioned separately from the first electrode 191 to the third electrode 193. In this case, the field dispersion layer may be positioned on the first gate electrode 151 and the second gate electrode 152 and is floating. The field dispersion layer can be used to disperse the electric field concentrated around the first gate electrode 151 and the second gate electrode 152.

[0108] In the following text, we will refer to... Figure 8 to Figure 10 Describes multiple diode elements in a semiconductor device.

[0109] Figure 8 It is based on some implementation methods along Figure 5 The sectional view taken by line B-B'. Figure 9 It is based on some implementation methods along Figure 5 A sectional view taken by line C-C'. Figure 10 It is based on some implementation methods along Figure 5 A sectional view taken by line D-D'. Figure 5 and Figure 8 to Figure 10 The plurality of diode elements 510, 520 and 530 of the semiconductor device 10 may respectively correspond to Figure 2 Multiple diode elements 510, 520 and 530.

[0110] exist Figure 5 In the semiconductor device 10, a plurality of diode elements 510, 520 and 530 may include a first diode element 510 electrically connecting a first electrode 191 and a substrate 110, a second diode element 520 electrically connecting a second electrode 192 and a substrate 110, and a third diode element 530 electrically connecting a third electrode 193 and a substrate 110.

[0111] Multiple diode elements 510, 520, and 530 may be positioned separately from each other. For example, the multiple diode elements 510, 520, and 530 may be spaced apart from each other in a first direction (X direction). In some embodiments, the multiple diode elements 510, 520, and 530 may be separated from each other by a separation structure 160. Through the separation structure 160, the multiple diode elements 510, 520, and 530 may be electrically insulated from each other. In some embodiments, the first diode element 510 to the third diode element 530 may have the same structure and shape. Hereinafter, for ease of explanation, the first diode element 510 will be described.

[0112] exist Figure 8 and Figure 9 In the semiconductor device 10, the first diode element 510 may include a sub-channel layer 132s positioned on the substrate 110, a sub-barrier layer 136s positioned on the sub-channel layer 132s, a sub-gate electrode 150s positioned on the sub-barrier layer 136s, a sub-gate semiconductor layer 180s positioned between the sub-barrier layer 136s and the sub-gate electrode 150s, and a sub-source electrode 170s and a sub-drain electrode 190s positioned on opposite sides of the sub-gate electrode 150s.

[0113] Sub-channel layer 132s may be positioned on substrate 110. Sub-channel layer 132s may be a layer forming a channel between sub-drain electrode 190s and sub-source electrode 170s, and two-dimensional electron gas (2DEG) 134 may be positioned inside sub-channel layer 132s. In semiconductor device 10, two-dimensional electron gas 134 may appear at the interface between sub-channel layer 132s and sub-barrier layer 136s. For example, two-dimensional electron gas 134 may appear in a portion of sub-channel layer 132s adjacent to sub-barrier layer 136s.

[0114] In some embodiments, the sub-channel layer 132s can be integrally formed with the main channel layer 132m of the bidirectional transistor 100 using the same process. The sub-channel layer 132s can be positioned on the same layer as the main channel layer 132m. The lower surface of the sub-channel layer 132s can be positioned at the same height as the lower surface of the main channel layer 132m, and the upper surface of the sub-channel layer 132s can be positioned at the same height as the upper surface of the main channel layer 132m. In other words, the lower surface of the sub-channel layer 132s and the lower surface of the main channel layer 132m can be positioned at the same distance from the upper surface of the substrate 110. Additionally, the upper surface of the sub-channel layer 132s and the upper surface of the main channel layer 132m can be positioned at substantially the same distance from the upper surface of the substrate 110. The thickness of the sub-channel layer 132s in the third direction (Z direction) can be substantially equal to the thickness of the main channel layer 132m in the third direction (Z direction), but this disclosure is not limited thereto.

[0115] In some embodiments, the sub-channel layer 132s may comprise the same material as the main channel layer 132m located in the main element region MA. As an example, the sub-channel layer 132s may comprise at least one material selected from group III-V materials (such as nitrides comprising Al, Ga, In, B, or combinations thereof).

[0116] Sub-channel layer 132s may be positioned on substrate 110, and seed layer 121 and buffer layer 120 may be positioned between substrate 110 and sub-channel layer 132s. Substrate 110, seed layer 121, and buffer layer 120 may be layers required to form sub-channel layer 132s, and may be omitted in some cases. In an embodiment, substrate 110, seed layer 121, and buffer layer 120 positioned in peripheral circuit region PA may be integrally formed with substrate 110, seed layer 121, and buffer layer 120 positioned in main component region MA by the same process.

[0117] The sub-barrier layer 136s can be positioned on the sub-channel layer 132s. The sub-barrier layer 136s can be directly positioned on the sub-channel layer 132s. However, this disclosure is not limited thereto, and other predetermined layers can be further positioned between the sub-channel layer 132s and the sub-barrier layer 136s. The region of the sub-channel layer 132s overlapping with the sub-barrier layer 136s can become a drift region. Specifically, since the sub-barrier layer 136s differs from the sub-channel layer 132s in at least one of polarization characteristics, band gap, and lattice constant, a two-dimensional electron gas 134 can be generated through the sub-barrier layer 136s in the sub-channel layer 132s, which has relatively low polarization.

[0118] In some embodiments, the sub-channel layer 132s may include a sub-drift region DTR_d between the sub-source electrode 170s and the sub-drain electrode 190s. In other words, the sub-drift region DTR_d may refer to the region of the sub-channel layer 132s from the side of the sub-channel layer 132s that contacts the sub-drain electrode 190s to the sub-source electrode 170s. The sub-drift region DTR_d may also refer to the region of the sub-channel layer 132s that is superimposed with the sub-barrier layer 136s between the sub-source electrode 170s and the sub-drain electrode 190s. For example, the boundary between the sub-drain electrode 190s and the sub-channel layer 132s may be one edge of the sub-drift region DTR_d, and the boundary between the sub-source electrode 170s and the sub-channel layer 132s may be another edge of the sub-drift region DTR_d. In other words, the sub-drift region DTR_d can refer to the region of carrier migration in the peripheral circuit region PA between the sub-channel layer 132s, which is in contact with the sub-drain electrode 190s, and the sub-source electrode 170s.

[0119] According to an embodiment, the first protective layer 140 of the semiconductor device 10 may further extend to the upper surface of the sub-barrier layer 136s. The first protective layer 140 may be positioned on the sub-barrier layer 136s. The lower surface of the first protective layer 140 may contact the sub-barrier layer 136s.

[0120] The sub-gate electrode 150s may be positioned on the sub-barrier layer 136s. In an embodiment, the sub-gate electrode 150s may extend in a first direction (X direction). The sub-gate electrode 150s may extend in a direction intersecting the directions in which the first gate electrode 151 and the second gate electrode 152 extend. The sub-gate electrode 150s may be covered by a first protective layer 140.

[0121] The sub-gate electrode 150s can be formed together with the first gate electrode 151 and the second gate electrode 152 in the same process. The sub-gate electrode 150s can be positioned in the same layer as the first gate electrode 151 and the second gate electrode 152. The sub-gate electrode 150s can contain the same material as the first gate electrode 151 and the second gate electrode 152.

[0122] The sub-gate semiconductor layer 180s can be positioned between the sub-barrier layer 136s and the sub-gate electrode 150s. In other words, the sub-gate semiconductor layer 180s can be positioned on the sub-barrier layer 136s, and the sub-gate electrode 150s can be positioned on the sub-gate semiconductor layer 180s. The sub-gate electrode 150s can have a Schottky contact or an ohmic contact with the sub-gate semiconductor layer 180s. Through the sub-gate semiconductor layer 180s, the sub-depletion region DPR_d can be formed inside the sub-channel layer 132s.

[0123] The sub-gate semiconductor layer 180s may be formed together with the first gate semiconductor layer 181 and the second gate semiconductor layer 182 in the same process. The sub-gate semiconductor layer 180s may be positioned in the same layer as the first gate semiconductor layer 181 and the second gate semiconductor layer 182. The sub-gate semiconductor layer 180s may contain the same material as the first gate semiconductor layer 181 and the second gate semiconductor layer 182.

[0124] The source electrode 170s and the drain electrode 190s may be positioned on opposite sides of the gate electrode 150s. The source electrode 170s and the drain electrode 190s may be spaced apart from each other. The source electrode 170s and the drain electrode 190s may extend in a first direction (X direction) and be spaced apart from each other in a second direction (Y direction). The source electrode 170s and the drain electrode 190s may extend in a direction intersecting the directions in which the first electrode 191 to the third electrode 193 extend. As an example, the first electrode 191 to the third electrode 193 may extend in the second direction (Y direction), and the source electrode 170s and the drain electrode 190s may extend in the first direction (X direction); however, this disclosure is not limited thereto.

[0125] The source electrode 170s and the drain electrode 190s may contain conductive materials. The source electrode 170s and the drain electrode 190s may contain the same material. Alternatively, the source electrode 170s and the drain electrode 190s may contain the same material as the first electrode 191 to the third electrode 193. The source electrode 170s and the drain electrode 190s may be formed together with the first electrode 191 to the third electrode 193 using the same process. For example, the source electrode 170s may contain metal, metal alloy, conductive metal nitride, metal silicide, doped semiconductor material, conductive metal oxide, conductive metal oxide nitride, etc.

[0126] The sub-source electrode 170s can be positioned on the sub-channel layer 132s. The sub-source electrode 170s can contact the sub-channel layer 132s and can be electrically connected to the sub-channel layer 132s. The sub-source electrode 170s can pass through the first protective layer 140 and the sub-barrier layer 136s and is positioned inside a trench formed by recessing the upper surface of the sub-channel layer 132s.

[0127] exist Figure 9 In this process, the sub-source electrode 170s can be integrally formed with the first electrode 191. The sub-source electrode 170s can be positioned together with the first electrode 191 in the same layer and contain the same material as the first electrode. The sub-source electrode 170s can be integrally formed with the first electrode 191 through the same process, but this disclosure is not limited thereto.

[0128] In some embodiments, the sub-source electrode 170s may be electrically connected to the sub-gate electrode 150s. Specifically, the sub-source electrode 170s may include a first connection portion EP1 positioned on the first protective layer 140. The first connection portion EP1 may extend on the first protective layer 140 toward the sub-gate electrode 150s. Additionally, the first connection portion EP1 may be positioned on the sub-gate electrode 150s and located inside a first gate via GV1 passing through the first protective layer 140. The first connection portion EP1 may completely fill the first gate via GV1. The sub-source electrode 170s and the sub-gate electrode 150s may be connected to each other via the first connection portion EP1. The first connection portion EP1 may be stacked with the sub-gate electrode 150s in the third direction (Z direction).

[0129] However, this disclosure is not limited thereto, and for example, the protective layer may be further positioned between the first connection portion EP1 and the first protective layer 140, and connect the sub-source electrode 170s and the sub-gate electrode 150s. As another example, the sub-source electrode 170s may include multiple source electrode layers, and the source electrode layer positioned on top may pass through the first protective layer 140 and connect to the sub-gate electrode 150s. As another example, the sub-source electrode 170s and the sub-gate electrode 150s may be connected via separate top wirings positioned on the sub-source electrode 170s and the sub-gate electrode 150s. Figure 15The figure in the attached diagram is connected by the reference numeral "540". The following will refer to... Figure 15 This will be described.

[0130] In some embodiments, since the sub-source electrode 170s and the sub-gate electrode 150s are electrically connected, a signal having the same voltage can be applied to the sub-source electrode 170s and the sub-gate electrode 150s. Therefore, the first diode element 510 of the semiconductor device 10 may have the following diode element characteristics: in which current flows in response to forward voltage and no current flows in response to reverse voltage.

[0131] In some embodiments, the sub-drain electrode 190s may be positioned on the substrate 110. The sub-drain electrode 190s may be connected to the substrate 110. For example, the sub-drain electrode 190s may pass through the first protective layer 140, the sub-barrier layer 136s, and the sub-channel layer 132s, and be positioned within a trench formed by recessing the upper surface of the substrate 110. Therefore, the sub-drain electrode 190s may be electrically connected to the substrate 110. The side surfaces of the sub-drain electrode 190s may contact the sub-barrier layer 136s and the sub-channel layer 132s. Additionally, the sub-drain electrode 190s may pass through the seed layer 121 and the buffer layer 120.

[0132] The semiconductor device 10 may further include a separation structure 160 positioned between the bidirectional transistor 100 and the first diode element 510. The first diode element 510 may be separated from the bidirectional transistor 100 via the separation structure 160. The separation structure 160 may extend through the sub-barrier layer 136s, the sub-channel layer 132s, the seed layer 121, and the buffer layer 120, and recess at least a portion of the substrate 110. Thus, the sub-drift region DTR_d of the first diode element 510 may be electrically insulated from the bidirectional transistor 100. However, this disclosure is not limited thereto, and, as another example, the separation structure 160 may extend only through the sub-barrier layer 136s and be positioned on the sub-channel layer 132s. As another example, the separation structure 160 may extend only through the sub-barrier layer 136s and the sub-channel layer 132s. As yet another example, the separation structure 160 may extend through the sub-barrier layer 136s and the sub-channel layer 132s, and recess at least a portion of the buffer layer 120.

[0133] The separation structure 160 may be stacked with the first electrode 191 to the third electrode 193 in the third direction (Z direction). The separation structure 160 may contact the lower surface of the first electrode 191 to the third electrode 193, but this disclosure is not limited thereto.

[0134] In some embodiments, the separation structure 160 can be formed by forming a main barrier layer 136m and a sub-barrier layer 136s on the main channel layer 132m and the sub-channel layer 132s, and performing an ion implantation process on the interior of the sub-barrier layer 136s positioned between the bidirectional transistor 100 and the first diode element 510. For example, in the region of the sub-channel layer 132s that overlaps with the main barrier layer 136m and in the region of the sub-barrier layer 136s that undergoes ion implantation in the third direction (Z direction), a two-dimensional electron gas may be absent or very little formed. In this case, the ion implantation regions of the sub-barrier layer 136s, the sub-channel layer 132s, and the buffer layer 120 can correspond to the separation structure 160. As another example, the separation structure 160 can be formed by performing an ion implantation process on the sub-channel layer 132s. The ion-implanted region of the sub-channel layer 132s can correspond to the separation structure 160. The material used in the ion implantation process can be argon (Ar) ions. However, this disclosure is not limited to this, and the separation structure 160 can be formed by forming a main barrier layer 136m and a sub-barrier layer 136s on the main channel layer 132m and the sub-barrier layer 132s, forming trenches to pass through the main barrier layer 136m and the sub-barrier layer 136s, and filling the trenches with an insulating material. The insulating material constituting the separation structure 160 may contain the same material as the first protective layer 140. For example, the insulating material constituting the separation structure 160 may contain oxides (such as SiO2 or Al2O3). As another example, the insulating material constituting the separation structure 160 may contain nitrides (such as SiN) or oxynitrides (such as SiON). However, the insulating material constituting the separation structure 160 is not limited to this, and may contain a material different from the material of the first protective layer 140. In this case, at least a portion of at least one of the main channel layer 132m and the sub-channel layer 132s may also be recessed.

[0135] The sub-source electrode 170s of the second diode element 520 can be electrically connected to the second electrode 192. The sub-source electrode 170s of the second diode element 520 can be integrally formed with the second electrode 192. The sub-source electrode 170s of the second diode element 520 can be positioned in the same layer as the second electrode 192 and contains the same material as the second electrode. The sub-drain electrode 190s of the second diode element 520 can pass through the first protective layer 140, the sub-barrier layer 136s, and the sub-channel layer 132s, and is positioned inside a trench formed by recessing the upper surface of the substrate 110. Therefore, the sub-drain electrode 190s of the second diode element 520 can be electrically connected to the substrate 110.

[0136] Furthermore, the sub-source electrode 170s of the third diode element 530 can be electrically connected to the third electrode 193. The sub-source electrode 170s of the third diode element 530 can be integrally formed with the third electrode 193. The sub-source electrode 170s of the third diode element 530 can be positioned in the same layer as the third electrode 193 and contains the same material as the third electrode. The sub-drain electrode 190s of the third diode element 530 can pass through the first protective layer 140, the sub-barrier layer 136s, and the sub-channel layer 132s, and is positioned inside a trench formed by recessing the upper surface of the substrate 110. Therefore, the sub-drain electrode 190s of the third diode element 530 can be electrically connected to the substrate 110.

[0137] exist Figure 9 and Figure 10 In this design, multiple diode elements 510, 520, and 530 can be separated from each other via a separation structure 160. For example, the separation structure 160 can be positioned between the first diode element 510 and the second diode element 520, and between the first diode element 510 and the third diode element 530. Through the separation structure 160, the multiple diode elements 510, 520, and 530 can be electrically insulated from each other. In this case, the source electrodes 170s of the first diode element 510, the second diode element 520, and the third diode element 530 can be spaced apart from each other in a first direction (X direction). A first protective layer 140 can be positioned between the source electrodes 170s of the first diode element 510 and the second diode element 520, and between the source electrodes 170s of the second diode element 520 and the third diode element 530; however, this disclosure is not limited thereto.

[0138] The remaining description of the second diode element 520 and the third diode element 530 is substantially the same as that of the first diode element 510 and will not be repeated. The second diode element 520 and the third diode element 530 may have the same structure and shape as the first diode element 510.

[0139] In the following text, reference will be made to Figure 11 to Figure 15 Describe the resistive element of a semiconductor device.

[0140] Figure 11 This illustrates an example of a semiconductor device according to some embodiments and corresponds to Figure 5 A sectional view of line A-A'. Figure 12 This illustrates an example of a semiconductor device according to some embodiments and corresponds to Figure 5 A sectional view of line B-B'. Figure 13 This is a plan view illustrating an example of a semiconductor device according to some embodiments.Figure 14 It is based on some implementation methods along Figure 13 A sectional view taken from line E-E'. Figure 15 This illustrates an example of a semiconductor device according to some embodiments and corresponds to Figure 13 A sectional view of line E-E'.

[0141] Figure 11 to Figure 15 Show Figure 1 to Figure 10 Various embodiments of the semiconductor device 10 shown. Due to Figure 11 to Figure 15 The embodiments shown have many similarities to Figure 1 to Figure 10 The parts that are identical to those in the above embodiments will not be described, and the differences will be the main focus. Furthermore, components that are identical to those in the above embodiments are indicated by the same reference numerals.

[0142] exist Figure 11 In the semiconductor device 10, the first electrode 191 to the third electrode 193 may include multiple electrode layers stacked in a third direction (Z direction). For example, the first electrode 191 may include a first lower electrode layer 191a positioned on the main channel layer 132m and a first upper electrode layer 191b positioned on the first lower electrode layer 191a. The first lower electrode layer 191a may pass through the first protective layer 140 and the main barrier layer 136m and is in contact with the main channel layer 132m. The first upper electrode layer 191b may pass through the second protective layer 210 and is connected to the first lower electrode layer 191a. The lower surface of the first upper electrode layer 191b may be in contact with the first lower electrode layer 191a.

[0143] The second electrode 192 may include a second lower electrode layer 192a positioned on the main channel layer 132m and a second upper electrode layer 192b positioned on the second lower electrode layer 192a. The second lower electrode layer 192a may pass through the first protective layer 140 and the main barrier layer 136m and is in contact with the main channel layer 132m. The second upper electrode layer 192b may pass through the second protective layer 210 and is connected to the second lower electrode layer 192a. The lower surface of the second upper electrode layer 192b may be in contact with the second lower electrode layer 192a.

[0144] The third electrode 193 may include a third lower electrode layer 193a positioned on the main channel layer 132m and a third upper electrode layer 193b positioned on the third lower electrode layer 193a. The third lower electrode layer 193a may pass through the first protective layer 140 and the main barrier layer 136m and is in contact with the main channel layer 132m. The third upper electrode layer 193b may pass through the second protective layer 210 and is connected to the third lower electrode layer 193a. The lower surface of the third upper electrode layer 193b may be in contact with the third lower electrode layer 193a.

[0145] The semiconductor device 10 may further include a second protective layer 210 positioned on the first protective layer 140. The second protective layer 210 may be positioned on the first protective layer 140 and the first lower electrode layers 191a to the third lower electrode layers 193a. The second protective layer 210 may comprise an insulating material. The second protective layer 210 may comprise the same material as the first protective layer 140, but this disclosure is not limited thereto. For example, the second protective layer 210 may comprise an oxide (such as SiO2 or Al2O3). As another example, the second protective layer 210 may comprise a nitride (such as SiN) or an oxide oxynitride (such as SiON).

[0146] exist Figure 11 and Figure 12 In the semiconductor device 10, the sub-source electrode 170s and sub-drain electrode 190s may include multiple layers. For example, the sub-source electrode 170s may include a first sub-source electrode 170s positioned on the sub-channel layer 132s and a second sub-source electrode 170s positioned on the first sub-source electrode 170s. The first sub-source electrode 170s may pass through the first protective layer 140 and the sub-barrier layer 136s and is connected to the sub-channel layer 132s. The second sub-source electrode 170s may pass through the second protective layer 210 and is connected to the first sub-source electrode 170s.

[0147] In some embodiments, the second sub-source electrode 170s may be electrically connected to the sub-gate electrode 150s. Specifically, the second sub-source electrode 170s may include a second connection portion EP2 positioned on the second protective layer 210. The second connection portion EP2 may extend on the second protective layer 210 toward the sub-gate electrode 150s. Additionally, the second connection portion EP2 may be positioned on the sub-gate electrode 150s and located inside the second gate via GV2 passing through the second protective layer 210 and the first protective layer 140. The second connection portion EP2 may completely fill the second gate via GV2. Through the second connection portion EP2, the first sub-source electrode 170s and the sub-gate electrode 150s may be connected to each other. The second connection portion EP2 may be stacked with the sub-gate electrode 150s in the third direction (Z direction).

[0148] In some embodiments, the second sub-source electrode 170s may be positioned on the same layer as the first upper electrode layer 191b and comprises the same material as the first upper electrode layer. The second sub-source electrode 170s may be integrally formed with the first upper electrode layer 191b, but this disclosure is not limited thereto. The second sub-source electrode 170s may be formed simultaneously with the first upper electrode layer 191b in the same process. Alternatively, the first sub-source electrode 170s may be positioned on the same layer as the first lower electrode layer 191a and comprises the same material as the first lower electrode layer.

[0149] Furthermore, the sub-drain electrode 190s may include a first sub-drain electrode 190s positioned on the substrate 110 and a second sub-drain electrode 190s positioned on the first sub-drain electrode 190s. The first sub-drain electrode 190s may pass through the first protective layer 140, the sub-barrier layer 136s, the sub-channel layer 132s, and the buffer layer 120, and is connected to the substrate 110. The second sub-drain electrode 190s may pass through the second protective layer 210 and is connected to the first sub-drain electrode 190s.

[0150] exist Figure 11 and Figure 12 In the diagram, the first electrode 191 to the third electrode 193, the source electrode 170s, and the drain electrode 190s are shown as comprising two layers; however, this disclosure is not limited thereto. For example, the first electrode 191 to the third electrode 193, the source electrode 170s, and the drain electrode 190s may comprise three or more layers.

[0151] exist Figure 13 to Figure 15 In this embodiment, the first electrode 191 of the semiconductor device 10 may be positioned separately from the sub-source electrode 170s. In some embodiments, the first protective layer 140 may be positioned between the first electrode 191 and the sub-source electrode 170s. The separation structure 160 may be positioned between the first electrode 191 and the sub-source electrode 170s; however, this disclosure is not limited thereto.

[0152] The semiconductor device 10 may further include an upper wiring 550 electrically connecting the first electrode 191 and the sub-source electrode 170s. The upper wiring 550 may be positioned on a second protective layer 210, which is positioned on a first protective layer 140. The upper wiring 550 may extend in a second direction (Y direction), but is not limited thereto. The upper wiring 550 may overlap with the first electrode 191 and the sub-source electrode 170s in a third third direction (Z direction). The upper wiring 550 may contact the first electrode 191 and the sub-source electrode 170s. In some embodiments, the upper wiring 550 may be positioned inside a first via 541 passing through the second protective layer 210 on the first electrode 191. Alternatively, the upper wiring 550 may be positioned inside a second via 542 passing through the second protective layer 210 on the sub-source electrode 170s. The upper wiring 550 may completely fill the first via 541 and the second via 542. Therefore, the upper wiring 550 can electrically connect the first electrode 191 and the sub-source electrode 170s.

[0153] exist Figure 15In some embodiments, the upper wiring 550 of the semiconductor device 10 may include a third connection portion EP3. The third connection portion EP3 may extend on the second protective layer 210 toward the sub-gate electrode 150s. Furthermore, the third connection portion EP3 may be positioned on the sub-gate electrode 150s and located inside a third gate via GV3 passing through the second protective layer 210 and the first protective layer 140. The third connection portion EP3 may completely fill the third gate via GV3. The sub-source electrode 170s and the sub-gate electrode 150s may be connected to each other via the third connection portion EP3. The third connection portion EP3 may be superimposed on the sub-gate electrode 150s in the third direction (Z direction); however, this disclosure is not limited thereto.

[0154] In the following text, reference will be made to Figure 16 and Figure 17 Describe the resistive element of a semiconductor device.

[0155] Figure 16 This is a circuit diagram illustrating an example of a semiconductor device according to some embodiments. Figure 17 It shows a reference. Figure 16 A plan view of an example semiconductor device.

[0156] Figure 16 and Figure 17 It shows Figure 1 to Figure 10 Various implementations of semiconductor devices in [the context]. Due to [the context], Figure 16 and Figure 17 The embodiments shown have many similarities to Figure 1 to Figure 10 The parts that are identical to those in the above embodiments will not be described, and the differences will be mainly described. Furthermore, components that are identical to those in the above embodiments are indicated by the same reference numerals.

[0157] exist Figure 16 In the semiconductor device 10, the bidirectional transistor 100 may further include a third transistor 100c and a fourth diode element 540 electrically connected to the third transistor 100c. In some embodiments, the third transistor 100c may include a third terminal D3, a second terminal D2, and a third gate electrode G3. In other words, one electrode of the third transistor 100c may be shared with the second transistor 100b, and the other electrode of the third transistor 100c may be shared with the first transistor 100a. The third transistor 100c may control the current between the third terminal D3 and the second terminal D2 according to a gate signal applied to the third gate electrode G3. In this case, the current may flow bidirectionally between the third terminal D3 and the second terminal D2 according to the potential difference between the third terminal D3 and the second terminal D2. In some embodiments, the third gate electrode G3 may correspond to Figure 17 The third gate electrode ( Figure 17 (See attached figure "153").

[0158] The fourth diode element 540 can be electrically connected to one terminal of the third transistor 100c. The fourth diode element 540 can also be electrically connected to the second terminal D2 of the third transistor 100c and the substrate 110.

[0159] exist Figure 17 In the semiconductor device 10, the bidirectional transistor 100 may further include a fourth electrode 194 and a connection electrode 310 electrically connecting the third gate electrode 153 and the second electrode 192 to the fourth electrode 194. In some embodiments, the fourth electrode 194 and the second electrode 192 may correspond to... Figure 16 The third terminal ( Figure 16 (See the attached figure labeled "D3").

[0160] The fourth electrode 194 can be positioned on the main channel layer 132m. The fourth electrode 194 can be positioned separately from the first electrodes 191 to the third electrodes 193. For example, the fourth electrode 194 can extend in the second direction (Y direction) and be positioned on one side of the third electrode 193 in the first direction (X direction). The first electrodes 191 to the fourth electrode 194 can be arranged in the first direction (X direction). For example, the second electrode 192, the first electrode 191, the third electrode 193, and the fourth electrode 194 can be sequentially positioned in the first direction (X direction). The remaining description of the fourth electrode 194 is consistent with... Figure 1 to Figure 10 The descriptions of the first electrode 191 to the third electrode 193 in the embodiments are substantially the same and will not be repeated.

[0161] The third gate electrode 153 may be positioned on the main barrier layer 136m. The third gate electrode 153 may be positioned between the third electrode 193 and the fourth electrode 194. The third gate electrode 153 may extend in a direction parallel to the fourth electrode 194. The third gate electrode 153 may extend in a second direction (Y direction), but is not limited thereto.

[0162] In some embodiments, the first electrode 191 and the second electrode 192 may be positioned on opposite sides of the first gate electrode 151, and the third electrode 193 and the fourth electrode 194 may be positioned on opposite sides of the third gate electrode 153. In this case, the second gate electrode 152 may be positioned between the second electrode 192 and the third electrode 193.

[0163] A connecting electrode 310 may be positioned on a first protective layer 140, which is positioned on a second electrode 192. The connecting electrode 310 may be positioned inside a third via 320 and a fourth via 330, the third via 320 passing through the first protective layer 140 positioned on the second electrode 192, and the fourth via 330 passing through the first protective layer 140 positioned on the fourth electrode 194. The third via 320 may expose the upper surface of the second electrode 192, and the fourth via 330 may expose the upper surface of the fourth electrode 194. The connecting electrode 310 may fill the third via 320 and the fourth via 330. Therefore, the connecting electrode 310 may contact the second electrode 192 and the fourth electrode 194. The connecting electrode 310 may overlap with the second electrode 192 and the fourth electrode 194 in the third direction (Z direction). In some embodiments, the connecting electrode 310 may be stacked with the first electrode 191, the third electrode 193, the first gate electrode 151, the second gate electrode 152, and the third gate electrode 153 in a third direction (Z direction); however, this disclosure is not limited thereto. Therefore, the fourth electrode 194 and the second electrode 192 may be electrically connected to form a configuration. Figure 16 The second electrode ( Figure 16 (See the attached figure labeled "D2").

[0164] In some embodiments, the semiconductor device 10 may further include a fourth diode element 540 electrically connected to a fourth electrode 194. The fourth diode element 540 may include a sub-source electrode 170s, a sub-gate electrode 150s, and a sub-drain electrode 190s. The sub-source electrode 170s of the fourth diode element 540 may be electrically connected to the fourth electrode 194. The sub-source electrode 170s of the fourth diode element 540 may be integrally formed with the fourth electrode 194; however, this disclosure is not limited thereto. The sub-source electrode 170s of the fourth diode element 540 may be positioned in the same layer as the fourth electrode 194 and may contain the same material as the fourth electrode. The sub-drain electrode 190s of the fourth diode element 540 may pass through the sub-barrier layer 136s, the sub-channel layer 132s, and the buffer layer 120, and is positioned within a trench formed by recessing the upper surface of the substrate 110.

[0165] exist Figure 16 and Figure 17 In the diagram, four electrodes 191 to 194 are shown to constitute a bidirectional transistor 100; however, the number of electrodes constituting the bidirectional transistor 100 is not limited thereto. For example, the bidirectional transistor 100 may include five or more electrodes.

[0166] In the following text, refer to Figure 18 to Figure 19 Describe the resistive element of a semiconductor device.

[0167] Figure 18 This is a circuit diagram illustrating an example of a semiconductor device according to some embodiments.Figure 19 It shows according to the reference Figure 18 A plan view of an example of a semiconductor device in some implementations.

[0168] Figure 18 and Figure 19 Show Figure 16 and Figure 17 Various embodiments of the semiconductor device shown are illustrated. Due to... Figure 18 and Figure 19 The embodiments shown have many similarities to Figure 16 and Figure 17 The parts that are identical to those in the above embodiments will not be described, and the differences will be mainly described. Furthermore, components that are identical to those in the above embodiments are indicated by the same reference numerals.

[0169] exist Figure 18 In the semiconductor device 10, a first transistor 100a, a second transistor 100b, and a third transistor 100c may be included. The first transistor 100a may include a first terminal D1, a second terminal D2, and a first gate electrode G1; the second transistor 100b may include a first terminal D1, a third terminal D3, and a second gate electrode G2; and the third transistor 100c may include a third terminal D3, a second terminal D2, and a third gate electrode G3. Current can flow bidirectionally among the first transistors 100a, 100b, and 100c according to a conduction signal for the first gate electrode G1. For example, according to a conduction signal for the first gate electrode G1, current can flow from the first terminal D1 to the second terminal D2, or from the second terminal D2 to the first terminal D1. According to a conduction signal for the second gate electrode G2, current can flow from the first terminal D1 to the third terminal D3, or from the third terminal D3 to the first terminal D1. According to the turn-on signal for the third gate electrode G3, current can flow from the third terminal D3 to the second terminal D2, or from the second terminal D2 to the third terminal D3.

[0170] exist Figure 19 In this configuration, connecting electrode 310 can electrically connect the second electrode 192 and the fourth electrode 194. Connecting electrode 310 can be positioned on a first protective layer 140, which is positioned on the second electrode 192. Connecting electrode 310 can be positioned inside a third via 320 and a fourth via 330, with the third via 320 passing through the first protective layer 140 positioned on the second electrode 192 and the fourth via 330 passing through the first protective layer 140 positioned on the fourth electrode 194. The remaining description of connecting electrode 310 is consistent with... Figure 17 The description of the connecting electrode 310 is essentially the same and will not be repeated.

[0171] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of the claims, their equivalents, and the claims described later. Specific features described in the context of individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a specific combination, in some cases, one or more features derived from the combination may be removed from the combination, and the combination may be for sub-combinations or variations thereof.

Claims

1. A semiconductor device comprising: a substrate; a bidirectional transistor on the substrate; and a plurality of diode elements electrically connected to the bidirectional transistor, wherein the bidirectional transistor includes: a main channel layer on the substrate; a main barrier layer on the main channel layer, the main barrier layer including a material having a band gap different from a band gap of the main channel layer; a first gate electrode and a second gate electrode on the main barrier layer, the first gate electrode and the second gate electrode spaced apart from each other; a first gate semiconductor layer between the main barrier layer and the first gate electrode; a second gate semiconductor layer between the main barrier layer and the second gate electrode; a first electrode between a first side of the first gate electrode and a first side of the second gate electrode, the first electrode electrically connected to the main channel layer; a second electrode arranged adjacent to a second side of the first gate electrode and spaced apart from the first gate electrode; and a third electrode arranged adjacent to a second side of the second gate electrode and spaced apart from the second gate electrode, and wherein the plurality of diode elements are respectively electrically connected the substrate and the first electrode, the substrate and the second electrode, and the substrate and the third electrode.

2. The semiconductor device according to claim 1, the first gate electrode is between the first electrode and the second electrode, and wherein, wherein the second gate electrode is between the first electrode and the third electrode.

3. The semiconductor device according to claim 2, a distance between the first gate electrode and the first electrode is equal to a distance between the first gate electrode and the second electrode, and wherein wherein a distance between the second gate electrode and the first electrode is equal to a distance between the second gate electrode and the third electrode.

4. The semiconductor device according to claim 1, each of the plurality of diode elements includes: wherein, a sub-channel layer on the substrate; a sub-barrier layer on the sub-channel layer, the sub-barrier layer including a material having a band gap different from a band gap of the sub-channel layer; a sub-gate electrode on the sub-barrier layer; a sub-gate semiconductor layer between the sub-barrier layer and the sub-gate electrode; and a sub-source electrode and a sub-drain electrode on opposite sides of the sub-gate electrode, and wherein the sub-source electrode is electrically connected to the sub-gate electrode. the sub-drain electrode extends into the sub-barrier layer and the sub-channel layer, and is connected to the substrate.

5. The semiconductor device according to claim 4, wherein 6. The semiconductor device according to claim 4, each of the plurality of diode elements further includes a first protective layer on the first gate electrode, wherein, wherein the sub-source electrode includes a connection portion on the first protective layer, and wherein the connection portion extends into the first protective layer, and is connected to the sub-gate electrode.

7. The semiconductor device according to claim 4, the sub-source electrode and the sub-drain electrode extend in a first direction, and are spaced apart from each other in a second direction, wherein wherein the first electrode, the second electrode, and the third electrode extend in the second direction, and wherein the first direction intersects the second direction.

8. The semiconductor device according to claim 4, the sub-channel layer and the main channel layer are in the same layer, wherein wherein the sub-gate electrode, the first gate electrode, and the second gate electrode are in the same layer, and wherein the sub-source electrode, the first electrode, the second electrode, and the third electrode are in the same layer.

9. The semiconductor device according to claim 4, the plurality of diode elements include a first diode element electrically connected the substrate and the first electrode, and wherein ​ wherein the sub-source electrode and the first electrode of the first diode element are in the same layer, and wherein the sub-source electrode comprises the same material as the first electrode.

10. The semiconductor device according to claim 9, wherein the sub-source electrode and the first electrode of the first diode element are integral.

11. The semiconductor device according to claim 9, further comprising: a separation structure between the sub-source electrode and the first electrode of the first diode element, wherein the separation structure extends into the main barrier layer and the main channel layer.

12. The semiconductor device according to claim 9, wherein, the plurality of diode elements comprising: a second diode element electrically connected to the base and a second electrode; and a third diode element electrically connected to the base and a third electrode, wherein the sub-source electrode and the second electrode of the second diode element are integral, and wherein the sub-source electrode and the third electrode of the third diode element are integral.

13. The semiconductor device of claim 12, further comprising: a separation structure extending into the sub-barrier layer, wherein the separation structure is between the first diode element and the second diode element.

14. The semiconductor device according to claim 1, wherein The bidirectional transistor further comprises: a fourth electrode extending into the main barrier layer, the fourth electrode being on the main channel layer and spaced apart from the third electrode; a third gate electrode on the main barrier layer, the third gate electrode being between the third electrode and the fourth electrode; and a connection electrode connecting the second electrode and the fourth electrode.

15. A semiconductor device comprising: a base; a bidirectional transistor on the base; and a first diode element electrically connected to the bidirectional transistor, wherein the bidirectional transistor comprises: a main channel layer on the base; a main barrier layer on the main channel layer, the main barrier layer comprising a material having a different energy band gap than the main channel layer; first and second gate electrodes on the main barrier layer, the first and second gate electrodes being spaced apart from each other; a first gate semiconductor layer between the main barrier layer and the first gate electrode; a second gate semiconductor layer between the main barrier layer and the second gate electrode; a first electrode between a first side of the first gate electrode and a first side of the second gate electrode, the first electrode being electrically connected to the main channel layer; a second electrode arranged adjacent to a second side of the first gate electrode, the second electrode being spaced apart from the first gate electrode; and a third electrode arranged adjacent to a second side of the second gate electrode, the third electrode being spaced apart from the second gate electrode, and wherein the first diode element comprises: a sub-channel layer on the base; a sub-barrier layer on the sub-channel layer, the sub-barrier layer comprising a material having a different energy band gap than the sub-channel layer; a sub-gate electrode on the sub-barrier layer; a sub-gate semiconductor layer between the sub-barrier layer and the sub-gate electrode; and a sub-source electrode and a sub-drain electrode on opposite sides of the sub-gate electrode, the sub-source electrode and the sub-drain electrode being connected to the sub-channel layer, and wherein the sub-source electrode is connected to the sub-gate electrode and is integral with the first electrode.

16. The semiconductor device according to claim 15, wherein the sub-drain electrode extending into the sub-barrier layer and the sub-channel layer, and wherein the sub-drain electrode is connected to the base.

17. The semiconductor device according to claim 15, wherein the sub-channel layer and the main channel layer are in the same layer, wherein the sub-gate electrode, the first gate electrode, and the second gate electrode are in the same layer, and wherein the sub-source electrode, the first electrode, the second electrode, and the third electrode are in the same layer.

18. The semiconductor device according to claim 15, wherein the first gate electrode is between the first electrode and the second electrode, and wherein the second gate electrode is between the first electrode and the third electrode.

19. The semiconductor device according to claim 18, wherein, a distance between the first gate electrode and the first electrode is equal to a distance between the first gate electrode and the second electrode, and wherein a distance between the second gate electrode and the first electrode is equal to a distance between the second gate electrode and the third electrode.

20. A semiconductor device comprising: a substrate; a main channel layer on the substrate; a main barrier layer on the main channel layer, the main barrier layer including a material having a different energy band gap than an energy band gap of the main channel layer; first, second, and third gate electrodes on the main barrier layer, the first, second, and third gate electrodes being spaced apart from each other; a protective layer on the main barrier layer, the protective layer covering the first, second, and third gate electrodes; first and second electrodes extending into the protective layer and the main barrier layer, the first and second electrodes being on the main channel layer and on opposite sides of the first gate electrode; third and fourth electrodes extending into the protective layer and the main barrier layer, the third and fourth electrodes being on the main channel layer and on opposite sides of the third gate electrode; and a connecting electrode on the protective layer, the connecting electrode connecting the second electrode and the fourth electrode, wherein the second gate electrode is between the second electrode and the third electrode. ​

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