Semiconductor device

Abstract

The invention provides a semiconductor device capable of adjusting a cathode voltage of a diode to a proper voltage even if a high voltage is applied to an N-type high potential region. The semiconductor device (51) includes N-type semiconductor regions (21, 22) selectively provided in an upper layer portion of the N-type high withstand voltage separation region (2), and a P-type semiconductor region (31) selectively provided in an upper layer portion of the N-type high withstand voltage separation region (2) and to which a power supply voltage (V1) lower than the power supply voltage (V2) is supplied. The N-type semiconductor region (22) is disposed closer to the N-type high-potential region (3) than the N-type semiconductor region (21) and the P-type semiconductor region (31), and the P-type semiconductor region (31) is disposed between the N-type semiconductor region (21) and the N-type high-potential region (3) in plan view. A power supply voltage (V2) is supplied to the anode of the diode (D4), the cathode of the diode (D4) is electrically connected to the N-type semiconductor region (21), and the N-type semiconductor region (22) is electrically connected to the N-type high potential region (3).

Description

Technical Field

[0001] This disclosure relates to a semiconductor device including an N-type high-potential region with a high-voltage side drive circuit. Background Technology

[0002] As an existing semiconductor device that includes a high-voltage side drive circuit and includes an N-type high-potential region, there is, for example, the semiconductor device disclosed in Patent Document 1.

[0003] In the semiconductor device disclosed in Patent Document 1, a high-voltage holding section is provided for the purpose of supplying voltage to an N-type high-potential region equipped with a high-voltage side drive circuit (high-voltage floating circuit), so that a high voltage is not applied to the cathode of the bootstrap diode when a high voltage is supplied to the high-voltage side drive circuit. The anode of the bootstrap diode is connected to the low-voltage side drive circuit. Existing technical documents Patent documents

[0004] Patent Document 1: Japanese Patent Application Publication No. 2004-47937 Summary of the Invention The technical problem that the invention aims to solve

[0005] In conventional semiconductor devices, such as the semiconductor device disclosed in Patent Document 1, the n-type high-voltage element portion surrounding the cathode connected to the diode is... + layer p + Layer fixed to p - The substrate is at the same potential, and the depletion layer is expanded to mitigate the electric field.

[0006] Existing semiconductor devices with this structure cannot adjust the expansion of the depletion layer, thus presenting the following problem: the cathode voltage applied to the diode's cathode cannot be suppressed to an appropriate voltage that is not too high.

[0007] Existing semiconductor devices have the above-mentioned problems, and therefore cannot cope with product performance deviations caused by manufacturing process variations, thus limiting layout design.

[0008] This disclosure was made to solve the above-mentioned problems, and its purpose is to provide a semiconductor device that can be adjusted so that the cathode voltage of the diode is an appropriate voltage even when a higher voltage is applied to the N-type high potential region. Technical means for solving technical problems

[0009] The semiconductor device according to the present disclosure includes: a P-type semiconductor layer; an N-type high-potential region provided on the P-type semiconductor layer; an N-type high-withstand voltage separation region provided on the P-type semiconductor layer so as to surround the N-type high-potential region in plan view; a diode region provided on the P-type semiconductor layer independently of the N-type high-withstand voltage separation region, the diode region having a diode that supplies a second voltage higher than a first voltage to an anode; a first N-type semiconductor region and a second N-type semiconductor region selectively provided in an upper layer portion of the N-type high-withstand voltage separation region; and a P-type semiconductor region selectively provided in the upper layer portion of the N-type high-withstand voltage separation region, the P-type semiconductor region supplying the first voltage lower than the second voltage, wherein an N-type impurity concentration of the first N-type semiconductor region and the second N-type semiconductor region is set to be higher than an N-type impurity concentration of the N-type high-withstand voltage separation region, the first N-type semiconductor region and the second N-type semiconductor region and the P-type semiconductor region are provided without contact with each other, the second N-type semiconductor region is disposed closer to the N-type high-potential region than the first N-type semiconductor region and the P-type semiconductor region, the P-type semiconductor region is disposed between the first N-type semiconductor region and the N-type high-potential region in plan view, a cathode of the diode is electrically connected to the first N-type semiconductor region, and the second N-type semiconductor region is electrically connected to the N-type high-potential region. Effects of the Invention

[0010] In the semiconductor device according to the present disclosure, the first voltage applied to the P-type semiconductor region is set to be lower than the second voltage applied to the first N-type semiconductor region, and thus a reverse bias can be applied between the P-type semiconductor region and the N-type high-withstand voltage separation region.

[0011] Therefore, the electric field of the peripheral region of the first N-type semiconductor region electrically connected to the cathode of the diode can be moderated by a depletion layer generated at an interface between the P-type parallel region of the P-type semiconductor region and the N-type high-withstand voltage separation region.

[0012] Therefore, even if a high-potential-side power supply voltage higher than the second voltage is applied to the first electrode for the high-potential-side power supply voltage, the value of the first voltage can be adjusted so that the cathode voltage applied to the cathode of the diode becomes an appropriate voltage that is not excessively high.

[0013] Further, even if the condition that the cathode voltage becomes an appropriate voltage differs between devices due to a variation in product performance, the semiconductor device according to the present disclosure can adjust the value of the first voltage for each product, and thus the variation in product performance can be suppressed, and improvement in the device failure rate can be attempted. Attached Figure Description

[0014] Figure 1 This is an explanatory diagram schematically showing the planar structure of the semiconductor device according to Embodiment 1 of the present disclosure. Figure 2 This is an explanatory diagram schematically showing the planar structure of the semiconductor device according to Embodiment 2 of the present disclosure. Figure 3 This is an explanatory diagram schematically showing the planar structure of the semiconductor device according to Embodiment 3 of the present disclosure. Figure 4 This is an explanatory diagram schematically showing the planar structure of the semiconductor device according to Embodiment 4 of this disclosure. Figure 5 This is an explanatory diagram schematically showing the planar structure of a semiconductor device according to the first embodiment of the present disclosure 5. Figure 6 This is an explanatory diagram schematically showing the planar structure of a semiconductor device according to the second embodiment of the present disclosure 5. Figure 7 This is an explanatory diagram schematically showing the planar structure of a semiconductor device according to the first embodiment of 6 of this disclosure. Figure 8 This is an explanatory diagram schematically showing the planar structure of a semiconductor device according to the second embodiment of this disclosure 6. Figure 9 This is an explanatory diagram schematically showing the planar structure of a semiconductor device according to the third embodiment of this disclosure 6. Figure 10 This is an explanatory diagram schematically showing the planar structure of a semiconductor device according to the first embodiment of 7 of this disclosure. Figure 11 This is an explanatory diagram schematically showing the planar structure of a semiconductor device according to the second embodiment of this disclosure 7. Figure 12 This is an explanatory diagram schematically showing the planar structure of a semiconductor device according to the third embodiment of this disclosure 7. Figure 13 This is a cross-sectional view showing the basic structure of a semiconductor device including an N-type high-potential region with a high-voltage side drive circuit. Detailed Implementation

[0015] <Basic Techniques> Figure 13 This is a cross-sectional view showing the basic structure of a semiconductor device including an N-type high-potential region with a high-voltage side drive circuit. Figure 13 It corresponds to the one disclosed in Patent Document 1. Figure 2 The attached diagrams are as follows.

[0016] As shown in the figure, a bootstrapping method is illustrated, which utilizes the diode D3 region 206 and the n-voltage island. - The drift layer Rn region 208 is mounted on a single high-voltage IC chip. - The drift layer Rn region 208 functions as a high-voltage holding part.

[0017] One end of the external capacitor C1 connected between the VB terminal and the VS terminal is connected via n on a single-chip IC. - The drift layer Rn and diode D3 region 206 are connected to, for example, a power supply voltage of 15V, Vcc.

[0018] Therefore, in Figure 13 In the monolithic high-voltage IC shown, the anode p of diode D3 region 206 is... + Layer 221 is connected to the power supply voltage Vcc. Then, current flows from the cathode n... + Layer 222 via n - The drift layer Rn flows to the external capacitor C1 to charge the external capacitor C1. Figure 13 The monolithic high-voltage IC shown provides a way to use the charging voltage of the external capacitor C1 as the power supply voltage for the high-voltage side drive circuit, thus eliminating the need for a separate high-voltage side floating power supply.

[0019] Figure 13 The cross-sectional structure of the bootstrap circuit shown includes diode D3 region 206 and high-voltage island n. - The drift layer region 208 and the high-voltage side driving CMOS transistor region 209, within the diode D3 region 206, enable the embedded n + Layer 110 is between n - Semiconductor layer 106 and p - Between substrates 105. The CMOS transistor region 209 for high-voltage side drive is provided with a high-voltage floating circuit as a high-voltage side drive circuit.

[0020] Furthermore, in the high-pressure island n - The drift layer region 208 is equipped with p - substrate 105 at the same potential p + Layers 213 and 214 are used to extend the depletion layer and mitigate n. + The electric field is concentrated in region 212. Furthermore, this causes diode D3 in region 206 to be connected to the high-voltage island n. - drift layer region 208 joint separation p + Diffusion region 218 forms as an interlayer insulating film in n - Within semiconductor layer 106, until p is reached - up to the depth of substrate 105.

[0021] Based on the cross-sectional structure of this bootstrap circuit, it can be seen that in region 206 of diode D3, n... - An anode p is disposed within the semiconductor layer 106. + Layer 221 and cathode n + Layer 222, making the embedding n + Layer 110 is located in region 206 of diode D3. - Semiconductor layer 106 and p - Between substrates 105, the base concentration is increased to reduce the HFE of the parasitic PNP transistor and suppress its conduction. This prevents current from flowing from the anode p... + Layer 221 via diode D3 region 206 n - Semiconductor layer 106 in p - The flow is in the direction of substrate 105.

[0022] On the other hand, high-pressure island n - The drift layer region 208 employs a Multiple Floating Field Plate (MFFP). That is, the high-pressure island n - Drift layer Rn region 208 is set in the n of the high-pressure island - n on the high potential side within semiconductor layer 106 + Layer 211 and the n of the opening + Both sides of layer 212 are fixed to p. - A pair of p-type substrates 105 at the same potential (GND) + Surrounded by layers 213 and 214, thus diffusing and depleting the layer, and causing the opening n + The electric field concentration in layer 212 is mitigated. Therefore, when the power element on the high-voltage side is turned on and the power element on the low-voltage side is turned off, the opening n... + Layer 212 becomes a floating potential, but can suppress this potential to a low potential and maintain a high voltage.

[0023] Therefore, in the context of Figure 13 In the bootstrap method of the semiconductor device shown in the basic technology, the diode D3 region 206 and the high-voltage island n are configured to... - The drift layer region 208 is mounted on a high-voltage IC chip, thereby effectively reducing circuit current consumption. Furthermore, Figure 13 In the middle, the diode D3 region 206 and the high voltage island n are used. - The drift layer Rn region 208 has a bonded and separated structure, which allows it to be mounted on a single high-voltage IC chip.

[0024] In Figure 13 The basic technology shown represents existing semiconductor devices, as described above, where a pair of p +The potentials of layers 213 and 214 are fixed at p - The substrate 105 has the same potential (GND). Therefore, conventional semiconductor devices cannot adjust the expansion of the depletion layer, resulting in the problem that the cathode voltage applied to the cathode of diode D3 cannot be adjusted to be an appropriate voltage that is not too high. The embodiments 1 to 7 of this disclosure described below attempt to solve this problem.

[0025] <Implementation Method 1> Figure 1 This is an explanatory diagram schematically showing the planar structure of the semiconductor device 51 according to Embodiment 1 of this disclosure.

[0026] As shown in the figure, the semiconductor device 51 of Embodiment 1 includes a P-type semiconductor layer 1, an N-type high-voltage separation region 2, an N-type high-potential region 3 and a diode region 4 disposed on the P-type semiconductor layer 1, a power supply 11 and a power supply 12, and a capacitor C3 as the main structural elements.

[0027] Figure 1 The P-type semiconductor layer 1, N-type high-voltage separation region 2, N-type high-potential region 3, and diode region 4 shown correspond, for example, to... Figure 13 p shown - Substrate 105, High Voltage Island n - Drift layer region 208 (n) - Semiconductor layer 106), CMOS transistor region 209 for high-voltage side drive (n) - Semiconductor layer 106) and diode D3 region 206.

[0028] The N-type high-voltage separation region 2 is disposed on the P-type semiconductor layer 1 and completely surrounds the N-type high-potential region 3 when viewed from above. That is, the N-type high-voltage separation region 2 surrounds the N-type high-potential region 3 when viewed from above, thereby enabling, for example, a reduced surface electric field structure.

[0029] Diode region 4 is independently disposed on the P-type semiconductor layer 1, separate from N-type high-voltage separation region 2 and N-type high-potential region 3, and contains diode D4 internally. Diode D4 is a bootstrap diode, and its anode is connected to... Figure 1 The low-voltage side drive circuit is not shown in the diagram.

[0030] The N-type high-potential region 3 has a power supply electrode 5, which serves as the first electrode for the high-potential side power supply voltage VB, and a reference electrode 6, which serves as the second electrode for the high-potential side reference voltage VS.

[0031] The upper part of the N-type high-voltage separation region 2 is selectively provided with N-type semiconductor regions 21 and 22, which serve as the first N-type semiconductor region and the second N-type semiconductor region.

[0032] The upper part of the N-type high-voltage separation region 2 is selectively provided with a P-type semiconductor region 31. The N-type semiconductor regions 21 and 22 and the P-type semiconductor region 31 are disposed on the upper part of the N-type high-voltage separation region 2 and do not have contact with each other.

[0033] Figure 1 The cross-sectional structures of the N-type semiconductor regions 21 and 22 shown are, for example, equivalent to Figure 13 The n shown + Regions 212 and n + Layer 211. Figure 1 The cross-sectional structure of the P-type semiconductor region 31 shown is, for example, equivalent to Figure 13 p shown + Layer 214.

[0034] The N-type impurity concentrations in N-type semiconductor regions 21 and 22 are set to be higher than those in N-type high-voltage separation region 2, and the P-type impurity concentration in P-type semiconductor region 31 is set to be higher than those in P-type semiconductor layer 1.

[0035] The N-type high-potential region 3 appears as a quadrilateral, which is more than a triangle, when viewed from above. Figure 1 The N-type high-potential region 3 shown has a rectangular shape with a relatively long lateral length when viewed from above. The N-type semiconductor region 22 is positioned closer to the N-type high-potential region 3 than the N-type semiconductor region 21 and the P-type semiconductor region 31. That is, when viewed from above, the N-type semiconductor region 22 is positioned inside the N-type semiconductor region 21.

[0036] The N-type semiconductor region 21 has a first N-type parallel region that, when viewed from above, is parallel to at least one side of the N-type high-potential region 3. The aforementioned at least one side becomes parallel to... Figure 1 Any one of the corresponding edges on the right, left, and bottom of the N-type high-potential region 3 shown.

[0037] When viewed from above, the N-type semiconductor region 22 is disposed between the N-type high-potential region 3 and the N-type semiconductor region 21. The N-type semiconductor region 22 has a second N-type parallel region that is parallel to at least one side of the N-type high-potential region 3 when viewed from above. The aforementioned at least one side is common between the N-type semiconductor regions 21 and 22.

[0038] Furthermore, the P-type semiconductor region 31 has a P-type parallel region that, when viewed from above, is parallel to at least one side of the N-type high-potential region 3. This at least one side is a common side between the N-type semiconductor regions 21 and 22 and the P-type semiconductor region 31.

[0039] The entire region of the P-type semiconductor region 31, when viewed from above, is positioned between the N-type semiconductor region 21, which is a first N-type semiconductor region, and the N-type semiconductor region 22, which is a second N-type semiconductor region. Therefore, the P-type parallel region of the P-type semiconductor region 31, when viewed from above, is positioned between the first N-type parallel region of the N-type semiconductor region 21 and the second N-type parallel region of the N-type semiconductor region 22. The aforementioned P-type semiconductor region 31, when viewed from above, is positioned between the N-type semiconductor region 21 and the N-type high-potential region 3.

[0040] Figure 1 In terms of appearance, the first N-type parallel region, the second N-type parallel region, and the P-type parallel region together form a region parallel to the three sides (right, left, and top) of the N-type high-potential region 3. In this specification, the feature of Embodiment 1 is described as follows: "The first N-type parallel region of the N-type semiconductor region 21, the second N-type parallel region of the N-type semiconductor region 22, and the P-type parallel region of the P-type semiconductor region 31 are all parallel to at least one side of the N-type high-potential region 3 as described above."

[0041] Furthermore, in the N-type high-voltage separation region 2, in the gap region where N-type semiconductor regions 21 and 22 and P-type semiconductor region 31 are not formed, a transmission element for transmitting signals between the low-voltage side drive circuit and the high-voltage side drive circuit (high-voltage floating circuit) is provided, for example. The high-voltage side drive circuit is located in the N-type high-potential region 3.

[0042] Power supply 11, serving as the first power supply, provides a power supply voltage V1 as the first voltage. Power supply 12, serving as the second power supply, provides a power supply voltage V2 as the second voltage. Furthermore, the power supply voltage V1 is set to be lower than the power supply voltage V2. Specifically, when the voltage drop across diode D4 is set to VF, it is set to satisfy {V1 < (V2 - VF)}.

[0043] The power supply voltage V1 supplied from power source 11 is applied to the P-type semiconductor region 31 via wiring L1. Specifically, one end of wiring L1 is electrically connected to node P1 on the P-type semiconductor region 31, and the other end of wiring L1 is electrically connected to the positive terminal of power source 11. Furthermore, the negative terminal of power source 11 is electrically connected to ground, which serves as a reference potential. Additionally, the power supply voltage V1 from power source 11 is not supplied to the P-type semiconductor layer 1.

[0044] The power supply voltage V2 supplied from power supply 12 is applied to the anode of diode D4 via wiring L2. That is, node P2 on wiring L2 is electrically connected to the anode of diode D4, and the positive terminal of power supply 12 is electrically connected to wiring L2. In addition, the negative terminal of power supply 12 is electrically connected to the ground level, which serves as a reference potential.

[0045] The cathode of diode D4 is electrically connected to the N-type semiconductor region 21 via wiring L22. That is, the cathode of diode D4 is electrically connected to one end of wiring L22, and node P13 on the N-type semiconductor region 21 is electrically connected to the other end of wiring L22.

[0046] Therefore, the cathode of diode D4 is electrically connected to the N-type high-potential region 3 via a high-voltage splitter element. The "high-voltage splitter element" refers to the region within the N-type high-voltage splitter region 2 that provides the electrical connection between N-type semiconductor regions 21 and 22. For example, a "high-voltage splitter element" corresponds to... Figure 13 The basic technology shown in n - Drift layer Rn.

[0047] The N-type semiconductor region 22 is electrically connected to the power supply electrode 5, which serves as the first electrode, via wiring L21. That is, one end of wiring L21 is electrically connected to node P12 on the N-type semiconductor region 22, and the other end of wiring L21 is electrically connected to node P11 on the power supply electrode 5. Thus, the N-type semiconductor region 22 is electrically connected to the N-type high-potential region 3.

[0048] One electrode of capacitor C3, which is an external charging element, is electrically connected via wiring L3 to power electrode 5, which is the first electrode of N-type high-potential region 3, and the other electrode is connected via wiring L4 to reference electrode 6, which is the second electrode of N-type high-potential region 3.

[0049] That is, one end of wiring L3 is electrically connected to node P3 on power supply electrode 5, and the other end of wiring L3 is electrically connected to one electrode of capacitor C3. One end of wiring L4 is electrically connected to node P4 on reference electrode 6, and the other end of wiring L4 is electrically connected to the other electrode of capacitor C3.

[0050] A bootstrap circuit can be constructed using capacitor C3 and diode D4. Therefore, the charge applied to capacitor C3 can drive the high-potential side drive circuit located in the N-type high-potential region 3.

[0051] Furthermore, the electrical connection between power supplies 11 and 12 and capacitor C3 is not limited to the method described above using wiring L1 to L4 and L22; any method can be considered. For example, pattern wiring provided on the P-type semiconductor layer 1 can be provided, and wire wiring can be used to attempt to achieve electrical connection with the external power supply (equivalent to power supplies 11 and 12) and capacitor C3 via electrode pads provided on the power supply electrode 5 or reference electrode 6.

[0052] In the semiconductor device 51 of Embodiment 1, the first voltage applied to the P-type semiconductor region 31, i.e., the power supply voltage V1, is set to be lower than the second voltage applied to the N-type semiconductor region 21, i.e., the power supply voltage V2. Therefore, a reverse bias can be applied between the P-type semiconductor region 31 and the N-type high-voltage separation region 2.

[0053] Therefore, the depletion layer generated at the interface between the P-type parallel region of the P-type semiconductor region 31 and the N-type high-voltage separation region 2 can mitigate the electric field around the N-type semiconductor region 21 that is electrically connected to the cathode of the diode D4.

[0054] Therefore, even if a high-potential side power supply voltage VB, which is higher than the power supply voltage V2, is applied to the power supply electrode 5, the value of the power supply voltage V1, which is the first voltage, can be adjusted so that the cathode voltage applied to the cathode of the diode D4 constituting the bootstrap circuit becomes an appropriate voltage that is not too high.

[0055] This is because the power supply voltage V1 provided from power supply 11 is used as a dedicated setting voltage for the P-type semiconductor region 31. That is, as Figure 13 The basic technology shown is a pair of p + As with the set potentials of layers 213 and 214, the power supply voltage V1 is not fixed to p. - Limitation of the same potential of substrate 105.

[0056] Therefore, the semiconductor device 51 of Embodiment 1 can change the power supply voltage V1 without being limited as described above, and thus can adjust the extension of the depletion layer with high precision so that the cathode voltage of the diode D4 becomes an appropriate voltage. Therefore, the freedom of layout design of the semiconductor device 51 is also improved.

[0057] Furthermore, even when the cathode voltage of diode D4 is at an appropriate voltage, and this condition varies between devices due to product performance deviations, the semiconductor device 51 of Embodiment 1 can adjust the power supply voltage V1 individually per device unit, thereby suppressing product performance deviations and striving to improve device defect rates.

[0058] Furthermore, the semiconductor device 51 in Embodiment 1 is configured as a bootstrap circuit including a diode D4 and a capacitor C3 as a charging element, thereby enabling the charging voltage charged to the capacitor C3 to discharge and drive the high-potential side region circuit provided in the N-type high-potential region 3.

[0059] <Implementation Method 2> Figure 2 This is an explanatory diagram schematically showing the planar structure of the semiconductor device 52 according to Embodiment 2 of this disclosure.

[0060] As shown in the figure, the semiconductor device 52 of Embodiment 2 is similar to that of Embodiment 1, including a P-type semiconductor layer 1, an N-type high-voltage separation region 2, an N-type high-potential region 3 and a diode region 4 disposed on the P-type semiconductor layer 1, power supplies 11 and 12 and a capacitor C3 as the main structural elements.

[0061] The semiconductor device 52 of embodiment 2 has Figure 1 In addition to all the features of the semiconductor device 51 of Embodiment 1 shown, it also has the following features.

[0062] The N-type semiconductor region 21 has a first N-type parallel region that, when viewed from above, is parallel to the three sides of the N-type high-potential region 3. These three sides become parallel to the three sides of the N-type high-potential region 3. Figure 2 The right, left, and bottom edges of the N-type high-potential region 3 are shown. Furthermore, the first N-type parallel region has a region parallel to a portion of the upper edge of the N-type high-potential region 3.

[0063] Thus, the N-type semiconductor region 21 has a first N-type parallel region that is parallel to at least three sides of the N-type high-potential region 3 when viewed from above. Therefore, the N-type semiconductor region 21 surrounds more than three-quarters of the outer perimeter of the N-type high-potential region 3 when viewed from above.

[0064] The N-type semiconductor region 22 has a second N-type parallel region that, when viewed from above, is parallel to the aforementioned three sides of the N-type high-potential region 3. The aforementioned three sides are parallel to... Figure 2 The right, left, and bottom edges of the N-type high-potential region 3 are shown. Furthermore, the second N-type parallel region has a region parallel to a portion of the upper edge of the N-type high-potential region 3.

[0065] Thus, the N-type semiconductor region 22 has a second N-type parallel region that is parallel to at least three sides of the N-type high-potential region 3 when viewed from above. These at least three sides are common to the N-type semiconductor regions 21 and 22. Therefore, the N-type semiconductor region 22, when viewed from above, surrounds more than three-quarters of the outer perimeter of the N-type high-potential region 3.

[0066] The P-type semiconductor region 31 has a P-type parallel region that, when viewed from above, is parallel to the aforementioned three sides of the N-type high-potential region 3. These three sides are parallel to... Figure 2 The right, left, and bottom edges of the N-type high-potential region 3 are shown. Furthermore, the P-type parallel region has a region parallel to a portion of the upper edge of the N-type high-potential region 3.

[0067] Thus, the P-type semiconductor region 31 has a P-type parallel region that, when viewed from above, is parallel to at least three sides of the N-type high-potential region 3. These at least three sides are common to both the N-type semiconductor regions 21 and 22 and the P-type semiconductor region 31. Therefore, the P-type semiconductor region 31, when viewed from above, surrounds more than three-quarters of the outer perimeter of the N-type high-potential region 3.

[0068] Therefore, the semiconductor device 52 of Embodiment 2 is characterized as follows: Figure 2 As shown, "the first N-type parallel region of the N-type semiconductor region 21, the second N-type parallel region of the N-type semiconductor region 22, and the P-type parallel region of the P-type semiconductor region 31 are all parallel to at least three sides of the N-type high-potential region 3".

[0069] When viewed from above, the entire P-type semiconductor region 31 is positioned between N-type semiconductor regions 21 and 22. Therefore, when viewed from above, the P-type parallel region of the P-type semiconductor region 31 is positioned between the first N-type parallel region of the N-type semiconductor region 21 and the second N-type parallel region of the N-type semiconductor region 22.

[0070] Therefore, in the semiconductor device 52 of Embodiment 2, the N-type semiconductor regions 21 and 22 and the P-type semiconductor region 31 are configured to surround more than half of the outer periphery of the N-type high-potential region 3 when viewed from above. Furthermore, the P-type semiconductor region 31 is configured to surround more than half of the outer periphery of the N-type semiconductor region 22, and the N-type semiconductor region 21 is configured to surround more than half of the outer periphery of the P-type semiconductor region 31.

[0071] In the semiconductor device 52 of Embodiment 2, the first voltage applied to the P-type semiconductor region 31, i.e., the power supply voltage V1, is set to be lower than the second voltage applied to the N-type semiconductor region 21, i.e., the power supply voltage V2. Therefore, a reverse bias can be applied between the P-type semiconductor region 31 and the N-type high-voltage separation region 2.

[0072] Therefore, the semiconductor device 52 of Embodiment 2 can mitigate the electric field around the N-type semiconductor region 21 that is electrically connected to the cathode of the diode D4 by generating a depletion layer at the interface between the P-type parallel region of the P-type semiconductor region 31 and the N-type high-voltage separation region 2.

[0073] Therefore, the semiconductor device 52 of Embodiment 2, like that of Embodiment 1, can increase the freedom of layout design of the semiconductor device 52, suppress deviations in product performance, and strive to improve the defect rate of the device.

[0074] Furthermore, in Embodiment 2, the P-type parallel region of the P-type semiconductor region 31, and the first N-type parallel region and the second N-type parallel region of the N-type semiconductor regions 21 and 22 become regions parallel to at least three sides of the N-type high-potential region 3. These at least three sides are common to the N-type semiconductor regions 21 and 22 and the P-type semiconductor region 31.

[0075] Therefore, a first N-type parallel region, a second N-type parallel region, and a P-type parallel region exist at equal intervals from the at least three sides of the N-type high-potential region 3. Furthermore, in the semiconductor device 52 of Embodiment 2, when a reverse bias is applied between the P-type semiconductor region 31 and the N-type high-voltage separation region 2, a depletion layer is provided along the P-type parallel regions of the P-type semiconductor region 31 that are parallel to the at least three sides of the N-type high-potential region 3.

[0076] As a result, the semiconductor device 52 of Embodiment 2 can uniformly set the electric field around the N-type semiconductor regions 21 and 22 and the P-type semiconductor region 31, respectively. Correspondingly, the adjustment accuracy of the cathode voltage of the diode D4 is improved, and the reliability of the device is improved compared with Embodiment 1. This will be explained in detail below.

[0077] The P-type parallel region of the P-type semiconductor region 31 is parallel to at least three sides of the N-type high-potential region 3, therefore, the distance from the N-type high-potential region 3 to the P-type parallel region of the P-type semiconductor region 31 is equal. Consequently, the electric field becomes uniform at locations such as the P-type parallel region of the P-type semiconductor region 31, and the depletion layer extending toward the N-type semiconductor region 21 also expands in the same manner. Therefore, by applying a power supply voltage V1 to the P-type semiconductor region 31, the cathode voltage of the diode D4 can be adjusted with high precision.

[0078] Furthermore, in the semiconductor device 51 of Embodiment 1, the P-type parallel region of the P-type semiconductor region 31 is also parallel to at least one side of the N-type high-potential region 3, thus achieving the effect that the electric field becomes uniform at any point in the P-type parallel region. In addition, to further improve the uniformity of the extension direction of the depletion layer, it is preferable that the formation widths of the P-type semiconductor region 31, the N-type semiconductor regions 21, and 22 are each equal.

[0079] Furthermore, the N-type semiconductor regions 21 and 22 and the P-type semiconductor region 31 of the semiconductor device 52 constituting Embodiment 2 are configured to surround more than half of the outer periphery of the N-type high-potential region 3 when viewed from above.

[0080] Therefore, the semiconductor device 52 of Embodiment 2 can mitigate the electric field in the surrounding area of ​​the N-type semiconductor region 21 by generating a depletion layer over a wide range at the boundary between the P-type semiconductor region 31 and the N-type high-voltage separation region 2, thereby improving the cathode voltage suppression capability of the diode D4 accordingly.

[0081] Furthermore, the N-type semiconductor regions 21 and 22 and the P-type semiconductor region 31 of the semiconductor device 52 constituting Embodiment 2 surround the N-type high-potential region 3 in a range exceeding 3 / 4 of its outer periphery when viewed from above. Therefore, the cathode voltage suppression capability of the diode D4 can be further improved.

[0082] Furthermore, in order to cut off the current path between the N-type semiconductor regions 21 and 22 and to fully utilize the cathode voltage suppression effect of the diode D4, it is preferable to set the range of the P-type semiconductor region 31 surrounding the N-type high-potential region 3 to the same extent as the range of the N-type semiconductor regions 21 and 22 surrounding the N-type high-potential region 3.

[0083] <Implementation Method 3> Figure 3 This is an explanatory diagram schematically showing the planar structure of the semiconductor device 53 according to Embodiment 3 of this disclosure.

[0084] As shown in the figure, the semiconductor device 53 of Embodiment 3, like that of Embodiments 1 and 2, includes a P-type semiconductor layer 1, an N-type high-voltage separation region 2, an N-type high-potential region 3 and a diode region 4 disposed on the P-type semiconductor layer 1, power supplies 11 and 12 and a capacitor C3 as the main structural elements.

[0085] The following is about... Figure 1 and Figure 2 The same structures shown in Embodiment 1 and Embodiment 2 are labeled with the same reference numerals and descriptions are omitted as appropriate. The description will focus on the characteristic parts of the semiconductor device 53 in Embodiment 3.

[0086] Compared with Embodiments 1 and 2, the semiconductor device 53 of Embodiment 3 is characterized by having a P-type semiconductor region group 31G instead of the P-type semiconductor region 31. That is, the P-type semiconductor region group 31G becomes the P-type semiconductor region in the semiconductor device 53 of Embodiment 3. Figure 3 The cross-sectional structure of the P-type semiconductor region group 31G shown is the same as that of the P-type semiconductor region 31 shown in Embodiment 1 and Embodiment 2.

[0087] The P-type semiconductor region group 31G is composed of a plurality of P-type partial semiconductor regions 41 disposed separately from each other. In addition, the P-type impurity concentration of each of the plurality of P-type partial semiconductor regions 41 in the P-type semiconductor region group 31G is set to be higher than the P-type impurity concentration of the P-type semiconductor layer 1.

[0088] Similar to the P-type semiconductor region 31 in Embodiment 2, the P-type semiconductor region group 31G has a P-type parallel region that, when viewed from above, is parallel to the three sides of the N-type high-potential region 3. These three sides are parallel to the three sides of the N-type high-potential region 3. Figure 3 The right, left, and bottom edges of the N-type high-potential region 3 are shown. Furthermore, the P-type parallel region has a region parallel to a portion of the upper edge of the N-type high-potential region 3.

[0089] Therefore, the P-type semiconductor region group 31G has a P-type parallel region that is parallel to at least three sides of the N-type high-potential region 3 when viewed from above. These at least three sides are common to the N-type semiconductor regions 21 and 22 and the P-type semiconductor region group 31G. Thus, the P-type semiconductor region group 31G, when viewed from above, encloses more than three-quarters of the outer perimeter of the N-type high-potential region 3.

[0090] In the P-type semiconductor region group 31G, there is a relay wiring 25 that is electrically connected to a plurality of P-type partial semiconductor regions 41 respectively. The relay wiring 25 is electrically connected to wiring L1 via node P1.

[0091] Therefore, the power supply voltage V1 supplied from the power supply 11 is applied to the plurality of P-type partial semiconductor regions 41 constituting the P-type semiconductor region group 31G via the relay wiring 25.

[0092] In the semiconductor device 53 of embodiment 3 of this structure, the power supply voltage V1 applied to the P-type semiconductor region group 31G is set to be lower than the power supply voltage V2 applied to the N-type semiconductor region 21. Therefore, a reverse bias can be applied between the P-type semiconductor region group 31G and the N-type high-voltage separation region 2.

[0093] Therefore, similar to Embodiments 1 and 2, the semiconductor device 53 of Embodiment 3 can mitigate the electric field around the N-type semiconductor region 21 by generating a depletion layer at the interface between the P-type semiconductor region group 31G and the N-type high-voltage separation region 2.

[0094] The multiple P-type partial semiconductor regions 41 in the P-type semiconductor region group 31G are arranged separately from each other. Therefore, the electric field around the N-type semiconductor region 21 can be mitigated by the partial depletion layer units corresponding to the local areas of the multiple P-type partial semiconductor regions 41.

[0095] As a result, in the semiconductor device 53 of Embodiment 3, the cathode voltage of the diode D4 can be finely adjusted by adjusting the spacing Δ41 between adjacent P-type partial semiconductor regions 41, 41 in the plurality of P-type partial semiconductor regions 41, thereby enabling an increase in the design freedom of circuits and layouts within the semiconductor device 53.

[0096] For example, when the power supply voltage V1 of power supply 11 is limited due to layout design convenience, the cathode voltage of diode D4 can be adjusted by adjusting the spacing Δ41 between adjacent P-type semiconductor regions 41, 41. When the spacing Δ41 is set larger, the cathode voltage of diode D4 tends to increase; when the spacing Δ41 is set smaller, the cathode voltage of diode D4 tends to decrease. The cathode voltage of diode D4 can be adjusted using these tendencies of the spacing Δ41.

[0097] <Implementation Method 4> Figure 4 This is an explanatory diagram schematically showing the planar structure of the semiconductor device 54 according to Embodiment 4 of this disclosure.

[0098] As shown in the figure, the semiconductor device 54 of Embodiment 4 is similar to that of Embodiments 1 to 3, including a P-type semiconductor layer 1, an N-type high-voltage separation region 2, an N-type high-potential region 3 and a diode region 4 disposed on the P-type semiconductor layer 1, power supplies 11 and 12 and a capacitor C3 as the main structural elements.

[0099] The following is about... Figure 1 and Figure 2 The same structures shown in Embodiment 1 and Embodiment 2 are labeled with the same reference numerals and descriptions are omitted as appropriate. The description will focus on the characteristic parts of the semiconductor device 54 in Embodiment 4.

[0100] Compared with Embodiments 1 and 2, the semiconductor device 54 of Embodiment 4 is characterized by having a P-type semiconductor region 33 instead of a P-type semiconductor region 31. That is, the P-type semiconductor region 33 becomes the P-type semiconductor region in the semiconductor device 54 of Embodiment 4.

[0101] In the N-type high-voltage separation region 2, the peripheral region of the N-type semiconductor region 21, which is the first N-type semiconductor region, includes a peripheral region 61 that is a first peripheral region close to the side (inner side) of the N-type semiconductor region 22, and a peripheral region 62 that is a second peripheral region far away from the side (outer side) of the N-type semiconductor region 22.

[0102] The P-type semiconductor region 33 is configured to seamlessly surround the periphery of the N-type semiconductor region 21, which forms the first N-type semiconductor region, when viewed from above. The P-type impurity concentration of the P-type semiconductor region 33 is set to be higher than that of the P-type semiconductor layer 1.

[0103] In this description, "surrounding the P-type semiconductor region" refers to a region provided in at least a portion of the peripheral regions 61 and 62 of the N-type semiconductor region 21, which surrounds the periphery of the N-type semiconductor region 21 when viewed from above. On the other hand, "completely surrounding the P-type semiconductor region" included in "surrounding the P-type semiconductor region" refers to a region provided in the peripheral regions 61 and 62 of the N-type semiconductor region 21, which surrounds the periphery of the N-type semiconductor region 21 without gaps when viewed from above.

[0104] Therefore, the P-type semiconductor region 33 completely surrounds the P-type semiconductor region. The P-type semiconductor region 33 has an inner P-type parallel region 331, an outer P-type parallel region 332, and a connecting region 333 as the P-type parallel region. The inner P-type parallel region 331 is formed in the peripheral region 61, which is the first peripheral region, and the outer P-type parallel region 332 is formed in the peripheral region 62, which is the second peripheral region. Then, the inner P-type parallel region 331 and the outer P-type parallel region 332 are connected via the connecting region 333.

[0105] The inner P-type parallel region 331, similar to the P-type semiconductor region 31 in Embodiment 2, is a region that, when viewed from above, is parallel to the three sides of the N-type high-potential region 3. These three sides are parallel to... Figure 4 The right, left, and bottom edges of the N-type high-potential region 3 are shown. Furthermore, the inner P-type parallel region 331 has a region parallel to a portion of the upper edge of the N-type high-potential region 3.

[0106] Therefore, the inner P-type parallel region 331 is a region that is parallel to at least three sides of the N-type high-potential region 3 when viewed from above. These at least three sides are common to the N-type semiconductor regions 21 and 22 and the inner P-type parallel region 331. Thus, the inner P-type parallel region 331, when viewed from above, encloses more than three-quarters of the outer perimeter of the N-type high-potential region 3.

[0107] The outer P-type parallel region 332 is the region that is parallel to the three sides of the N-type high-potential region 3 when viewed from above. These three sides are parallel to... Figure 4 The right, left, and bottom edges of the N-type high-potential region 3 are shown. Furthermore, the outer P-type parallel region 332 has a region parallel to a portion of the upper edge of the N-type high-potential region 3.

[0108] Therefore, the outer P-type parallel region 332 is a region that, when viewed from above, is parallel to at least three sides of the N-type high-potential region 3. These at least three sides are common to the N-type semiconductor regions 21 and 22, as well as to the inner P-type parallel region 331 and the outer P-type parallel region 332. Thus, the outer P-type parallel region 332, when viewed from above, encloses more than three-quarters of the outer perimeter of the N-type high-potential region 3.

[0109] Thus, the P-type semiconductor region 33, which completely surrounds the P-type semiconductor region, has an inner P-type parallel region 331 and an outer P-type parallel region 332 as P-type parallel regions.

[0110] in addition, Figure 4 The cross-sectional structure of the P-type semiconductor region 33 shown is similar to that of the P-type semiconductor region 31 shown in Embodiments 1 and 2, for example, equivalent to... Figure 13 p shown + Layer 213 or p + Layer 214.

[0111] Similar to the P-type semiconductor region 31 in Embodiments 1 and 2, the entire area of ​​the inner P-type parallel region 331 in the P-type semiconductor region 33 is disposed between the N-type semiconductor region 21 and the N-type semiconductor region 22 when viewed from above. Therefore, the inner P-type semiconductor region 331 is disposed between the first N-type parallel region of the N-type semiconductor region 21 and the second N-type parallel region of the N-type semiconductor region 22 when viewed from above.

[0112] In the semiconductor device 54 of embodiment 4 of this structure, the power supply voltage V1 applied to the P-type semiconductor region 33 is set to be lower than the power supply voltage V2 applied to the N-type semiconductor region 21. Therefore, a reverse bias can be applied between the P-type semiconductor region 33 and the N-type high-voltage separation region 2.

[0113] Therefore, the semiconductor device 54 in Embodiment 4 has the same effect as in Embodiments 1 and 2.

[0114] Furthermore, the P-type semiconductor region 33, which completely surrounds the P-type semiconductor region, includes peripheral regions 61 and 62, and is provided to surround the periphery of the N-type semiconductor region 21 when viewed from above. Therefore, the aforementioned depletion layer becomes a surrounding depletion layer that surrounds the N-type semiconductor region 21.

[0115] Therefore, the semiconductor device 54 of Embodiment 4 can mitigate the electric field around the N-type semiconductor region 21, which includes peripheral regions 61 and 62, when a reverse bias is applied.

[0116] Furthermore, since the P-type semiconductor region 33 is provided to completely surround the N-type semiconductor region without gaps when viewed from above, the N-type semiconductor region 21 is surrounded by the depletion layer from all directions, which correspondingly improves the suppression effect of the cathode voltage of the diode D4 when the high potential side power supply voltage VB, which is higher than the power supply voltage V2, is applied to the power supply electrode 5.

[0117] <Implementation Method 5> (Method 1) Figure 5 This is an explanatory diagram schematically showing the planar structure of the semiconductor device 55A according to the first embodiment of the present disclosure 5.

[0118] As shown in the figure, the semiconductor device 55A of the first embodiment 5 includes a P-type semiconductor layer 1, an N-type high-voltage separation region 2, an N-type high-potential region 3 and a diode region 4 disposed on the P-type semiconductor layer 1, power supplies 11 to 13 and a capacitor C3 as the main structural elements.

[0119] The following is about... Figure 4 The same structure as in Embodiment 4 is labeled with the same reference numerals and descriptions are omitted as appropriate. The description will focus on the characteristic parts of the semiconductor device 55A of Embodiment 5 in the first manner.

[0120] Compared with Embodiment 4, the semiconductor device 55A of Embodiment 5 is characterized by having a pair of P-type semiconductor regions 34 and 35 instead of the P-type semiconductor region 33. That is, the pair of P-type semiconductor regions 34 and 35 are the P-type semiconductor regions in the semiconductor device 55A of Embodiment 5 in the first aspect, and they surround the P-type semiconductor region.

[0121] In the N-type high-voltage separation region 2, similarly to the semiconductor device 54 of Embodiment 4, the peripheral region of the N-type semiconductor region 21 includes a peripheral region 61 that becomes a first peripheral region close to the side of the N-type semiconductor region 22, and a peripheral region 62 that becomes a second peripheral region far from the side of the N-type semiconductor region 22.

[0122] P-type semiconductor regions 34 and 35 are disposed independently without contact with each other, and the P-type impurity concentration of each of the P-type semiconductor regions 34 and 35 is set to be higher than the P-type impurity concentration of the P-type semiconductor layer 1.

[0123] The combination of P-type semiconductor regions 34 and 35, which constitute the P-type semiconductor region, is arranged around the periphery of the N-type semiconductor region 21, which becomes the first N-type semiconductor region, when viewed from above.

[0124] The P-type semiconductor region 34 is a first portion surrounding the P-type semiconductor region, which is at least a portion of the peripheral region 61 of the N-type semiconductor region 21. The P-type semiconductor region 35 is a second portion surrounding the P-type semiconductor region, which is at least a portion of the peripheral region 62 of the N-type semiconductor region 21.

[0125] The P-type semiconductor region 34 located in the peripheral region 61 becomes... Figure 4 The region corresponding to the inner P-type parallel region 331 of the P-type semiconductor region 33 shown. Similarly, the P-type semiconductor region 35 disposed in the peripheral region 62 becomes the region corresponding to the P-type parallel region 331 of the peripheral region 62. Figure 4 The regions corresponding to the outer P-type parallel region 332 and the connecting region 333 of the P-type semiconductor region 33 shown.

[0126] Therefore, the combination of P-type semiconductor regions 34 and 35 forms a P-type semiconductor region with the same planar and cross-sectional structure as the P-type semiconductor region 33 of Embodiment 4, which has an inner P-type parallel region 331, an outer P-type parallel region 332, and a connecting region 333.

[0127] That is, similar to the inner P-type parallel region 331 of the P-type semiconductor region 33, the P-type semiconductor region 34 has a region that, when viewed from above, is parallel to at least three sides of the N-type high-potential region 3, serving as a first part of the parallel region. Similarly to the outer P-type parallel region 332 of the P-type semiconductor region 33, the P-type semiconductor region 35 has a region that, when viewed from above, is parallel to at least three sides of the N-type high-potential region 3, serving as a second part of the parallel region. Thus, the P-type semiconductor regions 34 and 35 have the aforementioned first part of the parallel region and second part of the parallel region, serving as P-type parallel regions.

[0128] The P-type semiconductor region 34, which forms the first part surrounding the P-type semiconductor region, and the P-type semiconductor region 35, which forms the second part surrounding the P-type semiconductor region, are disposed separately from each other. Therefore, there are gap regions 65 and 66 between the P-type semiconductor region 34 and the P-type semiconductor region 35.

[0129] Therefore, the P-type semiconductor regions 34 and 35 are arranged around the periphery of the N-type semiconductor region 21 in such a way that the gap regions 65 and 66 are open when viewed from above. Furthermore, it is preferable that the narrower gap regions 65 and 66 between the P-type semiconductor regions 34 and 35 can suppress the rise of the cathode voltage of the diode D4.

[0130] Then, the entire region of the P-type semiconductor region 34, corresponding to the inner P-type parallel region 331 of the P-type semiconductor region 33, is disposed between the N-type semiconductor region 21 and the N-type semiconductor region 22 when viewed from above. Therefore, similarly to the inner P-type parallel region 331 of the P-type semiconductor region 33, the first part of the parallel region included in the P-type semiconductor region 34 is disposed between the first N-type parallel region of the N-type semiconductor region 21 and the second N-type parallel region of the N-type semiconductor region 22 when viewed from above.

[0131] The semiconductor device 55A of the first embodiment 5 further includes a power supply 13, which serves as a third power supply providing a power supply voltage V3 as a third voltage. The power supply voltage V3 as the third voltage is set to be lower than the power supply voltage V2 as the second voltage. Specifically, when the voltage drop across diode D4 is set to VF, it is set to satisfy {V3 < (V2 - VF)}.

[0132] Furthermore, the relationship between power supply voltage V1 and power supply voltage V3 is arbitrary. That is, within the range of {V1 < V2, V3 < V2}, the relationship between power supply voltage V1 and power supply voltage V3 can be arbitrarily set.

[0133] The power supply voltage V1 is applied from the power supply 11 via wiring L1 to the first part surrounding the P-type semiconductor region, namely the P-type semiconductor region 34. That is, node P1 on the P-type semiconductor region 34 is electrically connected to one end of wiring L1.

[0134] A power supply voltage V3, serving as a third voltage, is applied to the second part surrounding the P-type semiconductor region 35 via wiring L5. Specifically, node P5 on the P-type semiconductor region 35 is electrically connected to one end of wiring L5, and the positive terminal of power supply 13 is connected to the other end of wiring L5. Furthermore, the negative terminal of power supply 13 is electrically connected to ground, serving as a reference potential. Additionally, the power supply voltage V3 from power supply 13 is not supplied to the P-type semiconductor layer 1.

[0135] In the semiconductor device 55A of the first embodiment of this structure, the power supply voltage V1 applied to the P-type semiconductor region 34 and the power supply voltage V3 applied to the P-type semiconductor region 35 are set to be lower than the power supply voltage V2 applied to the N-type semiconductor region 21. Therefore, a reverse bias can be applied between the P-type semiconductor regions 34 and 35 and the N-type high-voltage separation region 2.

[0136] Therefore, the semiconductor device 55A of the first embodiment 5 has the same effect as that of embodiments 1 and 2.

[0137] Furthermore, the P-type semiconductor regions 34 and 35 that constitute the P-type semiconductor region include peripheral regions 61 and 62, and are provided to surround the periphery of the N-type semiconductor region 21 when viewed from above. Therefore, the aforementioned depletion layer becomes a surrounding depletion layer that surrounds the N-type semiconductor region 21.

[0138] That is, a first peripheral depletion layer is provided at the interface between the P-type semiconductor region 34, which becomes the first surrounding P-type semiconductor region, and the N-type high-voltage separation region 2, and a second peripheral depletion layer is provided at the interface between the P-type semiconductor region 35, which becomes the second surrounding P-type semiconductor region, and the N-type high-voltage separation region 2. The combination of the first peripheral depletion layer and the second peripheral depletion layer constitutes the surrounding depletion layer.

[0139] As a result, the semiconductor device 55A of the first embodiment 5 can surround the N-type semiconductor region 21 when viewed from above by the first peripheral depletion layer and the second peripheral depletion layer, thereby mitigating the electric field around the N-type semiconductor region 21.

[0140] Furthermore, since the power supply voltages V1 and V3 can be set separately, the expansion of the first peripheral depletion layer and the second peripheral depletion layer relative to the N-type semiconductor region 21 can be different. Therefore, the semiconductor device 55A of the first embodiment 5 has the inherent effect that the electric field distribution at the periphery of the N-type semiconductor region 21 can be adjusted more easily.

[0141] (Method 2) Figure 6 This is an explanatory diagram schematically showing the planar structure of the semiconductor device 55B according to the second embodiment of the present disclosure 5.

[0142] As shown in the figure, with Figure 5 Similarly, in the first embodiment of the illustrated embodiment 5, the semiconductor device 55B in the second embodiment of the illustrated embodiment 5 includes a P-type semiconductor layer 1, an N-type high-voltage separation region 2, an N-type high-potential region 3 and a diode region 4 disposed on the P-type semiconductor layer 1, power supplies 11 to 13 and a capacitor C3 as the main structural elements.

[0143] The following is about... Figure 5 The same structures of Embodiment 5 shown in the first embodiment are labeled with the same reference numerals and descriptions are omitted as appropriate. The description will focus on the feature parts of the semiconductor device 55B of Embodiment 5 in the second embodiment.

[0144] Compared to semiconductor device 55A, semiconductor device 55B of embodiment 5 is characterized by having a group of P-type semiconductor regions 34G instead of P-type semiconductor regions 34. That is, the P-type semiconductor regions 34G and 35 are the P-type semiconductor regions in semiconductor device 55B of embodiment 5 in the second embodiment, and are arranged around the P-type semiconductor regions.

[0145] The P-type semiconductor region group 34G is arranged to surround the N-type semiconductor region 21, which forms the first N-type semiconductor region when viewed from above, and is positioned between the N-type semiconductor region 21 and the N-type semiconductor region 22 when viewed from above.

[0146] P-type semiconductor region group 34G becomes the first part surrounding the P-type semiconductor region, which is set as part of the peripheral region 61 that becomes the first peripheral region of the N-type semiconductor region 21.

[0147] The P-type semiconductor region group 34G is composed of a plurality of P-type partial semiconductor regions 44 disposed separately from each other. Furthermore, the P-type impurity concentration of each of the plurality of P-type partial semiconductor regions 44 in the P-type semiconductor region group 34G is set to be higher than the P-type impurity concentration of the P-type semiconductor layer 1. The cross-sectional structure of the P-type semiconductor region 34G is the same as that of the P-type semiconductor region 34 in the first embodiment.

[0148] In the P-type semiconductor region 34G, there is a relay wiring 26 that is electrically connected to multiple P-type partial semiconductor regions 44 respectively. The relay wiring 26 is electrically connected to wiring L1 via node P1.

[0149] Therefore, the power supply voltage V1 supplied from the power supply 11 is applied to the plurality of P-type partial semiconductor regions 44 constituting the P-type semiconductor region group 34G via the relay wiring 26.

[0150] On the other hand, similar to the first method, the P-type semiconductor region 35 becomes the second part of the peripheral region 62 of the N-type semiconductor region 21 surrounding the P-type semiconductor region.

[0151] The P-type semiconductor region group 34G, which forms the first part surrounding the P-type semiconductor region, and the P-type semiconductor region 35, which forms the second part surrounding the P-type semiconductor region, are disposed separately from each other. Therefore, there are gap regions 65 and 66 between the P-type semiconductor region 34G and the P-type semiconductor region 35.

[0152] Furthermore, among the plurality of P-type partial semiconductor regions 44 constituting a P-type semiconductor region group 34G that partially surrounds a P-type semiconductor region group, there is a spacing Δ44 between adjacent P-type partial semiconductor regions 44, 44.

[0153] Thus, the P-type semiconductor regions 34G and 35 are arranged around the periphery of the N-type semiconductor region 21 in a manner that opens the gap regions 65 and 66 and multiple intervals Δ44 when viewed from above.

[0154] In the second embodiment of the semiconductor device 55B of this structure, the power supply voltage V1 applied to the P-type semiconductor region group 34G and the power supply voltage V3 applied to the P-type semiconductor region 35 are set to be lower than the power supply voltage V2 applied to the N-type semiconductor region 21. Therefore, a reverse bias can be applied between the P-type semiconductor regions 34G and 35 and the N-type high-voltage separation region 2.

[0155] Therefore, the semiconductor device 55B of the second embodiment 5 has the same effect as that of embodiments 1 and 2.

[0156] Furthermore, the P-type semiconductor regions 34G and 35, which are surrounding the P-type semiconductor region, include peripheral regions 61 and 62, and are arranged to surround the periphery of the N-type semiconductor region 21 when viewed from above. Therefore, the aforementioned depletion layer becomes a surrounding depletion layer that surrounds the N-type semiconductor region 21.

[0157] Therefore, the semiconductor device 55B of the second embodiment 5 has the same effect as the semiconductor device 55A of the first embodiment.

[0158] Furthermore, since multiple P-type partial semiconductor regions 44 in the P-type semiconductor region group 34G, which are partially surrounded by the P-type semiconductor region group, are respectively arranged separately from each other, the electric field in the peripheral region 61 of the N-type semiconductor region 21 can be mitigated by the partial depletion layer units corresponding to the local areas of the multiple P-type partial semiconductor regions 44.

[0159] As a result, in the semiconductor device 55B of the second embodiment 5, the cathode voltage of the diode D4 can be adjusted by adjusting the spacing Δ44 between adjacent P-type partial semiconductor regions 44 in the plurality of P-type partial semiconductor regions 44 in the P-type semiconductor region group 34G, thereby increasing the design freedom of the circuit and layout in the semiconductor device 55B.

[0160] In addition, in the semiconductor device 55B, the first part surrounding the P-type semiconductor region in the peripheral region 61 is configured as a P-type semiconductor region group 34G composed of multiple P-type partial semiconductor regions 44, and the second part surrounding the P-type semiconductor region in the peripheral region 62 is configured as a single-structure P-type semiconductor region 35.

[0161] In contrast to the above structure, a first variation may also be adopted, wherein the first part surrounding the P-type semiconductor region in the peripheral region 61 is a single-structure P-type semiconductor region 34, and the second part surrounding the P-type semiconductor region in the peripheral region 62 is a group of P-type semiconductor regions composed of multiple P-type partial semiconductor regions.

[0162] In the first modification, a relay wiring for the modification is provided, which is electrically connected to the plurality of P-type partial semiconductor regions respectively, and a power supply voltage V3 is applied from the power supply 13 to the P-type semiconductor region group via the relay wiring for the modification. Therefore, in the first modification, the electric field in the peripheral region 62 of the N-type semiconductor region 21 is mitigated by local partial depletion layer units.

[0163] Alternatively, a second variation can be adopted, in which the first part surrounding the P-type semiconductor region and the second part surrounding the P-type semiconductor region are each a group of P-type semiconductor regions composed of multiple P-type partial semiconductor regions.

[0164] Therefore, the second embodiment of implementation 5 includes the first and second modifications described above, wherein at least one of the first part surrounding the P-type semiconductor region and the second part surrounding the P-type semiconductor region is configured as a group of P-type semiconductor regions composed of a plurality of P-type partial semiconductor regions.

[0165] <Implementation Method 6> (Method 1) Figure 7 This is an explanatory diagram schematically showing the planar structure of the semiconductor device 56A according to the first embodiment of 6 of this disclosure.

[0166] As shown in the figure, the semiconductor device 56A of Embodiment 6 in the first embodiment is similar to that in Embodiments 1 to 4, including a P-type semiconductor layer 1, an N-type high-voltage separation region 2, an N-type high-potential region 3 and a diode region 4 disposed on the P-type semiconductor layer 1, power supplies 11 and 12 and a capacitor C3 as the main structural elements.

[0167] The following is about... Figure 1 and Figure 2 The same structures shown in Embodiment 1 and Embodiment 2 are labeled with the same reference numerals and descriptions are omitted as appropriate. The description will focus on the characteristic parts of the semiconductor device 56A in Embodiment 6.

[0168] Compared with Embodiments 1 and 2, the semiconductor device 56A of Embodiment 6 is characterized by having P-type semiconductor regions 31A and 31B constituting a plurality of P-type semiconductor regions, in place of P-type semiconductor region 31. That is, P-type semiconductor regions 31A and 31B become the P-type semiconductor regions in the semiconductor device 56A of Embodiment 6 in the first embodiment.

[0169] In semiconductor device 56A, P-type semiconductor regions 31A and 31B are provided as multiple P-type semiconductor regions that are separately arranged from each other. That is, the multiple P-type semiconductor regions in semiconductor device 56A include P-type semiconductor region 31A as a first P-type semiconductor region and P-type semiconductor region 31B as a second P-type semiconductor region.

[0170] The P-type semiconductor regions 31A and 31B, which constitute multiple P-type semiconductor regions, are respectively disposed between the N-type semiconductor region 21 and the N-type semiconductor region 22 when viewed from above. Therefore, the N-type semiconductor region 22 is disposed closer to the N-type high-potential region 3 than the N-type semiconductor region 21 and the P-type semiconductor regions 31A and 31B. Furthermore, the P-type semiconductor regions 31A and 31B are respectively disposed between the N-type semiconductor region 21 and the N-type high-potential region 3 when viewed from above.

[0171] P-type semiconductor regions 31A and 31B are selectively and independently disposed on the upper layer of the N-type high-voltage separation region 2. The P-type semiconductor regions 31A and 31B are not in contact with each other. The P-type impurity concentration of each of the P-type semiconductor regions 31A and 31B is set to be higher than the P-type impurity concentration of the P-type semiconductor layer 1.

[0172] Figure 7 The cross-sectional structures of the P-type semiconductor regions 31A and 31B shown are, for example, equivalent to Figure 13 p shown + Layer 213 and p + Layer 214.

[0173] The entire regions of P-type semiconductor regions 31A and 31B are respectively positioned between N-type semiconductor region 21 and N-type semiconductor region 22 when viewed from above.

[0174] In the P-type semiconductor regions 31A and 31B, the P-type semiconductor region 31A is disposed outside the P-type semiconductor region 31B. That is, compared with the P-type semiconductor region 31B, the P-type semiconductor region 31A is disposed closer to the N-type semiconductor region 21, and compared with the P-type semiconductor region 31A, the P-type semiconductor region 31B is disposed closer to the N-type semiconductor region 22.

[0175] Furthermore, the P-type semiconductor region 31A has a first P-type parallel region that, when viewed from above, is parallel to the three sides of the N-type high-potential region 3. These three sides are parallel to... Figure 7 The right, left, and bottom edges of the N-type high-potential region 3 are shown. Furthermore, the first P-type parallel region has a region parallel to a portion of the upper edge of the N-type high-potential region 3.

[0176] Thus, the P-type semiconductor region 31A has a first P-type parallel region that, when viewed from above, is parallel to at least three sides of the N-type high-potential region 3. These at least three sides are common to both the N-type semiconductor regions 21 and 22 and the P-type semiconductor region 31A. Therefore, the P-type semiconductor region 31A, when viewed from above, encloses more than three-quarters of the outer perimeter of the N-type high-potential region 3.

[0177] Similarly, the P-type semiconductor region 31B has a second P-type parallel region that, when viewed from above, is parallel to the three sides of the N-type high-potential region 3. These three sides are parallel to... Figure 7 The right, left, and bottom edges of the N-type high-potential region 3 are shown. Furthermore, the second P-type parallel region has a region parallel to a portion of the upper edge of the N-type high-potential region 3.

[0178] Therefore, the P-type semiconductor region 31B has a second P-type parallel region that, when viewed from above, is parallel to at least three sides of the N-type high-potential region 3. These at least three sides are common to the N-type semiconductor regions 21 and 22 and the P-type semiconductor regions 31A and 31B. Thus, the P-type semiconductor region 31B, when viewed from above, surrounds more than three-quarters of the outer perimeter of the N-type high-potential region 3.

[0179] As described above, in the first embodiment of 6, the P-type parallel regions of the P-type semiconductor region include a first P-type parallel region of the P-type semiconductor region 31A and a second P-type parallel region of the P-type semiconductor region 31B.

[0180] As described above, the entire regions of P-type semiconductor regions 31A and 31B are disposed between N-type semiconductor regions 21 and 22 when viewed from above. Therefore, the first P-type parallel region and the second P-type parallel region of P-type semiconductor regions 31A and 31B are disposed between the first N-type parallel region of N-type semiconductor region 21 and the second N-type parallel region of N-type semiconductor region 22 when viewed from above.

[0181] The power supply voltage V1 supplied from power source 11 is applied to P-type semiconductor region 31A via wiring L1 and wiring L12, and to P-type semiconductor region 31B via wiring L1 and wiring L12. Wiring L11 and wiring L12 are branches from node P8 of wiring L1. One end of wiring L11 is electrically connected to node P1 on P-type semiconductor region 31A, one end of wiring L12 is electrically connected to node P6 on P-type semiconductor region 31B, and the other ends of wiring L11 and L12 are respectively electrically connected to intermediate node P8.

[0182] Therefore, in the semiconductor device 56A of the first embodiment 6, the power supply voltage V1, which is the first voltage, is generally applied to the P-type semiconductor regions 31A and 31B, which are the first P-type parallel region and the second P-type semiconductor region.

[0183] In the semiconductor device 56A of the first embodiment 6, the power supply voltage V1 applied to the P-type semiconductor regions 31A and 31B is generally set to be lower than the power supply voltage V2 applied to the N-type semiconductor region 21. Therefore, a reverse bias can be applied between each of the P-type semiconductor regions 31A and 31B and the N-type high-voltage separation region 2.

[0184] Therefore, by generating a depletion layer at the interface between the first P-type parallel region and the second P-type parallel region of the P-type semiconductor regions 31A and 31B and the N-type high-voltage separation region 2, the electric field around the N-type semiconductor region 21 electrically connected to the cathode of the diode D4 can be mitigated.

[0185] Therefore, the semiconductor device 56A of Embodiment 6 in the first embodiment has the same effect as Embodiment 1 and Embodiment 2.

[0186] Furthermore, the semiconductor device 56A of the first embodiment 6 uses multiple P-type semiconductor regions (P-type semiconductor regions 31A and 31B) that are set separately from each other as P-type semiconductor regions, thereby gradually mitigating the electric field around the N-type semiconductor region 21.

[0187] The semiconductor device 56A of embodiment 6 can mitigate the electric field around the N-type semiconductor region 21 in two stages by providing P-type semiconductor regions 31A and 31B as the first P-type parallel region and the second P-type semiconductor region.

[0188] Furthermore, the power supply voltage V1, which is the first voltage, is applied to the P-type semiconductor regions 31A and 31B in a common manner, so the semiconductor device 56A of Embodiment 6 can be constructed without adding a new power supply.

[0189] (Method 2) Figure 8 This is an explanatory diagram schematically showing the planar structure of the semiconductor device 56B according to the second embodiment of this disclosure 6.

[0190] As shown in the figure, with Figure 7 Similarly, in the first embodiment of the illustrated embodiment 6, the semiconductor device 56B in the second embodiment of the illustrated embodiment 6 includes a P-type semiconductor layer 1, an N-type high-voltage separation region 2, an N-type high-potential region 3 and a diode region 4 disposed on the P-type semiconductor layer 1, power supplies 11 and 12, and a capacitor C3 as the main structural elements.

[0191] The following is about... Figure 7The same structures of Embodiment 6 shown in the first embodiment are labeled with the same reference numerals and descriptions are omitted as appropriate. The description will focus on the feature parts of the semiconductor device 56B of Embodiment 6 in the second embodiment.

[0192] Compared with Embodiment 6 and the first embodiment, the semiconductor device 56B of Embodiment 6 is characterized by having P-type semiconductor region groups 31AG and 31BG constituting a plurality of P-type semiconductor regions, in place of P-type semiconductor regions 31A and 31B. That is, the P-type semiconductor region groups 31AG and 31BG become the P-type semiconductor regions in the semiconductor device 56B of Embodiment 6, the second embodiment.

[0193] In semiconductor device 56B, P-type semiconductor region groups 31AG and 31BG are provided as multiple P-type semiconductor regions that are separately arranged from each other. That is, the multiple P-type semiconductor regions in semiconductor device 56B include P-type semiconductor region group 31AG as a first P-type semiconductor region group and P-type semiconductor region group 31BG as a second P-type semiconductor region group.

[0194] P-type semiconductor region group 31AG and P-type semiconductor region group 31BG are selectively and independently disposed on the upper part of N-type high-voltage separation region 2.

[0195] P-type semiconductor region group 31AG is composed of multiple P-type partial semiconductor regions 41A that are separately arranged from each other. P-type semiconductor region group 31BG is composed of multiple P-type partial semiconductor regions 41B that are separately arranged from each other. In addition, the P-type impurity concentration of each of the multiple P-type partial semiconductor regions 41A and the multiple P-type partial semiconductor regions 41B is set to be higher than the P-type impurity concentration of the P-type semiconductor layer 1.

[0196] Furthermore, among the plurality of P-type partial semiconductor regions 41A constituting the P-type semiconductor region group 31AG, there is a gap Δ41A between adjacent P-type partial semiconductor regions 41A, 41A, and among the plurality of P-type partial semiconductor regions 41B constituting the P-type semiconductor region group 31BG, there is a gap Δ41B between adjacent P-type partial semiconductor regions 41B, 41B.

[0197] The P-type semiconductor region group 31AG has the same structure as the P-type semiconductor region 31A in the first embodiment, except that it is composed of multiple P-type partial semiconductor regions 41A. The P-type semiconductor region group 31BG has the same structure as the P-type semiconductor region 31B in the first embodiment, except that it is composed of multiple P-type partial semiconductor regions 41B.

[0198] In the P-type semiconductor region group 31AG, there is a relay wiring 25A that is electrically connected to multiple P-type partial semiconductor regions 41A respectively. The relay wiring 25A is electrically connected to one end of the wiring L11 via node P1.

[0199] Therefore, the power supply voltage V1 supplied from the power supply 11 is applied to a plurality of P-type partial semiconductor regions 41A constituting the P-type semiconductor region group 31AG via relay wiring 25A.

[0200] In the P-type semiconductor region group 31BG, there is a relay wiring 25B that is electrically connected to multiple P-type partial semiconductor regions 41B respectively. The relay wiring 25B is electrically connected to one end of the wiring L12 via node P6.

[0201] Therefore, the power supply voltage V1 supplied from the power supply 11 is applied to the plurality of P-type partial semiconductor regions 41B constituting the P-type semiconductor region group 31BG via the relay wiring 25B.

[0202] In the semiconductor device 56B of the second embodiment 6, the power supply voltage V1 commonly applied to the P-type semiconductor region groups 31AG and 31BG is set to be lower than the power supply voltage V2 applied to the N-type semiconductor region 21. Therefore, a reverse bias can be applied between each of the P-type semiconductor region groups 31AG and 31BG and the N-type high-voltage separation region 2.

[0203] Therefore, by generating a depletion layer at the interface between the first P-type parallel region and the second P-type parallel region of the P-type semiconductor region group 31AG and 31BG and the N-type high-voltage separation region 2, the electric field around the N-type semiconductor region 21 electrically connected to the cathode of the diode D4 can be mitigated.

[0204] Therefore, the semiconductor device 56B of Embodiment 6 in the second embodiment has the same effect as Embodiment 1 and Embodiment 2.

[0205] Furthermore, the semiconductor device 56B of the second embodiment 6 uses multiple P-type semiconductor regions (P-type semiconductor region groups 31AG and 31BG) that are set separately from each other as P-type semiconductor regions, thereby gradually mitigating the electric field around the N-type semiconductor region 21.

[0206] Furthermore, the semiconductor device 56B of Embodiment 6 can mitigate the electric field around the N-type semiconductor region 21 in two stages by providing P-type semiconductor region groups 31AG and 31BG, which are the first P-type semiconductor region and the second P-type semiconductor region.

[0207] Furthermore, the power supply voltage V1, which is the first voltage, is applied to the P-type semiconductor region groups 31AG and 31BG in a common manner, so the semiconductor device 56B of Embodiment 6 can be constructed without adding a new power supply.

[0208] Furthermore, the multiple P-type partial semiconductor regions 41A in the P-type semiconductor region group 31AG and the multiple P-type partial semiconductor regions 41B in the P-type semiconductor region group 31BG are respectively arranged separately from each other, so that the electric field around the N-type semiconductor region 21 can be mitigated in a local partial depletion layer unit.

[0209] As a result, regarding the P-type semiconductor region groups 31AG and 31BG, the semiconductor device 56B of the second embodiment of 6 functions in conjunction with... Figure 3 The semiconductor device 53 of Embodiment 3 shown has the same effect.

[0210] In addition, the semiconductor device 56B shows the following structure: the P-type semiconductor regions 31A and 31B of the first embodiment are replaced together with P-type semiconductor region groups 31AG and 31BG.

[0211] In addition to the above structure, a first variation can be considered in which only the P-type semiconductor region 31A in the P-type semiconductor regions 31A and 31B is replaced with the P-type semiconductor region group 31AG, and a second variation can be considered in which only the P-type semiconductor region 31B in the P-type semiconductor regions 31A and 31B is replaced with the P-type semiconductor region group 31BG.

[0212] That is, in the second embodiment of 6, at least one of the first P-type semiconductor region and the second P-type semiconductor region is set as a group of P-type semiconductor regions composed of a plurality of P-type partial semiconductor regions.

[0213] (Method 3) Figure 9 This is an explanatory diagram schematically showing the planar structure of the semiconductor device 56C according to the third embodiment of the present disclosure 6.

[0214] As shown in the figure, with Figure 7 Similarly, in the first embodiment of the illustrated embodiment 6, the semiconductor device 56C in the third embodiment of the illustrated embodiment 6 includes a P-type semiconductor layer 1, an N-type high-voltage separation region 2, an N-type high-potential region 3 and a diode region 4 disposed on the P-type semiconductor layer 1, power supplies 11 and 12, and a capacitor C3 as the main structural elements.

[0215] The following is about... Figure 7 The same structures of Embodiment 6 shown in the first embodiment are labeled with the same reference numerals and descriptions are omitted as appropriate. The description will focus on the characteristic parts of the semiconductor device 56C of Embodiment 6 in the third embodiment.

[0216] Compared to the first embodiment of embodiment 6, the semiconductor device 56C of embodiment 6 is characterized by having a P-type semiconductor region 33A that completely surrounds the P-type semiconductor region instead of the P-type semiconductor region 31A. That is, the P-type semiconductor regions 33A and 31B become the P-type semiconductor regions in the semiconductor device 56C of the third embodiment.

[0217] Similar to the P-type semiconductor region 33 in Embodiment 4, the P-type semiconductor region 33A has an inner P-type parallel region 331A formed in the peripheral region 61 and an outer P-type parallel region 332A formed in the peripheral region 62, and a connection region 333A that combines the inner P-type parallel region 331A and the outer P-type parallel region 332A. The inner P-type parallel region 331A is oriented in the same direction as the outer P-type parallel region 332A. Figure 4 The inner P-type parallel region 331 shown has an equivalent structure, while the outer P-type parallel region 332A is similar to... Figure 4 The equivalent structure of the outer P-type parallel region 332 shown.

[0218] The P-type semiconductor region 33A is arranged to completely surround the P-type semiconductor region, and when viewed from above, it surrounds the N-type semiconductor region 21, which is the first N-type semiconductor region, without any gaps.

[0219] and Figure 4 Similarly, in the semiconductor device 54 of Embodiment 4, all regions of the inner P-type parallel regions 331A of the P-type semiconductor region 33A are disposed between the N-type semiconductor region 21 and the N-type semiconductor region 22. Therefore, when viewed from above, the inner P-type parallel regions 331A are disposed between the first N-type parallel region of the N-type semiconductor region 21 and the second N-type parallel region of the N-type semiconductor region 22.

[0220] The power supply voltage V1 supplied from power source 11 is applied to the P-type semiconductor region 33A via wiring L1 and wiring L11. That is, node P1 on the P-type semiconductor region 33 is electrically connected to one end of wiring L11.

[0221] P-type semiconductor region 33A corresponds to P-type semiconductor region 31A in the first embodiment, and has an inner P-type parallel region 331A and an outer P-type parallel region 332A as the first P-type parallel region.

[0222] In the semiconductor device 56C of the third embodiment 6, the power supply voltage V1 commonly applied to the P-type semiconductor region 33A and the P-type semiconductor region 31B is set to be lower than the power supply voltage V2 applied to the N-type semiconductor region 21. Therefore, a reverse bias can be applied between each of the P-type semiconductor region 33A and the P-type semiconductor region 31B and the N-type high-voltage separation region 2.

[0223] Therefore, by generating a depletion layer at the interface between the first P-type parallel region and the second P-type parallel region of the P-type semiconductor region 33A and the N-type high-voltage separation region 2, the electric field around the N-type semiconductor region 21 electrically connected to the cathode of the diode D4 can be mitigated.

[0224] Therefore, the semiconductor device 56C of the third embodiment 6 has the same effect as that of embodiments 1 and 2.

[0225] Furthermore, the semiconductor device 56C of the third embodiment 6 uses multiple P-type semiconductor regions (P-type semiconductor region 33A and P-type semiconductor region 31B) that are set separately from each other as P-type semiconductor regions, thereby gradually mitigating the electric field around the N-type semiconductor region 21.

[0226] The semiconductor device 56C of Embodiment 6 can mitigate the electric field around the N-type semiconductor region 21 in two stages by providing P-type semiconductor regions 33A and 31B as the first P-type semiconductor region and the second P-type semiconductor region, respectively.

[0227] Furthermore, the power supply voltage V1, which is the first voltage, is applied to both the P-type semiconductor region 33A and the P-type semiconductor region 31B, so the semiconductor device 56C of Embodiment 6 can be constructed without adding a new power supply.

[0228] Furthermore, since the P-type semiconductor region 33A is arranged to completely surround the periphery of the N-type semiconductor region 21 without gaps when viewed from above, the P-type semiconductor region 33A has the same effect as the semiconductor device 54 in Embodiment 4.

[0229] In addition, in the semiconductor device 56C, a first modification in which the P-type semiconductor region 33A is replaced with a group of P-type semiconductor regions composed of multiple P-type partial semiconductor regions, and a second modification in which the P-type semiconductor region 31B is replaced with a group of P-type semiconductor regions 31BG, are also possible.

[0230] Alternatively, a third variation could be considered, replacing the P-type semiconductor region 31B with a structure that completely surrounds the P-type semiconductor region 33A when viewed from above. Specifically, the third variation could be a structure that double-encloses the N-type semiconductor region 21, consisting of a first completely surrounding P-type semiconductor region and a second completely surrounding P-type semiconductor region.

[0231] <Implementation Method 7> (Method 1) Figure 10This is an explanatory diagram schematically showing the planar structure of the semiconductor device 57A according to the first embodiment of this disclosure 7.

[0232] As shown in the figure, the semiconductor device 57A of the first embodiment 7 includes a P-type semiconductor layer 1, an N-type high-voltage separation region 2, an N-type high-potential region 3 and a diode region 4 disposed on the P-type semiconductor layer 1, power supplies 11, 12 and 14, and a capacitor C3 as the main structural elements.

[0233] The following is about... Figure 7 The same structures of Embodiment 6 shown in the first embodiment are labeled with the same reference numerals and descriptions are omitted as appropriate. The description will focus on the characteristic parts of the semiconductor device 57A of Embodiment 7.

[0234] Compared to the first embodiment of embodiment 6, the semiconductor device 57A of the first embodiment of embodiment 7 is characterized by further including a power supply 14, which serves as a fourth power supply providing a power supply voltage V4 as a fourth voltage. The power supply voltage V4 as the fourth voltage is set to be lower than the power supply voltage V2 as the second voltage. Specifically, when the voltage drop of diode D4 is set to VF, it is set to satisfy {V4 < (V2 - VF)}.

[0235] Furthermore, the relationship between power supply voltage V1 and power supply voltage V4 is arbitrary. That is, within the range of {V1 < V2, V4 < V2}, the relationship between power supply voltage V1 and power supply voltage V4 can be arbitrarily set.

[0236] A power supply voltage V4, serving as the fourth voltage, is applied to the second P-type semiconductor region, namely the P-type semiconductor region 31B, via wiring L6. Specifically, node P6 on the P-type semiconductor region 31B is electrically connected to one end of wiring L6, and the positive terminal of power supply 14 is connected to the other end of wiring L6. Furthermore, the negative terminal of power supply 14 is electrically connected to ground, serving as a reference potential. Additionally, the power supply voltage V4 from power supply 14 is not supplied to the P-type semiconductor layer 1.

[0237] In the semiconductor device 57A of the first embodiment 7, the power supply voltage V1 applied to the P-type semiconductor region 31A and the power supply voltage V4 applied to the P-type semiconductor region 31B are set to be lower than the power supply voltage V2 applied to the N-type semiconductor region 21. Therefore, a reverse bias can be applied between each of the P-type semiconductor regions 31A and 31B and the N-type high-voltage separation region 2.

[0238] Therefore, by generating a depletion layer at the interface between the first P-type parallel region and the second P-type parallel region of the P-type semiconductor regions 31A and 31B and the N-type high-voltage separation region 2, the electric field around the N-type semiconductor region 21 electrically connected to the cathode of the diode D4 can be mitigated.

[0239] Therefore, the semiconductor device 57A of the first embodiment 7 has the same effect as that of embodiments 1 and 2.

[0240] Furthermore, the semiconductor device 57A of Embodiment 7 achieves the same effect as the semiconductor device 56A of Embodiment 6 by providing a plurality of P-type semiconductor regions (P-type semiconductor regions 31A and 31B) that are separately provided from each other as P-type semiconductor regions.

[0241] Furthermore, in the semiconductor device 57A of the first embodiment 7, a power supply voltage V1, which is a first voltage, is applied to the P-type semiconductor region 31A, which is a first P-type semiconductor region, and a power supply voltage V4, which is a fourth voltage, is applied to the P-type semiconductor region 31B, which is a second P-type semiconductor region. The power supply 11 and the power supply 14, which are the first and fourth power supplies, are set independently of each other. That is, the power supply voltage V1 and the power supply voltage V4 are independent of each other. Therefore, the power supply voltage V1 and the power supply voltage V4 can be set independently.

[0242] Therefore, the semiconductor device 57A of the first embodiment 7 gradually mitigates the electric field around the N-type semiconductor region 21 in two stages, thereby making it easier to adjust the electric field distribution around the N-type semiconductor region 21.

[0243] (Method 2) Figure 11 This is an explanatory diagram schematically showing the planar structure of the semiconductor device 57B according to the second embodiment of this disclosure 7.

[0244] As shown in the figure, the semiconductor device 57B of the second embodiment 7 includes a P-type semiconductor layer 1, an N-type high-voltage separation region 2, an N-type high-potential region 3 and a diode region 4 disposed on the P-type semiconductor layer 1, power supplies 11, 12 and 14, and a capacitor C3 as the main structural elements.

[0245] The following is about... Figure 8 The same structure as the second embodiment of Embodiment 6 is labeled with the same reference numerals and descriptions are omitted as appropriate. The description will focus on the feature parts of the semiconductor device 57B of the second embodiment of Embodiment 7.

[0246] and Figure 10 Similarly, in the second embodiment of Embodiment 7, the semiconductor device 57B further includes a power supply 14, which serves as a fourth power supply providing a power supply voltage V4 as a fourth voltage. The power supply voltage V4 is set to be lower than the power supply voltage V2.

[0247] A power supply voltage V4, which is the fourth voltage, is applied to the second P-type semiconductor region, namely the P-type semiconductor region group 31BG, via wiring L6. That is, node P6 on the P-type semiconductor region group 31BG is electrically connected to one end of wiring L6, and the positive terminal of power supply 14 is connected to the other end of wiring L6.

[0248] In the semiconductor device 57B of the second embodiment 7, the power supply voltage V1 applied to the P-type semiconductor region group 31AG and the power supply voltage V4 applied to the P-type semiconductor region group 31BG are set to be lower than the power supply voltage V2 applied to the N-type semiconductor region 21. Therefore, a reverse bias can be applied between each of the P-type semiconductor region groups 31AG and 31BG and the N-type high-voltage separation region 2.

[0249] Therefore, by generating a depletion layer at the interface between the first P-type parallel region and the second P-type parallel region of the P-type semiconductor region group 31AG and 31BG and the N-type high-voltage separation region 2, the electric field around the N-type semiconductor region 21 electrically connected to the cathode of the diode D4 can be mitigated.

[0250] Therefore, the semiconductor device 57B of Embodiment 7 in the second embodiment has the same effect as Embodiment 1 and Embodiment 2.

[0251] Furthermore, the semiconductor device 57B of Embodiment 7 achieves the same effect as the semiconductor device 56B of Embodiment 6 by providing multiple P-type semiconductor regions (P-type semiconductor region groups 31AG and 31BG) that are separately provided from each other as P-type semiconductor regions.

[0252] Furthermore, in the semiconductor device 57B of the second embodiment 7, a power supply voltage V1 is applied to the P-type semiconductor region group 31AG, and a power supply voltage V4 is applied to the P-type semiconductor region group 31BG. The power supply 11 and the power supply 14 are set independently of each other. Therefore, the power supply voltage V1 and the power supply voltage V4 can be set independently.

[0253] Therefore, similar to the first embodiment of embodiment 7, the semiconductor device 57B of the second embodiment of embodiment 7 gradually mitigates the electric field around the N-type semiconductor region 21 in two stages, thereby making it easy to adjust the electric field distribution around the N-type semiconductor region 21.

[0254] In addition, similar to the second embodiment of embodiment 6, the second embodiment of embodiment 7 adopts the following method: at least one of the first P-type semiconductor region and the second P-type semiconductor region is set as a P-type semiconductor region group composed of a plurality of P-type partial semiconductor regions.

[0255] (Method 3) Figure 12This is an explanatory diagram schematically showing the planar structure of the semiconductor device 57C according to the third embodiment of this disclosure 7.

[0256] As shown in the figure, the semiconductor device 57C of the third embodiment 7 includes a P-type semiconductor layer 1, an N-type high-voltage separation region 2, an N-type high-potential region 3 and a diode region 4 disposed on the P-type semiconductor layer 1, power supplies 11, 12 and 14, and a capacitor C3 as the main structural elements.

[0257] The following is about... Figure 9 The same structures of Embodiment 6 shown in the third embodiment are labeled with the same reference numerals and descriptions are omitted as appropriate. The description will focus on the characteristic parts of the semiconductor device 57C of Embodiment 7 in the third embodiment.

[0258] and Figure 10 The first method shown and Figure 11 Similarly, the semiconductor device 57C of the third embodiment of embodiment 7 is characterized by further including a power supply 14, which serves as a fourth power supply providing a power supply voltage V4 as a fourth voltage. The power supply voltage V4 is set to be lower than the power supply voltage V2.

[0259] A power supply voltage V4, serving as the fourth voltage, is applied to the second P-type semiconductor region, namely the P-type semiconductor region 31B, via wiring L6. Specifically, node P6 on the P-type semiconductor region 31B is electrically connected to one end of wiring L6, and the positive terminal of the power supply 14 is connected to the other end of wiring L6.

[0260] In the semiconductor device 57C of the third embodiment 7, the power supply voltage V1 applied to the P-type semiconductor region 33A and the power supply voltage V4 applied to the P-type semiconductor region 31B are set to be lower than the power supply voltage V2 applied to the N-type semiconductor region 21. Therefore, a reverse bias can be applied between each of the P-type semiconductor regions 33A and 31B and the N-type high-voltage separation region 2.

[0261] Therefore, by generating a depletion layer at the interface between the first P-type parallel region and the second P-type parallel region of the P-type semiconductor region 33A and the N-type high-voltage separation region 2, the electric field around the N-type semiconductor region 21 electrically connected to the cathode of the diode D4 can be mitigated.

[0262] Therefore, the semiconductor device 57C of the third embodiment 7 has the same effect as that of embodiments 1 and 2.

[0263] Furthermore, the semiconductor device 57C of the third embodiment 7 uses multiple P-type semiconductor regions (P-type semiconductor region 33A and P-type semiconductor region 31B) that are separately disposed from each other as P-type semiconductor regions, thereby achieving the same effect as the semiconductor device 56C of the third embodiment 6.

[0264] Furthermore, in the semiconductor device 57C of the third embodiment 7, a power supply voltage V1 is applied to the P-type semiconductor region 33A, and a power supply voltage V4 is applied to the P-type semiconductor region 31B. The power supply 11 and the power supply 14 are set independently of each other. That is, the power supply voltage V1 and the power supply voltage V4 are independent of each other. Therefore, the power supply voltage V1 and the power supply voltage V4 can be set independently.

[0265] Therefore, similar to the first and second embodiments of Embodiment 7, the semiconductor device 57C of Embodiment 7 in the third embodiment gradually mitigates the electric field around the N-type semiconductor region 21 in two stages, thereby making it easy to adjust the electric field distribution around the N-type semiconductor region 21.

[0266] In addition, in the third embodiment of embodiment 7, as a variation of the combination of P-type semiconductor region 33A and P-type semiconductor region 31B, similar to the third embodiment of embodiment 6, the first to third variations are considered.

[0267] <Other> In the above embodiments, the top view shape of the N-type high-potential region 3 is set to a quadrilateral shape, but it can also be set to a polygon shape of triangle or more.

[0268] Furthermore, within the scope of this disclosure, various embodiments can be freely combined, or appropriately modified or omitted.

[0269] The various methods disclosed herein are summarized and recorded below as appendices.

[0270] (Note 1) A semiconductor device, comprising: P-type semiconductor layer; An N-type high-potential region is disposed on the P-type semiconductor layer; The N-type high-voltage separation region is disposed on the P-type semiconductor layer and surrounds the N-type high-potential region when viewed from above. A diode region, which is disposed independently of the N-type high-voltage separation region on the P-type semiconductor layer, has a diode that provides a second voltage to the anode that is higher than the first voltage; Type 1N semiconductor region and Type 2N semiconductor region, wherein the Type 1N semiconductor region and Type 2N semiconductor region are selectively disposed on the upper part of the Type N high-voltage-resistant separation region; and A P-type semiconductor region, selectively disposed above the N-type high-voltage separation region, provides a first voltage that is lower than the second voltage. In the semiconductor device The N-type impurity concentrations of the first N-type semiconductor region and the second N-type semiconductor region are set to be higher than the N-type high-voltage separation region. The first N-type semiconductor region, the second N-type semiconductor region, and the P-type semiconductor region are arranged without contact with each other. The second N-type semiconductor region is configured to be closer to the N-type high-potential region than the first N-type semiconductor region and the P-type semiconductor region. The P-type semiconductor region, when viewed from above, is positioned between the first N-type semiconductor region and the N-type high-potential region. The cathode of the diode is electrically connected to the type 1N semiconductor region. The second N-type semiconductor region is electrically connected to the N-type high-potential region.

[0271] (Note 2) The semiconductor device as described in Note 1 The N-type high-potential region appears as a polygon with a shape greater than a triangle when viewed from above. The first N-type semiconductor region has a first N-type parallel region that is parallel to at least one side of the N-type high-potential region when viewed from above. The second-N type semiconductor region has a second-N type parallel region that, when viewed from above, is parallel to at least one side of the N type high-potential region. The P-type semiconductor region has a P-type parallel region that is parallel to at least one side of the N-type high-potential region when viewed from above, and the P-type parallel region is disposed between the first N-type parallel region and the second N-type parallel region when viewed from above.

[0272] (Note 3) Semiconductor devices as described in Note 1 or 2 The P-type semiconductor region comprises a group of P-type semiconductor regions consisting of multiple P-type partial semiconductor regions that are separated from each other. The semiconductor device further includes relay wiring that is electrically connected to each of the plurality of said P-type partial semiconductor regions. The semiconductor device applies the first voltage to a plurality of P-type partial semiconductor regions of the P-type semiconductor region group via the relay wiring.

[0273] (Note 4) Semiconductor devices as described in Note 1 or 2 In the N-type high-voltage separation region, the peripheral region of the first N-type semiconductor region includes a first peripheral region close to the side of the second N-type semiconductor region and a second peripheral region away from the side of the second N-type semiconductor region. The P-type semiconductor region includes a surrounding area disposed in at least a portion of the first peripheral region and the second peripheral region, and which surrounds the first N-type semiconductor region when viewed from above.

[0274] (Note 5) Semiconductor devices as described in Note 4 The region surrounding the P-type semiconductor includes a region that completely surrounds the P-type semiconductor region, which, when viewed from above, seamlessly encloses the periphery of the 1N-type semiconductor region.

[0275] (Note 6) Semiconductor devices as described in Note 4 The region surrounding the P-type semiconductor region includes a first portion surrounding the P-type semiconductor region disposed in at least a portion of the first peripheral region, and a second portion surrounding the P-type semiconductor region disposed in at least a portion of the second peripheral region, wherein the first portion surrounding the P-type semiconductor region and the second portion surrounding the P-type semiconductor region are disposed separately from each other. The first portion is around the P-type semiconductor region where the first voltage is applied. The second part is surrounded by a third voltage that is lower than the second voltage.

[0276] (Note 7) Semiconductor devices as described in Note 6 At least one of the first part surrounding the P-type semiconductor region and the second part surrounding the P-type semiconductor region includes a group of partially surrounding P-type semiconductor regions, which is composed of a plurality of P-type partially semiconductor regions disposed separately from each other. The semiconductor device further includes relay wiring that is electrically connected to each of the plurality of said P-type partial semiconductor regions. The semiconductor device applies the first voltage or the third voltage to the portion surrounding the P-type semiconductor region group via the relay wiring.

[0277] (Note 8) The semiconductor device as described in any one of Notes 1 to 7, The P-type semiconductor region comprises multiple P-type semiconductor regions that are separated from each other.

[0278] (Note 9) Semiconductor devices as described in Note 8 The plurality of said P-type semiconductor regions include a first P-type semiconductor region and a second P-type semiconductor region. The semiconductor device applies the first voltage to both the first P-type semiconductor region and the second P-type semiconductor region.

[0279] (Note 10) Semiconductor devices as described in Note 8 The plurality of said P-type semiconductor regions include a first P-type semiconductor region and a second P-type semiconductor region. The first voltage is applied to the first P-type semiconductor region. The second P-type semiconductor region is subjected to a fourth voltage that is lower than the second voltage. The first voltage and the fourth voltage are independent of each other.

[0280] (Note 11) The semiconductor device as described in any one of Notes 1 to 10, The N-type high-potential region has a first electrode for the high-potential side power supply voltage and a second electrode for the high-potential side reference voltage. The semiconductor device further includes a charging element, one electrode of which is electrically connected to the first electrode of the N-type high-potential region, and the other electrode of which is electrically connected to the second electrode of the N-type high-potential region.

[0281] (Note 12) The semiconductor device as described in any one of Notes 1 to 10, The first N-type semiconductor region, the second N-type semiconductor region, and the P-type semiconductor region are configured to each surround more than half of the outer periphery of the N-type high-potential region when viewed from above. Label Explanation

[0282] 1P type semiconductor layer 2N type high pressure resistant separation zone 3N type high potential region 4 diode region 5 power electrodes 6 reference electrodes 11-14 power supply 21, 22N type semiconductor regions 31, 31A, 31B, 33, 33A, 34, 35P type semiconductor regions 31G, 31AG, 31BG, 34G P-type semiconductor region groups Semiconductor regions of types 41, 41A, 41B, and 44P Semiconductor devices 51-54, 55A, 55B, 56A-56C, 57A-57C 61, 62 surrounding areas C3 capacitor D4 diode.

Claims

1. A semiconductor device comprising: a P-type semiconductor layer; an N-type high-potential region provided on the P-type semiconductor layer; an N-type high-withstand-voltage separation region provided on the P-type semiconductor layer so as to surround the N-type high-potential region in plan view; a diode region provided on the P-type semiconductor layer independently of the N-type high-withstand-voltage separation region, having a diode that supplies a second voltage higher than a first voltage to an anode; a first N-type semiconductor region and a second N-type semiconductor region selectively provided in an upper layer portion of the N-type high-withstand-voltage separation region; and a P-type semiconductor region selectively provided in the upper layer portion of the N-type high-withstand-voltage separation region, supplying the first voltage lower than the second voltage, the semiconductor device being characterized in that: N-type impurity concentrations of the first and second N-type semiconductor regions are set higher than an N-type impurity concentration of the N-type high-withstand-voltage separation region, the first and second N-type semiconductor regions and the P-type semiconductor region are provided without contact relation to each other, the second N-type semiconductor region is disposed closer to the N-type high-potential region than the first N-type semiconductor region and the P-type semiconductor region, the P-type semiconductor region is disposed between the first N-type semiconductor region and the N-type high-potential region in plan view, a cathode of the diode is electrically connected to the first N-type semiconductor region, the second N-type semiconductor region is electrically connected to the N-type high-potential region.

2. The semiconductor device according to claim 1, characterized in that: the N-type high-potential region has a polygonal shape of three or more sides in plan view, the first N-type semiconductor region has a first N-type parallel region parallel to at least one side of the N-type high-potential region in plan view, the second N-type semiconductor region has a second N-type parallel region parallel to the at least one side of the N-type high-potential region in plan view, the P-type semiconductor region has a P-type parallel region parallel to the at least one side of the N-type high-potential region in plan view, the P-type parallel region being disposed between the first N-type parallel region and the second N-type parallel region in plan view.

3. The semiconductor device according to claim 1 or 2, characterized in that: the P-type semiconductor region includes a P-type semiconductor region group composed of a plurality of P-type partial semiconductor regions provided independently of each other, the semiconductor device further includes a relay wiring electrically connected to the plurality of P-type partial semiconductor regions, respectively, the semiconductor device applies the first voltage to the plurality of P-type partial semiconductor regions of the P-type semiconductor region group, respectively, via the relay wiring.

4. The semiconductor device according to claim 1 or 2, characterized in that: ​ In the N-type high-voltage-withstand separation region, a peripheral region of the first N-type semiconductor region includes a first peripheral region close to the second N-type semiconductor region side and a second peripheral region away from the second N-type semiconductor region side, The P-type semiconductor region includes a surrounding P-type semiconductor region disposed around the first peripheral region and the second peripheral region each at least a portion thereof, and disposed so as to surround the first N-type semiconductor region when viewed from above.

5. The semiconductor device according to claim 4, wherein The surrounding P-type semiconductor region includes a complete surrounding P-type semiconductor region disposed so as to surround the periphery of the first N-type semiconductor region without a gap when viewed from above.

6. The semiconductor device according to claim 4, wherein The surrounding P-type semiconductor region includes a first partial surrounding P-type semiconductor region disposed at least a portion of the first peripheral region, and a second partial surrounding P-type semiconductor region disposed at least a portion of the second peripheral region, the first partial surrounding P-type semiconductor region and the second partial surrounding P-type semiconductor region being disposed separately from each other, The first partial surrounding P-type semiconductor region is applied with the first voltage, The second partial surrounding P-type semiconductor region is applied with a third voltage lower than the second voltage.

7. The semiconductor device according to claim 6, wherein At least one of the first partial surrounding P-type semiconductor region and the second partial surrounding P-type semiconductor region includes a partial surrounding P-type semiconductor region group composed of a plurality of P-type partial semiconductor regions disposed separately from each other, The semiconductor device further includes a relay wiring electrically connected to the plurality of P-type partial semiconductor regions respectively, The semiconductor device applies the first voltage or the third voltage to the partial surrounding P-type semiconductor region group via the relay wiring.

8. The semiconductor device according to any one of claims 1 to 7, wherein The P-type semiconductor region includes a plurality of P-type semiconductor regions disposed separately from each other.

9. The semiconductor device according to claim 8, wherein The plurality of P-type semiconductor regions includes a first P-type semiconductor region and a second P-type semiconductor region, The semiconductor device commonly applies the first voltage to the first P-type semiconductor region and the second P-type semiconductor region.

10. The semiconductor device according to claim 8, wherein The plurality of P-type semiconductor regions includes a first P-type semiconductor region and a second P-type semiconductor region, The first P-type semiconductor region is applied with the first voltage, The second P-type semiconductor region is applied with a fourth voltage lower than the second voltage, The first voltage and the fourth voltage are independent of each other.

11. The semiconductor device according to any one of claims 1 to 10, wherein The N-type high-potential region has a first electrode for a high-potential side power supply voltage and a second electrode for a high-potential side reference voltage, The semiconductor device further includes a charging element having one electrode electrically connected to the first electrode of the N-type high-potential region and the other electrode electrically connected to the second electrode of the N-type high-potential region.

12. The semiconductor device according to any one of Claims 1 to 11, wherein The first N-type semiconductor region and the second N-type semiconductor region and the P-type semiconductor region are each disposed so as to enclose more than half of the outer periphery of the N-type high-potential region in plan view.

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