Semiconductor device

Abstract

Provided is a semiconductor device provided with: an n-type first semiconductor region (11) which is formed on the front surface side of a p-type semiconductor substrate (10) and which serves as a common path for currents flowing through a switching element and a protection element; an n-type common contact region (12) that is formed on the first semiconductor region at a high impurity concentration and that is connected to a common electrode (21) that also serves as a first main electrode and a protection element-side first electrode; a p-type second semiconductor region (13) and a p-type third semiconductor region (14), which are locally formed in the first semiconductor region (11) at a location separated from the common contact region; and an n-type fourth semiconductor region (15) partially formed in the second semiconductor region (13) in plan view, the second main electrode (22) being connected to the fourth semiconductor region (15), and a protection element-side second electrode (26) being provided inside the third semiconductor region (14).

Description

Technical Field

[0001] This disclosure relates to a semiconductor device that combines a horizontal switching element with a protection element. Background Technology

[0002] As power semiconductor devices, laterally diffused MOS (LDMOS) transistors, which have a drift layer through which conduction current flows in the planar direction of the semiconductor layer, are preferred as switching devices due to their improved breakdown voltage. In this case, the length of the region (high-voltage region) along the electric field direction, which should be ensured to achieve a particularly high electric field strength at the off state, is set in the in-plane direction of the semiconductor layer in a way that ensures the breakdown voltage.

[0003] Furthermore, as described in Patent Document 1, a protective element (e.g., a diode) is connected between the source and drain of the LDMOS in the LDMOS. When a surge voltage exceeding the withstand voltage is applied to the LDMOS, the protective element breaks down instead of the LDMOS to bypass the current, thereby preventing the LDMOS or the circuit connected to it from being damaged.

[0004] In this case, the breakdown voltage of the protective element (diode) is set to be higher than that of the LDMOS. Therefore, the diode is also horizontal, and a high-voltage region of a certain size is set in the diode, similar to that of the LDMOS. In the technology described in Patent Document 1, the LDMOS is formed in a region on a plane, and the region constituting the diode surrounds the LDMOS.

[0005] Patent Document 1: Japanese Patent Application Publication No. 2006-319072

[0006] As described above, in order to form an LDMOS and a lateral protection element on a common semiconductor substrate and to improve the voltage withstand capability of both, a large area is required considering the combined area occupied by the two. Alternatively, with limited area, it is not possible to increase the current capacity flowing through the LDMOS or the protection element, thus reducing the protection function. Therefore, it is difficult to obtain a small semiconductor device with high voltage withstand capability that combines a switching element and a protection element protecting the switching element. Summary of the Invention

[0007] This disclosure was made in view of such problems, and its purpose is to provide a semiconductor device that solves the aforementioned problems.

[0008] To address the aforementioned issues, this disclosure has the following structure.

[0009] The semiconductor device disclosed herein comprises, on a semiconductor substrate, a switching element controlled to switch on and off between a first main electrode on a high-potential side and a second main electrode on a low-potential side; and a protection element that, when the switching element is turned off, allows current to bypass between the first electrode on the protection element side on the high-potential side and the second electrode on the protection element side on the low-potential side. The semiconductor device is characterized by comprising: a first semiconductor region of a second conductivity type opposite to a first conductivity type, formed on the surface side of the semiconductor substrate of the first conductivity type; a common electrode that serves as both the first main electrode and the first electrode on the protection element side; and a common contact region of the second conductivity type, locally formed with a high impurity concentration above the first semiconductor region and connected to the... The common electrode is connected; a second semiconductor region of the first conductivity type is partially formed in the first semiconductor region and is separated from the common contact region when viewed from above; a third semiconductor region of the first conductivity type is partially formed in the first semiconductor region, separated from the common contact region and the second semiconductor region when viewed from above; and a fourth semiconductor region of the second conductivity type is partially formed in the second semiconductor region when viewed from above, wherein a square in the second semiconductor region and the third semiconductor region surrounds the other side when viewed from the common contact region, the fourth semiconductor region is connected to the second main electrode, and the third semiconductor region is connected to the second electrode on the protection element side.

[0010] Alternatively, when viewed from above, a fifth semiconductor region of the second conductivity type is disposed in the third semiconductor region, and the second electrode on the protection element side is connected to the fifth semiconductor region and the third semiconductor region.

[0011] Alternatively, when viewed from above, the second semiconductor region can be formed as a ring surrounding the common contact region.

[0012] Alternatively, the other of the second semiconductor region and the third semiconductor region may be the third semiconductor region.

[0013] Alternatively, the third semiconductor region may be segmented and comprised of multiple regions when viewed from above.

[0014] Alternatively, the other of the second semiconductor region and the third semiconductor region may be the third semiconductor region, wherein the first semiconductor region is formed deeper on the underside of the third semiconductor region than the inner side of the third semiconductor region when viewed from above.

[0015] Alternatively, the semiconductor device may include: a first control electrode formed on the second semiconductor region, which controls the switching between the first main electrode and the second main electrode in the switching element; and a second control electrode connected to the second semiconductor region.

[0016] Alternatively, the semiconductor device may include an inter-element field plate electrically connected to any one of the first control electrode, the second control electrode, and the third semiconductor region, and facing the surface of the first semiconductor region between the second semiconductor region and the third semiconductor region when viewed from above, separated by an insulating layer.

[0017] Alternatively, one of the second semiconductor region and the third semiconductor region may be the third semiconductor region.

[0018] Alternatively, the first semiconductor region may not be formed at a position that is further outward than either the second semiconductor region or the third semiconductor region.

[0019] Because this disclosure is configured as described above, it is possible to obtain a small semiconductor device with high voltage resistance that combines a switching element and a protective element for protecting the switching element. Attached Figure Description

[0020] Figure 1 This is a circuit diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0021] Figure 2 This is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0022] Figure 3 This is a top view showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0023] Figure 4 This is a cross-sectional view showing the structure of a first modified example of a semiconductor device according to an embodiment of the present disclosure.

[0024] Figure 5 This is a cross-sectional view showing the structure of a second modified example of a semiconductor device according to an embodiment of the present disclosure.

[0025] Figure 6 This is a cross-sectional view showing the structure of a third modified example of a semiconductor device according to an embodiment of the present disclosure.

[0026] Figure 7 This is a top view showing the structure of a fourth modified example of a semiconductor device according to an embodiment of the present disclosure.

[0027] Figure 8This is a top view showing the structure of a fifth modified example of a semiconductor device according to an embodiment of the present disclosure.

[0028] Figure 9 This is a circuit diagram illustrating the structure of a sixth modified example of a semiconductor device according to an embodiment of the present disclosure.

[0029] Figure 10 This is a circuit diagram illustrating the structure of a seventh modified example of a semiconductor device according to an embodiment of the present disclosure.

[0030] Label Explanation

[0031] 1-8: Semiconductor devices;

[0032] 10: p-type substrate (semiconductor substrate);

[0033] 11:n - Layer (first semiconductor region);

[0034] 12:n + Floor (public contact area);

[0035] 13:p - Layer (second semiconductor region);

[0036] 14:p - Layer (third semiconductor region);

[0037] 15:n + Layer (fourth semiconductor region);

[0038] 16, 18: p + layer;

[0039] 17:n + Layer (fifth semiconductor region);

[0040] 20: Interlayer insulation layer;

[0041] 21: Drain electrode (common electrode, first main electrode, first electrode on the protection element side);

[0042] 22, 32: Source electrode (second main electrode);

[0043] 23, 33: Back gate electrode (second control electrode);

[0044] 24: Gate oxide film;

[0045] 25, 35: Gate electrode (first control electrode);

[0046] 26, 36: Emitter electrode (second electrode on the protection element side);

[0047] 30: Field board;

[0048] 37, 251: Inter-component field board;

[0049] AN: Anode (second electrode on the protection element side);

[0050] B: Base;

[0051] BG: Back gate (second control electrode);

[0052] C: Collector (first electrode on the protection element side);

[0053] CA: Cathode (first electrode on the protection element side);

[0054] D: Drain electrode (first main electrode: high potential side electrode);

[0055] E: Emitter: (Second electrode on the protection element side);

[0056] G: Gate (first control electrode);

[0057] S: Source electrode (second main electrode: low potential side electrode);

[0058] T1: Component (switching component);

[0059] T2, T3, T4: Components (protective components). Detailed Implementation

[0060] The semiconductor device according to the embodiments of the present disclosure will be described below. Furthermore, in the following description of the drawings, the same or similar parts are labeled with the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the length ratios of various parts, etc., may differ from reality. Therefore, specific dimensions should be determined by referring to the following description. Additionally, the drawings naturally include parts with different dimensional relationships or ratios. Furthermore, the embodiments shown below exemplify a device for embodying the technical concept of the present disclosure; the technical concept of the present disclosure does not limit the shape, structure, arrangement, etc., of the constituent components to the following content. Various modifications can be made to the embodiments of the present invention in the claims. Furthermore, in this disclosure, terms such as "upper" and "lower" are used for ease of description, and even when disposed on a side surface, as long as they are substantially the same as the constituent elements of the present disclosure, they are still within the scope of the present disclosure. In addition, "upper" includes not only the case formed in contact with the object but also the case formed across other layers. Furthermore, in this disclosure, "connection" is not limited to direct connection. Even when some components such as resistors are connected in between, as long as the connection is substantially the same as the constituent elements of this disclosure, it falls within the scope of this disclosure.

[0061] Figure 1 This is a circuit diagram showing the structure of the semiconductor device 1. Here, an n-channel MOSFET (LDMOS) element (switching element) T1, which serves as a switching element, and an npn-type bipolar transistor element (protection element) T2 are formed on a common semiconductor substrate. Here, the n-type layer (drift layer) connected to the drain (D: high-potential side electrode (first main electrode)) in element T1 and the collector layer (n-type layer) connected to the collector (C) in element T2 are shared. The source (S: low-potential side electrode (second main electrode)), gate (G: first control electrode), and their associated structures are the same as those of a conventional MOSFET. When the potential VS of the source (S) is usually set to ground potential (GND) and the potential VD of the drain (D) is set to a positive potential, the current between the drain (D) and the source (S) is controlled by the potential VG of the gate (G).

[0062] At this time, the potential VBG of the body layer (BG) of element T1 (MOSFET) is sometimes equal to VS, but sometimes it is controlled independently of VS by applying a specified potential to the back gate electrode (second control electrode). Thus, the characteristics of element T1 can be adjusted.

[0063] Furthermore, component T2 is an npn bipolar transistor (npn transistor), and its collector (C: the first electrode on the protection element side) is connected to the drain (D) of component T1, thus being subjected to the aforementioned VD. Additionally, the potential of its emitter (E: the second electrode on the protection element side) is set to VISO, close to the potential of the outer periphery of the component, similar to VBG. However, the p-type layer that becomes its base (B) and the n-type layer that becomes its emitter (E) are actually short-circuited through wiring, so component T2 effectively operates with two terminals. With the VD and VISO potentials set as described above, component T2 is normally off, but when VD increases, component T2 turns on, allowing a large current to flow. This operation is similar to the breakdown in parasitic transistor operation. The characteristics of component T2, such as its on-state voltage, can be understood through the n... + Layer 17 and n - The spacing of layer 11, p - Layer 14 or n - Fine-tune the impurity concentration or VISO of layer 11.

[0064] If a high voltage surge or other positive voltage is applied to the drain (D) side when component T1 is turned off, component T1 may break down. The large current flowing during this breakdown would cause damage to component T1 or the circuit connected to it, which is therefore undesirable. By turning on component T2 earlier than the time component T1 fails, damage to component T1 can be suppressed. That is, component T2 can be used as a protective element to protect component T1.

[0065] Furthermore, VBG in component T1 and VISO in component T2 are sometimes shared (shown as dashed lines in the diagram), and sometimes adjusted independently. This can be easily achieved through wiring connections. Additionally, as described later, it is also possible to achieve... Figure 1 Either VBG or VISO in the structure automatically becomes part of the GND structure.

[0066] Here, on the device T1 side, the region on the plane of the semiconductor layer where the electric field strength increases during cutoff is particularly the region between the gate (G) and drain (D) where the potential difference between its two ends increases. On the device T2 side, the region where the electric field strength increases during cutoff is the region between the collector (C) and base (B). Therefore, to achieve high breakdown voltage, these regions need to be expanded along the direction of the electric field. Figure 1 In this semiconductor device 1, the drain (D) of element T1 and the collector (C) of element T2 are shared (potential VD). Furthermore, in this semiconductor device 1, these regions (the voltage withstand assurance region J described later) are formed to be repeatedly shared when viewed from above. Therefore, in this semiconductor device 1, even when the voltage withstand of elements T1 and T2 is set to be relatively high, the overall size can be reduced.

[0067] Figure 2 This is a cross-sectional view showing the structure of the semiconductor device 1. Here, it is shown... Figure 1 The cross-sections of the portions containing elements T1 and T2 are formed on a p-type substrate (semiconductor substrate) 10, which is a p-type (first conductivity type). Here, the regions where element T1 functions (switching element region R1), where element T2 functions (protection element region R2), and the voltage withstand assurance region J are also shown. In this structure, [the following is described]... Figure 1 The case where the dashed line does not exist (the case where VBG in component T1 and VISO in component T2 are controlled independently).

[0068] In the figure, on the surface of the p-type substrate 10, there is a low concentration of n-type (second conductivity type) n - Layer 11 (first semiconductor region) is formed more extensively in the shape shown in the figure. Figure 1 Both components T1 and T2 in the n-axis use this n-axis. - Layer 11 is formed. Figure 2 In, n - The right side of layer 11 is the low potential side (the side closest to ground potential), and the left side is the high potential side (e.g., above +1000V). - Layer 11 has varying depths, forming deeper on the high-potential and low-potential sides, and shallower in the middle at a certain depth. This makes n -Layer 11, with its structure extending deeper on the high-potential side and shallower on the low-potential side at a certain depth, improves n. - Layer 11 is effective in terms of voltage withstand capability. However, the profile in the depth direction at such a high potential side is appropriately set.

[0069] In the diagram, at n - A high concentration of n-type layers, i.e., n, is formed on the left side (high potential side) of layer 11. + Floor (public contact area) 12. + Layer 12 as Figure 1 The contact layers in the drain (D) region of T1 and the collector (C) region of T2 function, and their potential is set to... Figure 1 VD in the diagram. On the other hand, in the figure, n - On the right side (low potential side) surface of layer 11, low concentrations of p-type p-type polymers are formed separately from each other. - Layer (second semiconductor region) 13 and p - Layer (third semiconductor region) 14, p - Layer 13 is used in component T1 and is located on the right side of the figure, while layer 14 is used in component T2 and is located on the left side of the figure. - The surface of layer 13 has a high concentration of n-type n. + Layer 15 (fourth semiconductor region) is locally formed on the left side of the figure, with a high concentration of p-type p + Layer 16 is locally formed on the right side of the figure. On the other hand, in p - Similarly, on the surface of layer 14, n + Layer (fifth semiconductor region) 17 is locally formed on the left side of the figure, p + Layer 18 is locally formed on the right side of the figure.

[0070] p - Layer 13 functions as the body layer of component T1 (MOSFET), p - The potential of layer 13 is set to Figure 1 VBG in Chinese. + Layer 15 functions as the source (S) region of element T1, n + The potential of layer 15 is set to Figure 1 VS in p + Layer 16 is formed to contact with p-layer 13, which forms a bulk layer. + The potential of layer 16 is set to VBG. On the other hand, p - Layer 14 functions as the base (B) region of element T2, n + Layer 17 functions as the emitter (E) region of T2. + Layer 18 is formed for use with p, which becomes the base.- Layer 14 contact, p + Layer 18, n + The potential of layer 17 is set to Figure 1 VISO in the context of VISO.

[0071] An interlayer insulating layer 20 composed of a silicon oxide film is formed on the semiconductor substrate 10 on which this structure is formed. Each wiring is connected to the aforementioned layers through an opening formed in the interlayer insulating layer 20, thereby realizing... Figure 1 The circuit structure. First, in n + Layer 12 connects to the drain electrode (common electrode) 21 of element T1. As described above, the drain electrode 21, whose potential is set to VD in the figure, also serves as the collector electrode of element T2. In n + Layer 15 is connected to a source electrode (second main electrode) 22 with a potential set to VS, on its right side in the figure, at p + Layer 16 is connected to a back gate electrode (second control electrode) 23 with a potential set to VBG. As described above, in this semiconductor device 1, independent control is achieved. Figure 1 The VS, VBG, and VISO values ​​are specified. Additionally, the potential of the p-type substrate 10 is typically set to GND.

[0072] Additionally, in n + Layer 15, and n exposed on its left side surface. - p up to layer 11 - On the surface of layer 13, a gate oxide film 24, thinner than the interlayer insulating layer 20, is formed opposite to it, with a potential set to... Figure 1 The gate electrode (first control electrode) 25 of VG is formed. With this structure, a MOSFET, i.e., device T1, is formed that operates using the drain electrode 21, source electrode 22, and gate electrode 25 (and consequently, back gate electrode 23). In this MOSFET, when turned on, at p... - Layer 13, and up to n + n up to layer 12 - When a conduction current flows through layer 11 and a high voltage is applied to the drain electrode 21 during the cutoff state, the n region... - At least a portion of layer 11 is exhausted.

[0073] On the other hand, in n + Layer 17, p + Layer 18 is connected to a potential that is set to Figure 1 The emitter electrode (second electrode on the protection element side) 26 of the VISO is thus formed. Figure 1 Component T2. When component T1 is normally disconnected, VISO in component T2 also becomes close to ground potential, and n, as part of component T2, functions... -At least a portion of layer 11 is depleted. Therefore, element T2 has a relatively small impact on the operation of element T1.

[0074] In addition, Figure 2 In the middle, regarding the surface side, p - Layer 14 and n + n between layers 1 and 2 - Layer 11, due to the increased electric field strength in the depletion layer formed when component T1 is turned off, becomes the region where withstand voltage must be ensured (withstand voltage assurance region) J. Here, to ensure withstand voltage, in n + On the surface between layer 17 and layer n+ 12, separated by a silicon oxide film thicker than the gate oxide film 24, multiple field plates 30 are arranged along the left-right direction (the direction in which the electric field distribution is generated during use). The field plate 30 on the highest potential side (left side in the figure) is connected to the drain electrode 21, and the field plate 30 on the lowest potential side (right side in the figure) is connected to the emitter electrode 26. + Layer 17 (potential VISO) and n + The potential between layers 12 (potential VD) is distributed to adjacent field plates 30 located between them through capacitive coupling with each other, thereby increasing the potential of the region J in which the field plates 30 are arranged. - The surface potential of layer 11 is appropriately distributed, and local increases in electric field strength are suppressed. The function of such a field plate 30 is as described, for example, in Japanese Patent No. 3275964. That is, this structure can improve the withstand voltage in the withstand voltage assurance region J.

[0075] In addition, Figure 2 In the diagram, the leftmost field plate 30 is connected to the drain electrode 21 via vias formed in the interlayer insulating layer 20, and the rightmost field plate 30 is connected to the emitter electrode 26 vias formed in the interlayer insulating layer 20. Thus, as described above, the potentials of the field plates 30 at both ends are determined. However, for example, instead of providing such vias, the leftmost field plate and drain electrode can be arranged close together laterally or longitudinally in the diagram, and capacitively coupled to the other field plates in the same way. The same applies to the rightmost field plate 30 and emitter electrode 26. That is, as long as the same effect can be obtained by arranging the field plates, the positional (connection, coupling) relationships between the field plates at the left and right ends (high potential side, low potential side) and the drain electrode (high potential side electrode) and emitter electrode (low potential side electrode) can be appropriately set.

[0076] Furthermore, the thicker silicon oxide film in region J where the field plate 30 is formed is actually a LOCOS oxide film. Therefore, the surface of the semiconductor layer (n-layer 11, etc.) in this region is actually located at a p-value directly below the gate electrode 35. -The surfaces of layer 13, located towards the lower side, are not on the same plane. Figure 2 In simplified terms, this is described as the surfaces of the semiconductor layers forming a single plane. The same applies to the sectional views described later.

[0077] Additionally, as described above, the gate electrode 25 is formed on p - On layer 13, but the gate electrode 25 is on Figure 2 China further towards p - Layer 14 extends to the side, and in this portion, it is separated from n by a silicon oxide film of the same thickness as the aforementioned field plate 30. - The surfaces of layer 11 are opposite. When element T1 is normally off, the depletion layer from p... - Layer 14 and n - The interface of layer 11 is extended, but when VBG in component T1 and VISO in component T2 are controlled independently, due to p - The potentials of layer 13 and p-layer 14 and n - The potential of layer 11 is different, therefore in n - From p in layer 11 - The depletion layer extending from layer 13 on the side and from p - The depleted layer extending to the side of layer 14 may abut (penetrate).

[0078] Through p - Layer 13 and p - Setting between layer 14 and n - The portion of layer 11 whose surface is opposed and whose surface potential is controlled in the same manner as that of the field plate 30 (inter-element field plate 251) serves as part of the gate electrode 25 (or an extension of the gate electrode 25), making punch-through difficult to occur. Alternatively, an inter-element field plate may be provided that is separate from the gate electrode.

[0079] exist Figure 2 In the structure, when a high voltage is applied to the drain electrode 21 when component T1 is turned off, n - Layer 11 is depleted. With a gradual increase in the voltage of the drain electrode 21, breakdown may occur in the depletion layer. The large current flowing during this breakdown can cause damage to component T1 or the circuit connected to it, which is therefore undesirable. By turning on component T2 earlier than the time when component T1 fails, damage to component T1 can be suppressed. That is, component T2 can be used as a protective element for component T1. At this time, for example, by adjusting p... - The impurity concentration of layer 14 makes it easy to design the turn-on voltage of component T2 to be lower than the breakdown voltage of component T1.

[0080] In addition, during the normal operation of component T1, Figure 2 p in -The lower side of layer 14 becomes the path for the conduction current to flow through component T1. Therefore, as shown in the figure, in order to fully ensure p - n on the lower side of layer 14 - The thickness of layer 11 is preferably such that p - n on the lower side of layer 14 - Layer 11 is formed at a greater depth. As mentioned above, n - Layer 11 is formed at a relatively shallow depth in the pressure-resistant assurance region J, but in p - Layer 14 and p - The layer 13 is formed deeper than the pressure-resistant assurance region J.

[0081] Figure 3 It is shown Figure 2 A top view of the structure of semiconductor device 1 as seen from above. Figure 2 The cross-section corresponds to the cross-section along direction AA in the figure. Here, semiconductor device 1 is positioned with n becoming the high-potential side. + A circle centered on layer 12 records the various layers (n) formed on the semiconductor substrate. + Layer 12, n-layer 11, p - Layer 13 and n therein + Layer 15, p + Layer 16, p - Layer 14 and its n+ layers 17, p + The planar shape of layer 18) means that all the aforementioned layers on the surface of the semiconductor substrate used here are annular. The aforementioned electrodes, etc., are as follows: Figure 2 As shown, they are connected to each layer accordingly. The gate electrode 25 is also shaped into a ring to directly control the on / off state of the current path, but the other electrodes do not need to be shaped into a ring like the layers. Alternatively, for example, the gate electrode can be disconnected in the circumferential direction as long as the on / off state of the current path can be controlled in the same way.

[0082] As shown here, semiconductor device 1 is formed with n as the high potential side region. + A circular shape with layer 12 at its center and a low-potential side region extending radially outwards is formed. An element T1, serving as a MOSFET, is formed in the radially extending region (switching element region) R1, and an element T2, serving as an npn transistor, is formed in the region (protection element region) R2, which is part of its inner side. Since the interior of region R2 can overlap with that of region R1, the semiconductor device 1 can be miniaturized compared to the technology described in Patent Document 1, etc. Therefore, the semiconductor device 1 becomes a small, high-voltage semiconductor device that combines the element T1 as a switching element and the element T2 as a protection element protecting the element T1. Furthermore, regarding the changes... Figure 3Examples of the planar shapes of the layers shown will be described later. Additionally, n becomes the common contact area. + Layers, including the drain electrode which becomes the common electrode, can also appear as a ring shape when viewed from above, but in reality, the n-shaped structure is not formed at their center. + The shape of the semiconductor layer or the metal layer constituting the electrode. In this case, their center is also understood to be the center of the circle or the like that constituting the shape.

[0083] A modified example (first modified example) of the semiconductor device 1 described above will be described. The circuit constructed by this semiconductor device 2 is similar to... Figure 1 The structure on the semiconductor substrate that implements this circuit is the same, but the structure on the semiconductor substrate that implements this circuit is the same. Figure 2 different. Figure 4 This illustrates the structure of the semiconductor device 2. Figure 2 The corresponding sectional view.

[0084] Here, n - Layer 11, n + Layer 12, drain electrode 21 and Figure 2 The structure is the same. However, the positional relationship of the structures related to the elements T1 and T2 here is different from that of the elements T2. Figure 2 The structure is the opposite. That is, in Figure 4 In the middle, p constitutes element T1 - Layer 13 and n therein + Layer 15, p + Layer 16 is formed on the side near the drain electrode 21. Figure 3 The radial inner side of the component T2 constitutes the p-axis of the component T2. - Layer 14 and n therein + Layer 17, p + Layer 18 is formed on the side away from the drain electrode 21. Figure 3 (Radially outward from the center), along with this, the source electrode 32, back gate electrode 33, and gate electrode 35 are also disposed on p. - On the side closest to layer 13, the emitter electrode 36 is located on p - The far side where layer 14 is located.

[0085] In this case, the field plate 30 is also with Figure 2 The same configuration applies. Here, regarding the field plate 30 on the highest potential side, and... Figure 2 Similarly connected to the drain electrode 21, but at the field plate 30 on the lowest potential side, as shown, by extending the gate electrode 35 to the left of the field plate 30, it becomes connected to... Figure 2 The structure is equivalent to the field plate 30 on the lowest potential side in the middle.

[0086] Additionally, in this case, p is set. - Layer 13 and p- Inter-element field plate 37 is located between layers 14 and is connected to the back gate electrode 33. The potential VBG applied to the back gate electrode 33 is also close to the ground potential. Therefore, if the potential of this portion of the n-layer 11 is used as a reference, the inter-element field plate 37 becomes a potential further negative than it, thus obtaining a potential similar to... Figure 2 The same effect is achieved with the inter-component field plate 251. In this case, also as described above, by adjusting p... - The impurity concentration of layer 14 allows the on-state voltage of device T2 to be lower than the breakdown voltage of device T1. The inter-device field plate 37 can also replace the back gate electrode 33 and have a potential of VISO at p. + Layer 18 connection.

[0087] Another modification (second modification) of the semiconductor device 1 described above will be described. Figure 5 This illustrates the structure of the semiconductor device 3. Figure 2 The corresponding sectional view.

[0088] exist Figure 2 In the structure, the outer p - Layer 13 is formed in n - In layer 11, in contrast, Figure 5 In, n - The end of the low-potential side (right side in the figure) of layer 11 is set at a potential ratio Figure 2 The structure has a higher high potential side (left side of the figure), therefore n - Layer 11 did not form as well as p - Layer 13 is further outward, n-layer 11's outermost p - Layer 13 directly abuts against the p-type substrate 10. Therefore, Figure 1 The VBG in the middle is equal to the GND, which is the potential of the p-type substrate 10. Apart from this, Figure 5 Structure and Figure 2 The structure remains unchanged compared to the previous version.

[0089] In this case, VBG in component T1 is set to GND. On the other hand, since it is not necessary to set p... - Layer 13 and p-type substrate 10 are separated by n - Layer 11 is separated, thus enabling the semiconductor device 3 to be miniaturized compared to the semiconductor device 1 described above.

[0090] Similarly, Figure 6 This is a cross-sectional view showing the structure of a semiconductor device 4 (third variation) which is modified in the same way as the semiconductor device 3 described above.

[0091] exist Figure 4 In the structure, the outer p -Layer 14 is formed in n - In layer 11, in contrast, Figure 6 In, n - The end of the low-potential side (right side in the figure) of layer 11 is set at a potential ratio Figure 4 The structure has a higher high potential side (left side of the figure), n - Layer 11 did not form as well as p - Layer 14 is further out, n - p on the outer side of layer 11 - Layer 14 abuts against the p-type substrate 10. Therefore, Figure 1 The VISO in the p-type substrate 10 is equal to the potential GND. Apart from this, Figure 6 Structure and Figure 4 The structure remains unchanged compared to the previous version.

[0092] In this case, the VISO of component T2 is set to GND. On the other hand, since it is not necessary to go through n... - Layer 11 will p - Layer 14 is separated from p-type substrate 10, thus enabling the semiconductor device 4 to be miniaturized compared to the semiconductor device 2 described above.

[0093] The cross-sectional structures of the first to third variations (semiconductor devices 2 to 4) described above ( Figures 4-6 ) and the aforementioned semiconductor device 1 ( Figure 2 This differs from the planar structure of the modified example described below (1). Figure 3 )different.

[0094] Figure 7 This illustrates the structure of the semiconductor device 5 in the fourth modified example, and... Figure 3 The corresponding top view. In this semiconductor device 5, similarly to the semiconductor device 1 described above, element T1(p - Layer 13, etc.) is formed on the radially outer side, element T2 (p - Layer 14, etc., is formed radially inward. Figure 3 In the middle, p - Layer 14 and n therein + Layer 17, p + Layer 18 is formed with p - Layer 13 and its n+ layers 15, p + Layer 16 has the same annular shape. In contrast, in this semiconductor device 5, the p-shaped structure constituting element T1... - Layer 14 and n therein + Layer 17, p + Layer 18 is divided into four sections circumferentially. Therefore, in Figure 7 In the structure, p is not formed in the circumferential direction. -The region of layer 14 was formed in Figure 7 The four parts: top, bottom, left, and right.

[0095] exist Figure 3 In the structure, p - Layer 14 is annular and located at p - The inner side of layer 13, therefore the current flowing through element T1 in element region R1 needs to be p - n directly below layer 14 - Flowing through layer 11. (Example) Figure 7 As shown, by forming p adjacent in the circumferential direction - No p is formed between the areas of layer 14. - In the region of layer 14, the conducting current of element T1 can flow smoothly. That is, the conducting current of element T1, which is formed radially outward from element T2, can be increased.

[0096] exist Figure 7 Set in the structure Figure 2 Inter-component field plate 251 (p) - Layer 13 and p - In the case of the field plates between layers 14, it is preferable to have adjacent p in the circumferential direction. - The field plate extends above the n-layer 11 between layers 14. This allows for the suppression of adjacent p-layers in the circumferential direction. - The area between layers 14 is blocked by the depleted layer, which can be used effectively as a current path as described above.

[0097] Furthermore, in Figure 8 In the semiconductor device 6 shown (fifth modification), the fragmented p - n in layer 14 + Layer 17, p + Layer 18 is further subdivided. This allows for fine-tuning of the characteristics of component T2 (such as on-state voltage).

[0098] In the semiconductor devices 5 and 6, p - The total area of ​​layer 14 (the base layer of element T2) is smaller than that of the semiconductor device 1 described above, therefore the protection capability of element T2 may be reduced. To address this, it is possible to utilize p... - The problem is addressed by adjusting the impurity concentration of layer 14 to reduce the on-state voltage of component T2. On the other hand, as described above, since the current path for the on-state current of component T1 can be easily ensured, the allowable on-state current of component T1 can be increased.

[0099] In addition, Figure 1In the circuit, component T2, which is an npn transistor, is used as a protection element. However, a diode can also be used instead of an npn transistor. Figure 1 Component T2 in the middle. Figure 9 This illustrates the structure of a semiconductor device 7 that uses a modified example (sixth modification) of element T3 (diode), which serves as a protective element, and... Figure 1 The corresponding circuit diagram. In this case, instead of Figure 1 The collector (C) of the diode is replaced by the cathode (CA) of the diode that becomes element T3. Figure 1 The diode uses the emitter (E) and the anode (AN). In this case, during normal operation when VD is positive, the diode becomes reverse biased and therefore no current flows. However, by making VD exceed the diode's breakdown voltage, current flows, thus protecting element T1 in the same way as when using element T2 described above. Therefore, by setting the diode's breakdown characteristics in a way that protects element T1, element T1 is protected.

[0100] In this case, for example in Figure 2 In this process, the n-type layer constituting the cathode (CA) can also utilize n... - Layer 11, n + Layer 12, as the p-type layer constituting the anode (AN), can also use p... - Layer 14, p + Layer 18 does not form an n that becomes the emitter (E). + Layer 17. That is, except that n is not set in the semiconductor layer. + Layer 17, the rest of the structure is the same as semiconductor devices 1-6, and it can obtain Figure 9 Semiconductor device 7. In this case, the breakdown voltage (breakdown characteristics) of element T3 can be set via p - The concentration of impurities in layer 14 is adjusted accordingly.

[0101] Alternatively, as a protection element, the same n-channel MOSFET (LDMOS) as element T1 can be used instead of the npn transistor. Figure 10 The structure of a semiconductor device 8 as such a variation (seventh variation) is shown. The element (protection element) T4 used here is the same MOSFET as element T1, and as shown, its source (S), gate (G), and back gate (BG) are connected. For example, if... Figure 2 In the diagram where the field plate 30 on the far right is connected to the emitter electrode 26, the interlayer insulating layer 20 directly below it is made into a thinner gate oxide film 24. Therefore, by using this field plate 30 as... Figure 10 The gate (G) of element T4 in the middle is connected to the emitter electrode 26 and p. + Layer 18, n+ Layer 17 is connected, thereby making this structure easy to implement. In the element T2 of the first to third modified examples (semiconductor devices 2 to 6) described above, the protective element T4 can also be implemented in the same way by modifying the structure near the field plate.

[0102] Furthermore, the overall shape of the aforementioned semiconductor device 1, etc., is circular, p - Layer 13 and other regions are all in a ring shape. However, it is clear that even if they are not circular (ring-shaped), as long as the regions are ring-shaped (e.g., elliptical rings), the same effect can be achieved. Furthermore, it is obvious that even when these regions are not closed rings, or even when n... + The same effect can be achieved when at least one of layers 15 and 17 is configured discontinuously in the circumferential direction. For example, in Figure 2 The same effect is achieved when the structure extends uniformly perpendicular to the paper surface and each region forms parallel strips. In these cases, the shape of the field plate set in the pressure-resistant assurance zone is also appropriately set accordingly. The same applies to the field plates between components.

[0103] However, as Figure 3 As shown, by altering each layer (especially p) - Layers 13 and 14 are set to n + The annular shape centered on layer 12 can make the potential distribution uniform in the circumference and suppress the rise of electric field intensity in specific parts of the circumference, thus achieving a higher withstand voltage.

[0104] Furthermore, in the example above, multiple field plates 30 were used in the voltage withstand assurance region. However, if the voltage withstand can be ensured even without using such field plates, then it is unnecessary to provide field plates in the voltage withstand assurance region. Alternatively, a known resistive field plate can be used instead of multiple field plates 30 in the voltage withstand assurance region.

[0105] In this case, the structure of the semiconductor device becomes simpler. The same applies to the inter-component field plates.

[0106] Furthermore, other layers can be added or removed appropriately within the semiconductor layer. Additionally, in the example above, the same structure can obviously be applied even if the p-type and n-type phases in the semiconductor are completely reversed.

Claims

1. A semiconductor device, which is provided with, on a semiconductor substrate, a switching element controlled to be turned on and off between a first main electrode on a high potential side and a second main electrode on a low potential side, and a protection element which bypasses a current between a protection element side first electrode on a high potential side and a protection element side second electrode on a low potential side when the switching element is turned off, characterized by comprising: a first semiconductor region of a second conductivity type opposite to a first conductivity type, which is formed on a surface side of the semiconductor substrate of the first conductivity type; a common electrode which serves as the first main electrode and the protection element side first electrode; a common contact region of the second conductivity type which is locally formed with a high impurity concentration over the first semiconductor region and connected to the common electrode; a second semiconductor region of the first conductivity type which is locally formed in the first semiconductor region and separated from the common contact region in plan view; a third semiconductor region of the first conductivity type which is locally formed in the first semiconductor region separately from the common contact region and the second semiconductor region in plan view; and a fourth semiconductor region of the second conductivity type which is locally formed in the second semiconductor region in plan view, one of the second semiconductor region and the third semiconductor region is formed to surround the other as viewed from the outside of the common contact region, the fourth semiconductor region is connected to the second main electrode, and the third semiconductor region is connected to the protection element side second electrode.

2. The semiconductor device according to claim 1, characterized in that a fifth semiconductor region of the second conductivity type is provided in the third semiconductor region in plan view, and the protection element side second electrode is connected to the fifth semiconductor region and the third semiconductor region.

3. The semiconductor device according to claim 1 or 2, characterized in that the second semiconductor region is formed in a ring shape so as to surround the common contact region in plan view.

4. The semiconductor device according to claim 1 or 2, characterized in that the other of the second semiconductor region and the third semiconductor region is the third semiconductor region.

5. The semiconductor device according to claim 4, characterized in that the third semiconductor region is divided to be provided with a plurality of regions in plan view.

6. The semiconductor device according to claim 1, characterized in that the other of the second semiconductor region and the third semiconductor region is the third semiconductor region, and the first semiconductor region is formed deeper than an inner side of the third semiconductor region in plan view on a lower side of the third semiconductor region.

7. The semiconductor device according to claim 1 or 2, characterized by comprising: a first control electrode which is formed over the second semiconductor region and controls the switching element to be turned on and off between the first main electrode and the second main electrode; and a second control electrode which is connected to the second semiconductor region. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 8. The semiconductor device according to claim 7, wherein the semiconductor device includes an inter-element field plate electrically connected to any of the first control electrode, the second control electrode, and the third semiconductor region, and opposing a surface of the first semiconductor region between the second semiconductor region and the third semiconductor region in plan view via an insulating layer.

9. The semiconductor device according to claim 1 or 2, wherein the one of the second semiconductor region and the third semiconductor region is the third semiconductor region.

10. The semiconductor device according to claim 3, wherein the first semiconductor region is not formed at a position further outward than the one of the second semiconductor region and the third semiconductor region.

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