Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device may include a substrate including a first well region including an impurity of a first conductivity type; first active patterns on the first well region and spaced apart from each other in a first direction parallel to a top surface of the substrate; second active patterns on the first well region and spaced apart from each other in the first direction; a source / drain pattern on the first active pattern, the source / drain pattern including an impurity of a second conductivity type; and a first impurity pattern on the second active pattern, the first impurity pattern including an impurity of the first conductivity type. A width of a top surface of each of the second active patterns in the first direction may be greater than a width of a top surface of each of the first active patterns in the first direction.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0116081, filed on August 28, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a semiconductor device including a field-effect transistor and a method of manufacturing the semiconductor device. Background Technology

[0004] Semiconductor devices can include integrated circuits, including metal-oxide-semiconductor field-effect transistors (MOSFETs). To meet the growing demand for semiconductor devices with smaller pattern sizes and reduced design rules, MOSFETs are being miniaturized dramatically. This miniaturization of MOSFETs can lead to a degradation in the operational performance of semiconductor devices. Various studies are underway to overcome the technological limitations associated with the miniaturization of semiconductor devices and to achieve high-performance semiconductor devices. Summary of the Invention

[0005] An exemplary embodiment of the present invention provides a semiconductor device with improved electrical properties and a method for manufacturing the semiconductor device.

[0006] An exemplary embodiment of the present invention provides a semiconductor device with improved productivity and a method for manufacturing the semiconductor device.

[0007] According to some embodiments of the present invention, a semiconductor device may include: a substrate including a first well region, the first well region including impurities of a first conductivity type; a first active pattern spaced apart from each other on the first well region and in a first direction parallel to the top surface of the substrate; a second active pattern spaced apart from each other on the first well region and in the first direction; a source / drain pattern on the first active pattern, the source / drain pattern including impurities of a second conductivity type; and a first impurity pattern on the second active pattern, the first impurity pattern including impurities of the first conductivity type. The width of the top surface of each of the second active patterns in the first direction may be greater than the width of the top surface of each of the first active patterns in the first direction.

[0008] According to some embodiments of the present invention, a semiconductor device may include: a substrate including a first well region, the first well region including impurities of a first conductivity type; a first active pattern and a second active pattern on the first well region; a source / drain pattern on the first active pattern, the source / drain pattern including impurities of a second conductivity type; and a first impurity pattern on the second active pattern, the first impurity pattern including impurities of the first conductivity type. A first side surface of the second active pattern may protrude beyond the first side surface of the first active pattern in a first direction parallel to the top surface of the substrate.

[0009] According to some embodiments of the present invention, a semiconductor device may include: a substrate including a first well region, the first well region including an impurity of a first conductivity type; a first active pattern spaced apart from each other on the first well region and in a first direction parallel to the top surface of the substrate; a second active pattern spaced apart from each other on the first well region and in the first direction; a separator pattern between the first active pattern and the second active pattern; a source / drain pattern on the first active pattern, the source / drain pattern including an impurity of a second conductivity type; a first impurity pattern on the second active pattern, the first impurity pattern including an impurity of the first conductivity type; a first semiconductor pattern on the first active pattern; a second semiconductor pattern on the second active pattern; a gate electrode intersecting at least one of the first semiconductor patterns; and an active contact on the source / drain pattern and the first impurity pattern. The width of the top surface of each of the second active patterns in the first direction may be greater than the width of the top surface of each of the first active patterns in the first direction. Attached Figure Description

[0010] Figure 1 and Figure 2 This is a conceptual diagram illustrating the logic unit of a semiconductor device according to some embodiments of the present invention.

[0011] Figure 3 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention.

[0012] Figure 4 It shows Figure 3 A magnified view of a portion of it.

[0013] Figure 5A It is along Figure 3 A cross-sectional view taken from line A-A'.

[0014] Figure 5B It is along Figure 3 The cross-sectional view taken by line B-B'.

[0015] Figure 5C It is along Figure 3 A cross-sectional view taken from line C-C'.

[0016] Figure 5D It is along Figure 3 The cross-sectional view taken by line D-D'.

[0017] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 7A , Figure 7B and Figure 8 This is a diagram illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. Detailed Implementation

[0018] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments.

[0019] Figure 1 and Figure 2 This is a conceptual diagram illustrating the logic unit of a semiconductor device according to some embodiments of the present invention.

[0020] Reference Figure 1 A single-height cell (SHC) can be formed on the substrate 100. More specifically, a first electric field line M1_R1 and a second electric field line M1_R2 can be formed on the substrate 100. The first electric field line M1_R1 can be a conductive path providing the source voltage VSS (e.g., ground voltage). The second electric field line M1_R2 can be a conductive path providing the drain voltage VDD (e.g., power supply voltage).

[0021] A single-height cell SHC can be defined between a first electric field line M1_R1 and a second electric field line M1_R2. The single-height cell SHC may include a PMOSFET region PR and an NMOSFET region NR. The PMOSFET region PR and the NMOSFET region NR may be spaced apart from each other in a first direction D1 and may extend in a second direction D2. The first direction D1 and the second direction D2 may be parallel to the bottom surface and / or top surface of the substrate 100 and may intersect each other. For example, the first direction D1 and the second direction D2 may be orthogonal to each other, but this disclosure is not limited thereto.

[0022] A single-height cell (SHC) can constitute a single logic cell. In this specification, a logic cell can refer to a logic device configured to perform a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). In other words, a logic cell can include transistors constituting the logic device and interconnects connecting the transistors to each other.

[0023] Reference Figure 2A single-height unit SHC may include a first single-height unit SHC1 and a second single-height unit SHC2. The first single-height unit SHC1 and the second single-height unit SHC2 may be adjacent to each other in a first direction D1. The first single-height unit SHC1 may be defined between a first electric field line M1_R1 and a second electric field line M1_R2. The second single-height unit SHC2 may be defined between the second electric field line M1_R2 and a third electric field line M1_R3. The third electric field line M1_R3 may be a conductive path providing the source voltage VSS.

[0024] The first single-height unit SHC1 may include a first PMOSFET region PR1 and a first NMOSFET region NR1. The second single-height unit SHC2 may include a second PMOSFET region PR2 and a second NMOSFET region NR2. Although two single-height units SHC1 and SHC2 are shown in the figure, the inventive concept is not limited to this example.

[0025] The first PMOSFET region PR1 of the first single-height unit SHC1 and the second PMOSFET region PR2 of the second single-height unit SHC2 can operate together as a single PMOSFET region. Although not shown, the first NMOSFET region NR1 of the first single-height unit SHC1 and / or the second NMOSFET region NR2 of the second single-height unit SHC2 can operate together with the NMOSFET regions of adjacent single-height units as a single NMOSFET region.

[0026] First tap unit TC1 and second tap unit TC2 can be disposed next to single-height unit SHC. First tap unit TC1 can be located between single-height unit SHC and second tap unit TC2. First separator pattern DB1 can be located between single-height unit SHC and first tap unit TC1. Second separator pattern DB2 can be located between first tap unit TC1 and second tap unit TC2. In some embodiments, a third separator pattern DB3 can be disposed next to second tap unit TC2. In some other embodiments, the third separator pattern DB3 can be omitted. The first to third separator patterns DB1, DB2 and DB3 can constitute separator pattern DB. The active regions of single-height units SHC1 and / or SHC2 (e.g., logic cells) can be electrically separated from the active regions of tap units TC1 and / or TC2 by separator pattern DB.

[0027] Each of the first tap unit TC1 and the second tap unit TC2 can be used to apply voltages from power lines M1_R1 to M1_R3 to the well region of the substrate 100. Figure 2An example of the arrangement of tap units TC1 and TC2 and logic units SHC1 and SHC2 is shown, and those skilled in the art can make various changes to the arrangement of the logic units and tap units.

[0028] Figure 3 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention. Figure 4 It shows Figure 3 A magnified view of a portion of it. Figure 5A It is along Figure 3 A cross-sectional view taken from line A-A'. Figure 5B It is along Figure 3 The cross-sectional view taken by line B-B'. Figure 5C It is along Figure 3 A cross-sectional view taken from line C-C'. Figure 5D It is along Figure 3 The cross-sectional view taken by line D-D'.

[0029] Reference Figure 3 , Figure 4 and Figures 5A to 5D The substrate 100 may be configured to include a first region P1 and a second region P2. In some embodiments, the substrate 100 may be a semiconductor substrate formed of at least one of silicon, germanium, silicon-germanium, or a compound semiconductor material. In this specification, each of the expressions “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B, or C,” “at least one of A, B, and C,” and “at least one of A, B, or C” may be used to represent one of the elements listed in the expression or any possible combination of the listed elements.

[0030] The first region P1 can be a PMOSFET region. Specifically, the first region P1 may include a reference... Figure 2 The first PMOSFET region PR1 and the second PMOSFET region PR2 are described. The second region P2 may be an NMOSFET region. In some embodiments, the second region P2 may include a reference... Figure 2 The second NMOSFET region NR2 and the adjacent single-height cell NMOSFET region are described.

[0031] The substrate 100 may include a height unit HC, a first tap unit TC1, and a second tap unit TC2. The height unit HC may represent a reference. Figure 1 and Figure 2 The described logical unit. The first tap unit TC1 can represent a reference. Figure 2 The first tap unit TC1 is described. The second tap unit TC2 can be represented by reference. Figure 2 The second tap unit TC2 is described.

[0032] Substrate 100 may include a well region WE. The well region WE may include at least one of a first conductivity type and a second conductivity type impurity. In some embodiments, the first conductivity type impurity may be an n-type impurity, and the second conductivity type impurity may be a p-type impurity. The well region WE may include a first well region WE1 on a first region P1 and a second well region WE2 on a second region P2.

[0033] The first well region WE1 and the second well region WE2 may contain impurities of different conductivity types. In some embodiments, the first well region WE1 may contain impurities of a first conductivity type, and the second well region WE2 may contain impurities of a second conductivity type.

[0034] A bias voltage can be applied to the first well region WE1 in the first region P1 by means of elements provided on the first tap unit TC1 and described below. A bias voltage can be applied to the second well region WE2 in the second region P2 by means of elements provided on the second tap unit TC2 and described below.

[0035] Each of the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3 may be defined by a trench TR formed in the upper portion of the substrate 100. A device isolation pattern ST including insulating material may be formed in the trench TR (e.g., filling the trench TR). Each of the first to third active patterns ACT1, ACT2, and ACT3 may extend on the substrate 100 along a second direction D2. Each of the first to third active patterns ACT1, ACT2, and ACT3 may be a portion of the substrate 100. In some embodiments, this portion of the substrate 100 may protrude in a third direction D3. The third direction D3 may be perpendicular to the top surface of the substrate 100. In this specification, for ease of explanation, unless otherwise stated, the substrate 100 may be referred to as the remaining portion of the substrate 100 excluding the first to third active patterns ACT1, ACT2, and ACT3.

[0036] A first active pattern ACT1 may be disposed on the height unit HC. In some embodiments, multiple first active patterns ACT1 may be disposed. The first active patterns ACT1 may be spaced apart from each other in the first direction D1. In some embodiments, a pair of first active patterns ACT1 spaced apart from each other in the first direction D1 may be disposed on the first region P1. A pair of first active patterns ACT1 spaced apart from each other in the first direction D1 may be disposed on the second region P2.

[0037] A second active pattern ACT2 may be disposed on the first tap unit TC1. In some embodiments, multiple second active patterns ACT2 may be disposed. The second active patterns ACT2 may be spaced apart from each other in the first direction D1. In some embodiments, a pair of second active patterns ACT2 spaced apart from each other in the first direction D1 may be disposed on the first region P1. The pair of second active patterns ACT2 on the first region P1 may include an extension portion LR and a center portion CR between the extension portions LR. A pair of second active patterns ACT2 spaced apart from each other in the first direction D1 may be disposed on the second region P2.

[0038] A third active pattern ACT3 can be provided on the second tap unit TC2. In some embodiments, multiple third active patterns ACT3 can be provided. The third active patterns ACT3 can be spaced apart from each other in the first direction D1. In some embodiments, a pair of third active patterns ACT3 spaced apart from each other in the first direction D1 can be provided on the first region P1. A pair of third active patterns ACT3 spaced apart from each other in the first direction D1 can be provided on the second region P2. The pair of third active patterns ACT3 on the second region P2 may include an extension portion LR and a center portion CR between the extension portions LR.

[0039] The first active pattern ACT1 and the third active pattern ACT3 on the first region P1 may contain impurities of a different conductivity type than that of the first well region WE1 (e.g., p-type impurities). The second active pattern ACT2 on the first region P1 may contain impurities of the same conductivity type as that of the first well region WE1 (e.g., n-type impurities). The first active pattern ACT1 and the second active pattern ACT2 on the second region P2 may contain impurities of a different conductivity type than that of the second well region WE2 (e.g., n-type impurities). The third active pattern ACT3 on the second region P2 may contain impurities of the same conductivity type as that of the second well region WE2 (e.g., p-type impurities).

[0040] The first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3 can be spaced apart from each other in the second direction D2. The first active pattern ACT1 can be spaced apart from the second active pattern ACT2, with the separator pattern DB located between the first active pattern ACT1 and the second active pattern ACT2. The second active pattern ACT2 can be spaced apart from the third active pattern ACT3, with the separator pattern DB located between the second active pattern ACT2 and the third active pattern ACT3.

[0041] When measured in the first direction D1, the top surface of the second active pattern ACT2 on the first region P1 may have a first width W1. When measured in the first direction D1, the top surface of the first active pattern ACT1 on the first region P1 may have a second width W2. When measured in the first direction D1, the top surface of the third active pattern ACT3 on the second region P2 may have a third width W3. When measured in the first direction D1, the top surface of the first active pattern ACT1 on the second region P2 may have a fourth width W4.

[0042] The first width W1 can be greater than (i.e., longer than) the second width W2. The third width W3 can be greater than the fourth width W4. The second width W2 can be substantially equal to the fourth width W4. When measured in the first direction D1, the width of the third active pattern ACT3 on the first region P1 can be less than (i.e., shorter than) the first width W1 and can be substantially equal to the second width W2. When measured in the first direction D1, the width of the second active pattern ACT2 on the second region P2 can be less than the third width W3 and can be substantially equal to the fourth width W4.

[0043] In summary, the active pattern ACT2 on the first tap unit TC1 can have the largest width among the active patterns ACT1, ACT2, and ACT3 on the first region P1. The active pattern ACT3 on the second tap unit TC2 can have the largest width among the active patterns ACT1, ACT2, and ACT3 on the second region P2. The active patterns ACT2 on the first tap unit TC1 and ACT3 on the second tap unit TC2 can be adjacent to each other in the fourth direction D4. Here, the fourth direction D4 can be parallel to the top surface of the substrate 100 and can be tilted relative to each of the first direction D1 and the second direction D2. The angle between the first direction D1 and the fourth direction D4 can be smaller than the angle between the first direction D1 and the second direction D2. That is, the fourth direction D4 can be a direction defined between the first direction D1 and the second direction D2 or tilted towards the first direction D1 and the second direction D2.

[0044] The distance between the second active patterns ACT2 on the first region P1 can be less than the distance between the first active patterns ACT1 on the first region P1 and the distance between the third active patterns ACT3 on the first region P1. For example, the distance between adjacent second active patterns ACT2 in the first region P1 along the first direction D1 can be less than the distance between adjacent first active patterns ACT1 in the first region P1 along the first direction D1 and the distance between adjacent third active patterns ACT3 in the first region P1 along the first direction D1. The distance between the third active patterns ACT3 on the second region P2 can be less than the distance between the first active patterns ACT1 on the second region P2 and the distance between the second active patterns ACT2 on the second region P2. For example, the distance between adjacent third active patterns ACT3 in the third active pattern ACT3 in the second region P2 in the first direction D1 can be less than the distance between adjacent first active patterns ACT1 in the first active pattern ACT1 in the second region P2 in the first direction D1 and the distance between adjacent second active patterns ACT2 in the second active pattern ACT2 in the second region P2 in the first direction D1.

[0045] The first active pattern ACT1 may have a first side surface S1, the second active pattern ACT2 may have a second side surface S2, and the third active pattern ACT3 may have a third side surface S3. Each of the first to third side surfaces S1, S2, and S3 may face a first direction D1 and its opposite direction. In the first region P1, the second side surface S2 may protrude in the first direction D1 and its opposite direction compared to each of the first side surface S1 and the third side surface S3. In the second region P2, the third side surface S3 may protrude in the first direction D1 and its opposite direction compared to each of the first side surface S1 and the second side surface S2. For example, the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3 in the first region P1 may be adjacent to each other in the second direction D2. In the first region P1, the second side surface S2 may not be collinear with each of the first side surface S1 and the third side surface S3 along the second direction D2. As another example, the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3 on the second region P2 can be adjacent to each other in the second direction D2. On the second region P2, the third side surface S3 can be non-collinear with each of the first side surface S1 and the second side surface S2 along the second direction D2.

[0046] A first semiconductor pattern CH1 can be disposed on a first active pattern ACT1. A second semiconductor pattern CH2 can be disposed on a second active pattern ACT2. A third semiconductor pattern (not shown) can be disposed on a third active pattern ACT3. In some embodiments, a plurality of first semiconductor patterns CH1, a plurality of second semiconductor patterns CH2, and a plurality of third semiconductor patterns can be disposed. The first semiconductor patterns CH1 can be spaced apart from each other in the second direction D2, and the second semiconductor patterns CH2 and the third semiconductor patterns can be disposed to have the same characteristics. Each of the first semiconductor pattern CH1, the second semiconductor pattern CH2, and the third semiconductor pattern can include a plurality of semiconductor layers SP1, SP2, and SP3 stacked on the third direction D3. For example, the semiconductor layers SP1, SP2, and SP3 can be spaced apart from each other in the third direction D3. Figure 5D An example in which three semiconductor layers SP1, SP2, and SP3 are stacked is shown, but the inventive concept is not limited to this example; for example, in some embodiments, four or more semiconductor layers may be provided. Each of the semiconductor layers SP1, SP2, and SP3 may comprise crystalline silicon.

[0047] Due to the aforementioned widths of the active patterns ACT1, ACT2, and ACT3, when measured in the first direction D1, the width of the second semiconductor pattern CH2 on the first region P1 can be greater than the width of the first semiconductor pattern CH1 on the first region P1. Similarly, when measured in the first direction D1, the width of the third semiconductor pattern on the second region P2 can be greater than the width of the first semiconductor pattern CH1 on the second region P2.

[0048] A first groove RS1 may be defined between first semiconductor patterns CH1. A second groove RS2 may be defined between second semiconductor patterns CH2. A third groove RS3 may be defined between third semiconductor patterns.

[0049] A source / drain pattern SD can be formed on a first active pattern ACT1 to be located in a first recess RS1 (e.g., filling the first recess RS1). A first impurity pattern EP1 can be formed on a second active pattern ACT2 to be located in a second recess RS2 (e.g., filling the second recess RS2). A second impurity pattern EP2 can be formed on a third active pattern ACT3 to be located in a third recess RS3 (e.g., filling the third recess RS3). The source / drain pattern SD, the first impurity pattern EP1, and the second impurity pattern EP2 can be connected to semiconductor layers SP1, SP2, and SP3.

[0050] The source / drain pattern SD may include a first pattern T1 on a first region P1 and a second pattern T2 on a second region P2.

[0051] In some embodiments, the first pattern T1 and the second impurity pattern EP2 of the source / drain pattern SD may comprise a semiconductor material (e.g., SiGe) with a lattice constant greater than that of the semiconductor materials of semiconductor layers SP1, SP2, and SP3. The second pattern T2 and the first impurity pattern EP1 of the source / drain pattern SD may comprise the same semiconductor material (e.g., Si) as the semiconductor layers SP1, SP2, and SP3.

[0052] The second pattern T2 and the first impurity pattern EP1 of the source / drain pattern SD can contain impurities of the same conductivity type as the first well region WE1 (e.g., n-type impurities). The first pattern T1 and the second impurity pattern EP2 of the source / drain pattern SD can contain impurities of the same conductivity type as the second well region WE2 (e.g., p-type impurities).

[0053] Due to the aforementioned widths of the active patterns ACT1, ACT2, and ACT3, when measured in the first direction D1, the width of the first impurity pattern EP1 on the first region P1 can be greater than the width of the first pattern T1 of the source / drain pattern SD. For example, when measured in the first direction D1, the width of the first impurity pattern EP1 on the first region P1 can be greater than the width of the first impurity pattern EP1 on the second region P2. When measured in the first direction D1, the width of the second impurity pattern EP2 on the second region P2 can be greater than the width of the second pattern T2 of the source / drain pattern SD. For example, when measured in the first direction D1, the width of the second impurity pattern EP2 on the second region P2 can be greater than the width of the second impurity pattern EP2 on the first region P1.

[0054] The distance between the first impurity patterns EP1 on the first region P1 can be less than the distance between the first patterns T1 of the source / drain patterns SD. For example, the distance between adjacent first impurity patterns EP1 in the first region P1 in the first direction D1 can be less than the distance between adjacent first patterns T1 in the first direction D1 of the source / drain patterns SD. The distance between the second impurity patterns EP2 on the second region P2 can be less than the distance between the second patterns T2 of the source / drain patterns SD. For example, the distance between adjacent second impurity patterns EP2 in the second region P2 in the first direction D1 can be less than the distance between adjacent second patterns T2 in the first direction D1 of the source / drain patterns SD.

[0055] A gate electrode GE can be disposed on each of the first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern (e.g., CH1 and CH2) to intersect each semiconductor pattern. In some embodiments, multiple gate electrodes GE can be disposed. The gate electrodes GE can be spaced apart from each other in the first direction D1 and the second direction D2.

[0056] The gate electrode GE may include an inner portion PO1 and an outer portion PO2. The inner portion PO1 may be disposed below the uppermost semiconductor layer in semiconductor layers SP1, SP2, and SP3. The outer portion PO2 may be disposed on the uppermost semiconductor layer in semiconductor layers SP1, SP2, and SP3. In some embodiments, the inner portion PO1 may include three inner portions, but the inventive concept is not limited to this example. For example, the inner portion PO1 may include four or more inner portions.

[0057] The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. In some embodiments, the first metal pattern may be formed of or include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co) and a metal nitride material (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co). In some embodiments, the first metal pattern may further include carbon (C). The first metal pattern may be formed of or include at least one of a metallic material having a different work function.

[0058] In some embodiments, the second metal pattern may be formed of or include at least one of a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co) whose resistance is lower than that of the first metal pattern.

[0059] The inner portion PO1 may include a first metal pattern. The outer portion PO2 may include a first metal pattern and a second metal pattern.

[0060] The gate capping pattern GC can be disposed on the top surface of the gate electrode GE. In some embodiments, the gate capping pattern GC can be formed or include at least one of SiON, SiCN, SiOCN or SiN.

[0061] The outer gate spacer OGS may be disposed on the side surface of the outer portion PO2 of the gate electrode GE and may extend to the side surface of the gate cap pattern GC (e.g., covering and / or overlapping the side surface of the gate cap pattern GC). As used herein, “element A overlaps element B in direction X” (or similar language) means that there is at least one straight line extending in direction X and intersecting both elements A and B.

[0062] The inner gate spacer (not shown) may be located between the second pattern T2 of the source / drain pattern SD and the inner sub-pattern PO1 of the gate electrode GE, and between the first impurity pattern EP1 and the inner sub-pattern PO1 of the gate electrode GE. In some embodiments, each of the outer gate spacer OGS and the inner gate spacer may include an insulating material.

[0063] The gate insulating pattern GI may be located between the gate electrode GE and the semiconductor layers SP1, SP2, and SP3. The gate insulating pattern GI may be formed of at least one of silicon oxide (SiO2), silicon oxynitride (SiON), or a high-k dielectric material, or may include at least one of silicon oxide (SiO2), silicon oxynitride (SiON), or a high-k dielectric material. In this specification, a high-k dielectric material may be defined as a material with a dielectric constant higher than that of silicon oxide.

[0064] A cutting pattern CT can be formed between gate electrodes GE spaced apart from each other in the first direction D1. In some embodiments, the cutting pattern CT may include an insulating material.

[0065] A separator pattern DB may be disposed on the substrate 100. The separator pattern DB may include a first separator pattern DB1 between the height unit HC and the first tap unit TC1, a second separator pattern DB2 between the first tap unit TC1 and the second tap unit TC2, and a third separator pattern DB3 between the second tap unit TC2 and an adjacent logic unit. For example, the first separator pattern DB1 may be between a first active pattern ACT1 and a second active pattern ACT2 (e.g., in the second direction D2). The second separator pattern DB2 may be between the second active pattern ACT2 and the third active pattern ACT3 (e.g., in the second direction D2). In some embodiments, the separator pattern DB may include an insulating material.

[0066] A first interlayer insulating layer ILD1 may be disposed on the substrate 100. The first interlayer insulating layer ILD1 may be disposed on (e.g., may cover and / or overlap) the outer gate spacer OGS, the source / drain pattern SD, the first impurity pattern EP1 and the second impurity pattern EP2.

[0067] A second interlayer insulating layer ILD2 may be disposed on the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may be (e.g., may cover and / or overlap) the top surface of the gate cap pattern GC. In some embodiments, each of the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 may comprise silicon oxide (SiO2).

[0068] An active contact CA can be provided to penetrate the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 (i.e., extend into the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2). The lower part of the active contact CA can be inserted into the upper part of each of the source / drain pattern SD, the first impurity pattern EP1, and the second impurity pattern EP2. In some embodiments, the active contact CA can be formed or comprise at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co), a metal nitride material (e.g., a nitride material containing Ti, Mo, W, Cu, Al, Ta, Ru, Ir, or Co), or a metal silicide material (e.g., a silicide material containing Ti, Mo, W, Cu, Al, Ta, Ru, or Ir).

[0069] The voltage applied to the active contact CA on the first tap unit TC1 can be transmitted to the first well region WE1 through the first impurity pattern EP1 and the second active pattern ACT2. The voltage applied to the active contact CA on the second tap unit TC2 can be transmitted to the second well region WE2 through the second impurity pattern EP2 and the third active pattern ACT3.

[0070] Gate contacts (not shown) may be provided to penetrate the gate cap pattern GC. Each of the gate contacts may be inserted into the upper portion of the outer portion PO2 of the gate electrode GE. In some embodiments, the gate contacts may be formed of or include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co) or a metal nitride material (e.g., a nitride material comprising Ti, Mo, W, Cu, Al, Ta, Ru, Ir, or Co).

[0071] Although not shown, multiple interconnect layers may be further provided on the above structure, and each of the interconnect layers may include an interconnect pattern formed of or comprising a conductive material. The interconnect pattern may be connected to the active contact CA and the gate contact (not shown).

[0072] At least one interconnect pattern can be used to apply voltage to the first well region WE1 through the active contact CA, the first impurity pattern EP1, and the second active pattern ACT2 in the first tap unit TC1. At least one interconnect pattern can be used to apply voltage to the second well region WE2 through the active contact CA, the second impurity pattern EP2, and the third active pattern ACT3 in the second tap unit TC2.

[0073] According to some embodiments of the present invention, the width W1 of the top surface of the second active pattern ACT2 on the first well region WE1 containing n-type impurities can be greater than the width W2 of the top surface of the first active pattern ACT1 on the first well region WE1. Furthermore, the width W3 of the top surface of the third active pattern ACT3 on the second well region WE2 containing p-type impurities can be greater than the width W4 of the top surface of the first active pattern ACT1 on the second well region WE2. Therefore, the overlap region between the second active pattern ACT2 and the first well region WE1, and the overlap region between the third active pattern ACT3 and the second well region WE2, can be increased. As a result, when a voltage is applied to the well region WE through peripheral elements, the resistance between the second active pattern ACT2 and the first well region WE1, and the resistance between the third active pattern ACT3 and the second well region WE2, can be reduced. Accordingly, latch-up phenomena in the semiconductor device can be suppressed, thereby improving the electrical characteristics of the semiconductor device.

[0074] Furthermore, the second active pattern ACT2, including the extension LR in the first tap unit TC1, and the third active pattern ACT3, including the extension LR in the second tap unit TC2, can be adjacent to each other in the fourth direction D4. In other words, the second active pattern ACT2 and the third active pattern ACT3, which have a larger width, can be arranged diagonally. Therefore, the difficulty of placing and forming the active contacts CA and interconnect patterns connected to the second active pattern ACT2 and the third active pattern ACT3 can be reduced. This can increase the degree of freedom in designing semiconductor devices.

[0075] In the following text, reference will be made to Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 7A , Figure 7B and Figure 8 Methods for manufacturing semiconductor devices according to some embodiments of the present invention are described. In the following description, for the sake of brevity, previously described elements may be identified by the same reference numerals without repeating their redundant descriptions.

[0076] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 7A , Figure 7B and Figure 8 This is a diagram illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. More specifically, Figure 6A It is along Figure 3 A cross-sectional view taken from line A-A'. Figure 6B It is along Figure 3 The cross-sectional view taken by line B-B'. Figure 6C and Figure 7A It is along Figure 3 A cross-sectional view taken from line C-C'. Figure 6D , Figure 7B and Figure 8 It is along Figure 3 The cross-sectional view taken by line D-D'.

[0077] Reference Figure 3 and Figures 6A to 6D A substrate 100 can be configured to include a first well region WE1 and a second well region WE2.

[0078] A stacked pattern STP can be formed on the substrate 100. In some embodiments, forming the stacked pattern STP may include: alternately stacking a semiconductor layer SL and a sacrificial layer SAL on the substrate 100 to form a mask pattern (not shown) extending in a second direction D2, and performing a first patterning process using the mask pattern as an etch mask. When performing the first patterning process, a portion of the substrate 100 may be removed to form a trench TR.

[0079] In some embodiments, due to the first patterning process, the active patterns ACT1, ACT2 and ACT3 can be formed to have different widths from each other.

[0080] A second patterning process can be performed on the substrate 100 to form a separation trench STR. As a result of the first and second patterning processes, a first active pattern ACT1, a second active pattern ACT2, and a third active pattern ACT3 spaced apart from each other in a first direction D1 and a second direction D2 can be formed on the substrate 100.

[0081] The sacrificial layer SAL may comprise a material that is etch-selective relative to the semiconductor layer SL. Therefore, when the sacrificial layer SAL is removed in a subsequent step, the semiconductor layer SL may not be removed. The semiconductor layer SL and the sacrificial layer SAL may be formed of or comprise at least one of silicon (Si), germanium (Ge), or silicon-germanium (SiGe), but the material of the sacrificial layer SAL may differ from the material of the semiconductor layer SL.

[0082] Reference Figure 3 , Figure 7A and Figure 7BThe device isolation pattern ST can be formed in a trench TR (e.g., filling the trench TR). The preliminary separation pattern PDB can be formed in a separation trench STR (e.g., filling the separation trench STR). The preliminary separation pattern PDB may include: a first preliminary separation pattern PDB1 disposed between a first active pattern ACT1 and a second active pattern ACT2; and a second preliminary separation pattern PDB2 spaced apart from the first preliminary separation pattern PDB1, the second active pattern ACT2 being located between the second preliminary separation pattern PDB2 and the first preliminary separation pattern PDB1.

[0083] A sacrificial pattern PP may be formed on substrate 100 to extend in a first direction D1. The sacrificial pattern PP may be formed on (e.g., covering and / or overlapping) the top surface of a device isolation pattern ST and the side and top surfaces of a stacked pattern STP. In some embodiments, forming the sacrificial pattern PP may include: forming a sacrificial layer (not shown) on substrate 100, forming a hard mask pattern MP on the sacrificial layer, and forming the sacrificial pattern PP by removing a portion of the sacrificial layer using the hard mask pattern MP as an etch mask. In some embodiments, the sacrificial pattern PP may comprise polysilicon. Subsequently, an external gate spacer OGS may be formed on the side surface of the sacrificial pattern PP.

[0084] The first groove RS1 can be formed in the stacked pattern STP on the first active pattern ACT1. The second groove RS2 can be formed in the stacked pattern STP on the second active pattern ACT2. Figure 5B The third groove RS3 can be formed in Figure 6B In the third active pattern ACT3, the stacked pattern STP is formed. In some embodiments, the first to third grooves RS1, RS2 and RS3 can be formed by partially removing the stacked pattern STP using a hard mask pattern MP as an etch mask.

[0085] The first groove RS1 can divide the semiconductor layer SL on the first active pattern ACT1 into first semiconductor patterns CH1 spaced apart from each other in the second direction D2. The second groove RS2 can divide the semiconductor layer SL on the second active pattern ACT2 into second semiconductor patterns CH2 spaced apart from each other in the second direction D2. Figure 5B The third groove RS3 can Figure 6B The semiconductor layer SL on the third active pattern ACT3 is divided into third semiconductor patterns spaced apart from each other in the second direction D2.

[0086] A source / drain pattern SD can be formed in the first groove RS1. A first impurity pattern EP1 can be formed in the second groove RS2. Figure 5B The second impurity pattern EP2 can be formed in Figure 5BIn the third groove RS3.

[0087] In some embodiments, when the first pattern T1 of the source / drain pattern SD is formed and Figure 5B When forming the second impurity pattern EP2, p-type impurities (e.g., boron, gallium, or indium) can be doped into them using in-situ doping. In some other embodiments, after forming the first pattern T1 and the second impurity pattern EP2, impurities can be implanted into the first pattern T1 and the second impurity pattern EP2 (e.g., through an implantation process).

[0088] In some embodiments, when forming the second pattern T2 and the first impurity pattern EP1 of the source / drain pattern SD, they can be doped with n-type impurities (e.g., phosphorus, arsenic, or antimony) in situ. In some other embodiments, after forming the second pattern T2 and the first impurity pattern EP1, the impurities can be implanted into the second pattern T2 and the first impurity pattern EP1 (e.g., by an implantation process).

[0089] Reference Figure 3 and Figure 8 The first interlayer insulating layer ILD1 can be formed in (e.g., covering and / or overlapping) the source / drain pattern SD, the first impurity pattern EP1, Figure 5B The second impurity pattern EP2, the hard mask pattern MP (see...) Figure 7B On the outer gate spacer OGS and the sacrificial pattern PP (see...). Figure 7B The first interlayer insulating layer ILD1 is removed from the top surface of the mask. In some embodiments, a removal process may be performed to remove the hard mask pattern MP, thereby exposing the sacrificial pattern PP. A portion of the initial separator pattern PDB and the first interlayer insulating layer ILD1 may form the separator pattern DB.

[0090] Subsequently, the exposed sacrificial pattern PP can be removed to form an empty space, which will be referred to as the outer region ORG. The first semiconductor pattern CH1, the second semiconductor pattern CH2, the third semiconductor pattern, and the sacrificial layer SAL can be exposed to the outside through the outer region ORG.

[0091] Next, the exposed sacrificial layer SAL can be selectively removed. Here, due to the high etch selectivity of the sacrificial layer SAL, the first to third semiconductor layers SP1, SP2 and SP3 may not be removed.

[0092] The inner region IRG can be an empty space, formed by removing the sacrificial layer SAL. More specifically, the inner region IRG can be formed between the first semiconductor layer and the third semiconductor layers SP1, SP2, and SP3.

[0093] According to some embodiments of the present invention, the second active patterns ACT2 on the first region P1 can be spaced apart from each other, and the third active patterns ACT3 on the second region P2 can be spaced apart from each other. Therefore, the space between the sacrificial layers SAL on the second active patterns ACT2 and the space between the sacrificial layers SAL on the third active patterns ACT3 can be ensured. Therefore, the sacrificial layers SAL on the second active patterns ACT2 and the third active patterns ACT3 can be easily removed during the removal of the sacrificial layers SAL. For example, no sacrificial layers SAL can be left in subsequent processes, which can reduce the failure rate in the semiconductor manufacturing process and thus improve the productivity of the semiconductor manufacturing process.

[0094] Return to reference Figure 3 and Figures 5A to 5D The gate insulating pattern GI can be formed in Figure 8 In each of the inner region IRG and the outer region ORG. The gate insulating pattern GI can be formed around each of the first to third semiconductor layers SP1, SP2 and SP3.

[0095] The gate electrode GE can be formed on the gate insulating pattern GI. The gate capping pattern GC can be formed on the outer portion PO2 of the gate electrode GE. The second interlayer insulating layer ILD2 can be formed on the first interlayer insulating layer ILD1 and the gate capping pattern GC.

[0096] The active contact CA can be formed to penetrate the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2. The active contact CA can be formed to connect to the source / drain pattern SD, the first impurity pattern EP1, and the second impurity pattern EP2.

[0097] The gate contact (not shown) can be formed to penetrate the second interlayer insulating layer ILD2 and the gate cap pattern GC, and can be connected to the gate electrode GE.

[0098] Although not shown, additional interconnect patterns formed of or including conductive materials may be formed on the second interlayer insulating layer ILD2.

[0099] According to an exemplary embodiment of the present invention, the width of the top surface of the active pattern on the tap unit can be greater than its width on the height unit. Therefore, the overlap between the active pattern on the tap unit and the well region containing n-type or p-type impurities can be increased. In this case, the resistance between the active pattern on the tap unit and the well region can be reduced when a voltage is applied to the well region. Therefore, latch-up can be suppressed and the electrical characteristics of the semiconductor device can be improved.

[0100] According to an exemplary embodiment of the invention, a pair of active patterns spaced apart from each other can be formed on a tap unit. Therefore, the space between sacrificial layers on the active patterns can be ensured. As a result, the sacrificial layers can be easily removed. For example, no sacrificial layers can be left in subsequent processes, which can reduce the failure rate in the semiconductor manufacturing process and improve the productivity of the semiconductor manufacturing process.

[0101] As used herein, the terms “comprising,” “including,” “containing,” “comprising,” “having,” “containing,” and any other variations thereof specify the presence of the stated features, steps, operations, elements, components, and / or groups, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. Furthermore, it will be understood that while various elements may be described herein using terms such as “first,” “second,” “third,” etc., these elements should not be limited by these terms. Rather, these terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element without departing from the scope of this disclosure, and similarly, a second element may be referred to as a first element. Additionally, as used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0102] While exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made therein without departing from the scope of the appended claims.

Claims

1. A semiconductor device comprising: a substrate including a first well region, the first well region including impurities of a first conductivity type; first active patterns on the first well region and spaced apart from each other in a first direction parallel to a top surface of the substrate; second active patterns on the first well region and spaced apart from each other in the first direction; source / drain patterns on the first active patterns, the source / drain patterns including impurities of a second conductivity type; and a first impurity pattern on the second active patterns, the first impurity pattern including impurities of the first conductivity type, wherein a width of a top surface of each of the second active patterns in the first direction is greater than a width of a top surface of each of the first active patterns in the first direction. the impurities of the first conductivity type are n-type impurities, and 2. The semiconductor device of claim 1, wherein, wherein the impurities of the second conductivity type are p-type impurities. a distance between adjacent ones of the second active patterns is less than a distance between adjacent ones of the first active patterns.

3. The semiconductor device of claim 1, wherein, a distance between adjacent ones of the first impurity patterns is less than a distance between adjacent ones of the source / drain patterns.

4. The semiconductor device of claim 1, wherein, a first one of the second active patterns is adjacent to a first one of the first active patterns in a second direction parallel to the top surface of the substrate and perpendicular to the first direction, and 5. The semiconductor device of claim 1, wherein, wherein a side surface of the first one of the second active patterns protrudes beyond a side surface of the first one of the first active patterns in the first direction. the substrate further includes a second well region adjacent to the first well region in the first direction and including impurities of the second conductivity type, 6. The semiconductor device of claim 1, wherein, wherein the semiconductor device further comprises: third active patterns on the second well region and spaced apart from the first active patterns in the first direction; and fourth active patterns on the second well region and spaced apart from the third active patterns in a second direction parallel to the top surface of the substrate and perpendicular to the first direction, and wherein a width of a top surface of the fourth active patterns in the first direction is greater than a width of a top surface of the third active patterns in the first direction. the source / drain patterns are first source / drain patterns, and 7. The semiconductor device of claim 6, wherein, wherein the semiconductor device further comprises: second source / drain patterns on the third active patterns, the second source / drain patterns including impurities of the first conductivity type; and a second impurity pattern on the fourth active patterns, the second impurity pattern including impurities of the second conductivity type. the substrate further includes a second well region adjacent to the first well region in the first direction and including impurities of the second conductivity type, 8. The semiconductor device of claim 1, wherein, wherein the semiconductor device further comprises: third active patterns on the second well region and spaced apart from the second active patterns in the first direction; and fourth active patterns on the second well region and spaced apart from the third active patterns in a second direction parallel to the top surface of the substrate and perpendicular to the first direction, and wherein a width of a top surface of the fourth active patterns in the first direction is greater than a width of a top surface of the third active patterns in the first direction. a fourth active pattern on the second well region and spaced apart from the third active pattern in a second direction parallel to the top surface of the substrate and perpendicular to the first direction, and wherein a width of a top surface of the fourth active pattern in the first direction is greater than a width of a top surface of the third active pattern in the first direction.

9. The semiconductor device of claim 8, further comprising: a second impurity pattern on the fourth active pattern, the second impurity pattern including impurities of the second conductivity type; and a third impurity pattern on the third active pattern, the third impurity pattern including impurities of the first conductivity type.

10. The semiconductor device of claim 9, wherein, each of the first impurity patterns has a width in the first direction that is greater than a width of the third impurity pattern in the first direction.

11. The semiconductor device of claim 1, wherein, each of the first impurity patterns has a width in the first direction that is greater than a width of each of the source / drain patterns in the first direction.

12. The semiconductor device of claim 1, wherein, each of the first active patterns includes impurities of the second conductivity type, and wherein each of the second active patterns includes impurities of the first conductivity type.

13. A semiconductor device, comprising: a substrate including a first well region, the first well region including impurities of a first conductivity type; first and second active patterns on the first well region; source / drain patterns on the first active patterns, the source / drain patterns including impurities of a second conductivity type; and first impurity patterns on the second active patterns, the first impurity patterns including impurities of the first conductivity type, wherein a first side surface of the second active pattern protrudes beyond a first side surface of the first active pattern in a first direction parallel to a top surface of the substrate.

14. The semiconductor device of claim 13, wherein, a second side surface of the second active pattern opposite the first side surface of the second active pattern protrudes beyond a second side surface of the first active pattern opposite the first side surface of the first active pattern.

15. The semiconductor device of claim 13, wherein, a width of a top surface of the second active pattern in the first direction is greater than a width of a top surface of the first active pattern in the first direction.

16. The semiconductor device of claim 13, wherein, the first active patterns include a plurality of first active patterns on the first well region and spaced apart from each other in the first direction, wherein the second active patterns include a plurality of second active patterns on the first well region and spaced apart from each other in the first direction, and wherein a distance between adjacent ones of the second active patterns is less than a distance between adjacent ones of the first active patterns.

17. The semiconductor device of claim 16, wherein, the first active patterns are spaced apart from the second active patterns in a second direction parallel to the top surface of the substrate and perpendicular to the first direction, wherein each of the first active patterns includes impurities of the second conductivity type, and wherein each of the second active patterns includes impurities of the first conductivity type.

18. The semiconductor device of claim 13, wherein, The substrate further includes a second well region adjacent to the first well region in the first direction and including impurities of the second conductivity type, wherein the semiconductor device further includes: a third active pattern on the second well region and spaced apart from the first active pattern in the first direction; and a fourth active pattern on the second well region and spaced apart from the third active pattern in a second direction parallel to the top surface of the substrate and perpendicular to the first direction, and wherein a width of a top surface of the fourth active pattern in the first direction is greater than a width of a top surface of the third active pattern in the first direction.

19. The semiconductor device of claim 18, wherein, The second active pattern and the fourth active pattern are spaced apart from each other in a third direction parallel to the top surface of the substrate and oblique to each of the first direction and the second direction.

20. A semiconductor device, comprising: a substrate including a first well region including impurities of a first conductivity type; first active patterns on the first well region and spaced apart from each other in a first direction parallel to a top surface of the substrate; second active patterns on the first well region and spaced apart from each other in the first direction; a separation pattern between the first active patterns and the second active patterns; source / drain patterns on the first active patterns, the source / drain patterns including impurities of a second conductivity type; a first impurity pattern on the second active patterns, the first impurity pattern including impurities of the first conductivity type; first semiconductor patterns on the first active patterns; second semiconductor patterns on the second active patterns; a gate electrode crossing at least one of the first semiconductor patterns; and an active contact on the source / drain patterns and the first impurity pattern, wherein a width of a top surface of each of the second active patterns in the first direction is greater than a width of a top surface of each of the first active patterns in the first direction. ​

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