Semiconductor device
By setting spaced gate lines and a peripherally disconnected gate connection layer in the semiconductor device, the problem of insufficient ability to increase the cutoff frequency and maximum oscillation frequency in the prior art is solved, and performance improvement is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-20
- Publication Date
- 2026-03-10
AI Technical Summary
Existing semiconductor devices are inadequate in improving cutoff frequency and maximum oscillation frequency, which affects device performance.
In a semiconductor device, multiple gate lines are spaced apart from each other and not connected, and a gate connection layer is disposed above the substrate. The gate connection layer is located outside the active region and is disconnected to reduce parasitic capacitance.
It effectively improves the cutoff frequency and maximum oscillation frequency of semiconductor devices, reduces noise, and enhances device performance.
Smart Images
Figure CN121645992A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device. BACKGROUND
[0002] In the application process of integrated circuits, the performance of various devices will be affected by the structure of each layer, especially the widespread use of wireless communication technology, which tends to be low cost, higher level of integration, lower power consumption and higher millimeter wave frequency.
[0003] In current semiconductor devices, in order to improve the performance of semiconductor devices, especially low noise amplifiers, optimization is usually performed from the aspects of device selection and optimization, and circuit topology design. However, after the optimization of device selection and circuit topology, it is difficult to further improve the cutoff frequency and maximum oscillation frequency of the semiconductor device from these two aspects, thereby affecting the performance of the semiconductor device. SUMMARY
[0004] The technical problem solved by the present application is to provide a semiconductor device that can effectively improve the cutoff frequency and maximum oscillation frequency of the semiconductor device, thereby improving the performance of the semiconductor device.
[0005] To solve the above technical problems, one technical solution adopted by the present application is to provide a semiconductor device, comprising: a substrate, the substrate comprising an active region, a plurality of gate lines being spaced apart and not connected on the substrate; a gate connection layer is arranged on the substrate, the gate connection layer is located above the periphery of the active region, and is arranged to be disconnected.
[0006] In an embodiment of the present application, the gate connection layer comprises a first side gate connection line, the first side gate connection line is located on a first side of the active region; each of the gate lines extends along a second direction, the first side gate connection line extends along a first direction, the first direction intersects the second direction, and the first side gate connection line is configured to connect a first end of the plurality of gate lines.
[0007] In an embodiment of the present application, the gate connection layer further comprises a second side gate connection line, the first side gate connection line is parallel to the second side gate connection line, the second side gate connection line is located on a second side of the active region, and the first side and the second side are opposite to each other; the second side gate connection line is configured to connect a second end of the plurality of gate lines, and the second end is away from the first end.
[0008] In one embodiment of this application, the gate connection layer further includes a gate connection portion disposed between the first-side gate connection line and the second-side gate connection line to connect the first-side gate connection line and the second-side gate connection line; the gate connection portion is located on the third side of the active region.
[0009] In one embodiment of this application, a plurality of gate connection regions are respectively provided on the first-side gate connection line and / or the second-side gate connection line, and the first-side gate connection line and / or the second-side gate connection line are respectively connected to the first end and / or the second end of the plurality of gate lines through the gate connection regions; or the gate connection layer further includes a plurality of connection branches extending from the first-side gate connection line and / or the second-side gate connection line, the connection branches extending along the second direction, and the first-side gate connection line and / or the second-side gate connection line are respectively connected to the first end and / or the second end of the plurality of gate lines through the connection branches.
[0010] In one embodiment of this application, it further includes a first metal pattern layer disposed on the substrate; a second metal pattern layer disposed on the first metal pattern layer; wherein, one of the first metal pattern layer and the second metal pattern layer includes the gate connection layer; the gate line is located on a different layer from the first metal pattern layer and the second metal pattern layer, and the gate connection layer is connected to the gate line through a gate contact connection post, or through a gate contact connection post, the first metal pattern layer and a gate via connection post.
[0011] In one embodiment of this application, the other of the first metal pattern layer and the second metal pattern layer includes a source connection layer and a drain connection layer, wherein the source connection layer connects a plurality of source regions and the drain connection layer connects a plurality of drain regions.
[0012] In one embodiment of this application, the source connection layer includes a plurality of source lead-out branches and source lead-out lines, wherein each source lead-out branch extends along the second direction to the source region, and each source lead-out branch is connected to a corresponding source region; the source lead-out lines extend along the first direction to connect the plurality of source lead-out branches; the drain connection layer includes a plurality of drain lead-out branches and drain lead-out lines, wherein each drain lead-out branch extends along the second direction to the drain region, and each drain lead-out branch is connected to a corresponding drain region; the drain lead-out lines extend along the first direction to connect the plurality of drain lead-out branches.
[0013] In one embodiment of this application, the gate connection layer is connected to one end of a corresponding gate line through a first gate contact connection post; or the gate connection layer is connected to one end of a corresponding gate line through a plurality of second gate contact connection posts; wherein the cross-sectional area of each first gate contact connection post is greater than the cross-sectional area of the second gate contact connection post.
[0014] In one embodiment of this application, the width of the first end and / or the second end of the gate line in a first direction is greater than the width at the middle of the gate line.
[0015] In one embodiment of this application, the substrate is an SOI substrate.
[0016] Unlike existing technologies, the semiconductor device provided in this application includes: a substrate, the substrate including an active region, and a plurality of spaced-apart and unconnected gate lines disposed on the substrate; and a gate connection layer disposed on the substrate, the gate connection layer being connected to the plurality of gate lines, wherein the gate connection layer is located above the periphery of the active region and is disconnected. That is, in this application, the plurality of gate lines are spaced-apart and unconnected, the gate connection layer is located above the periphery of the active region, and the gate connection layer is disconnected, thereby reducing the parasitic capacitance generated by the wiring in the gate lines and the gate connection layer, thereby increasing the cutoff frequency and the maximum oscillation frequency, thus reducing noise and improving the performance of the semiconductor device. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a schematic diagram of the structure of the first embodiment of the semiconductor device in this application; Figure 2 This is a schematic diagram of the structure of the second embodiment of the semiconductor device in this application; Figure 3 This is a schematic diagram of the structure of the third embodiment of the semiconductor device in this application; Figure 4 This is a schematic diagram of the structure of the fourth embodiment of the semiconductor device in this application.
[0018] In the attached figures, there is a substrate 100, a gate line 110, a gate connection layer 200, a gate connection region 201, a connection branch 202, a first-side gate connection line 210, a second-side gate connection line 220, a gate connection portion 230, a source connection layer 300, a drain connection layer 400, an active region A, a first metal pattern layer M1, a second metal pattern layer M2, a contact connection pillar CT, a gate contact connection pillar CT1, a via connection pillar V, a gate via connection pillar V1, a first direction X, a second direction Y, a source region S, and a drain region D. Detailed Implementation
[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0020] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.
[0021] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0022] The present application will now be described in detail with reference to the accompanying drawings and embodiments.
[0023] This application provides a semiconductor device that reduces the parasitic capacitance generated by wiring in the gate line and gate interconnect layer, thereby increasing the cutoff frequency and maximum oscillation frequency, reducing noise, and thus improving the performance of the semiconductor device.
[0024] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the semiconductor device in this application.
[0025] like Figure 1 As shown, the semiconductor device in this application includes a substrate 100 and a gate interconnect layer 200. The substrate 100 includes an active region A, and a plurality of gate lines 110 are disposed on the substrate 100 and are spaced apart from each other, i.e., the plurality of gate lines 110 are disconnected from each other. The gate interconnect layer 200 is disposed on the substrate 100 and is connected to the plurality of gate lines 110. The gate interconnect layer 200 is located above the periphery of the active region A and is disconnected.
[0026] The gate connection layer 200 being located above the periphery of the active region A means that the gate connection layer 200 is not located above the active region A, that is, the projection of the gate connection layer 200 on the substrate is outside the active region; the gate connection layer 200 being disconnected means that the gate connection layer 200 is not ring-shaped, that is, the projection of the gate connection layer 200 on the substrate does not surround the active region A.
[0027] In this context, substrate 100 refers to any suitable material known in the art; for example, substrate 100 can be a silicon substrate, a germanium substrate, or an SOI (Silicon-On-Insulator) substrate, etc. Gate connection layer 200 refers to the connection layer of gate lines on substrate 100, such as a metal connection layer, and is connected to multiple gate lines 110. Active area A refers to the physical region in substrate 100 that implements the core functions of the device. Each gate line 110 refers to the gate of a transistor. Specifically, substrate 100 is divided into active area A, and multiple gate lines 110 are disposed on substrate 100, wherein the multiple gate lines 110 are spaced apart in a first direction X, and each gate line 110 serves as the gate of a transistor; the first direction X and the second direction Y are both parallel to the substrate and intersect in a horizontal plane, for example, perpendicular to each other in a horizontal plane. The gate connection layer 200 is disposed on the plurality of gate lines 110 and is connected to the plurality of gate lines 110 via contact connection pillars CT (Contact), or contact connection pillars and via connection pillars V (Via). Drain regions D and source regions S are formed in the substrate on both sides of each gate line, the plurality of source regions S are spaced apart in the first direction X, and the plurality of drain regions D are spaced apart in the first direction X.
[0028] It is understandable that when the gate connection layer 200 is located on the M1 layer, that is, the first connection layer above the substrate, the gate connection layer 200 is connected to the gate line 110 through the contact connection post (Contact, CT); when the gate connection layer 200 is located above the M1 layer, such as the M2 layer, the M1 layer is connected to the gate line 110 through the contact connection post, and then the M1 layer is connected to the gate connection layer 200 through the via connection post (Via, V).
[0029] In the direction perpendicular to the substrate 100, the gate connection layer 200 is located above the periphery of the active region A and is disconnected. That is, the gate connection layer 200 is located above at least one side of the active region A, but does not surround the active region A. For example, the gate connection layer 200 is only above one side of the active region A, or the gate connection layer 200 is above two sides of the active region A, or the gate connection layer 200 is above three sides of the active region A.
[0030] Semiconductor devices often incorporate multiple transistors based on their design requirements. The interconnected gate lines of these transistors generate parasitic capacitance, which can be quite large and consequently affect the performance of the semiconductor device.
[0031] In this embodiment, a plurality of gate lines are provided on the substrate, spaced apart from each other and not connected. The gate connection layer is connected to the plurality of gate lines and is located above the periphery of the active region A and is disconnected, so that the parasitic capacitance is effectively reduced and the performance of the semiconductor device can be effectively improved. For example, when the semiconductor device is a low noise amplifier, the cutoff frequency and maximum oscillation frequency of the low noise amplifier can be effectively improved, thereby effectively improving the power frequency of the low noise amplifier and improving the performance of the low noise amplifier.
[0032] The following describes the specific structure in conjunction with specific embodiments.
[0033] Please see Figures 1-4 , Figure 2 This is a schematic diagram of the structure of the second embodiment of the semiconductor device in this application; Figure 3 This is a schematic diagram of the structure of the third embodiment of the semiconductor device in this application; Figure 4 This is a schematic diagram of the structure of the fourth embodiment of the semiconductor device in this application.
[0034] Understandable, Figure 1 , Figure 2 , Figure 3 The first metal pattern layer M1 includes a gate interconnect layer 200, and the second metal pattern layer M2 includes a source interconnect layer 300 and a drain interconnect layer 400. Figure 4 The first metal pattern layer M1 includes a source interconnect layer 300 and a drain interconnect layer 400, and the second metal pattern layer M2 includes a gate interconnect layer 200. Additionally, Figure 1, Figure 2 Each connection branch 202 is connected to the gate line 110 via a gate contact connection post CT1. Figure 3 Each connection branch 202 is connected to the gate line 110 via multiple gate contact connection posts CT1. Figure 4 Each gate connection region 201 is connected to the gate line 110 via a via connection post V1, a first metal pattern layer M1, and a gate contact connection post CT1. Additionally, each gate connection region 201 or connection branch 202 can also be connected to the gate line 110 via multiple gate contact connection posts CT1.
[0035] In some embodiments, the gate interconnect layer 200 includes a first-side gate interconnect line 210, the projection of which onto the substrate 100 is located on a first side of the active region A. (See also...) Figure 1 .
[0036] Each gate line 110 extends along the second direction Y, and the first side gate connection line 210 extends along the first direction X; the first side gate connection line 210 is configured to connect the first ends of the plurality of gate lines 110.
[0037] The first-side gate connection line 210 is used to connect to a plurality of gate lines 110 on the substrate 100. The first side of the active region A refers to one of the sides of the active region A, which can be the upper side or the lower side of the active region A. The first end of the gate line 110 refers to one end of the gate line 110 located on the first side of the active region A.
[0038] Specifically, each gate line 110 extends along the second direction Y and is spaced apart in the first direction X. The first side gate connection line 210 extends along the first direction X and is located on the first side of the active region A. The first end of the gate line 110 is also located on the first side of the active region A, so that the first side gate connection line 210 can be connected to the first end of the plurality of gate lines 110.
[0039] It is understood that the first-side gate connection line 210 can be connected to the same gate line 110 through one or more gate contact connection posts CT1.
[0040] In some embodiments, the gate interconnect layer 200 further includes a second-side gate interconnect line 220, that is, the gate interconnect layer 200 includes a first-side gate interconnect line 210 and a second-side gate interconnect line 220. (See also...) Figure 2 .
[0041] The first-side gate connection line 210 and the second-side gate connection line 220 are arranged in parallel. The first-side gate connection line 210 is located on the first side of the active region A, and the second-side gate connection line 210 is located on the second side of the active region A. The first side and the second side are opposite to each other. The second-side gate connection line 220 is configured to connect the second ends of a plurality of gate lines 110, and the second ends are far away from the first ends.
[0042] In this context, the second side and the first side of the active region A are opposite to each other, referring to the two sides of the active region A, such as the upper side and the lower side. The second end and the first end of the gate line 110 are far apart from each other, meaning they are far apart from each other in the same direction.
[0043] Specifically, the first side gate connection line 210 and the second side gate connection line 220 are arranged in parallel. For example, the first side gate connection line 210 is located on the upper side of the active region A and is configured to connect the first end of the plurality of gate lines 110; while the second side gate connection line 220 is located on the lower side of the active region A and is configured to connect the second end of the plurality of gate lines 110.
[0044] In some embodiments, the gate interconnect layer 200 further includes a gate interconnect portion 230, that is, the gate interconnect layer 200 includes a first-side gate interconnect line 210, a second-side gate interconnect line 220, and a gate interconnect portion 230. (See also...) Figure 3 .
[0045] The first gate connection line 210 and the second gate connection line 220 are arranged in parallel. A gate connection portion 230 is disposed between the first gate connection line 210 and the second gate connection line 220 to connect them. Furthermore, the gate connection portion 230 is located on the third side of the active region A, and the third side of the active region A connects to the first and second sides of the active region A.
[0046] In some embodiments, a plurality of gate connection regions 201 are provided on the first-side gate connection line 210 and / or the second-side gate connection line 220, and the first-side gate connection line 210 and / or the second-side gate connection line 220 are respectively connected to the first end and / or the second end of the plurality of gate lines 110 through the gate connection regions 201. Please refer to Figure 4 .
[0047] For example, a plurality of gate connection regions 201 are provided on the first-side gate connection line 210. The first-side gate connection line 210 is connected to the first end of a plurality of gate lines 110 through the corresponding gate connection regions 201. That is, each gate connection region 201 on the first-side gate connection line 210 is connected to the first end of a corresponding gate line 110. A plurality of gate connection regions 201 are also provided on the second-side gate connection line 220. The second-side gate connection line 220 is connected to the second end of a plurality of gate lines 110 through the corresponding gate connection regions 201. That is, each gate connection region 201 on the second-side gate connection line 220 is connected to the second end of a corresponding gate line 110.
[0048] In other embodiments, the gate interconnect layer further includes a plurality of interconnect branches 202 extending from the first-side gate interconnect 210 and / or the second-side gate interconnect 220. (See also...) Figure 1 , Figure 2 and Figure 3 .
[0049] The connecting branches 202 extend along the second direction respectively; the first side gate connection line 210 and / or the second side gate connection line 220 are respectively connected to the first end and / or the second end of the plurality of gate lines 110 through the connecting branches 202.
[0050] In some embodiments, the system further includes a first metal pattern layer M1 and a second metal pattern layer M2. The first metal pattern layer M1 is disposed on the substrate 100, and the second metal pattern layer M2 is disposed on the first metal pattern layer M1. One of the first metal pattern layer M1 and the second metal pattern layer M2 includes a gate interconnect layer 200, and the other of the first metal pattern layer M1 and the second metal pattern layer M2 includes a source interconnect layer 300 and a drain interconnect layer 400. That is, the gate interconnect layer 200 and the source interconnect layer 300 and drain interconnect layer 400 are located in different metal pattern layers.
[0051] The gate line 110 is located on a different layer from the first metal pattern layer M1 and the second metal pattern layer M2. For example, the first metal pattern layer M1 includes a gate interconnect layer 200; the second metal pattern layer M2 includes a source interconnect layer 300 and a drain interconnect layer 400. Please refer to [link to relevant documentation]. Figure 1 , Figure 2 , Figure 3 Alternatively, the first metal pattern layer M1 may include a source interconnect layer 300 and a drain interconnect layer 400, and the second metal pattern layer M2 may include a gate interconnect layer 200. Please refer to [link to relevant documentation]. Figure 4 .
[0052] It is worth noting that, in Figure 1 , Figure 2 , Figure 3Alternatively, the gate interconnect layer 200 can be disposed in the second metal pattern layer, and the source interconnect layer 300 and the drain interconnect layer 400 can be disposed in the first metal pattern layer. Figure 4 Alternatively, the gate interconnect layer 200 can be disposed in the first metal pattern layer, and the source interconnect layer 300 and the drain interconnect layer 400 can be disposed in the second metal pattern layer.
[0053] Then, when the first metal pattern layer M1 includes a gate connection layer 200 and the second metal pattern layer M2 includes a source connection layer 300 and a drain connection layer 400, the gate connection layer 200 is connected to the gate line 110 through a gate contact connection post CT1, the source connection layer 300 is connected to multiple source regions S through a source via connection post, the first metal pattern layer and the source contact connection post, and the drain connection layer 400 is connected to multiple drain regions D through a drain via connection post, the first metal pattern layer and the drain contact connection post.
[0054] If the first metal pattern layer M1 includes a source interconnect layer 300 and a drain interconnect layer 400, and the second metal pattern layer M2 includes a gate interconnect layer 200, then... Figure 4 As shown, the active connection layer 300 and the source region S are connected through a source contact connection post, the drain connection layer 400 and the drain region D are connected through a drain contact connection post, and the gate connection layer 200 and the gate line 110 are connected through a gate via connection post V1, the first metal pattern layer M1 and a gate contact connection post (not marked in the figure).
[0055] It is understood that the first metal pattern layer M1 is connected to the gate line, source region, and drain region respectively through contact pillars, and the second metal pattern layer M2 is connected to the first metal pattern layer M1 through vias. It is also understood that the contact pillars CT connect the substrate 100 and the first metal pattern layer M1, and the via pillars V connect the first metal pattern layer M1 and the second metal pattern layer M2. Furthermore, the gate contact pillar CT1, source contact pillar, and drain contact pillar are all contact pillars CT, and the gate via pillar V1, source via pillar, and drain via pillar are all via pillars V.
[0056] In some embodiments, when the first metal pattern layer M1 includes a gate connection layer 200, the first side gate connection line 210 and / or the second side gate connection line 220 in the gate connection layer 200 are connected to a plurality of gate lines 110 through the gate connection region 201 or the connection branch line 202 using the gate contact connection post CT1.
[0057] For example, the first-side gate connection line 210 in the gate connection layer 200 is connected to the corresponding gate lines 110 via multiple connection branches 202 using gate contact connection pillars CT1, such as Figure 1As shown; or the first-side gate connection line 210 and the second-side gate connection line 220 in the gate connection layer 200 are connected to the corresponding multiple gate lines 110 through multiple connection branches 202 using gate contact connection pillars CT1, such as Figure 2 and Figure 3 As shown.
[0058] Furthermore, the second metal pattern layer M2 includes a source connection layer 300 and a drain connection layer 400.
[0059] The source connection layer 300 is connected to the source region S through source contact connection posts. There can be one source contact connection post connected to one source region S, or multiple source contact connection posts connected to one source region S. The drain connection layer 400 is connected to the drain region D through drain contact connection posts. There can be one drain contact connection post connected to one drain region D, or multiple drain contact connection posts connected to one drain region D.
[0060] Furthermore, the first metal pattern layer M1 includes a source interconnect layer 300 and a drain interconnect layer 400. (See attached diagram) Figure 4 .
[0061] The source connection layer 300 is connected to multiple source regions S spaced apart in the first direction X. This can be achieved by one contact connection post CT (source contact connection post) corresponding to one source region S, or by multiple contact connection posts CT (source contact connection posts) corresponding to one source region S.
[0062] In some embodiments, the source connection layer 300 includes a plurality of source lead-out branches and source lead-out lines, wherein each source lead-out branch extends along a second direction Y, and at least a portion of each source lead-out branch is located above a corresponding source region S, and each source lead-out branch is connected to a corresponding source region S; the source lead-out lines extend along a first direction X to connect the plurality of source lead-out branches, wherein the source lead-out lines are located above the periphery of the active region A.
[0063] The leak connection layer 400 is connected to a plurality of leak regions D spaced apart in the first direction. This can be achieved by one contact connection post CT (leak contact connection post) corresponding to one leak region D, or by multiple contact connection posts CT (leak contact connection posts) corresponding to one leak region D.
[0064] In some embodiments, the drain connection layer 400 includes a plurality of drain lead-out branches and drain lead-out lines, wherein each drain lead-out branch extends along a second direction Y, and at least a portion of each drain lead-out branch is located above a corresponding drain region D, and each drain lead-out branch is connected to a corresponding drain region D; the drain lead-out lines extend along a first direction X to connect the plurality of drain lead-out branches, wherein the drain lead-out lines are located above the periphery of the active region A.
[0065] It is understandable that the source lead and the drain lead are located on different sides of the active region A. For example, the source lead is located above the first side of the active region A, and the drain lead is located above the second side of the active region A.
[0066] In some embodiments, the gate connection layer 200 is connected to one end of a corresponding gate line 110 via a first gate contact connection post.
[0067] Specifically, each gate connection region 201 or connection branch 202 of the gate connection layer 200 is connected to one end of a corresponding gate line 110 through a first gate contact connection post CT1.
[0068] In other embodiments, the gate connection layer 200 is connected to one end of a corresponding gate line 110 via a plurality of second gate contact connection pillars.
[0069] Specifically, each gate connection region 201 or connection branch 202 of the gate connection layer 200 is connected to one end of the same corresponding gate line 110 through a plurality of second gate contact connection posts.
[0070] The cross-sectional area of each first gate contact post is greater than the cross-sectional area of the second gate contact post.
[0071] In some embodiments, each gate connection region 201 and connection branch 202 are connected to a corresponding gate line 110 through a gate contact connection post CT1.
[0072] For example, when the first metal pattern layer M1 includes a gate connection layer 200 and the second metal pattern layer M2 includes a source connection layer 300 and a drain connection layer 400, each gate connection region 201 is connected to a corresponding gate line 110 through a gate contact connection post CT1. (See also...) Figure 4 Alternatively, when the first metal pattern layer M1 includes a source connection layer 300 and a drain connection layer 400, and the second metal pattern layer M2 includes a gate connection layer 200, each gate connection region 201 is connected to the first metal pattern layer M1 through a gate via connection post V1, and then connected to a corresponding gate line 110 through a gate contact connection post CT1; or, each connection branch 202 is connected to a corresponding gate line 110 through a gate contact connection post CT1. Please refer to [link to relevant documentation]. Figure 1 and Figure 2 .
[0073] In other embodiments, each gate connection region 201 and connection branch 202 is connected to a corresponding gate line 110 through a plurality of gate contact connection posts CT1.
[0074] For example, when the first metal pattern layer M1 includes a gate connection layer 200 and the second metal pattern layer M2 includes a source connection layer 300 and a drain connection layer 400, each connection branch 202 is connected to a corresponding gate line 110 through multiple gate contact connection pillars CT1. (See also...) Figure 3 Alternatively, when the first metal pattern layer M1 includes a source connection layer 300 and a drain connection layer 400, and the second metal pattern layer M2 includes a gate connection layer 200, each gate connection region 201 is connected to the corresponding gate auxiliary connection branch 203 through multiple gate via connection posts V1, and is connected to a corresponding gate line 110 through multiple gate contact connection posts CT1.
[0075] The width of the gate line in the first direction and the width of the gate contact post in the first direction can be set according to actual needs, so that the gate contact post can be connected to the gate line.
[0076] In the appendix Figure 1-3 In the middle, the width of the gate line at both ends is the same as the width at the middle, and the width of the gate contact connection post CT1 in the first direction X is greater than the width of the gate line.
[0077] In another embodiment, the width L1 of the first end and / or the second end of the gate line in the first direction X is greater than the width L2 of the middle of the gate line. The middle of the gate line is the gate line located between the first end and the second end. This facilitates process control of forming gate contact connection pillars on the first end and / or the second end of the gate line. For example, the width L3 of the gate contact connection pillar in the first direction X is less than L1.
[0078] Experimental verification shows that when the projection of the gate interconnect layer onto the substrate is outside the active region and surrounds the active region, the corresponding low-noise amplifier has a cutoff frequency Ft of A1 (GHz), a maximum oscillation frequency Fmax of A2 (GHz), and a gate parasitic resistance Rg of A3 (ohms). However, using the technical solution of this application, with multiple gate lines disconnected, the projection of the gate interconnect layer onto the substrate outside the active region, and the projection of the gate interconnect layer onto the substrate not surrounding the active region, the low-noise amplifier has a cutoff frequency of A1*1.15 (GHz), a maximum oscillation frequency Fmax of A2*1.23 (GHz), and a gate parasitic resistance Rg of A3*0.9 (ohms). That is, the cutoff frequency Ft is increased by 15%, the maximum oscillation frequency Fmax is increased by 23%, and the gate parasitic resistance Rg is reduced by 10%.
[0079] In this embodiment, multiple transistors are set according to actual design requirements. The multiple gate wirings corresponding to the multiple transistors will generate parasitic capacitance, and the parasitic capacitance is relatively large, which affects the performance of the semiconductor device. By disconnecting the multiple gate lines and setting the projection of the gate connection layer on the substrate outside the active region, located above the periphery of the active region, and the projection of the gate connection layer on the substrate does not surround the active region, the parasitic capacitance can be effectively reduced, the cutoff frequency and maximum oscillation frequency of the low noise amplifier can be improved, and the power frequency of the low noise amplifier can be effectively improved, thereby improving the performance of the low noise amplifier.
[0080] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.
Claims
1. A semiconductor device, characterized by, Comprising: a substrate comprising an active region, the substrate having a plurality of gate lines spaced apart and disconnected from each other disposed thereon; a gate connection layer disposed above the substrate, the gate connection layer connected with the plurality of gate lines, wherein the gate connection layer is located above a periphery of the active region and is discontinuously disposed.
2. The semiconductor device of claim 1, wherein: the gate connection layer comprises a first side gate connection line located at a first side of the active region; each of the gate lines extends in a second direction, the first side gate connection line extends in a first direction, the first direction intersects the second direction, and the first side gate connection line is configured to connect first ends of the plurality of gate lines.
3. The semiconductor device of claim 2, wherein: the gate connection layer further comprises a second side gate connection line, the first side gate connection line is parallel to the second side gate connection line, the second side gate connection line is located at a second side of the active region, the first side and the second side are opposite to each other; the second side gate connection line is configured to connect second ends of the plurality of gate lines, the second ends are distanced from the first ends.
4. The semiconductor device of claim 3, wherein: the gate connection layer further comprises a gate connection portion disposed between the first side gate connection line and the second side gate connection line to connect the first side gate connection line and the second side gate connection line; the gate connection portion is located at a third side of the active region.
5. The semiconductor device of any one of claims 2-4, wherein: a plurality of gate connection regions are respectively disposed on the first side gate connection line and / or the second side gate connection line, the first side gate connection line and / or the second side gate connection line is connected with the first ends and / or the second ends of the plurality of gate lines through the gate connection regions; or the gate connection layer further comprises a plurality of connection branches extending from the first side gate connection line and / or the second side gate connection line, the connection branches respectively extend in the second direction, and the first side gate connection line and / or the second side gate connection line is connected with the first ends and / or the second ends of the plurality of gate lines through the connection branches.
6. The semiconductor device of claim 1, wherein Further comprising: a first metal pattern layer disposed above the substrate; a second metal pattern layer disposed above the first metal pattern layer; wherein one of the first metal pattern layer and the second metal pattern layer comprises the gate connection layer; the gate lines and the first metal pattern layer, the second metal pattern layer are respectively located in different layers, and the gate connection layer and the gate lines are connected through a gate contact connection column, or through a gate contact connection column, the first metal pattern layer, and a gate via connection column.
7. The semiconductor device of claim 6, wherein: the other one of the first metal pattern layer and the second metal pattern layer comprises a source connection layer and a drain connection layer. The source connection layer connects a plurality of source regions, and the drain connection layer connects a plurality of drain regions.
8. The semiconductor device of claim 7, wherein, the source connection layer comprises a plurality of source lead branches and a source lead line, each of the source lead branches extends to a corresponding one of the source regions along the second direction, and the source lead line extends along the first direction to connect the source lead branches; the drain connection layer comprises a plurality of drain lead branches and a drain lead line, each of the drain lead branches extends to a corresponding one of the drain regions along the second direction, and the drain lead line extends along the first direction to connect the drain lead branches.
9. The semiconductor device of claim 1, wherein, the gate connection layer is connected to one end of a corresponding one of the gate lines by a first gate contact connection pillar; or the gate connection layer is connected to one end of a corresponding one of the gate lines by a plurality of second gate contact connection pillars; each of the first gate contact connection pillars has a cross-sectional area larger than that of the second gate contact connection pillars.
10. The semiconductor device of claim 1, wherein, the gate lines have a width in the first direction that is larger at the first and / or second ends than at a middle of the gate lines.
11. The semiconductor device of claim 1, wherein, the substrate is an SOI substrate.