Semiconductor device and method of manufacturing the same

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a plurality of crystal grains, a protection layer, a plurality of gate metal layers, a plurality of source metal layers and a drain metal layer. Each crystal grain comprises a grid electrode contact, a source electrode contact and a drain electrode contact, wherein the drain electrode contact is arranged on the back surface of the crystal grain. The plurality of gate openings individually correspond to the gate contacts of the respective dies, and the plurality of source openings individually correspond to the source contacts of the respective dies. Each gate metal layer is electrically connected with a plurality of gate contacts in the same column through a plurality of gate openings of the protective layer. Each source metal layer is electrically connected with a plurality of source contacts in the same column through a plurality of source openings of the protection layer. The drain metal layer is formed on the back surfaces of the plurality of crystal grains. The drain metal layer is electrically connected to the plurality of drain contacts.

Description

Technical Field

[0001] This case relates to a semiconductor device and a method for manufacturing the same, which can reduce internal inductance and impedance and reduce wafer size. Background Technology

[0002] High-power-density power devices typically contain multiple dies. These dies are usually interconnected via wire bonding, allowing the gates or sources of each die to be connected in parallel. Each die has a drain contact on its back side, and these drain contacts are electrically connected to each other through a drain metal layer coated on the back side of the dies.

[0003] However, the power integrity and signal integrity of the device are affected by power ripple due to the inductance and impedance of the wires. The longer the wire length or the more wires there are, the greater the inductance and impedance, and the greater the impact of power ripple. In addition, the size of the device is also difficult to reduce due to the wire spacing that must be set by the wire bonding. Summary of the Invention

[0004] In some embodiments, a semiconductor device includes a plurality of dies, a protective layer, a plurality of gate metal layers, a plurality of source metal layers, and a drain metal layer. The plurality of dies are arranged in a matrix, and each die includes a gate contact, a source contact, and a drain contact. The drain contact is disposed on the back side of the die. The protective layer is formed on the active surface of the plurality of dies, and the protective layer includes a plurality of gate openings and a plurality of source openings. The plurality of gate openings individually correspond to the gate contacts of each die, and the plurality of source openings individually correspond to the source contacts of each die. The plurality of gate metal layers are formed on the protective layer and spaced apart from each other, and each gate metal layer is electrically connected to a plurality of gate contacts located in the same column via the plurality of gate openings of the protective layer. The plurality of source metal layers are formed on the protective layer and spaced apart from each other, and each source metal layer is electrically connected to a plurality of source contacts located in the same column via the plurality of source openings of the protective layer. The drain metal layer is formed on the back side of the plurality of dies. The drain metal layer is electrically connected to a plurality of drain contacts.

[0005] In some embodiments, the semiconductor device further includes a first wire and a second wire. The first wire is electrically connected to a plurality of gate metal layers. The second wire is electrically connected to a plurality of source metal layers.

[0006] In some embodiments, a plurality of gate metal layers and a plurality of source metal layers are arranged alternately with each other.

[0007] In some embodiments, the multiple gate metal layers and the multiple source metal layers are not in contact with each other.

[0008] In some embodiments, a method of manufacturing a semiconductor device includes: coating an insulating material onto gate contacts and source contacts on the active surfaces of a plurality of dies; subjecting the insulating material outside the gate contacts and source contacts of the plurality of dies to ultraviolet light exposure using a first photomask; dissolving the insulating material in the unexposed areas using a first developer to form a plurality of first gate openings and a plurality of first source openings, wherein the undissolved insulating material, the plurality of first gate openings, and the plurality of first source openings constitute a first protective layer; heating the first protective layer to cure the insulating material of the first protective layer; removing residues or scum around the plurality of first gate openings and the plurality of first source openings; sputtering a first seed UBM layer onto the first protective layer using multiple ion bombardment of a solid target; coating a first photoresist onto the first seed UBM layer; and subjecting the area outside the second region to ultraviolet light exposure using a second photomask. The process involves: exposing the photoresist to ultraviolet light; dissolving the first photoresist in the second region that was not exposed to ultraviolet light using a second developer; removing residues or scum around the opening region after development with the second developer; sequentially depositing a first metal layer, a second metal layer, and a third metal layer from bottom to top onto the first seed UBM layer in the opening region after development with the second developer; removing the remaining first photoresist; removing the exposed first seed UBM layer, wherein the remaining first seed UBM layer, first metal layer, second metal layer, and third metal layer are multiple first gate metal layers and multiple first source metal layers; acid washing the surface of the third metal layer to remove metal contaminants from the surface of the third metal layer; grinding the back sides of multiple dies; forming drain contacts on the back sides of each die; coating a drain metal layer on the back sides of multiple dies, wherein the drain metal layer electrically connects to the multiple drain contacts; and performing an automated visual inspection of the semiconductor device.

[0009] In some embodiments, a semiconductor device includes a plurality of dies, a first protective layer, a first gate metal layer, a plurality of first source metal layers, a second protective layer, a second gate metal layer, a second source metal layer, and a drain metal layer. The plurality of dies are arranged in a matrix, and each die includes a gate contact, a source contact, and a drain contact. The drain contact is disposed on the back side of the die. The first protective layer is formed on the active surface of the plurality of dies, and the first protective layer includes a plurality of first gate openings and a plurality of first source openings, each first gate opening individually corresponding to a gate contact of each die, and each first source opening individually corresponding to a source contact of each die. The first gate metal layer is formed on the first protective layer and is electrically connected to the plurality of gate contacts via the plurality of first gate openings of the first protective layer. The plurality of first source metal layers are individually formed on each source contact via each first source opening of the first protective layer. A second protective layer is formed on the first gate metal layer and a plurality of first source metal layers. The second protective layer includes a second gate opening and a plurality of second source openings. The second gate opening corresponds to one row of the first gate metal layers, and the plurality of second source openings individually correspond to each of the first source metal layers. The second gate metal layer is formed on the second protective layer and is formed on the first gate metal layer through the second gate opening of the second protective layer. The second source metal layer is formed on the second protective layer and is electrically connected to the plurality of first source metal layers through the plurality of second source openings of the second protective layer. A drain metal layer is formed on the back side of a plurality of dies. The drain metal layer is electrically connected to a plurality of drain contacts.

[0010] In some embodiments, the first gate metal layer and the plurality of first source metal layers are not in contact with each other.

[0011] In some embodiments, the second gate metal layer and the second source metal layer are not in contact with each other.

[0012] In some embodiments, a method of manufacturing a semiconductor device includes coating an insulating material onto gate contacts and source contacts on the active surfaces of a plurality of dies; subjecting the insulating material outside the areas on the gate contacts and source contacts to ultraviolet light exposure using a first photomask; dissolving the insulating material in the areas not exposed to ultraviolet light using a first developer to form a plurality of first gate openings and a plurality of first source openings, wherein the insulating material not dissolved by the first developer, the plurality of first gate openings, and the plurality of first source openings constitute a first protective layer; heating the first protective layer to cure the insulating material of the first protective layer; removing residues or scum around the plurality of first gate openings and the plurality of first source openings; and sputtering the material by bombarding a solid target with a plurality of ions. A first seed UBM layer is deposited on a first protective layer; a first photoresist is coated on the first seed UBM layer; the first photoresist in areas other than the second region is exposed to ultraviolet light using a second photomask; the first photoresist in the second region not exposed to ultraviolet light is dissolved using a second developer; residues or scum around the opening area after development with the second developer are removed; a first metal layer, a second metal layer, and a third metal layer are sequentially disposed from bottom to top on the first seed UBM layer in the opening area after development with the second developer; the remaining first photoresist is removed; the exposed first seed UBM layer is removed, wherein the remaining first seed UBM layer, first metal layer, second metal layer, and third metal layer are a first gate metal layer and multiple A first source metal layer; acid pickling of the surface of the third metal layer to remove metal contaminants from the surface of the third metal layer; coating an insulating material onto the first gate metal layer and multiple first source metal layers; ultraviolet exposure of the insulating material outside the areas on the first gate metal layer and multiple first source metal layers using a third photomask; dissolving the insulating material in the areas not exposed to ultraviolet light using a third developer to form a second gate opening on the first gate metal layer and multiple second source openings on the multiple first source metal layers, wherein the insulating material of the first gate metal layer and multiple first source metal layers not dissolved by the third developer, the second gate opening and multiple second source openings constitute a second protective layer; heating the second protective layer. The process involves: curing the insulating material of the second protective layer; removing residues or dross around the second gate opening and multiple second source openings; sputtering a second seed UBM layer onto the second protective layer using multiple ion bombardments on a solid target; applying a second photoresist onto the second seed UBM layer; exposing the second photoresist in areas other than the third region to ultraviolet light using a fourth photomask; dissolving the second photoresist in the third region that was not exposed to ultraviolet light using a fourth developer; removing residues or dross around the opening area after development with the fourth developer; sequentially depositing the fourth metal layer, the fifth metal layer, and the sixth metal layer from bottom to top onto the second seed UBM layer in the opening area after development with the fourth developer; and removing the remaining second photoresist.The exposed second seed UBM layer is removed, leaving the second seed UBM layer, fourth metal layer, fifth metal layer, and sixth metal layer as the second gate metal layer and second source metal layer, respectively. The surface of the sixth metal layer is acid-washed to remove metal contaminants. The back sides of multiple dies are ground. Drain contacts are formed on the back sides of each die. A drain metal layer is coated on the back sides of the multiple dies, electrically connecting the drain metal layer to the multiple drain contacts. Finally, an automated visual inspection of the semiconductor device is performed.

[0013] In some embodiments, a semiconductor device includes a plurality of dies, a first protective layer, a first gate metal layer, a plurality of first source metal layers, a plurality of first drain metal layers, a second protective layer, a plurality of second gate metal layers, a plurality of second source metal layers, and a plurality of second drain metal layers. The plurality of dies are arranged in a matrix. Each die includes a gate contact, a source contact, and a drain contact. The first protective layer is formed on the active surface of the plurality of dies and includes a plurality of first gate openings, a plurality of first source openings, and a plurality of first drain openings. The plurality of first gate openings individually correspond to the gate contacts of each die. The plurality of first source openings individually correspond to the source contacts of each die. The plurality of first drain openings individually correspond to the drain contacts of each die. A first gate metal layer is formed on the first protective layer. The first gate metal layer is electrically connected to the plurality of gate contacts through the plurality of first gate openings of the first protective layer. A plurality of first source metal layers are formed on the first protective layer. Each first source metal layer is electrically connected to a plurality of source contacts located in the same column through the plurality of first source openings of the first protective layer. Multiple first drain metal layers are formed on a first guard layer. Each first drain metal layer is electrically connected to multiple drain contacts located in the same column via multiple first drain openings in the first guard layer. A second guard layer is formed on a first gate metal layer, multiple first source metal layers, and multiple first drain metal layers, including multiple second gate openings, multiple second source openings, and multiple second drain openings. Each second gate opening corresponds to a portion of the first gate metal layer. Multiple second source openings individually correspond to each first source metal layer. Multiple second drain openings individually correspond to each first drain metal layer. Multiple second gate metal layers are formed on a second guard layer. Each second gate metal layer is formed on a first gate metal layer via each second gate opening in the second guard layer. Multiple second source metal layers are formed on a second guard layer. Each second source metal layer is formed on a first source metal layer via each second source opening in the second guard layer. Multiple second drain metal layers are formed on a second guard layer. Each second drain metal layer is formed on each first drain metal layer through each second drain opening of the second protective layer.

[0014] In some embodiments, the first gate metal layer, the plurality of first source metal layers, and the plurality of first drain metal layers are not in contact with each other.

[0015] In some embodiments, the plurality of second gate metal layers, the plurality of second source metal layers, and the plurality of second drain metal layers are not in contact with each other.

[0016] In some embodiments, a method of manufacturing a semiconductor device includes coating an insulating material onto gate contacts, source contacts, and drain contacts on the active surfaces of a plurality of dies; subjecting the insulating material outside the areas on the gate contacts, source contacts, and drain contacts of the plurality of dies to ultraviolet light exposure using a first photomask; dissolving the insulating material in the areas not exposed to ultraviolet light using a first developer to form a plurality of first gate openings, a plurality of first source openings, and a plurality of first drain openings, wherein the insulating material, the plurality of first gate openings, the plurality of first source openings, and the plurality of first drain openings not dissolved by the first developer constitute a first protective layer; heating the first protective layer to cure the insulating material of the first protective layer; and removing the plurality of first gate openings and the plurality of first source openings. and residues or scum around multiple first drain openings; sputter a first seed UBM layer onto a first protective layer by bombarding a solid target with multiple ions; coat a first photoresist onto the first seed UBM layer; expose the first photoresist in areas other than the second region to ultraviolet light through a second photomask; dissolve the first photoresist in the second region not exposed to ultraviolet light using a second developer; remove residues or scum around the opening area after development with the second developer; sequentially deposit a first metal layer, a second metal layer, and a third metal layer onto the first seed UBM layer in the opening area after development with the second developer from bottom to top; remove the remaining first photoresist; remove the exposed first seed UBM layer, wherein the remaining first seed UBM layer, the first... The metal layer, second metal layer, and third metal layer constitute a first gate metal layer, multiple first source metal layers, and multiple first drain metal layers. The surface of the third metal layer is acid-washed to remove metal contaminants. An insulating material is coated onto the first gate metal layer, multiple first source metal layers, and multiple first drain metal layers. The insulating material in areas other than those on the first gate metal layer, multiple first source metal layers, and multiple first drain metal layers is exposed to ultraviolet light using a third photomask. A third developer is used to dissolve the insulating material in areas not exposed to ultraviolet light to form multiple second gate openings on the first gate metal layer, multiple second source openings on the multiple first source metal layers, and multiple second drain openings on the multiple first drain metal layers. On the metal layer, the insulating material of the first gate metal layer, multiple first source metal layers, and multiple first drain metal layers that are not dissolved by the third developer, multiple second gate openings, multiple second source openings, and multiple second drain openings constitute a second protective layer; the second protective layer is heated to cure the insulating material of the second protective layer; residues or scum around the second gate openings, multiple second source openings, and multiple second drain openings are removed; a second seed UBM layer is sputtered onto the second protective layer by bombarding the solid target with multiple ions; a second photoresist is coated onto the second seed UBM layer; the second photoresist in the area other than the third region is exposed to ultraviolet light through a fourth photomask; the second photoresist in the third region that is not exposed to ultraviolet light is dissolved by the fourth developer;Remove residues or scum around the opening area after development with the fourth developer; sequentially deposit the fourth, fifth, and sixth metal layers from bottom to top on the second seed UBM layer of the opening area after development with the fourth developer; remove the remaining second photoresist; remove the exposed second seed UBM layer, wherein the remaining second seed UBM layer, fourth metal layer, fifth metal layer, and sixth metal layer constitute multiple second gate metal layers, multiple second source metal layers, and multiple second drain metal layers; acid-wash the surface of the sixth metal layer to remove metal contaminants from the surface of the sixth metal layer; and perform automated visual inspection on the semiconductor device.

[0017] The following detailed description of the features and advantages of this invention is sufficient to enable anyone skilled in the art to understand the technical content of this invention and implement it accordingly. Furthermore, based on the disclosure in this specification, the claims, and the drawings, anyone skilled in the art can easily understand the relevant objectives and advantages of this invention. Attached Figure Description

[0018] Figures 1A to 1C A schematic diagram of one embodiment of the grain;

[0019] Figures 2A to 2E This is a schematic diagram of an embodiment of a semiconductor device;

[0020] Figure 3 A schematic diagram of another embodiment of a semiconductor device;

[0021] Figure 4 This is a schematic diagram of a prior art semiconductor device;

[0022] Figures 5A to 5N A schematic diagram of an embodiment of a method for manufacturing a semiconductor device;

[0023] Figures 6A to 6B A flowchart of an embodiment of a method for manufacturing a semiconductor device;

[0024] Figures 7A to 7G This is a schematic diagram of yet another embodiment of a semiconductor device;

[0025] Figures 8A to 8D A flowchart of yet another embodiment of a method for manufacturing a semiconductor device;

[0026] Figures 9A to 9B A schematic diagram of another embodiment of the grain;

[0027] Figures 10A to 10E A schematic diagram of yet another embodiment of a semiconductor device;

[0028] Figures 11A to 11C This is a flowchart of another embodiment of a method for manufacturing a semiconductor device.

[0029] [Symbol Explanation]

[0030] 1: Semiconductor devices

[0031] 10: Grain

[0032] 101: Gate contact

[0033] 102: Source contact

[0034] 103: Drain contact

[0035] 19: Drain metal layer

[0036] 11: Protective layer

[0037] 111: Gate opening

[0038] 112: Source opening

[0039] 12: Gate metal layer

[0040] 13: Source metal layer

[0041] 2: Semiconductor devices

[0042] 20: Grain

[0043] 201: Gate contact

[0044] 202: Source contact

[0045] 30: Insulating materials

[0046] 31: First Light Mask

[0047] 39: Second Light Mask

[0048] 32,34,40,42: Areas

[0049] 33: First developer

[0050] 41: Second developer

[0051] 35: Solid target

[0052] 36: Ions

[0053] 37: First seed UBM layer

[0054] 38: First photoresist

[0055] 43: Third metal layer

[0056] 44: Second metal layer

[0057] 45: First metal layer

[0058] 46: Photoresist stripper

[0059] 47: Etching agent

[0060] 48: Acids

[0061] S01~S18: Steps

[0062] 111: First protective layer

[0063] 1111: First gate opening

[0064] 1112: First source opening

[0065] 14: First gate metal layer

[0066] 15: First source metal layer

[0067] 16: Second protective layer

[0068] 161: Second gate opening

[0069] 162: Second source opening

[0070] 17: Second gate metal layer

[0071] 18: Second source metal layer

[0072] S201~S232, S301~S329: Steps

[0073] 112: First protective layer

[0074] 1121: First gate opening

[0075] 1122: First source opening

[0076] 1123: First drain opening

[0077] 21: First gate metal layer

[0078] 22: First source metal layer

[0079] 23: First drain metal layer

[0080] 24: Second protective layer

[0081] 241: Second gate opening

[0082] 242: Second source opening

[0083] 243: Second drain opening

[0084] 25: Second gate metal layer

[0085] 26: Second source metal layer

[0086] 27: Second drain metal layer

[0087] 121: First conductor

[0088] 131: Second conductor Detailed Implementation

[0089] Figure 1A This is a cross-sectional view of one embodiment of grain 10. Figure 1B This is a top view of one embodiment of grain 10. Figure 1C This is a bottom view of one embodiment of grain 10. Please refer to [link / reference]. Figures 1A to 1C The die 10 includes a gate contact 101, a source contact 102, and a drain contact 103. The gate contact 101 and the source contact 102 are disposed on the active surface of the die 10. The drain contact 103 is disposed on the back side of the die 10. In some embodiments, the die 10 is a vertical metal-oxide-semiconductor field-effect transistor (Vertical MOSFET) wafer.

[0090] Please see Figure 2A Semiconductor device 1 includes multiple such... Figures 1A to 1C The grain 10 is shown. Multiple grains 10 are arranged in a matrix. Figure 2A In one embodiment, the semiconductor device 1 comprises 16 chips 10 and the 16 chips 10 are arranged in a 4x4 matrix, but this invention is not limited thereto. The number of chips 10 included in the semiconductor device 1 can be any number and the chips 10 included in the semiconductor device 1 can be arranged in a matrix of any size.

[0091] Please see Figure 2B The semiconductor device 1 further includes a protective layer 11. The protective layer 11 is formed on the active surfaces of the plurality of dies 10. The protective layer 11 includes a plurality of gate openings 111 and a plurality of source openings 112. The plurality of gate openings 111 individually correspond to the gate contact 101 of each die 10, and the plurality of source openings 112 individually correspond to the source contact 102 of each die 10.

[0092] Please see Figure 2CThe semiconductor device 1 further includes a plurality of gate metal layers 12 and a plurality of source metal layers 13. The plurality of gate metal layers 12 are formed on a protective layer 11 and are spaced apart from each other. Each gate metal layer 12 is electrically connected to a plurality of gate contacts 101 located in the same column via a plurality of gate openings 111 of the protective layer 11. The plurality of source metal layers 13 are formed on the protective layer 11 and are spaced apart from each other. Each source metal layer 13 is electrically connected to a plurality of source contacts 102 located in the same column via a plurality of source openings 112 of the protective layer 11. In some embodiments, the plurality of gate metal layers 12 and the plurality of source metal layers 13 are arranged alternately, but this is not a limitation of the present invention. In some embodiments, since each gate metal layer 12 is used to electrically connect a plurality of gate contacts 101 located in the same column and each source metal layer 13 is used to electrically connect a plurality of source contacts 102 located in the same column, the plurality of gate metal layers 12 and the plurality of source metal layers 13 do not contact each other to avoid the gate contacts 101 and source contacts 102 of the plurality of dies 10 from being interconnected.

[0093] Please see Figures 2D to 2E The semiconductor device 1 further includes a drain metal layer 19. The drain metal layer 19 is formed on the back side of a plurality of dies 10 and is electrically connected to a plurality of drain contacts 103. In some embodiments, the drain metal layer 19 may reduce the impedance of the semiconductor device 1 and the operating temperature of the semiconductor device 1.

[0094] It is hereby specifically stated that... Figures 2A to 2C This is a top-down view of semiconductor device 1. Figures 2D to 2E The semiconductor device 1 is viewed from a bottom-up angle. In some embodiments, when the semiconductor device 1 is viewed from a top-down angle, the gate contacts 101 and the plurality of gate openings 111 of the protective layer 11 of each die 10 are covered by the plurality of gate metal layers 12 and cannot be observed. Similarly, the source contacts 102 and the plurality of source openings 112 of the protective layer 11 of each die 10 are covered by the plurality of source metal layers 13 and cannot be observed. In some embodiments, when the semiconductor device 1 is viewed from a bottom-up angle, the drain contacts 103 of each die 10 are covered by the drain metal layer 19 and cannot be observed.

[0095] Please see Figure 3 In some embodiments, the semiconductor device 1 further includes a first wire 121 and a second wire 131. The first wire 121 is electrically connected to a plurality of gate metal layers 12. The second wire 131 is electrically connected to a plurality of source metal layers 13.

[0096] Please see Figures 2A to 4 .like Figure 4As shown, the prior art semiconductor device 2 includes multiple chips 20. Each chip 20 includes a gate contact 201 and a source contact 202. The gate contact 201 and the source contact 202 of each chip 20 must be interconnected by wire bonding to enable the multiple chips 20 to be interconnected. In the semiconductor device 1, each chip 10 only needs to be interconnected by multiple gate metal layers 12 and multiple source metal layers 13 via a first wire 121 and a second wire 131. Therefore, compared to the prior art semiconductor device 2, the number of wires required and the total length of the wires required for the semiconductor device 1 are significantly reduced, thereby significantly reducing the inductance and impedance of the semiconductor device 1, and resulting in a significant reduction in the impact of power supply ripple on the semiconductor device 1. In addition, the wire spacing that must be provided in the semiconductor device 1 is also reduced due to the reduction in the number of wires and the total length of the wires, thereby reducing the size of the semiconductor device 1.

[0097] Figures 5A to 5N This is a schematic diagram of an embodiment of a method for manufacturing a semiconductor device 1. Figures 6A to 6B This is a flowchart illustrating one embodiment of a method for manufacturing semiconductor device 1. Please refer to [link / reference]. Figures 5A to 5B First, an insulating material 30 is coated onto the gate contact 101 and source contact 102 on the active surfaces of the plurality of dies 10 (step S01). Figure 5A (As shown). Next, the insulating material 30 in the area excluding region 32 on the gate contact 101 and source contact 102 of the plurality of chips 10 is subjected to ultraviolet (UV) exposure through the first photomask 31 (step S02) (as shown). Figure 5B (As shown). Next, the insulating material 30 in the area 32 not exposed to ultraviolet light is dissolved using the first developer 33 (step S03) (as shown). Figure 5C As shown), the openings created after being dissolved by the first developer 33 are multiple first gate openings 111 and multiple first source openings 112, while the insulating material 30 that is not dissolved by the first developer 33, the multiple first gate openings 111 and the multiple first source openings 112 constitute the first protective layer 11. Next, the first protective layer 11 is heated to solidify the insulating material 30 of the first protective layer 11 (step S04) (as shown). Figure 5D (As shown). Next, the area around the multiple gate openings 111 and the multiple source openings 112 is removed (as shown). Figure 5E The residue or scum in area 34 shown (step S05) (as shown) Figure 5E (As shown).

[0098] In some embodiments, the insulating material 30 may be, but is not limited to, a photoresist material. In some embodiments, the insulating material 30 may be, but is not limited to, polyimide (PI). In some embodiments, the insulating material 30 is a photosensitive insulating material, and the pattern on the first photomask 31 and the first developer 33 need to be changed according to the photosensitivity (positive / negative) of the insulating material 30.

[0099] In some embodiments, in step S05, residues or scum are removed from the region 34 surrounding the plurality of gate openings 111 and the plurality of source openings 112 by plasma cleaning.

[0100] Then, multiple ions 36 are used to bombard the solid target 35 to sputter a first seed UBM (Under Bump Metallization) layer 37 onto the first protective layer 11 (step S06). Figure 5F (As shown). In some embodiments, the solid target 35 is titanium (Ti), titanium-tungsten (TiW) alloy, or copper (Cu). In other words, in some embodiments, the first seed UBM layer 37 is made of titanium, titanium-tungsten alloy, or copper. In some embodiments, the ion 36 may be, but is not limited to, argon (Ar) ions. In some embodiments, when the first seed UBM layer 37 is made of titanium or titanium-tungsten alloy, the thickness of the first seed UBM layer 37 is between 10 and 500 micrometers (μm). In some embodiments, when the first seed UBM layer 37 is made of copper, the thickness of the first seed UBM layer 37 is between 1 and 10 μm. In some embodiments, when the first seed UBM layer 37 is made of copper, the thickness of the first seed UBM layer 37 is less than 10 μm.

[0101] Next, the first photoresist (PR) 38 is coated onto the first seed UBM layer 37 (step S07) (as shown in the image). Figure 5G (As shown). Next, the first photoresist 38 in the area outside the second region 40 is exposed to ultraviolet light through the second photomask 39 (step S08) (as shown). Figure 5H (As shown). Next, the first photoresist 38 of the second region 40, which was not exposed to ultraviolet light, is dissolved using the second developer 41 (step S09) (as shown). Figure 5I (As shown). Next, remove the area around the opening after development with the second developer 41 (e.g., Figure 5J Area 42) Residue or scum (step S10) (as shown) Figure 5J (As shown). Next, the first metal layer 45, the second metal layer 44, and the third metal layer 43 are sequentially disposed from bottom to top on the first seed UBM layer 37 of the opening area after development with the second developer 41 (step S11) (as shown). Figure 5K (As shown).

[0102] In some embodiments, the pattern on the second photomask 39 and the second developer 41 need to be changed according to the photosensitivity (positive / negative) of the first photoresist 38.

[0103] Next, the remaining first photoresist 38 is removed using photoresist stripper 46 (step S12) (e.g. Figure 5L (As shown). Next, the exposed first seed UBM layer 37 is removed using etchant 47 (step S13) (as shown). Figure 5M (As shown). The remaining first seed UBM layer 37, first metal layer 45, second metal layer 44, and third metal layer 43 constitute multiple first gate metal layers 12 and multiple first source metal layers 13. In some embodiments, the first metal layer 45 may be made of, but is not limited to, copper; the second metal layer 44 may be made of, but is not limited to, nickel (Ni); and the third metal layer 43 may be made of, but is not limited to, gold (Au). In some embodiments, the second metal layer 44 and the third metal layer 43 may function as, but are not limited to, rust prevention. In some embodiments, the gate metal layer 12 and the source metal layer 13 may be, but are not limited to, bumps. Therefore, in some embodiments, the method of setting the gate metal layer 12 and the source metal layer 13 may be, but is not limited to, a bumping process. In some embodiments, the thickness of the first metal layer 45 is between 1 and 50 μm, the thickness of the second metal layer 44 is between 0.1 and 10 μm, and the thickness of the third metal layer 43 is between 0.02 and 0.5 μm. In some embodiments, when the second metal layer 44 is made of nickel and the third metal layer 43 is made of gold, a palladium (Pd) layer is further included between the second metal layer 44 and the third metal layer 43. Introducing palladium between nickel and gold can improve bond strength, prevent damage, increase reliability, and improve high-temperature stability. Furthermore, palladium / gold (Pd / Au) has lower electrical resistance compared to nickel / gold (Ni / Au). In some embodiments, the thickness of palladium can range from, but is not limited to, 0 to 2 μm. In some embodiments, the combination of the second metal layer 44 and the third metal layer 43 is a nickel alloy layer, which can be, but is not limited to, a nickel-palladium-gold alloy, a nickel-gold alloy, or a nickel-palladium alloy.

[0104] Next, the surface of the third metal layer 43 is acid-cleaned using acid agent 48 to remove metal contaminants from the surface of the third metal layer 43 (step S14). Figure 5N(As shown). Next, the back sides of the plurality of dies 10 are ground (step S15) and drain contacts 103 are formed on the back sides of each die 10 (step S16). Next, a drain metal layer 19 is coated on the back sides of the plurality of dies 10 (step S17), and the drain metal layer 19 is electrically connected to the plurality of drain contacts 103. Finally, the semiconductor device 1 is subjected to an automatic visual inspection (AVI) using an observation instrument (step S18). In some embodiments, grinding the back sides of the plurality of dies 10 (step S15) can reduce the thickness of the semiconductor device 1, thereby reducing the volume of the semiconductor device 1. In some embodiments, grinding the back sides of the plurality of dies 10 (step S15) can expose the drains of the heavily doped regions of the plurality of dies 10 so that drain contacts 103 are formed on the drains of each die 10.

[0105] Figures 7A to 7G This is a schematic diagram of yet another embodiment of semiconductor device 1. Figure 7A The content shown is the same as Figure 2A The content shown will not be repeated here. Please refer to [link / reference]. Figure 7B In some embodiments, the semiconductor device 1 includes a first protective layer 111. The first protective layer 111 is formed on the active surfaces of a plurality of dies 10. The first protective layer 111 includes a plurality of first gate openings 1111 and a plurality of first source openings 1112. The plurality of first gate openings 1111 individually correspond to the gate contact 101 of each die 10, and the plurality of first source openings 1112 individually correspond to the source contact 102 of each die 10.

[0106] Please see Figure 7C In some embodiments, the semiconductor device 1 further includes a first gate metal layer 14 and a plurality of first source metal layers 15. The first gate metal layer 14 is formed on a first protective layer 111. The first gate metal layer 14 is electrically connected to a plurality of gate contacts 101 via a plurality of first gate openings 1111 of the first protective layer 111. The plurality of first source metal layers 15 are individually formed on each source contact 102 via each first source opening 1112 of the first protective layer 111. In some embodiments, since the first gate metal layer 14 is used to electrically connect the plurality of gate contacts 101 and each first source metal layer 15 is formed on each source contact 102, the first gate metal layer 14 and the plurality of first source metal layers 15 do not contact each other to avoid interconnection between the gate contacts 101 and source contacts 102 of the plurality of dies 10.

[0107] Please see Figure 7DIn some embodiments, the semiconductor device 1 further includes a second protective layer 16. The second protective layer 16 is formed on the first gate metal layer 14 and a plurality of first source metal layers 15. The second protective layer 16 includes a second gate opening 161 and a plurality of second source openings 162. The second gate opening 161 corresponds to one row of the first gate metal layers 14. The plurality of second source openings 162 individually correspond to each of the first source metal layers 15.

[0108] Please see Figure 7E In some embodiments, the semiconductor device 1 further includes a second gate metal layer 17 and a second source metal layer 18. The second gate metal layer 17 is formed on the second protective layer 16. The second gate metal layer 17 is formed on the first gate metal layer 14 via a second gate opening 161 of the second protective layer 16. The second source metal layer 18 is formed on the second protective layer 16. The second source metal layer 18 is electrically connected to a plurality of first source metal layers 15 via a plurality of second source openings 162 of the second protective layer 16. In some embodiments, since the second gate metal layer 17 is formed on the first gate metal layer 14 and the second source metal layer 18 is used to electrically connect the plurality of first source metal layers 15, the second gate metal layer 17 and the second source metal layer 18 do not contact each other to avoid the gate contacts 101 and source contacts 102 of the plurality of dies 10 being interconnected.

[0109] Please see Figures 7F to 7G The semiconductor device 1 further includes a drain metal layer 19. The drain metal layer 19 is formed on the back side of a plurality of dies 10 and is electrically connected to a plurality of drain contacts 103. In some embodiments, the drain metal layer 19 may reduce the impedance of the semiconductor device 1 and the operating temperature of the semiconductor device 1.

[0110] It is hereby specifically stated that... Figures 7A to 7E This is a top-down view of semiconductor device 1. Figures 7F to 7G The semiconductor device 1 is viewed from a bottom-up angle. In some embodiments, when the semiconductor device 1 is viewed from a top-down angle, the gate contacts 101 and source contacts 102 of each die 10, the plurality of first gate openings 1111 and the plurality of first source openings 1112 of the first protective layer 111, the plurality of first source metal layers 15, and the second gate openings 161 and the plurality of second source openings 162 of the second protective layer 16 are covered by the second gate metal layer 17 and the second source metal layer 18 and cannot be observed. In some embodiments, when the semiconductor device 1 is viewed from a top-down angle, only a portion of the first gate metal layer 14 can be observed. In some embodiments, when the semiconductor device 1 is viewed from a bottom-up angle, the drain contacts 103 of each die 10 are covered by the drain metal layer 19 and cannot be observed.

[0111] At Figures 7A to 7GIn the semiconductor device 1 shown, each die 10 can be interconnected by only the second gate metal layer 17 and the second source metal layer 18. Figures 7A to 7G The semiconductor device 1 shown does not require any wires for wire bonding. Therefore, compared to Figures 2A to 2E The semiconductor device 1 shown, Figures 7A to 7G The semiconductor device 1 shown further reduces the number of wires required and the total length of the wires, thereby further reducing the inductance and impedance of the semiconductor device 1, its susceptibility to power supply ripple, and the size of the semiconductor device 1. Furthermore, due to... Figures 7A to 7G The semiconductor device 1 shown directly contacts external pins, lead frames, or circuits through the entire second gate metal layer 17 and the entire second source metal layer 18. Therefore, it has a larger contact area than the prior art, and thus has a better heat dissipation effect.

[0112] Figures 8A to 8D This is a flowchart of yet another embodiment of a method for manufacturing semiconductor device 1. Figures 8A to 8D The manufacturing method of the semiconductor device 1 shown is the same as Figures 6A to 6B The manufacturing method of the semiconductor device 1 shown is similar. Please refer to [link / reference]. Figures 8A to 8D First, an insulating material is coated onto the gate contacts 101 and source contacts 102 on the active surfaces of the plurality of chips 10 (step S201). Next, the insulating material in areas other than those on the gate contacts 101 and source contacts 102 is exposed to ultraviolet light using a first photomask (step S202). Next, the insulating material in the areas not exposed to ultraviolet light is dissolved using a first developer to form a plurality of first gate openings 1111 and a plurality of first source openings 1112 (step S203), wherein the insulating material not dissolved by the first developer, the plurality of first gate openings 1111, and the plurality of first source openings 1112 constitute a first protective layer 111. Next, the first protective layer 111 is heated to cure the insulating material of the first protective layer 111 (step S204). Next, residues or scum around the plurality of first gate openings 1111 and the plurality of first source openings 1112 are removed (step S205). In some embodiments, the insulating material is a photosensitive insulating material, and the pattern on the first photomask and the first developer need to be changed according to the photosensitivity (positive / negative) of the insulating material.

[0113] Then, a first seed UBM layer is sputtered onto the first protective layer 111 by bombarding a solid target with multiple ions (step S206). Next, a first photoresist is coated onto the first seed UBM layer (step S207). Next, the first photoresist in areas other than the second region is exposed to ultraviolet light through a second photomask (step S208). Next, the first photoresist in the second region that was not exposed to ultraviolet light is dissolved using a second developer (step S209). Next, residues or scum around the opening area after development with the second developer are removed (step S210). Next, a first metal layer, a second metal layer, and a third metal layer are sequentially disposed from bottom to top on the first seed UBM layer in the opening area after development with the second developer (step S211). In some embodiments, the pattern on the second photomask and the second developer need to be changed according to the photosensitivity (positive / negative) of the first photoresist.

[0114] Next, the remaining first photoresist is removed (step S212). Then, the exposed first seed UBM layer is removed (step S213), wherein the remaining first seed UBM layer, first metal layer, second metal layer, and third metal layer are a first gate metal layer 14 and a plurality of first source metal layers 15. In some embodiments, the first gate metal layer 14 and the first source metal layer 15 may be, but are not limited to, bumps. Therefore, in some embodiments, the method for setting the first gate metal layer 14 and the first source metal layer 15 may be, but is not limited to, a bump process. Next, the surface of the third metal layer is acid-washed to remove metal contaminants from the surface of the third metal layer (step S214).

[0115] Then, an insulating material is coated onto the first gate metal layer 14 and the plurality of first source metal layers 15 (step S215). Next, the insulating material in areas other than those on the first gate metal layer 14 and the plurality of first source metal layers 15 is exposed to ultraviolet light using a third photomask (step S216). Next, the insulating material in the areas not exposed to ultraviolet light is dissolved using a third developer to form a second gate opening 161 on the first gate metal layer 14 and a plurality of second source openings 162 on the plurality of first source metal layers (step S217), wherein the insulating material of the first gate metal layer 14 and the plurality of first source metal layers 15 that is not dissolved by the third developer, the second gate opening 161 and the plurality of second source openings 162 constitute a second protective layer 16. Next, the second protective layer 16 is heated to cure the insulating material of the second protective layer 16 (step S218). Next, the residue or scum around the second gate opening 161 and the plurality of second source openings 162 is removed (step S219). In some embodiments, the insulating material is a photosensitive insulating material, and the pattern on the third photomask and the third developer need to be changed according to the photosensitivity (positive / negative) of the insulating material.

[0116] Then, a second seed UBM layer is sputtered onto the second protective layer by bombarding a solid target with multiple ions (step S220). Next, a second photoresist is coated onto the second seed UBM layer (step S221). Next, the second photoresist in areas other than the third region is exposed to ultraviolet light through a fourth photomask (step S222). Next, the second photoresist in the third region that was not exposed to ultraviolet light is dissolved using a fourth developer (step S223). Next, residues or scum around the opening area after development with the fourth developer are removed (step S224). Next, a fourth metal layer, a fifth metal layer, and a sixth metal layer are sequentially deposited from bottom to top on the second seed UBM layer in the opening area after development with the fourth developer (step S225). In some embodiments, the pattern on the fourth photomask and the fourth developer need to be changed according to the photosensitivity (positive / negative) of the second photoresist.

[0117] Next, the remaining second photoresist is removed (step S226). Then, the exposed second seed UBM layer is removed (step S227), wherein the remaining second seed UBM layer, fourth metal layer, fifth metal layer, and sixth metal layer are the second gate metal layer 17 and the second source metal layer 18. In some embodiments, the fourth metal layer may be made of, but is not limited to, copper; the fifth metal layer may be made of, but is not limited to, nickel; and the sixth metal layer may be made of, but is not limited to, gold. In some embodiments, the function of the fifth and sixth metal layers may be, but is not limited to, rust prevention. In some embodiments, the second gate metal layer 17 or the second source metal layer 18 may be, but is not limited to, a bump. Therefore, in some embodiments, the method of setting the second gate metal layer 17 or the second source metal layer 18 may be, but is not limited to, a bump process.

[0118] Next, the surface of the sixth metal layer is acid-washed to remove metal contaminants (step S228). Next, the back sides of the plurality of grains 10 are ground (step S229) and drain contacts 103 are formed on the back sides of each grain 10 (step S230). Next, a drain metal layer 19 is coated on the back sides of the plurality of grains 10 (step S231), and the drain metal layer 19 is electrically connected to the plurality of drain contacts 103. Finally, the semiconductor device 1 is automatically visually inspected using an observation instrument (step S232).

[0119] Figure 9A This is a cross-sectional view of another embodiment of grain 10. Figure 9B This is a top view of another embodiment of grain 10. See also... Figures 9A to 9BThe die 10 includes a gate contact 101, a source contact 102, and a drain contact 103. The gate contact 101, source contact 102, and drain contact 103 are all disposed on the active surface of the die 10. In some embodiments, the die 10 is a lateral metal-oxide-semiconductor field-effect transistor (Lateral MOSFET) wafer.

[0120] Please see Figure 10A Semiconductor device 1 includes multiple such... Figures 9A to 9B The grain 10 is shown. Multiple grains 10 are arranged in a matrix. Figure 10A In one embodiment, the semiconductor device 1 comprises four chips 10 arranged in a 2x2 matrix, but this invention is not limited thereto. The number of chips 10 in the semiconductor device 1 can be arbitrary, and the chips 10 in the semiconductor device 1 can be arranged in a matrix of any size.

[0121] Please see Figure 10B In some embodiments, the semiconductor device 1 includes a first protective layer 112. The first protective layer 112 is formed on the active surfaces of a plurality of dies 10. The first protective layer 112 includes a plurality of first gate openings 1121, a plurality of first source openings 1122, and a plurality of first drain openings 1123. The plurality of first gate openings 1121 individually correspond to the gate contact 101 of each die 10, the plurality of first source openings 1122 individually correspond to the source contact 102 of each die 10, and the plurality of first drain openings 1123 individually correspond to the drain contact 103 of each die 10.

[0122] Please see Figure 10CIn some embodiments, the semiconductor device 1 further includes a first gate metal layer 21, a plurality of first source metal layers 22, and a plurality of first drain metal layers 23. The first gate metal layer 21 is formed on a first protective layer 112. The first gate metal layer 21 is electrically connected to a plurality of gate contacts 101 via a plurality of first gate openings 1121 in the first protective layer 111. The plurality of first source metal layers 22 are formed on the first protective layer 112. Each first source metal layer 22 is electrically connected to a plurality of source contacts 102 located in the same column via a plurality of first source openings 1122 in the first protective layer 112. The plurality of first drain metal layers 23 are formed on the first protective layer 112. Each first drain metal layer 23 is electrically connected to a plurality of drain contacts 103 located in the same column via a plurality of first drain openings 1123 in the first protective layer 112. In some embodiments, since the first gate metal layer 21 is used to electrically connect a plurality of gate contacts 101, each first source metal layer 22 is used to electrically connect a plurality of source contacts 102 located in the same column, and each first drain metal layer 23 is used to electrically connect a plurality of drain contacts 103 located in the same column, the first gate metal layer 21, the plurality of first source metal layers 22 and the plurality of first drain metal layers 23 do not contact each other to avoid the gate contacts 101, source contacts 102 and drain contacts 103 of the plurality of dies 10 being interconnected.

[0123] Please see Figure 10D In some embodiments, the semiconductor device 1 further includes a second protective layer 24. The second protective layer 24 is formed on a first gate metal layer 21, a plurality of first source metal layers 22, and a plurality of first drain metal layers 23. The second protective layer 24 includes a plurality of second gate openings 241, a plurality of second source openings 242, and a plurality of second drain openings 243. Each second gate opening 241 corresponds to a portion of the first gate metal layer 21. Each of the plurality of second source openings 242 individually corresponds to each of the first source metal layers 22. Each of the plurality of second drain openings 243 individually corresponds to each of the first drain metal layers 23.

[0124] Please see Figure 10EIn some embodiments, the semiconductor device 1 further includes a plurality of second gate metal layers 25, a plurality of second source metal layers 26, and a plurality of second drain metal layers 27. The plurality of second gate metal layers 25 are formed on the second protective layer 24. Each second gate metal layer 25 is formed on the first gate metal layer 21 via a second gate opening 241 of the second protective layer 24. The plurality of second source metal layers 26 are formed on the second protective layer 24. Each second source metal layer 26 is formed on each first source metal layer 22 via a second source opening 242 of the second protective layer 24. The plurality of second drain metal layers 27 are formed on the second protective layer 24. Each second drain metal layer 27 is formed on each first drain metal layer 23 via a second drain opening 243 of the second protective layer 24. In some embodiments, since the second gate metal layer 25 is formed on the first gate metal layer 21, each second source metal layer 26 is formed on each first source metal layer 22, and each second drain metal layer 27 is formed on each first drain metal layer 23, the plurality of second gate metal layers 25, the plurality of second source metal layers 26, and the plurality of second drain metal layers 27 do not contact each other to avoid the gate contacts 101, source contacts 102, and drain contacts 103 of the plurality of dies 10 being interconnected.

[0125] It is hereby specifically stated that... Figures 10A to 10E The semiconductor device 1 is viewed from a top-down angle. In some embodiments, when the semiconductor device 1 is viewed from a top-down angle, the gate contact 101, source contact 102 and drain contact 103 included in each die 10, the plurality of first gate openings 1121, the plurality of first source openings 1122 and the plurality of first drain openings 1123 of the first protective layer 112, the plurality of first source metal layers 22, the plurality of first drain metal layers 23, and the plurality of second gate openings 241, the plurality of second source openings 242 and the plurality of second drain openings 243 of the second protective layer 24 are covered by the plurality of second gate metal layers 25, the plurality of second source metal layers 26 and the plurality of second drain metal layers 27 and cannot be observed.

[0126] Figures 11A to 11C This is a flowchart of another embodiment of a method for manufacturing semiconductor device 1. Figures 11A to 11C The manufacturing method of the semiconductor device 1 shown is the same as Figures 6A to 6B and Figures 8A to 8D The manufacturing method of the semiconductor device 1 shown is similar. Please refer to [link / reference]. Figures 11A to 11CFirst, an insulating material is coated onto the gate contacts 101, source contacts 102, and drain contacts 103 on the active surfaces of the plurality of chips 10 (step S301). Next, the insulating material in areas other than those on the gate contacts 101, source contacts 102, and drain contacts 103 of the plurality of chips 10 is exposed to ultraviolet light using a first photomask (step S302). Next, the insulating material in the areas not exposed to ultraviolet light is dissolved using a first developer to form a plurality of first gate openings 1121, a plurality of first source openings 1122, and a plurality of first drain openings 1123 (step S303), wherein the insulating material not dissolved by the first developer, the plurality of first gate openings 1121, the plurality of first source openings 1122, and the plurality of first drain openings 1123 constitute a first protective layer 112. Next, the first protective layer 112 is heated to cure the insulating material of the first protective layer 112 (step S304). Next, residues or scum around the plurality of first gate openings 1121, the plurality of first source openings 1122, and the plurality of first drain openings 1123 are removed (step S305). In some embodiments, the insulating material is a photosensitive insulating material, and the pattern on the first photomask and the first developer need to be changed according to the photosensitivity (positive / negative) of the insulating material.

[0127] Then, a first seed UBM layer is sputtered onto the first protective layer 112 by bombarding a solid target with multiple ions (step S306). Next, a first photoresist is coated onto the first seed UBM layer (step S307). Next, the first photoresist in areas other than the second region is exposed to ultraviolet light through a second photomask (step S308). Next, the first photoresist in the second region that was not exposed to ultraviolet light is dissolved using a second developer (step S309). Next, residues or scum around the opening area after development with the second developer are removed (step S310). Next, a first metal layer, a second metal layer, and a third metal layer are sequentially disposed from bottom to top on the first seed UBM layer in the opening area after development with the second developer (step S311). In some embodiments, the pattern on the second photomask and the second developer need to be changed according to the photosensitivity (positive / negative) of the first photoresist.

[0128] Next, the remaining first photoresist is removed (step S312). Next, the exposed first seed UBM layer is removed (step S313), wherein the remaining first seed UBM layer, first metal layer, second metal layer, and third metal layer are a first gate metal layer 21, a plurality of first source metal layers 22, and a plurality of first drain metal layers 23. In some embodiments, the first gate metal layer 21, the plurality of first source metal layers 22, and the plurality of first drain metal layers 23 may be, but are not limited to, bumps. Therefore, in some embodiments, the method of setting the first gate metal layer 21, the plurality of first source metal layers 22, and the plurality of first drain metal layers 23 may be, but is not limited to, a bump process. Next, the surface of the third metal layer is acid-washed to remove metal contaminants from the surface of the third metal layer (step S314).

[0129] Then, an insulating material is coated onto the first gate metal layer 21, the plurality of first source metal layers 22, and the plurality of first drain metal layers 23 (step S315). Next, the insulating material in areas other than those on the first gate metal layer 21, the plurality of first source metal layers 22, and the plurality of first drain metal layers 23 is exposed to ultraviolet light using a third photomask (step S316). Next, the insulating material in the areas not exposed to ultraviolet light is dissolved using a third developer to form a plurality of second gate openings 241 on the first gate metal layer 21, a plurality of second source openings 242 on the plurality of first source metal layers 22, and a plurality of second drain openings 243 on the plurality of first drain metal layers 23 (step S317), wherein the insulating material of the first gate metal layer 21, the plurality of first source metal layers 22, and the plurality of first drain metal layers 23 that are not dissolved by the third developer, the plurality of second gate openings 241, the plurality of second source openings 242, and the plurality of second drain openings 243 constitute a second protective layer 24. Next, the second protective layer 24 is heated to cure the insulating material of the second protective layer 24 (step S318). Then, residues or scum around the plurality of second gate openings 241, the plurality of second source openings 242, and the plurality of second drain openings 243 are removed (step S319). In some embodiments, the insulating material is a photosensitive insulating material, and the pattern on the third photomask and the third developer need to be changed according to the photosensitivity (positive / negative) of the insulating material.

[0130] Then, a second seed UBM layer is sputtered onto the second protective layer by bombarding a solid target with multiple ions (step S320). Next, a second photoresist is coated onto the second seed UBM layer (step S321). Next, the second photoresist in areas other than the third region is exposed to ultraviolet light through a fourth photomask (step S322). Next, the second photoresist in the third region that was not exposed to ultraviolet light is dissolved using a fourth developer (step S323). Next, residues or scum around the opening area after development with the fourth developer are removed (step S324). Next, a fourth metal layer, a fifth metal layer, and a sixth metal layer are sequentially deposited from bottom to top on the second seed UBM layer in the opening area after development with the fourth developer (step S325). In some embodiments, the pattern on the fourth photomask and the fourth developer need to be changed according to the photosensitivity (positive / negative) of the second photoresist.

[0131] Next, the remaining second photoresist is removed (step S326). Then, the exposed second seed UBM layer is removed (step S327), wherein the remaining second seed UBM layer, fourth metal layer, fifth metal layer, and sixth metal layer are multiple second gate metal layers 25, multiple second source metal layers 26, and multiple second drain metal layers 27. In some embodiments, the fourth metal layer may be made of, but is not limited to, copper; the fifth metal layer may be made of, but is not limited to, nickel; and the sixth metal layer may be made of, but is not limited to, gold. In some embodiments, the function of the fifth and sixth metal layers may be, but is not limited to, rust prevention. In some embodiments, the multiple second gate metal layers 25, multiple second source metal layers 26, and multiple second drain metal layers 27 may be, but is not limited to, bumps. Therefore, in some embodiments, the method of setting multiple second gate metal layers 25, multiple second source metal layers 26, and multiple second drain metal layers 27 may be, but is not limited to, a bump process.

[0132] Next, the surface of the sixth metal layer is acid-washed to remove metal contaminants from the surface of the sixth metal layer (step S328). Finally, the semiconductor device 1 is automatically visually inspected using an observation instrument (step S329).

[0133] In some embodiments, multiple dies 10 can be disposed on the semiconductor device 1 through a die-to-wafer bonding integration process. That is, each die 10 can be bonded one after another through pick-and-place technology, thereby improving the yield of the semiconductor device 1, but this invention is not limited thereto.

[0134] In some embodiments, the die 10 may also be a diode chip, a gallium nitride (GaN) chip, a system-on-chip (SOC) chip, or an insulated-gate bipolar transistor (IGBT) chip, but this invention is not limited thereto.

[0135] In some embodiments, semiconductor device 1 simplifies its power electronics system by integrating multiple MOSFETs into a single package, thereby reducing its design complexity, design time, assembly time, labor costs, assembly errors, and overall area. Furthermore, the installation of semiconductor device 1 is very easy because it does not require complex wiring or soldering. In some embodiments, semiconductor device 1 incorporates protection mechanisms such as overcurrent protection, overtemperature protection, and short-circuit protection. Designers of semiconductor device 1 can utilize these protection mechanisms to enhance system reliability and durability, thereby reducing the risk of failure and associated repair or replacement costs.

[0136] In some embodiments, since semiconductor device 1 is a device integrating multiple MOSFETs, it has low on-resistance and high switching speed, thereby enabling minimal power loss and efficient power conversion. Furthermore, due to its low on-resistance, semiconductor device 1 has a faster switching speed, allowing the inductor current ripple to propagate within a shorter time interval, significantly reducing the impact of parasitic inductance. As mentioned earlier, compared to the prior art semiconductor device 2, semiconductor device 1 requires significantly fewer wires and has a much shorter total wire length, resulting in a significant reduction in both inductance and impedance. Reducing the impact of parasitic inductance improves the switching performance of semiconductor device 1 and reduces electromagnetic interference (EMI).

[0137] In some embodiments, the semiconductor device 1 is provided with a built-in heat sink to improve heat dissipation efficiency, but this invention is not limited thereto. In some embodiments, the semiconductor device 1 has better heat dissipation performance and greater power handling capacity due to the built-in heat sink.

[0138] In summary, the semiconductor device 1 of any embodiment significantly reduces the number of wires required and the total length of the wires, thereby significantly reducing the inductance and impedance of the semiconductor device 1, the impact of power supply ripple, and the size of the semiconductor device 1. The semiconductor device 1 of any embodiment simplifies its power electronics system by integrating multiple MOSFETs into a single package, thereby reducing its design complexity, design time, assembly time, labor costs, assembly errors, and overall area. Furthermore, the installation of the semiconductor device 1 of any embodiment is very easy because it does not require complex wiring or soldering. In addition, since the semiconductor device 1 of any embodiment is a device integrating multiple MOSFETs, it has low on-resistance and high switching speed, thereby enabling the semiconductor device 1 to achieve minimal power loss and efficient power conversion. Moreover, due to the low on-resistance of the semiconductor device 1 of any embodiment, it has a faster switching speed, allowing the inductor current ripple of the semiconductor device 1 to propagate within a shorter time interval, thus significantly reducing the impact of parasitic inductance on the semiconductor device 1. Reducing the influence of parasitic inductance can improve the switching performance of the semiconductor device 1 in any embodiment and reduce the electromagnetic interference experienced by the semiconductor device 1.

[0139] Although the technical content of this case has been disclosed above with reference to preferred embodiments, it is not intended to limit this case. Any modifications and refinements made by those skilled in the art without departing from the spirit of this case should be included within the scope of this case. Therefore, the scope of protection of this case shall be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a plurality of dies, the dies being arranged in a matrix, each of the dies comprising a gate contact, a source contact, and a drain contact, the drain contact being disposed on a back surface of the die; a passivation layer formed on active surfaces of the dies, the passivation layer comprising a plurality of gate openings and a plurality of source openings, the gate openings individually corresponding to the gate contacts of the dies, the source openings individually corresponding to the source contacts of the dies; a plurality of gate metal layers formed on the passivation layer and spaced apart from each other, each of the gate metal layers being electrically connected to the gate contacts in a same column of the dies via the gate openings of the passivation layer; a plurality of source metal layers formed on the passivation layer and spaced apart from each other, each of the source metal layers being electrically connected to the source contacts in a same column of the dies via the source openings of the passivation layer; and a drain metal layer formed on the back surfaces of the dies, the drain metal layer being electrically connected to the drain contacts.

2. The semiconductor device according to claim 1, wherein Further comprising a first wire and a second wire, the first wire being electrically connected to the gate metal layers, the second wire being electrically connected to the source metal layers.

3. The semiconductor device according to claim 2, wherein The gate metal layers and the source metal layers are staggered with each other.

4. The semiconductor device according to claim 3, wherein The gate metal layers and the source metal layers do not contact each other.

5. The semiconductor device according to claim 1, wherein The dies are Vertical MOSFET dies, Lateral MOSFET dies, diode dies, gallium nitride dies, SOC dies, or IGBT dies.

6. A method for manufacturing a semiconductor device, characterized by Comprising: coating an insulating material on a gate contact and a source contact of an active surface of a plurality of dies; performing UV exposure on the insulating material of regions other than a region of the gate contacts and the source contacts of the dies by a first mask; dissolving the insulating material of the region not exposed to UV by a first developer to form a plurality of first gate openings and a plurality of first source openings, wherein the insulating material not dissolved by the first developer, the first gate openings, and the first source openings are a first passivation layer; heating the first passivation layer to solidify the insulating material of the first passivation layer; descumming residues or scums around the first gate openings and the first source openings; sputtering a first seed UBM layer on the first passivation layer by using ions to impact a solid target; coating a first photoresist on the first seed UBM layer; performing UV exposure on the first photoresist of regions other than a second region by a second mask; dissolving the first photoresist of the second region not exposed to UV by a second developer; descumming residues or scums around the opening region developed by the second developer; sequentially disposing a first metal layer, a second metal layer, and a third metal layer on the first seed UBM layer of the opening region developed by the second developer from bottom to top; removing the remaining first photoresist; removing the exposed first seed UBM layer, wherein the remaining first seed UBM layer, the first metal layer, the second metal layer and the third metal layer are a plurality of first gate metal layers and a plurality of first source metal layers; performing acid cleaning on a surface of the third metal layer to remove metal contaminants on the surface of the third metal layer; grinding back surfaces of the dies; forming a drain contact on the back surface of each of the dies; applying a drain metal layer on the back surface of the dies, the drain metal layer electrically connecting the drain contacts; and performing automatic visual inspection on the semiconductor device.

7. The method for manufacturing a semiconductor device according to claim 6, wherein The insulating material is a photosensitive insulating material, the pattern on the first mask and the first developer need to be changed according to the photosensitivity (positive / negative) of the insulating material.

8. The method for manufacturing a semiconductor device according to claim 7, wherein The pattern on the second mask and the second developer need to be changed according to the photosensitivity (positive / negative) of the first photoresist.

9. A semiconductor device, characterized by comprising: Comprising: a plurality of dies arranged in a matrix, each of the dies comprising a gate contact, a source contact and a drain contact, the drain contact disposed on a back surface of the die; a first protective layer formed on active surfaces of the dies, comprising a plurality of first gate openings and a plurality of first source openings, the first gate openings individually corresponding to the gate contacts of the dies, the first source openings individually corresponding to the source contacts of the dies; a first gate metal layer formed on the first protective layer, the first gate metal layer electrically connecting the gate contacts through the first gate openings of the first protective layer; a plurality of first source metal layers, the first source metal layers individually formed on the source contacts through the first source openings of the first protective layer; a second protective layer formed on the first gate metal layer and the first source metal layers, comprising a second gate opening and a plurality of second source openings, the second gate opening corresponding to one column of the first gate metal layers, the second source openings individually corresponding to the first source metal layers; a second gate metal layer formed on the second protective layer, the second gate metal layer formed on the first gate metal layer through the second gate opening of the second protective layer; a second source metal layer formed on the second protective layer, the second source metal layer electrically connecting the first source metal layers through the second source openings of the second protective layer; and a drain metal layer formed on the back surfaces of the dies, the drain metal layer electrically connecting the drain contacts.

10. The semiconductor device according to claim 9, wherein The first gate metal layer and the first source metal layers do not contact each other.

11. The semiconductor device according to claim 10, wherein The second gate metal layer and the second source metal layer do not contact each other.

12. The semiconductor device according to claim 9, wherein The dies are Vertical MOSFET dies, Lateral MOSFET dies, diode dies, gallium nitride dies, SOC dies or IGBT dies.

13. A method of manufacturing a semiconductor device, characterized by Comprising: applying an insulating material on a gate contact and a source contact of an active surface of a plurality of dies; exposing the insulating material on an area other than the area of the gate contact and the source contact of the dies to ultraviolet light through a first mask; dissolving the insulating material of the second region not exposed to the ultraviolet light to form a second gate opening on the first gate metal layer and second source openings on the first source metal layers, wherein the insulating material of the first gate metal layer and the first source metal layers not dissolved by the third developer, the second gate opening and the second source openings are a second protection layer; heating the second protection layer to solidify the insulating material of the second protection layer; removing residues or scums around the second gate opening and the second source openings; sputtering a second seed UBM layer on the second protection layer by impinging the solid target with ions; coating a second photoresist on the second seed UBM layer; exposing the second photoresist of regions other than a third region to ultraviolet light through a fourth mask; dissolving the second photoresist of the third region not exposed to the ultraviolet light by a fourth developer; removing residues or scums around the opening region developed by the fourth developer; sequentially disposing a fourth metal layer, a fifth metal layer and a sixth metal layer on the second seed UBM layer of the opening region developed by the fourth developer from bottom to top; removing the remaining second photoresist; removing the exposed second seed UBM layer, wherein the remaining second seed UBM layer, the fourth metal layer, the fifth metal layer and the sixth metal layer are a first gate metal layer and first source metal layers; ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ removing the exposed second seed UBM layer, wherein the remaining second seed UBM layer, the fourth metal layer, the fifth metal layer and the sixth metal layer are a second gate metal layer and a second source metal layer; acid washing a surface of the sixth metal layer to remove metal contaminants on the surface of the sixth metal layer; polishing back surfaces of the dies; forming a drain contact on the back surface of each of the dies; applying a drain metal layer on the back surface of the dies, the drain metal layer electrically connecting the drain contacts; and automatically visually inspecting the semiconductor device.

14. The method for manufacturing a semiconductor device according to claim 13, wherein The insulating material is a photosensitive insulating material, the pattern on the first mask and the first developer need to be changed according to the photosensitivity (positive / negative) of the insulating material.

15. The method for manufacturing a semiconductor device according to claim 14, wherein The pattern on the second mask and the second developer need to be changed according to the photosensitivity (positive / negative) of the first photoresist.

16. The method for manufacturing a semiconductor device according to claim 15, wherein The pattern on the third mask and the third developer need to be changed according to the photosensitivity (positive / negative) of the insulating material.

17. The method for manufacturing a semiconductor device according to claim 16, wherein The pattern on the fourth mask and the fourth developer need to be changed according to the photosensitivity (positive / negative) of the second photoresist.

18. A semiconductor device, characterized by comprising: Comprise: a plurality of dies arranged in a matrix, each of the dies comprising a gate contact, a source contact and a drain contact; a first protective layer formed on active surfaces of the dies, comprising a plurality of first gate openings, a plurality of first source openings and a plurality of first drain openings, the first gate openings individually corresponding to the gate contacts of the dies, the first source openings individually corresponding to the source contacts of the dies, and the first drain openings individually corresponding to the drain contacts of the dies; a first gate metal layer formed on the first protective layer, the first gate metal layer electrically connecting the gate contacts through the first gate openings of the first protective layer; a plurality of first source metal layers formed on the first protective layer, each of the first source metal layers electrically connecting the source contacts in the same column through the first source openings of the first protective layer; a plurality of first drain metal layers formed on the first protective layer, each of the first drain metal layers electrically connecting the drain contacts in the same column through the first drain openings of the first protective layer; a second protective layer formed on the first gate metal layer, the first source metal layers and the first drain metal layers, comprising a plurality of second gate openings, a plurality of second source openings and a plurality of second drain openings, each of the second gate openings corresponding to a portion of the first gate metal layer, the second source openings individually corresponding to each of the first source metal layers, and the second drain openings individually corresponding to each of the first drain metal layers; a plurality of second gate metal layers formed on the second protective layer, each of the second gate metal layers formed on the first gate metal layer through each of the second gate openings of the second protective layer; a plurality of second source metal layers formed on the second protective layer, each of the second source metal layers formed on each of the first source metal layers through each of the second source openings of the second protective layer; and ​ a plurality of second drain metal layers formed on the second protective layer, each of the second drain metal layers being formed on each of the first drain metal layers via each of the second drain openings of the second protective layer.

19. The semiconductor device according to claim 18, wherein The first gate metal layer, the first source metal layers, and the first drain metal layers do not contact each other.

20. The semiconductor device according to claim 19, wherein The second gate metal layers, the second source metal layers, and the second drain metal layers do not contact each other.

21. The semiconductor device according to claim 18, wherein The dies are Vertical MOSFET dies, Lateral MOSFET dies, diode dies, gallium nitride dies, SOC dies, or IGBT dies.

22. A method of manufacturing a semiconductor device, characterized by comprising: coating an insulating material on gate contacts, source contacts, and drain contacts of active surfaces of a plurality of dies; exposing the insulating material on regions other than a first region of the gate contacts, the source contacts, and the drain contacts of the dies to ultraviolet light through a first mask; dissolving the insulating material of the regions not exposed to the ultraviolet light using a first developer to form a first protective layer of first gate openings, first source openings, and first drain openings, wherein the insulating material not dissolved by the first developer, the first gate openings, the first source openings, and the first drain openings are the first protective layer; heating the first protective layer to solidify the insulating material of the first protective layer; removing residues or scums around the first gate openings, the first source openings, and the first drain openings; sputtering a first seed UBM layer on the first protective layer using ions impinging on a solid target; coating a first photoresist on the first seed UBM layer; exposing the first photoresist on regions other than a second region to ultraviolet light through a second mask; dissolving the first photoresist of the second region not exposed to the ultraviolet light using a second developer; removing residues or scums around the opening region developed by the second developer; sequentially disposing a first metal layer, a second metal layer, and a third metal layer on the first seed UBM layer of the opening region developed by the second developer from bottom to top; removing the remaining first photoresist; removing the exposed first seed UBM layer, wherein the remaining first seed UBM layer, the first metal layer, the second metal layer, and the third metal layer are a first gate metal layer, first source metal layers, and first drain metal layers; acid washing a surface of the third metal layer to remove metal contaminants on the surface of the third metal layer; coating the insulating material on the first gate metal layer, the first source metal layers, and the first drain metal layers; exposing the insulating material on regions other than a region on the first gate metal layer, the first source metal layers, and the first drain metal layers to ultraviolet light through a third mask; dissolving the insulating material of the first gate metal layer, the first source metal layers and the first drain metal layers in a third developer to form a second protective layer of the insulating material of the first gate metal layer, the first source metal layers and the first drain metal layers not dissolved by the third developer, second gate openings on the first gate metal layer, second source openings on the first source metal layers and second drain openings on the first drain metal layers; heating the second protective layer to solidify the insulating material of the second protective layer; removing residues or scums around the second gate openings, the second source openings and the second drain openings; sputtering a second seed UBM layer on the second protective layer by using the ions to impinge on the solid target; applying a second photoresist on the second seed UBM layer; exposing the second photoresist of the regions other than a third region to ultraviolet light through a fourth mask; dissolving the second photoresist of the third region not exposed to ultraviolet light by a fourth developer; removing residues or scums around the opening region developed by the fourth developer; sequentially disposing a fourth metal layer, a fifth metal layer and a sixth metal layer on the second seed UBM layer of the opening region developed by the fourth developer from bottom to top; removing the remaining second photoresist; removing the exposed second seed UBM layer, wherein the remaining second seed UBM layer, the fourth metal layer, the fifth metal layer and the sixth metal layer are second gate metal layers, second source metal layers and second drain metal layers; acid washing a surface of the sixth metal layer to remove metal contaminants on the surface of the sixth metal layer; and automatically visually inspecting the semiconductor device. The insulating material is a photosensitive insulating material, the pattern on the first mask and the first developer need to be changed according to the photosensitivity (positive / negative) of the insulating material.

23. The method for manufacturing a semiconductor device according to claim 22, wherein The pattern on the second mask and the second developer need to be changed according to the photosensitivity (positive / negative) of the first photoresist.

24. The method for manufacturing a semiconductor device according to claim 23, wherein The pattern on the third mask and the third developer need to be changed according to the photosensitivity (positive / negative) of the insulating material.

25. The method for manufacturing a semiconductor device according to claim 24, wherein The pattern on the fourth mask and the fourth developer need to be changed according to the photosensitivity (positive / negative) of the second photoresist.

26. The method for manufacturing a semiconductor device according to claim 25, wherein ​

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