Light-emitting display device

Abstract

The light emitting display device includes: a substrate including a display area in which sub-pixels are arranged along row lines and column lines; a light emitting diode in the sub-pixel and including an anode electrode, a light emitting layer on the anode electrode, and a cathode electrode on the light emitting layer; a test transistor in the row line and including a source electrode connected to the anode electrode of one of the adjacent sub-pixels in the row line and a drain electrode connected to the cathode electrode of the other of the adjacent sub-pixels in the row line; and a test gate line connected to the gate electrode of the test transistor, in which the cathode electrode is in an electrically floating state when the test transistor is turned on and a current path is formed in the row line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0118395, filed in Korea on September 2, 2024, the entire contents of which are incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] This invention relates to a light-emitting display device. Background Technology

[0004] Recently, flat panel display devices with excellent characteristics such as thinness, light weight and low power consumption have been widely developed and applied in various fields.

[0005] In flat panel display devices, a light-emitting display device equipped with a light-emitting element such as a light-emitting diode is a display device that emits light when charge is injected into the light-emitting layer formed between the anode electrode and the cathode electrode and electrons and holes pair up, and then turns off.

[0006] When defects exist in a light-emitting display device, dark spots may appear, and the most likely cause of such dark spots is expected to be a short circuit between the anode and cathode electrodes, i.e., an AC short circuit. However, in reality, it is difficult to confirm whether the dark spot defect is caused by an AC short circuit, and therefore difficult to improve the dark spot defect. Summary of the Invention

[0007] The advantage of this invention is that it provides a light-emitting display device that can improve the detection rate of dark spot defects caused by AC short circuits.

[0008] Additional features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practice of the invention. These and other advantages of the invention will be realized and obtained by means of the structures particularly pointed out in the written description and its claims, as well as in the accompanying drawings.

[0009] To achieve these and other advantages, and for the purposes of the invention, as embodied and broadly described herein, a light-emitting display device includes: a substrate comprising a display area in which sub-pixels are arranged along row lines and column lines; a light-emitting diode in the sub-pixels and including an anode electrode, a light-emitting layer on the anode electrode, and a cathode electrode on the light-emitting layer; a test transistor in the row lines and including a source electrode connected to the anode electrode of one of the adjacent sub-pixels in the row lines and a drain electrode connected to the cathode electrode of the other of the adjacent sub-pixels in the row lines; and a test gate line connected to the gate electrode of the test transistor, wherein the cathode electrode is electrically floating when the test transistor is turned on and forms a current path in the row lines.

[0010] On the other hand, the light-emitting display device includes: a substrate including a display area in which sub-pixels are arranged along row lines and column lines; light-emitting diodes in the sub-pixels; and a test transistor in the row line and connected between the anode electrode of the light-emitting diode of one of the adjacent sub-pixels in the row line and the cathode electrode of the light-emitting diode of the other adjacent sub-pixel in the row line, wherein the cathode electrode is in an electrically floating state when the test transistor is turned on and the light-emitting diodes of the row line are electrically connected in series.

[0011] It should be understood that both the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0012] The accompanying drawings, included to provide a further understanding of this disclosure and incorporated into and forming part of this specification, illustrate embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings:

[0013] Figure 1 This is a schematic view illustrating a light-emitting display device according to an embodiment of the present invention;

[0014] Figure 2 This is a schematic view illustrating the circuit structure of a sub-pixel of a light-emitting display device according to an embodiment of the present invention;

[0015] Figure 3 This is a view showing the driving process during the testing of a light-emitting display device according to an embodiment of the present invention;

[0016] Figure 4 This is a view showing the light emission state during a test when a dark spot defect caused by an AC short circuit exists in a light-emitting display device according to an embodiment of the present invention;

[0017] Figure 5 This is a view showing the light emission state during a test when a dark spot defect, other than an AC short circuit, exists in a light-emitting display device according to an embodiment of the present invention.

[0018] Figure 6 This is a schematic plan view illustrating a sub-pixel of a light-emitting display device according to an embodiment of the present invention;

[0019] Figure 7 It is along Figure 6 A cross-sectional view taken from line VII-VII'; and

[0020] Figure 8 It is along Figure 6The cross-sectional view taken from line VIII-VIII'. Detailed Implementation

[0021] The advantages and features of the present invention, as well as the methods of implementing it, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only these embodiments enable the invention to be complete. The present invention is provided to fully inform those skilled in the art of this disclosure of its scope, and the invention can be defined by the scope of the claims.

[0022] The shapes, dimensions, proportions, angles, numbers, etc., disclosed in the accompanying drawings used to illustrate embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Throughout the specification, the same reference numerals refer to the same parts.

[0023] Furthermore, in describing this invention, if it is determined that a detailed description of the relevant known art unnecessarily obscures the subject matter of the invention, its detailed description may be omitted. When terms such as "comprising," "including," "having," and "consisting of" are used in this invention, other parts may be added unless "only" is used. When components are referred to in the singular, the plural cases are also included unless a specific statement is described.

[0024] When describing a component, even if there is no separate explicit description, it is stated that a margin range is included.

[0025] When describing positional relationships, for example, when the positional relationship between two parts is described as "on," "above," "above," "below," "beside," "below," etc., one or more other parts may be located between such two parts, unless "exactly" or "directly" is used.

[0026] When describing time relationships, such as when time priorities are described as "after", "next", "before", etc., discontinuous cases can be included unless "directly" or "immediately following" is used.

[0027] When describing the components of the present invention, terms such as first and second may be used. These terms are used only to distinguish the components from other components, and the nature, order, sequence, or number of the components are not limited by these terms.

[0028] The corresponding features of the various embodiments of the present invention can be partially or wholly connected or combined with each other, and can be technically interlocked and driven in various ways. Furthermore, the various embodiments can be implemented independently of each other or together in a related relationship.

[0029] In the following description, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Furthermore, in the following embodiments, the same and similar reference numerals are assigned to the same and similar parts, and their detailed descriptions may be omitted.

[0030] Figure 1 This is a schematic view illustrating a light-emitting display device according to an embodiment of the present invention. Figure 2 This is a schematic view illustrating the circuit structure of a sub-pixel of a light-emitting display device according to an embodiment of the present invention.

[0031] Before going into detail, the light-emitting display device 10 according to an embodiment of the present invention may include all types of display devices for displaying images, the display device including a light-emitting diode OD as a self-emissive element.

[0032] In this embodiment, for ease of explanation, an organic light-emitting display device is used as an example of the light-emitting display device 10.

[0033] Reference Figure 1 and Figure 2 In the light-emitting display device 10 (or its light-emitting display panel) of this embodiment, a display area AA for displaying images and a non-display area NA arranged around the display area AA can be defined.

[0034] In the display area AA, multiple sub-pixels SP can be formed on the substrate 101, arranged along multiple row lines (or horizontal lines) and multiple column lines (or vertical lines).

[0035] Additionally, on substrate 101, a plurality of gate lines GL extending along the row direction (or horizontal direction or a first direction) and a plurality of data lines DL extending along the column direction (or vertical direction or a second direction) can be formed. Furthermore, on substrate 101, a power line PL that transmits a high-potential voltage (or a first driving voltage) VDD to the sub-pixel SP can be formed, and a reference line RL can be formed. The reference line RL transmits a sensing voltage for compensating the characteristics of the driving transistor Td (e.g., threshold voltage and / or mobility compensation) and also provides a reference voltage to the sub-pixel SP.

[0036] Furthermore, in this embodiment, a plurality of test gate lines TGL extending along the row direction can be formed on the substrate 101. For example, the test gate lines TGL can extend parallel to the gate line GL in each row.

[0037] As described below, the test gate line TGL can be used to detect the anode electrode within the sub-pixel SP ( Figure 6 The dark spot defect caused by the short circuit between the AE and the cathode electrode CE (i.e., AC short circuit) is driven during the testing process.

[0038] During normal operation for displaying images, multiple gate lines GL can be scanned sequentially in rows and each line is given a corresponding gate signal.

[0039] Simultaneously, during the testing process for detecting dark spot defects, multiple test gate lines TGL can be sequentially scanned on a row-line basis, and corresponding test gate signals can be applied to them. Furthermore, during the testing process, sequential scanning operations can be performed on multiple gate lines GL.

[0040] Multiple subpixels SP may include subpixels SP of different colors that constitute a pixel, which is a unit for displaying a color image. In this regard, multiple subpixels SP may include subpixels SP that display a first color, a second color, and a third color respectively, for example, subpixels SP of red, green, and blue, but are not limited thereto.

[0041] Each sub-pixel SP may include a light-emitting diode OD, a plurality of transistors for driving the light-emitting diode OD, and at least one capacitor.

[0042] Meanwhile, in this embodiment, for ease of explanation, as shown in the example Figure 2 The sub-pixel SP shown is configured with a 3T1C structure consisting of three transistors T1, T2, and Td, and a capacitor Cst, as an example.

[0043] Reference Figure 2 Describe the subpixel SP. Also, for ease of explanation, Figure 2 The diagram illustrates sub-pixels SP arranged along a row line (or the nth row line). Additionally, as an example, it shows the case where two adjacent sub-pixels SP in a row line are jointly connected to a reference line RL arranged between them. Furthermore, as an example, it shows the case where two adjacent sub-pixels SP in a row line are jointly connected to an electric field line PL arranged between them.

[0044] Additionally, in the following description, the terms source electrode and drain electrode of a transistor are used to distinguish the two electrodes connected to the semiconductor layer, and these terms may be used interchangeably in some cases.

[0045] The sub-pixel SP may include a first transistor T1 and a second transistor T2 as switching transistors, a driving transistor Td, a storage capacitor Cst, and a light-emitting diode OD. The first transistor T1 may be a data supply transistor, and the second transistor T2 may be a sensing transistor.

[0046] The first transistor T1, the second transistor T2, the driving transistor Td, and the storage capacitor Cst can constitute a pixel driving circuit for driving the light-emitting diode OD in image display operation. In other words, the first transistor T1, the second transistor T2, the driving transistor Td, and the storage capacitor Cst can form a pixel driving circuit for performing normal driving to display an image through the light-emitting display device 10.

[0047] Furthermore, in this embodiment, a test transistor Tt can be formed, which is a switching transistor connected between adjacent sub-pixels SP in the row line.

[0048] The test transistor Tt can be operated and used in the testing process to detect dark spot defects caused by AC short circuits.

[0049] Additionally, after the test process is performed, the test transistor Tt can be essentially turned off (or disabled) and may not function.

[0050] Such a test transistor Tt can be placed, for example, in one of two adjacent sub-pixels SP. In this embodiment, for ease of explanation, an example is given in which the test transistor Tt is placed in the right sub-pixel SP of the two sub-pixels SP connected to the test transistor Tt. In this case, as... Figure 2 As shown, the test transistor Tt can be placed in each sub-pixel SP of the remaining column lines except for the first column line on the left.

[0051] As another example, the test transistor Tt can be placed in the left sub-pixel SP of the two sub-pixels SP connected to it.

[0052] Since the test transistor Tt is positioned as described above, the sub-pixels SP in each row line can be electrically connected in series via the test transistor Tt connected between them. More specifically, the light-emitting diodes OD of the sub-pixels SP in the row line can be electrically connected in series via the test transistor Tt.

[0053] Therefore, by testing the current path of the sub-pixel SP in the row line formed by the transistor Tt, dark spot defects caused by AC short circuits can be effectively detected. This is described in more detail below.

[0054] Regarding the electrical connections of the components placed in the sub-pixel SP, the first transistor T1 can be connected to the corresponding gate line GL and data line DL. In this respect, the drain electrode (or source electrode) of the first transistor T1 can be connected to the data line DL, and the gate electrode of the first transistor T1 can be connected to the gate line GL.

[0055] The driving transistor Td may have a gate electrode connected to the source electrode of the first transistor T1, a drain electrode (or source electrode) connected to the power line PL to receive a high potential voltage VDD, and a source electrode (or drain electrode) connected to the anode electrode of the light-emitting diode OD.

[0056] The second transistor T2 can be connected to the corresponding gate line GL and reference line RL. In this respect, the drain electrode (or source electrode) of the second transistor T2 can be connected to the reference line RL, the gate electrode of the second transistor T2 can be connected to the gate line GL, and the source electrode (or drain electrode) of the second transistor T2 can be connected to node N between the driving transistor Td and the light-emitting diode OD. In other words, the source electrode of the second transistor T2 can be connected to the source electrode of the driving transistor Td and the anode electrode of the light-emitting diode OD.

[0057] Therefore, in this embodiment, the case where the second transistor T2 and the first transistor T1 in the sub-pixel SP are connected to the same gate line GL and receive the same gate signal is taken as an example. As another example, the second transistor T2 can be configured to be connected to a different gate line GL than the gate line GL connected to the first transistor T1.

[0058] The cathode electrode CE of a light-emitting diode (LED) OD can be applied with a low-potential voltage (or a second driving voltage) VSS. The low-potential voltage VSS is a voltage with a lower potential than the high-potential voltage VDD and may include ground voltage.

[0059] At the same time, refer to Figure 1 The cathode electrode CE can be formed over the entire display area AA of the light-emitting display device 10. In other words, the cathode electrode CE can be integrally formed corresponding to all sub-pixels SP within the display area AA.

[0060] Regarding the cathode electrode CE, a low potential voltage VSS can be applied to display an image during normal operation of the light-emitting display device 10. During testing, when driving the test transistor Tt to detect dark spot defects, the cathode electrode CE can be in a floating state without actually applying a low potential voltage VSS in order to form a current path along the row lines.

[0061] In this regard, for example, the cathode electrode CE can be connected to a transmission line TL arranged in the non-display area NA, and the transmission line TL can be formed in a manner that surrounds the display area AA along its periphery. In this case, when a low potential voltage VSS is supplied to the transmission line TL from an external power circuit, the low potential voltage VSS can be applied to the cathode electrode CE through the transmission line TL, so that the low potential voltage VSS can be supplied uniformly (or equally) to the sub-pixels SP within the display area AA.

[0062] Simultaneously, when the low-potential voltage VSS output from the power circuit is turned off, the transmission line TL can become a floating state without applied voltage, allowing the cathode electrode CE within the display area AA to also become floating. In other words, under these conditions, the cathode electrode CE of the light-emitting diode OD of the sub-pixel SP within the display area AA can become floating.

[0063] The storage capacitor Cst can be connected between the gate electrode and the source electrode of the driving transistor Td.

[0064] With the above configuration, during operation in the display mode for displaying images, when a gate signal is applied via gate line GL, the first transistor T1 can be turned on and a data signal can be input to the sub-pixel SP, and the data signal can be applied to the gate electrode of the driving transistor Td. At this time, the second transistor T2 can be turned on and a reference voltage can be applied to the source electrode of the driving transistor Td. Therefore, the data signal and the reference voltage can be applied to both electrodes of the storage capacitor Cst, so that the data signal can be stored in the storage capacitor Cst.

[0065] Then, when the gate signal is not applied to the gate line GL and is in the off state, the first transistor T1 and the second transistor T2 can be turned off, the driving transistor Td can be turned on, and the emission current (or driving current) corresponding to the applied data signal can flow to the light-emitting diode OD through the driving transistor Td. Therefore, light corresponding to the emission current can be generated and output from the light-emitting diode OD.

[0066] Simultaneously, during operation in compensation mode for compensating the driving transistor Td, a sensed data signal can be applied to the sub-pixel SP, and a sensed voltage can be provided to the reference line RL via the second transistor T2. Based on this sensed voltage, the data signal used for image display can be compensated, and the compensated data signal can be applied to the sub-pixel SP to compensate the driving transistor Td.

[0067] The test transistor Tt used to detect AC short-circuit defects in sub-pixels SP is described in detail below.

[0068] The test transistor Tt can be configured to be connected between the cathode electrode CE of one of the adjacent sub-pixels SP and the anode electrode of another of the adjacent sub-pixels SP.

[0069] Reference Figure 2For example, the test transistor Tt can be connected between the cathode electrode CE of the left sub-pixel SP and the anode electrode (or node N) of the right sub-pixel SP. In other words, the drain electrode of the test transistor Tt can be connected to the cathode electrode CE of the left sub-pixel SP, and the source electrode of the test transistor Tt can be connected to the anode electrode of the right sub-pixel SP.

[0070] In addition, the gate electrode of the test transistor Tt can be connected to the test gate line TGL arranged in the corresponding row line.

[0071] The test gate signal applied to the test gate line TGL can be applied, for example, to the emitter portion (or emitter period) of the corresponding row line.

[0072] Simultaneously, when the test transistor Tt is connected as described above, the voltage line VSL can be connected to the cathode electrode CE of the sub-pixel SP located in the last column line of each row (e.g., the outermost column line on the right). A low-potential voltage VSS can be applied to this voltage line VSL. More specifically, the voltage line VSL can be connected to the cathode electrode CE corresponding to the sub-pixel SP located in the outermost column line on the right (or a portion of the cathode electrode CE located in the non-display area NA to the right of that sub-pixel SP), and a low-potential voltage VSS can be applied to the voltage line VSL during the test process. After the test process, the voltage line VSL can be in a floating state, or a low-potential voltage VSS can be applied.

[0073] With the test transistor Tt arranged as described above, as mentioned above, the direction of the current path through the test transistor Tt can be set from the cathode electrode CE connected to one side to the anode electrode connected to the other side.

[0074] To effectively achieve this current path direction, as mentioned above, the cathode electrode CE of the sub-pixel SP located to the right of the outermost column line, which is the last column line in the current path direction, can be configured to be connected to the voltage line VSL to which a low potential voltage VSS is applied.

[0075] In other words, the cathode electrode CE of the sub-pixel SP in the outermost column on the right can have a relatively low potential, so that a current path through the test transistor Tt can be formed from left to right in the row line.

[0076] Therefore, during the test, a current path through the test transistor Tt can be formed in the row line from one side to the other, which makes it possible to effectively detect whether the dark spot defects appearing in the sub-pixel SP are caused by AC short circuit.

[0077] Further reference Figure 3The driving of the test transistor Tt is described in more detail during the test process. Figure 3 This is a view showing the driving process during the testing of a light-emitting display device according to an embodiment of the present invention.

[0078] At the same time, Figure 3 For ease of explanation, an example is given in which the LED OD of the sub-pixel SP located in the first left column of the sub-pixels SP arranged along the row lines has an AC short-circuit defect, while the LED OD of the remaining sub-pixels SP are in a normal state.

[0079] Reference Figure 3 When the test transistor Tt is driven during testing, as mentioned above, the transmission line TL may not be supplied with a low potential voltage VSS and may be in a floating state. Therefore, the cathode electrode CE connected to the transmission line TL, i.e., the cathode electrode CE corresponding to the sub-pixel SP within the display area AA, can be essentially in an electrically floating state.

[0080] Additionally, as mentioned above, a low potential voltage VSS can be provided to the voltage line VSL of the cathode electrode CE connected to the rightmost sub-pixel SP of each row line, and thus, a state in which the low potential voltage VSS is electrically applied to the cathode electrode CE of the rightmost sub-pixel SP can be achieved.

[0081] In this state, for example, row lines can be scanned, and a gate signal Vg can be applied to gate line GL, and a test gate signal Vtg can be applied to test gate line TGL. Simultaneously with applying the gate signal Vg, a data signal DI (or test data signal) for transmission can be applied to the data line DL of the sub-pixel SP connected to the first column line on the left side of the row line (i.e., the first column line in the direction of the current path).

[0082] At this time, unlike normal operation, the data signal DI may not be applied to the data lines DL of the columns other than the first column line, and such data lines may be in a cut-off state. However, this disclosure is not limited thereto, as follows regarding... Figure 4 and Figure 5 The described method allows for the application of a data signal DI to the data line DL of a specific column line where a sub-pixel SP identified as having a dark spot defect during normal operation is located, and the output of the data signal DI to the data lines DL of the remaining sub-pixels SP that normally emit light during normal operation can be turned off. During normal operation, the test transistor Tt is turned off and the light-emitting display device 10 is normally driven.

[0083] Here, the application portion (or scan portion, pulse portion, or on-level portion) of the test gate signal Vtg can be configured to overlap with the emitter portion of the corresponding row line.

[0084] For example, a test gate signal Vtg can be generated after the gate signal Vg is applied, so that the application portion of the test gate signal Vtg can be set within the emission portion of the corresponding row line.

[0085] In the above scenario, the first transistor T1 of the first sub-pixel SP on the left can be turned on by the gate signal Vg, and the data signal DI transmitted via the data line DL can be supplied to the driving transistor Td. Therefore, the emission current Id corresponding to the data signal DI can be generated in the emission section and flow to the light-emitting diode OD of the first sub-pixel SP.

[0086] Simultaneously, in the emitting section, the test transistor Tt arranged in the row line can be turned on by the test gate signal Vtg. Therefore, a state can be formed in which the light-emitting diodes OD of the sub-pixels SP of the row line are electrically connected in series from left to right by the test transistor Tt, which can be turned on. Based on this series connection state of the light-emitting diodes OD, a current path can be realized in the left-to-right direction.

[0087] At this time, the LED OD of the first sub-pixel SP is in an AC short-circuit state, and the emission current Id can pass through the AC short-circuited LED OD, and can also be supplied to the LED OD of the second sub-pixel SP through the conducting test transistor Tt connected to the AC short-circuited LED OD. Then, the emission current Id passing through the LED OD of the second sub-pixel SP can be supplied to the LED OD of the third sub-pixel SP through the conducting test transistor Tt. In this way, the emission current Id can flow from left to right along the current path.

[0088] Therefore, when the emission current Id flows from left to right along the current path, the first sub-pixel SP with the AC short-circuit defect is displayed as a dark spot DP because its light-emitting diode OD does not emit light, and the remaining sub-pixels SP can be displayed as bright spots BP because their light-emitting diode OD emits light normally.

[0089] The test procedure for detecting dark spot defects caused by AC short circuits is described in more detail below.

[0090] Figure 4 This is a view showing the light emission state during a test process in a light-emitting display device according to an embodiment of the present invention when a dark spot defect caused by an AC short circuit exists. Figure 5 This is a view showing the light emission state during a test process in a light-emitting display device according to an embodiment of the present invention when a dark spot defect caused by a defect other than an AC short circuit exists.

[0091] exist Figure 4 and Figure 5For ease of explanation, an example is shown where subpixels SP are arranged in a 4x5 matrix and a dark spot defect appears in subpixel SP at position (2,2).

[0092] Reference Figure 4 and Figure 5 as well as Figures 1 to 3 During testing, for example, the normal driving process of the light-emitting display device 10 can be performed while a low potential voltage VSS is applied to the cathode electrode CE.

[0093] During this normal driving process, the test gate signal Vtg is not applied to the test gate line TGL. Therefore, the test transistor Tt arranged in each row line becomes off, so that the light-emitting diode OD of the sub-pixel SP in each row line is not electrically connected (i.e., electrically disconnected) and no current path is formed through it.

[0094] During this normal driving process, gate lines GL can be scanned sequentially, and gate signals Vg can be applied to each row line. Data signals DI can be simultaneously output to all data lines DL at the timing of applying gate signal Vg. Therefore, an emission current can be generated in the sub-pixel SP through the applied data signal DI, and this emission current can be applied to the light-emitting diode OD.

[0095] At this time, the position at (2,2) has the following characteristics: Figure 4 The AC short-circuit defect shown or as Figure 5 The sub-pixel SP shown, which has defects other than AC short circuit, does not emit light due to the defects and is displayed as a dark spot DP.

[0096] In addition, the sub-pixels SP at positions other than (2,2) are not defective and are in a normal state, so that these remaining sub-pixels SP can emit light normally in response to the corresponding input data signal DI and can be displayed as bright spots BP.

[0097] Through the above normal driving process, it can be confirmed that the sub-pixel SP at position (2,2) has a dark spot defect.

[0098] When the location of a sub-pixel SP with a dark spot defect is identified, in order to check whether the dark spot defect at such a location is caused by an AC short circuit, a process can be performed to drive the light-emitting display device 10 by setting the cathode electrode CE to a floating state. This driving can be used to detect the cause of the dark spot defect and can be referred to as a cathode floating driving process.

[0099] During this cathode floating drive process, gate lines GL can be scanned sequentially, and gate signals Vg can be applied to each row line. Additionally, during the scanning portion of the gate signal Vg for each row line, data signals DI can be output to the data line DL of the second column line, which is the column line of the sub-pixel SP identified as the dark spot DP. At this time, the output of data signals to the data lines DL of the column lines where the remaining sub-pixels SP are located (those emitting normal light) can be turned off.

[0100] Additionally, the test gate lines TGL can be scanned sequentially, and the test gate signal Vtg can be applied to each row line. The scanned portion of the test gate signal Vtg can overlap with the emitter portion of the corresponding row line.

[0101] Since the test gate signal Vtg is applied in this way, the test transistor Tt arranged in the corresponding row line can be turned on, so that the light-emitting diodes OD arranged in the row line can be connected in series and a current path can be formed from left to right.

[0102] In this state where a current path has been formed, when... Figure 4 When an AC short-circuit defect exists in the sub-pixel SP at position (2,2), the emission current generated by the data signal DI applied to the sub-pixel SP through the corresponding data line DL can pass through the AC short-circuited light-emitting diode OD, and then flow along the current path formed in the corresponding row line to the normal light-emitting diode OD located on the right.

[0103] Therefore, in the second row where the dark spot DP exists, the sub-pixel SP with AC short-circuit defect in the second column does not emit light and is displayed as the dark spot DP, while the sub-pixel SP in the column on the right emits light normally and can be displayed as the bright spot BP.

[0104] Meanwhile, in the remaining row lines where there are no dark spots (DP), the LEDs (OD) emit light normally through the emission current, so the sub-pixels (SP) in the second column can be displayed as bright spots (BP). Furthermore, this emission current can flow along the current path formed in the corresponding row line to the LEDs (OD) of the sub-pixels (SP) located on the right, allowing these LEDs (OD) to emit light normally and be displayed as bright spots (BP).

[0105] As described above, even when the cathode is floating, sub-pixels SP with AC short-circuit defects are identified as dark spots DP, and even when the cathode is floating, other sub-pixels SP in the same row can be identified as bright spots BP.

[0106] Therefore, during the test, by checking the positions of the dark spot DP and the bright spot BP during normal drive and cathode floating drive, if the positions of the dark spot DP and the bright spot BP are the same during normal drive and cathode floating drive, it can be detected that the dark spot DP is caused by AC short circuit.

[0107] At the same time, in such Figure 5 In the case of a defect other than an AC short circuit in the sub-pixel SP at position (2,2) shown, when the cathode floating drive is performed, even if the data signal DI is applied to the sub-pixel SP, no emission current may be generated, or the generated emission current may not pass through the light-emitting diode OD, so that the light-emitting diode OD does not emit light and the sub-pixel SP can be displayed as a dark spot DP.

[0108] In this case, in the defective sub-pixel SP, the emission current is not output from the cathode electrode CE of the light-emitting diode OD to the test transistor Tt, so that the emission current does not flow along the current path formed in the second row line.

[0109] Therefore, in the second row where the dark spot DP exists, the sub-pixel SP of the defective second column line does not emit light and is displayed as the dark spot DP. Also, since the emission current is not supplied through the current path, the sub-pixel SP of the column line on the right may not emit light and is displayed as the dark spot DP.

[0110] As described above, even when performing cathode floating drive, sub-pixels SP with defects other than AC short-circuit defects can be identified as dark spots DP, and when performing cathode floating drive, other sub-pixels SP in the same row line can be identified as dark spots DP.

[0111] Therefore, during the test, by checking the positions of dark spot DP and bright spot BP during normal drive and cathode floating drive, if the positions of dark spot DP and bright spot BP are different during normal drive and cathode floating drive, it can be detected that dark spot DP is caused by a defect other than AC short circuit.

[0112] As described above, during the test, by checking the positions of the dark spot DP and bright spot BP during normal drive and cathode floating drive, it is possible to effectively detect whether the dark spot BP displayed during normal drive is caused by AC short circuit.

[0113] Simultaneously, to more accurately detect the cause of dark spot defects, a normal drive can be performed after the cathode floating drive. This allows for reconfirmation of the defect location during the normal drive, further improving the accuracy of identifying the location and cause of dark spot defects. Furthermore, although... Figure 4 and Figure 5Only the case of a dark spot at position (2,2) (i.e., one dark spot on one row line) is shown, but this disclosure is not limited to this. In the case of multiple dark spots on one row line, it may be necessary to confirm the cause of each dark spot through multiple of the above-described test procedures. For example, if two dark spots (e.g., sub-pixels at positions (2,2) and (2,4)) are detected on the second row line during normal drive, a data signal can be input to the data line of the second column line for a cathode floating drive process, similar to the above description. If the positions of the dark spot and bright spot are the same during normal drive and cathode floating drive, it can be detected that both dark spots are caused by an AC short circuit. If the positions of the dark spot and bright spot are different during normal drive and cathode floating drive, and a... Figure 5 As shown on the right, the dark spot of the sub-pixel at position (2,2) can be determined to be caused by a defect other than an AC short circuit. For the sub-pixel at position (2,4), further testing is required. In this testing process, for example, the aforementioned cathode floating drive can be performed by inputting a data signal only to the data lines of the fourth column to confirm the cause of the dark spot at position (2,4). Alternatively, data signals can be input to the data lines of both the second and fourth columns simultaneously, and the cause of the dark spot can be determined based on its position during the cathode floating drive.

[0114] The following section describes an example of the structure of a light-emitting display device that implements the dark spot defect detection described above.

[0115] Figure 6 This is a schematic plan view illustrating a sub-pixel of a light-emitting display device according to an embodiment of the present invention. Figure 7 It is along Figure 6 The cross-sectional view taken from line VII-VII' shows the cross-sectional structure of the light-emitting diode and driving transistor of the sub-pixel. Figure 8 It is along Figure 6 The cross-sectional view taken from line VIII-VIII' shows the cross-sectional structure of the test transistor.

[0116] Meanwhile, for ease of explanation, Figure 6 The sub-pixels SP connected to both sides of the power line PL are illustrated by way of example, with the power line PL positioned between the two sub-pixels SP.

[0117] Reference Figures 1 to 5 and Figures 6 to 8On the substrate 101 of the light-emitting display device 10 of this embodiment, a first transistor T1, a second transistor T2, and a driving transistor Td in the driving circuit region of the sub-pixel SP can be formed, as well as a light-emitting diode OD located on transistors T1, T2, and Td and disposed in the emission region. Additionally, a test transistor Tt can be formed that is electrically connected between the cathode electrode CE of one of the adjacent sub-pixels SP and the anode electrode AE ​​of another adjacent sub-pixel SP.

[0118] A test transistor Tt can be formed in the corresponding sub-pixel SP, and for example, the source electrode St of the test transistor Tt can be connected to the anode electrode AE ​​of the corresponding sub-pixel SP, and the drain electrode Dt of the test transistor Tt can be connected to the cathode electrode CE. Through this connection structure of the test transistor Tt, such as... Figure 2 and Figure 3 As shown, the test transistor Tt disposed in the sub-pixel SP can be configured to be electrically connected to the cathode electrode CE of the adjacent left sub-pixel SP.

[0119] Meanwhile, the light-emitting diode OD can be configured as a top-emitting type or a bottom-emitting type. For example, in the case of a top-emitting type, light can pass through the cathode electrode CE and be output upward, while in the case of a bottom-emitting type, light can pass through the anode electrode AE ​​and be output downward.

[0120] The substrate 101 can be, for example, a glass substrate or a plastic substrate with insulating properties. As another example, the substrate 101 can be a silicon wafer. In this embodiment, for ease of explanation, the case where the substrate 101 is formed of a glass substrate or a plastic substrate is used as an example.

[0121] The first transistor T1 may include a source electrode (or a first source electrode) S1, a drain electrode (or a first drain electrode) D1, a gate electrode (or a first gate electrode) G1, and a semiconductor layer (or a first semiconductor layer) SL1.

[0122] The second transistor T2 may include a source electrode (or a second source electrode) S2, a drain electrode (or a second drain electrode) D2, a gate electrode (or a second gate electrode) G2, and a semiconductor layer (or a second semiconductor layer) SL2.

[0123] The driving transistor Td may include a source electrode (or a third source electrode) Sd, a drain electrode (or a third drain electrode) Dd, a gate electrode (or a third gate electrode) Gd, and a semiconductor layer (or a third semiconductor layer) SLd.

[0124] The test transistor Tt may include a source electrode (or fourth source electrode) St, a drain electrode (or fourth drain electrode) Dt, a gate electrode (or fourth gate electrode) Gt, and a semiconductor layer (or fourth semiconductor layer) SLt.

[0125] For example, regarding the stacked structure of transistors T1, T2, Td, and Tt, the drain electrode D1 of the first transistor T1 and the source electrode S2 of the second transistor T2 can be formed on the substrate 101, and a buffer layer 105 made of insulating material can be formed on such electrodes D1 and S2. Simultaneously, a data line DL can be formed on the same layer as such electrodes D1 and S2. Additionally, a second line PL2, as part of a power line PL, can be formed on the same layer as such electrodes D1 and S2.

[0126] The buffer layer 105 may be formed, for example, from an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx), but is not limited thereto.

[0127] On the buffer layer 105, semiconductor layers SL1, SL2, SLd, and SLt can be formed for the first transistor T1, the second transistor T2, the driving transistor Td, and the test transistor Tt. Each of these semiconductor layers SL1, SL2, SLd, and SLt may include a channel region in the middle and source and drain regions on both sides of the channel region.

[0128] Semiconductor layers SL1, SL2, SLd, and SLT can be formed from, for example, polycrystalline silicon, amorphous silicon, or oxide semiconductors.

[0129] A gate insulating layer 110 may be formed on semiconductor layers SL1, SL2, SLd, and SLt. The gate insulating layer 110 may be formed of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx), but is not limited thereto.

[0130] On the gate insulating layer 110, the gate electrodes G1, G2, Gd, and Gt of the first transistor T1, the second transistor T2, the driving transistor Td, and the test transistor Tt can be formed. Additionally, the source electrode S1 of the first transistor T1, the drain electrode D2 of the second transistor T2, the source electrode Sd and drain electrode Dd of the driving transistor Td, and the source electrode St and drain electrode Dt of the test transistor Tt can be formed on the same layer as the gate electrodes G1, G2, Gd, and Gt. Simultaneously, a gate line GL and a test gate line TGL can be formed on the same layer as the gate electrodes G1, G2, Gd, and Gt. Furthermore, a reference line RL and a first line PL1, which is part of the power line PL, can be formed on the same layer as the gate electrodes G1, G2, Gd, and Gt.

[0131] The source electrode S1 of the first transistor T1 and the gate electrode Gd of the driving transistor Td can be formed integrally.

[0132] The power line PL may include a first line PL1 and a second line PL2 connected to each other, and the second line PL2 may be formed to intersect the gate line GL and the test gate line TGL. The second line PL2 may be connected to the first line PL1, for example, through a contact hole CHp, and such a contact hole CHp may be formed in the buffer layer 105 and the gate insulating layer 110.

[0133] In addition, the drain electrode D1 of the first transistor T1 can, for example, contact the drain region of the corresponding semiconductor layer SL1 through the contact hole CHd1 formed in the buffer layer 105.

[0134] The source electrode S2 of the second transistor T2 can, for example, contact the source region of the corresponding semiconductor layer SL2 through a contact hole CHs2 formed in the buffer layer 105. The drain electrode D2 of the second transistor T2 can, for example, contact the drain region of the corresponding semiconductor layer SL2 through a contact hole CHd2 formed in the gate insulating layer 110.

[0135] The source electrode S1 of the first transistor T1 can, for example, contact the source region of the corresponding semiconductor layer SL1 through a contact hole CHs1 formed in the gate insulating layer 110. The source electrode Sd and drain electrode Dd of the driving transistor Td can, for example, contact the source region and drain region of the corresponding semiconductor layer SLd through corresponding contact holes CHsd and CHdd formed in the gate insulating layer 110, respectively.

[0136] The source electrode St and drain electrode Dt of the test transistor Tt can, for example, contact the source and drain regions of the corresponding semiconductor layer SLt through corresponding contact holes CHst and CHdt formed in the gate insulating layer 110, respectively.

[0137] At least one insulating layer may be formed on the transistors T1, T2, Td, and Tt configured as described above. In this embodiment, a passivation layer 115 and a planarization layer 120 may be formed on the transistors T1, T2, Td, and Tt as an example.

[0138] The passivation layer 115 can be formed, for example, of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx) or an organic insulating material such as photoacrylic acid or benzocyclobutene. The planarization layer 120 can be formed, for example, of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx) or an organic insulating material such as photoacrylic acid or benzocyclobutene.

[0139] On the planarization layer 120, an anode electrode AE ​​can be formed for each sub-pixel SP. For example, if the light-emitting display device 10 is a bottom-emitting type, the anode electrode AE ​​may include a transparent conductive layer formed of a transparent conductive material such as ITO or IZO. If the light-emitting display device 10 is a top-emitting type, the anode electrode AE ​​may include a reflective layer formed of a metal with high reflectivity, such as Ag.

[0140] The anode electrode AE ​​can contact the source electrode Sd of the driving transistor Td, for example, through a contact hole CHa formed in the planarization layer 120 and the passivation layer 115. Furthermore, the contact hole CHa can penetrate the source electrode Sd of the driving transistor Td and be formed in the gate insulating layer 110 and the buffer layer 105. Through the contact hole CHa formed in this way, the anode electrode AE ​​can contact the source electrode Sd of the driving transistor Td and the source electrode S2 of the second transistor T2.

[0141] Meanwhile, the anode electrode AE ​​may include an extension portion AEe that extends to the test transistor Tt and is connected to the source electrode St of the test transistor Tt.

[0142] For example, the extended portion AEe of the anode electrode AE ​​can extend above the source electrode St of the test transistor Tt and contact the source electrode St of the test transistor Tt through the contact hole CHe formed in the planarization layer 120 and the passivation layer 115.

[0143] Simultaneously, for example, an island-shaped connection electrode CON can be formed on the drain electrode Dt of the test transistor Tt, located in the same layer as the anode electrode AE. The connection electrode CON can be formed separately and physically spaced apart from the anode electrode AE. The connection electrode CON can contact the drain electrode Dt of the test transistor Tt, for example, through a contact hole CHo formed in the planarization layer 120 and the passivation layer 115.

[0144] Simultaneously, a dam 130 can be formed along the boundary of each sub-pixel SP on the planarization layer 120 and the anode electrode AE. The dam 130 may include an opening OP exposing the anode electrode AE, and the dam 130 may cover the edge of the anode electrode AE. The opening OP of the dam 130 may define the emission region of the sub-pixel SP. In this case, the region in the sub-pixel SP where the dam 130 is formed can be considered a non-emission region.

[0145] A light-emitting layer EL can be formed on the anode electrode AE. The light-emitting layer EL may include a light-emitting material (e.g., an organic light-emitting material) that generates colored light or emits white light for its sub-pixels SP.

[0146] A cathode electrode CE can be formed on the light-emitting layer EL. For example, the cathode electrode CE can be formed continuously over the entire display area AA to correspond to all sub-pixels SP.

[0147] In the case of a bottom-emitting display device 10, the cathode electrode CE may include a reflective layer, for example, formed of a metal with high reflectivity, such as Ag. In the case of a top-emitting display device 10, the cathode electrode CE may include a transparent conductive layer, for example, formed of a transparent conductive material such as ITO or IZO.

[0148] As described above, in each sub-pixel SP, a light-emitting diode OD configured with an anode electrode AE, a light-emitting layer EL, and a cathode electrode CE can be formed in the emission region.

[0149] Simultaneously, the portion of the cathode electrode CE located in the region where the test transistor Tt is formed can be connected to the drain electrode Dt of the test transistor Tt. For example, the cathode electrode CE can contact the connection electrode CON through the contact hole CHc formed in the dam 130. Therefore, the cathode electrode CE can be connected to the drain electrode Dt of the test transistor Tt via the connection electrode CON.

[0150] Through the connection structure of the test transistor Tt as described above, the test transistor Tt can electrically connect the anode electrode AE ​​of the sub-pixel SP and the cathode electrode CE of the adjacent left sub-pixel SP, thereby forming a current path between adjacent light-emitting diodes OD during the test.

[0151] As described above, according to an embodiment of the present invention, a test transistor can be formed between the cathode electrode of a sub-pixel on one side of an adjacent sub-pixel in a row line and the anode electrode of a sub-pixel on the other side of an adjacent sub-pixel in a row line, and the test transistor can be driven during the test to connect the light-emitting diode in series from one side of the row line to the other side, thereby forming a current path through which the emission current can flow.

[0152] Therefore, during testing, by examining and comparing the dark and bright spots during normal operation with those during the test transistor's operation, it is possible to effectively detect whether dark spot defects are caused by AC short circuits, thereby improving the detection rate of dark spot defects caused by AC short circuits. Thus, by improving the detection rate of dark spot defects caused by AC short circuits, appropriate improved methods for detecting dark spot defects can be designed.

[0153] It will be apparent to those skilled in the art that various modifications and variations can be made to this invention without departing from the spirit or scope thereof. Therefore, this invention is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A light emitting display device, comprising: a substrate including a display area in which sub-pixels are arranged along row lines and column lines; a light emitting diode in each of the sub-pixels and including an anode electrode, a light emitting layer on the anode electrode, and a cathode electrode on the light emitting layer; a test transistor in a row line of the row lines and including a source electrode connected to the anode electrode of a sub-pixel among adjacent sub-pixels in the row line and a drain electrode connected to the cathode electrode of another sub-pixel among the adjacent sub-pixels in the row line; and a test gate line connected to a gate electrode of the test transistor, wherein the cathode electrode of the another sub-pixel among the adjacent sub-pixels in the row line is in an electrically floating state when the test transistor is turned on and a current path is formed in the row line. A low potential voltage is applied to the cathode electrode of the another sub-pixel among the adjacent sub-pixels in the row line when the test transistor is turned off and the light emitting display device is normally driven.

2. The light-emitting display device according to claim 1, wherein A low potential voltage is applied to the cathode electrode of a last sub-pixel in a direction of the current path when the test transistor is turned on and the current path is formed in the row line.

3. The light-emitting display device according to claim 1, wherein The cathode electrode of the last sub-pixel in the direction of the current path is connected to a voltage line to which the low potential voltage is supplied.

4. The light-emitting display device according to claim 3, wherein The anode electrode of the sub-pixel among the adjacent sub-pixels in the row line includes an extension portion extending over and connected to the source electrode of the test transistor.

5. The light-emitting display device according to claim 1, wherein The extension portion contacts the source electrode of the test transistor through a first contact hole formed in an insulating layer under the extension portion.

6. The light-emitting display device according to claim 5, wherein The cathode electrode of the another sub-pixel among the adjacent sub-pixels in the row line is formed corresponding to the display area, and 7. The light-emitting display device according to claim 6, wherein wherein a bank is configured to cover edges of the anode electrode of the sub-pixel among the adjacent sub-pixels in the row line. A connection electrode formed at a same layer as the anode electrode of the sub-pixel among the adjacent sub-pixels in the row line contacts the drain electrode of the test transistor through a second contact hole formed in the insulating layer, and 8. The light-emitting display device according to claim 7, wherein wherein the cathode electrode of the another sub-pixel among the adjacent sub-pixels in the row line contacts the connection electrode through a third contact hole formed in the bank.

9. The light emitting display device of claim 7, further comprising a transfer line surrounding the display area and connected to the cathode electrode of the another sub-pixel among the adjacent sub-pixels in the row line, wherein the cathode electrode of the another sub-pixel among the adjacent sub-pixels in the row line is in the electrically floating state when a voltage output from a power circuit to the transfer line is turned off. wherein A scan portion of a test gate signal applied to the test gate line is set to overlap with an emission portion of the row line, wherein the emission portion is a period in which an emission current corresponding to an applied data signal is supplied to the light emitting diode.

10. The light-emitting display device according to claim 1, wherein during the scan portion of the test gate signal, 11. The light-emitting display device according to claim 10, wherein ​ a data signal is applied to a data line of a first column line located first in a direction of a current path of the test transistor, and output of a data signal to data lines of the remaining column lines other than the first column line is turned off, or a data signal is applied to a data line of a column line in which a sub-pixel having a dark spot defect is located during normal driving, and output of a data signal to a data line of a column line in which the remaining sub-pixels normally emitting light during the normal driving are located is turned off, wherein, during the normal driving, the test transistor is turned off and the light emitting display device is normally driven.

12. A light emitting display device, comprising: a substrate including a display area in which sub-pixels are arranged along row lines and column lines; a light emitting diode in each of the sub-pixels; and a test transistor in a row line of the row lines and connected between an anode electrode of the light emitting diode of a first sub-pixel of adjacent sub-pixels in the row line and a cathode electrode of the light emitting diode of a second sub-pixel of the adjacent sub-pixels in the row line, wherein, when the test transistor is turned on and the light emitting diodes of the row line are electrically connected in series, the cathode electrode of the light emitting diode of the second sub-pixel is in an electrically floating state.

13. The light-emitting display device according to claim 12, wherein a low potential voltage is applied to the cathode electrode of the light emitting diode of the second sub-pixel when the test transistor is turned off and the light emitting display device is normally driven.

14. The light-emitting display device according to claim 12, wherein a low potential voltage is applied to a cathode electrode of a last sub-pixel in a direction of a current path of the series-connected current path when the test transistor is turned on and the light emitting diodes of the row line are electrically connected in series.

15. The light-emitting display device according to claim 12, wherein the anode electrode of the light emitting diode of the first sub-pixel includes an extension portion extending over and connected to a source electrode of the test transistor.

16. The light-emitting display device according to claim 15, wherein the extension portion contacts the source electrode of the test transistor through a first contact hole formed in an insulating layer under the extension portion.

17. The light-emitting display device according to claim 16, wherein the cathode electrode of the light emitting diode of the second sub-pixel is formed corresponding to the display area, and wherein a bank is configured to cover an edge of the anode electrode of the light emitting diode of the first sub-pixel.

18. The light-emitting display device according to claim 17, wherein a connection electrode formed at a same layer as the anode electrode of the light emitting diode of the first sub-pixel contacts a drain electrode of the test transistor through a second contact hole formed in the insulating layer, and wherein the cathode electrode of the light emitting diode of the second sub-pixel contacts the connection electrode through a third contact hole formed in the bank.

19. The light-emitting display device according to claim 12, wherein the light emitting diode is one of a top emission type or a bottom emission type.

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