Flexible InP-based semiconductor film structure and preparation method thereof

Abstract

The invention discloses a flexible InP-based semiconductor film structure and a preparation method thereof, and the structure comprises an InP-based epitaxial wafer and a flexible substrate. The InP-based epitaxial wafer comprises a single-sided polished GaAs substrate, and an AlAs stripping layer, a GaAs buffer layer, a periodic Inx (Al1-yGay) 1-xAs / Al1-zInzAs strain buffer superlattice multiplication layer, an InP charge layer, an (InaGa1-a) (AsbP1-b) energy band transition layer, a GaInAs absorption layer and an AlInAs cap layer which sequentially grow on the front surface of the single-sided polished GaAs substrate from bottom to top, and the flexible substrate is arranged on the front surface of the AlInAs cap layer, so that the GaAs substrate of the InP-based epitaxial wafer is stripped. And further growing a GaAs diffusion layer. By adopting an epitaxial layer stripping (ELO) technology, the hard and brittle SPAD material is changed into a flexible form, and meanwhile, the excellent electrical and optical properties of the SPAD material are still kept.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor materials, and in particular to a flexible InP-based semiconductor thin film structure and its preparation method. Background Technology

[0002] InP and its related III-V compound semiconductors (such as InGaAs and InAlAs) offer significant advantages as core materials for high-performance electronic and optoelectronic devices. These materials possess extremely high electron mobility, excellent photoelectric properties, and a wide spectral response range. In electronic devices, they are suitable for high-speed, low-power radio frequency (RF) devices and transistors. In optoelectronic devices, InP-based materials are ideally suited for fiber optic communication bands (1310 nm and 1550 nm). By adjusting the composition (e.g., InGaAs), their response wavelengths can cover the near-infrared to mid-infrared bands, making them widely used in sensing, imaging, and spectral analysis. InP-based single-photon avalanche detectors (SPADs), as core devices for realizing near-infrared (900-1700 nm) single-photon detection, play an irreplaceable role in quantum communication (1550 nm), lidar, and bioimaging.

[0003] However, traditional InP device fabrication typically takes place on rigid, bulky, and expensive InP substrates. This method limits its application in emerging fields such as flexible electronics, wearable devices, bionic vision, and lightweight satellite communications. Therefore, how to "transplant" high-performance InP-based devices onto flexible substrates (such as polyimide (PI) and polyvinyl naphthalene (PEN)) has become a pressing technical challenge. This requires not only overcoming the brittleness of InP materials themselves but also solving limitations in the epitaxial growth process to ensure the fabrication of high-performance devices on flexible substrates. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a flexible InP-based semiconductor thin film structure and its preparation method. This invention overcomes the problems of the inherent brittleness of SPAD materials and the limitations of epitaxial growth. By employing epitaxial layer lift-off (ELO) technology, the originally "hard and brittle" high-performance SPAD material is transformed into a "soft and tough" form. While achieving flexibility, the excellent electrical and optical properties of the SPAD material are preserved to the maximum extent, providing strong technical support for the development of next-generation flexible optoelectronic and high-speed electronic devices.

[0005] The objective of this invention is achieved through the following technical solution: A flexible InP-based semiconductor thin film structure includes an InP-based epitaxial wafer and a flexible substrate. The InP-based epitaxial wafer includes a single-sided polished GaAs substrate and, on the front side of the single-sided polished GaAs substrate, an AlAs release layer, a GaAs buffer layer, and periodically grown InP layers sequentially from bottom to top. x (Al 1-y Ga y ) 1-x As / Al 1-z In z As strain-buffered superlattice multiplication layer, InP charge layer, (In a Ga 1-a (As) b P 1-b A bandgap transition layer, a GaInAs absorber layer, and an AlInAs cap layer are constructed. A flexible substrate is placed on the front side of the AlInAs cap layer. Then, the GaAs substrate of the InP-based epitaxial wafer is peeled off by etching the AlAs release layer. A GaAs buffer layer prevents the release solution from eroding the periodically growing InP. x (Al 1-y Ga y ) 1-x As / Al 1-z In z As strain-buffered superlattice multiplication layers, and then chemical deposition techniques are used to deposit periodic In... x (Al 1-y Ga y ) 1-x As / Al 1-z In z A GaAs diffusion layer is grown on the back side of the As strain-buffered superlattice multiplication layer.

[0006] Furthermore, the growth thickness of the AlAs exfoliation layer is 10~20 nm, the growth rate is 5~10 Å / s, and the growth temperature is 590~630 °C.

[0007] Furthermore, the GaAs buffer layer has a growth thickness of 150~300nm, a growth rate of 5~25Å / s, and a growth temperature of 610~630℃.

[0008] Furthermore, the periodic In x (Al 1-y Ga y ) 1-x As / Al 1-z In z As strain-buffered superlattice multiplication layers consist of several periodically cyclically arranged In... x (Al 1-y Ga y ) 1-x As layer and Al1-z In z The As layer has 30-80 growth pairs, and the In layer... x (Al 1-y Ga y ) 1-x The As layer has a growth thickness of 5–20 nm, a growth rate of 4–8 Å / s, and a growth temperature of 610–630 °C, with x-components of 0.0–0.6 and y-components of 0.0–0.5. Al 1-z In z The As layer has a growth thickness of 5~20 nm, a growth rate of 3~10 Å / s, and a growth temperature of 610~630℃, with a z-component of 0.00~0.55.

[0009] Furthermore, the InP charge layer has a growth thickness of 50~500nm, a growth rate of 2~6Å / s, and a growth temperature of 590~610℃.

[0010] Furthermore, the (In) a Ga 1-a (As) b P 1-b The number of band transition layers is 1 to 10, the growth thickness is 5 to 20 nm, the growth rate is 4 to 8 Å / s, and the growth temperature is 610 to 630 °C. The a component is 0.5 to 0.85 and the b component is 0.1 to 0.8.

[0011] Furthermore, the GaInAs absorber layer has a growth thickness of 50~500 nm, a growth rate of 2~6 Å / s, and a growth temperature of 590~610 °C.

[0012] Furthermore, the GaAs diffusion layer has a growth thickness of 2000~4000 nm, a growth rate of 2~6 Å / s, and a growth temperature of 610~630 °C.

[0013] A method for preparing a flexible InP-based semiconductor thin film structure includes the following steps: S1. An AlAs release layer, a GaAs buffer layer, and periodically formed In atoms are grown sequentially from bottom to top on the front side of a single-sided polished GaAs substrate. x (Al 1-y Ga y ) 1-x As / Al 1-z In z As strain-buffered superlattice multiplication layer, InP charge layer, (In a Ga 1-a (As) b P 1-bA bandgap transition layer, a GaInAs absorption layer, and an AlInAs cap layer are added to obtain an InP-based epitaxial wafer. S2. A flexible substrate is set on the front side of the AlInAs cap layer using chip technology. Then, the InP-based epitaxial wafer with the flexible substrate is immersed in an etching solution. The GaAs substrate of the InP-based epitaxial wafer is completely separated by etching the AlAs release layer to obtain the released epitaxial layer. S3. Clean the epitaxial layer and use chemical deposition technology on the periodic In... x (Al 1-y Ga y ) 1-x As / Al 1-z In z GaAs diffusion layer is grown on the back side of the As strain-buffered superlattice multiplication layer; S4. A high-temperature resistant dielectric film SiN is grown on the substrate of the epitaxial layer, and then diffusion holes are processed by photolithography etching technology to obtain a chip with diffusion holes. S5. Perform Zn diffusion on the chip with the diffusion holes processed to form the P region; S6. After diffusion is complete, the inside of the diffusion pore is micro-treated with an acidic solution to reduce the high defect layer on the upper surface of the diffusion zone and avoid the formation of leakage channels under high voltage. S7. Perform sulfur treatment on the chip to form a passivation layer, and grow the SiO2 passivation layer using a PECVD machine. S8. Contact holes and P / N electrodes are fabricated on the chip using photolithography, etching, and vapor deposition to complete the fabrication.

[0014] Furthermore, in step S5, the diffusion temperature is 500~550℃, the diffusion pressure is 60~140Tor, the diffusion time is 1000~2000s, and the diffusion flow rate is 60~130cc.

[0015] Compared with the prior art, the present invention has the following advantages and beneficial effects: This invention reduces costs and increases efficiency by selecting cost-effective GaAs substrates as the base material. By introducing epitaxial layer lift-off (ELO) technology, it transforms the "hard and brittle" SPAD high-performance material into a "soft and tough" material, achieving controllable lift-off of large-area superlattice thin films. This fills a domestic technological gap and provides valuable insights for the growth of epitaxial systems in single-photon detector materials, demonstrating excellent versatility. Furthermore, by introducing a strain-buffered superlattice multiplication layer, this invention effectively releases stress caused by lattice mismatch, reduces surface defects, and increases gain efficiency. The avalanche process, driven by more ionizing carriers, allows for faster multiplication, reducing device randomness and noise, and improving device conversion efficiency. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the InP-based epitaxial wafer of the present invention.

[0017] Figure 2 For the present invention in periodic In x (Al 1-y Ga y ) 1-x As / Al 1-z In z A schematic diagram of GaAs diffusion layer grown on the back side of the As strain-buffered superlattice multiplication layer.

[0018] Figure 3 This is a schematic diagram illustrating the Zn diffusion process of the present invention.

[0019] Figure 4 The graph shows the detectivity performance of the semiconductor thin film prepared using the preparation method of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0021] Example 1: like Figures 1 to 2 As shown, this embodiment provides a flexible InP-based semiconductor thin film structure, including an InP-based epitaxial wafer and a flexible substrate. The InP-based epitaxial wafer includes a single-sided polished GaAs substrate 1 and, on the front side of the single-sided polished GaAs substrate, an AlAs release layer 2, a GaAs buffer layer 3, and a periodic In... x (Al 1-y Ga y ) 1-x As / Al 1-z In z 4. As strain-buffered superlattice multiplication layer, 5. InP charge layer, (In a Ga 1-a (As) b P 1-b The InP-based epitaxial wafer consists of a bandgap transition layer 6, a GaInAs absorber layer 7, and an AlInAs cap layer 8. A flexible substrate 9 is placed on the front side of the AlInAs cap layer. The GaAs substrate of the InP-based epitaxial wafer is then peeled off by etching the AlAs release layer. A GaAs buffer layer prevents the release solution from eroding the periodically growing InP. x (Al1-y Ga y ) 1-x As / Al 1-z In z As strain-buffered superlattice multiplication layers, and then chemical deposition techniques are used to deposit periodic In... x (Al 1-y Ga y ) 1-x As / Al 1-z In z A GaAs diffusion layer 10 is grown on the back side of the As strain-buffered superlattice multiplication layer.

[0022] Specifically, the AlAs exfoliation layer has a growth thickness of 10-20 nm, a growth rate of 5-10 Å / s, and a growth temperature of 590-630 °C.

[0023] The GaAs buffer layer is grown with a thickness of 150~300nm, a growth rate of 5~25Å / s, and a growth temperature of 610~630℃.

[0024] Periodic In x (Al 1-y Ga y ) 1-x As / Al 1-z In z As strain-buffered superlattice multiplication layers consist of several periodically cyclically arranged In... x (Al 1-y Ga y ) 1-x As layer and Al 1-z In z The As layer has 30-80 growth pairs, and the In layer... x (Al 1-y Ga y ) 1-x The As layer has a growth thickness of 5–20 nm, a growth rate of 4–8 Å / s, and a growth temperature of 610–630 °C, with x-components of 0.0–0.6 and y-components of 0.0–0.5. Al 1-z In z The As layer has a growth thickness of 5~20 nm, a growth rate of 3~10 Å / s, and a growth temperature of 610~630℃, with a z-component of 0.00~0.55.

[0025] The InP charge layer is grown at a thickness of 50–500 nm, a growth rate of 2–6 Å / s, and a growth temperature of 590–610 °C.

[0026] (In a Ga 1-a (As) b P1-b The number of band transition layers is 1 to 10, the growth thickness is 5 to 20 nm, the growth rate is 4 to 8 Å / s, and the growth temperature is 610 to 630 °C. The a component is 0.5 to 0.85 and the b component is 0.1 to 0.8.

[0027] The GaInAs absorber layer is grown to a thickness of 50–500 nm, a growth rate of 2–6 Å / s, and a growth temperature of 590–610 °C.

[0028] The GaAs diffusion layer is grown with a thickness of 2000~4000 nm, a growth rate of 2~6 Å / s, and a growth temperature of 610~630℃.

[0029] This invention achieves controllable exfoliation of large-area InP / GaInAs superlattice films by optimizing the AlAs exfoliation layer. Due to the significant lattice mismatch between the GaAs substrate and the target layer, periodic In... x (Al 1-y Ga y ) 1-x As / Al 1-z In z As strain-buffered superlattice multiplication layers effectively avoid defects caused by filter mismatch, thereby effectively releasing the stress generated by lattice mismatch, preventing dislocations from penetrating to the upper cell, and improving the crystal quality of the epitaxial layer of the single-photon detector. At the same time, by using the superlattice as a multiplication layer, the energy band characteristics are utilized to effectively enhance the collision ability of avalanche carriers (electrons or holes) while reducing the collision ability of (holes or electrons), ultimately reducing dark current and dark count, improving detection capability, and maximizing the preservation and improvement of the excellent electrical and optical properties of InP / GaInAs materials.

[0030] Example 2: This embodiment provides a method for preparing the flexible InP-based semiconductor thin film structure described in Embodiment 1, including the following steps: S1. An AlAs lift-off layer 2, a GaAs buffer layer 3, and a periodic In layer are grown sequentially from bottom to top on the front side of a single-sided polished (100) 0° GaAs substrate 1 using MOCVD or MBE technology. x (Al 1-y Ga y ) 1-x As / Al 1-z In z 4. As strain-buffered superlattice multiplication layer, 5. InP charge layer, (In a Ga 1-a (As) b P 1-bA bandgap transition layer 6, a GaInAs absorber layer 7, and an AlInAs cap layer 8 are added to obtain an InP-based epitaxial wafer, such as... Figure 1 As shown; S2. A flexible substrate material is applied to the front side of the AlInAs cap layer using chip technology to form a flexible substrate 9. Then, the InP-based epitaxial wafer with the flexible substrate is immersed in an etching solution (such as HF:H2O). By etching the AlAs release layer, the GaAs substrate of the InP-based epitaxial wafer is completely separated, resulting in the epitaxial layer after release. Since the AlAs release layer release process erodes the strain superlattice, a GaAs buffer layer is grown between the AlAs release layer and the strain superlattice during the growth of the InP-based epitaxial wafer. In addition to serving as a buffer layer, it also serves as a protective layer to prevent the release solution from eroding the strain superlattice. S3. The stripped epitaxial layer is cleaned and then chemically deposited onto periodically In... x (Al 1- y Ga y ) 1-x As / Al 1-z In z As strain-buffered superlattice multiplication layer, GaAs diffusion layer 10 is grown on the back side, such as Figure 2 As shown; S4. A high-temperature resistant dielectric film SiN is grown on the substrate of the epitaxial layer by PECVD, and then diffusion holes are processed by photolithography etching technology to obtain a chip with diffusion holes. S5. Zn diffusion is performed on the chip with the prepared diffusion holes using MOCVD to form a P-region, such as... Figure 3 As shown; the specific diffusion conditions are: diffusion temperature of 500~550℃, diffusion pressure of 60~140Tor, diffusion time of 1000~2000s, and diffusion flow rate of 60~130cc. S6. After diffusion is complete, the inside of the diffusion pore is micro-treated with an acidic solution to reduce the high defect layer on the upper surface of the diffusion zone and avoid the formation of leakage channels under high voltage. S7. The chip is subjected to sulfidation treatment by electrochemical process to form a passivation layer, and the SiO2 passivation layer is grown by PECVD machine. S8. Contact holes and P / N electrodes are fabricated on the chip using photolithography, etching, and vapor deposition to complete the fabrication.

[0031] After preparation, the PDE and DCR of the semiconductor thin film were tested. At a low temperature of -40°C, the DCR of the semiconductor thin film in this embodiment decreased to 100 kHz, and the PDE increased to 15%. Figure 4 The figure shown is a graph illustrating the detectivity performance of semiconductor thin films.

[0032] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope disclosed in the present invention, based on the technical solution and inventive concept of the present invention, shall fall within the scope of protection of the present invention.

Claims

1. A flexible InP-based semiconductor thin film structure, characterized by: An InP-based wafer including a single-polished GaAs substrate and a flexible substrate, the InP-based wafer including, in order from the front surface of the single-polished GaAs substrate, an AlAs release layer, a GaAs buffer layer, a periodic In x (Al 1-y Ga y ) 1-x As / Al 1-z In z As strain buffer superlattice multiplication layer, an InP charge layer, a (In a Ga 1-a )(As b P 1-b ) band transition layer, a GaInAs absorption layer, and an AlInAs cap layer, the flexible substrate being disposed on the front surface of the AlInAs cap layer, then the GaAs substrate of the InP-based wafer is released by etching the AlAs release layer, the GaAs buffer layer prevents the release solution from attacking the periodic In x (Al 1-y Ga y ) 1-x As / Al 1-z In z As strain buffer superlattice multiplication layer, and further a GaAs diffusion layer is grown on the back surface of the periodic In x (Al 1-y Ga y ) 1-x As / Al 1-z In z As strain buffer superlattice multiplication layer using a chemical deposition technique.

2. The flexible InP-based semiconductor thin-film structure of claim 1, wherein: The growth thickness of the AlAs stripping layer is 10-20 nm, the growth rate is 5-10 Å / s, and the growth temperature is 590-630℃.

3. The flexible InP-based semiconductor thin-film structure of claim 1, wherein: The growth thickness of the GaAs buffer layer is 150-300 nm, the growth rate is 5-25 Å / s, and the growth temperature is 610-630℃.

4. The flexible InP-based semiconductor thin-film structure of claim 1, wherein: said periodic In x (Al 1- y Ga y ) 1-x As / Al 1-z In z The As strain buffer superlattice multiplication layer comprises a plurality of periodic In x (Al 1- y Ga y ) 1-x As layers and Al 1-z In z As layers, the growth number of which is 30-80 pairs, In x (Al 1-y Ga y ) 1-x As layers, the growth thickness of which is 5-20 nm, the growth rate of which is 4-8 Å / s, and the growth temperature of which is 610-630 ℃, wherein the x component is 0.0-0.6, the y component is 0.0-0.5, the Al 1-z In z As layer, the growth thickness of which is 5-20 nm, the growth rate of which is 3-10 Å / s, and the growth temperature of which is 610-630 ℃, wherein the z component is 0.00-0.

55.

5. The flexible InP-based semiconductor thin-film structure of claim 1, wherein: The growth thickness of the InP charge layer is 50-500 nm, the growth rate is 2-6 Å / s, and the growth temperature is 590-610℃.

6. The flexible InP-based semiconductor thin-film structure of claim 1, wherein: The (In a Ga 1-a )(As b P 1-b ) band transition layer is grown in 1-10 layers, with a growth thickness of 5-20 nm, a growth rate of 4-8 Å / s, a growth temperature of 610-630 ℃, wherein the a component is 0.5-0.85, and the b component is 0.1-0.

8.

7. The flexible InP-based semiconductor thin-film structure of claim 1, wherein: The growth thickness of the GaInAs absorption layer is 50-500 nm, the growth rate is 2-6 Å / s, and the growth temperature is 590-610℃.

8. The flexible InP-based semiconductor thin-film structure of claim 1, wherein: The growth thickness of the GaAs diffusion layer is 2000-4000 nm, the growth rate is 2-6 Å / s, and the growth temperature is 610-630℃.

9. A method of producing a flexible InP-based semiconductor thin film structure according to any one of claims 1 to 8, characterized in that: The method comprises the steps of: S1, AlAs exfoliation layer, GaAs buffer layer, periodic In x (Al 1-y Ga y ) 1-x As / Al 1-z In z As strained buffer superlattice multiplication layer, InP charge layer, (In a Ga 1-a )(As b P 1-b ) band transition layer, GaInAs absorption layer and AlInAs cap layer, to obtain an InP-based epitaxial wafer; S2, a flexible substrate is arranged on the front surface of the AlInAs cap layer by using a chip process, then the InP-based epitaxial wafer with the flexible substrate is immersed in an etching solution, the AlAs stripping layer is corroded to completely separate the GaAs substrate of the InP-based epitaxial wafer, and an epitaxial layer after stripping is obtained; S3, cleaning the epitaxial layer, using chemical deposition technology in periodic In x (Al 1-y Ga y ) 1-x As / Al 1-z In z As strain buffer superlattice multiplication layer of back growth GaAs diffusion layer; S4, a high-temperature-resistant dielectric film SiN is grown on the substrate of the epitaxial layer, then a diffusion hole is processed by using a photolithography etching technology, and a chip with the diffusion hole is obtained; S5, Zn diffusion is performed on the chip with the diffusion hole, and a P region is formed; S6, after the diffusion is completed, the inside of the diffusion hole is micro-processed by using an acidic solution, the high-defect layer on the upper layer of the diffusion region is reduced, and a leakage channel is avoided from being formed under high voltage; S7, the chip is subjected to sulfuration treatment to form a passivation layer, and an SIO2 passivation layer is grown by using a PECVD machine; S8, a contact hole and P / N electrodes are processed on the chip by using photolithography, etching and evaporation, and the preparation is completed.

10. The method of claim 9, wherein: In step S5, the diffusion temperature is 500-550℃, the diffusion pressure is 60-140 Tor, the diffusion time is 1000-2000 s, and the diffusion flow is 60-130 cc.

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