Inter-chip communication system

Abstract

The invention relates to the technical field of semiconductors, in particular to an inter-chip communication system, which comprises a light source; the glass substrate chip comprises a glass substrate layer and a waveguide layer; a calculation area and a processing area are arranged on the outer surface of the waveguide layer; the calculation area comprises a driving chip and a modulation chip, the modulation chip is connected with the light source through a first light channel passing through the waveguide layer, and the modulation chip is connected with the driving chip through a first electric channel; the computing chip is connected with the modulation chip through a second optical channel; the processing area comprises a detection chip, and the detection chip is connected with the calculation chip through a third optical channel; the amplification chip is connected with the detection chip through a second electric channel; and the processing chip is connected with the amplification chip through a third electric channel. According to the inter-chip communication system, through cooperative distribution of space and functions, the stability under high-speed operation can be maintained on the basis that the large-scale operation efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to an inter-chip communication system. BACKGROUND

[0002] In a traditional computing architecture, the interconnection between electrical chips is mainly realized through metal leads. When the number and scale of electrical chips are expanded, the number and length of interconnection channels increase accordingly. As a result, when the transmission rate is increased, the radio frequency crosstalk and loss will also increase, and thus the problem of excessive interconnection power consumption is very serious.

[0003] For example, patent application CN202411745343.0 discloses a preparation method of a 3DIC optoelectronic integrated semiconductor packaging structure, which collects an optical chip module, a 3D stacked chip and a horizontal storage chip through a TSV substrate, a rewiring layer, a first electrical chip, a second electrical chip, a dielectric layer and a conductive column. The optical chip module is connected to the 3D stacked chip through the first electrical chip, and the 3D stacked chip is connected to the horizontal storage chip through the second electrical chip, so as to realize short-distance connection of the optical integrated circuit and the electrical integrated circuit. This scheme uses a circuit (i.e., a metal lead) for main communication connection, and aims to reduce the circuit connection distance through multi-layer stacking to reduce power consumption.

[0004] However, with the rapid development of AI intelligent technology, the requirement for the operation capacity of optical and electrical chips is increasing, and the traditional metal lead communication scheme cannot meet the current application requirements. SUMMARY

[0005] The present application aims to provide an inter-chip communication system, which partially solves or alleviates the above-mentioned deficiencies in the prior art, and can reduce the operation loss and improve the operation bandwidth to a certain extent.

[0006] In order to solve the above-mentioned technical problems, the present application specifically adopts the following technical scheme: The first aspect of the present application provides an inter-chip communication system, which comprises: a light source; a glass substrate chip, which comprises a glass substrate layer and a waveguide layer, wherein the outer surface of the waveguide layer is provided with a calculation area and a processing area; The calculation area comprises: a driving chip, a modulation chip connected to the light source through a first optical channel via the waveguide layer, a first electrical channel connecting the modulation chip and the driving chip, and a calculation chip connected to the modulation chip through a second optical channel; The processing area comprises: a detection chip connected to the computing chip through a third optical channel; an amplification chip connected to the detection chip through a second electrical channel; and a processing chip connected to the amplification chip through a third electrical channel.

[0007] In some embodiments, the computing chip is an electrical matrix multiplier chip, an opto-electrical hybrid matrix multiplier chip, or an XPU electrical chip.

[0008] In some embodiments, when the computing chip is an XPU electrical chip, an optical switching chip is further arranged between the computing area and the processing area; correspondingly, the third optical channel includes: at least one first sub-channel for connecting the computing chip and the optical switching chip; a plurality of second sub-channels for connecting the optical switching chip and the detection chip; the optical switching chip is configured to control the start state of the second sub-channels.

[0009] In some embodiments, the waveguide layer includes a waveguide core layer and a cladding layer, and the material of the waveguide core layer is at least one or more of silicon nitride, silicon oxynitride, niobium oxide, and tantalum oxide.

[0010] In some embodiments, the glass substrate layer is a silicate glass substrate or a microcrystalline glass substrate.

[0011] In some embodiments, the modulation chip is an optical chip. In some embodiments, the driving chip is an electrical chip. In some embodiments, the detection chip is an optical chip. In some embodiments, the amplification chip is an electrical chip.

[0012] In some embodiments, the processing signal includes at least one of a storage chip, a signal preprocessing chip, and a post-processing chip; and / or the computing chip is an inference chip.

[0013] In some embodiments, an inter-chip coupling assembly is arranged at at least one end of at least one optical channel, the inter-chip coupling assembly including: a first coupler arranged at the light output end of one of the chips; a second coupler arranged at the light receiving end of the other chip arranged oppositely; wherein the coupler is a grating coupler.

[0014] In some embodiments, the first coupler causes the incoming first incident light to deflect by a first angle and be converted into a second incident light, while the second coupler is used to receive the second incident light and cause the second incident light to deflect by a second angle and be converted into a third incident light, wherein the second angle is greater than or equal to the first angle, and the first angle is less than or equal to 90°.

[0015] In some embodiments, the first angle is greater than 70°.

[0016] Beneficial technical effects: It is worth noting that in traditional optoelectronic computing, inter-chip data transfer between multiple chips often relies on electrical channels. However, in electrical channel applications, the greater the bandwidth, the greater the loss. Therefore, the applicant notes that in large-scale optoelectronic computing scenarios, long-distance electrical channels face significant challenges, including increased losses and the inability to improve bandwidth.

[0017] To address this, the present invention employs an optoelectronic collaborative system, which combines the computational requirements of the entire model training process to design computational areas (i.e., optical computational areas) and processing areas that are dominated by light and electricity, respectively. At the same time, different types of chips are used for the core optical computational area to complete different computational and transmission tasks. By multi-dimensionally allocating signal types, chip types, and chip tasks, the stability of high-speed computation can be ensured as much as possible while greatly improving the scale and efficiency of computation.

[0018] From another perspective, unlike typical centralized architectures (such as direct signal input modulation and multiplication operations on the optical chip), this invention decouples the optical computing functions of the optical chip and uses different types of optical chips connected in series based on optical channels to achieve the complete optical computing task. This decoupling-based classification of chip functions and chip materials can significantly improve the computing performance of the assembled chip system. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. The elements or parts in the drawings are not necessarily drawn to scale. Obviously, the drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0020] Figure 1 This is a schematic diagram of the communication relationship of an inter-chip communication system in an exemplary embodiment of the present invention; Figure 2This is a schematic diagram of the communication relationship of an inter-chip communication system in another exemplary embodiment of the present invention; Figure 3 This is a top view of an inter-chip communication system according to an exemplary embodiment of the present invention; Figure 4 This is a schematic diagram of the communication architecture between two chips in an exemplary embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of the second coupler in an exemplary embodiment of the present invention; Figure 6 This is a schematic diagram of different planar architectures of the second coupler in an exemplary embodiment of the present invention; Figure 7 This is a schematic diagram of a different cross-sectional architecture of the second coupler in another exemplary embodiment of the present invention.

[0021] Figure label: 3001, Glass substrate chip; 3001b, Glass substrate layer; 3002, Light source; 3003, Computing chip; 3004, Driver chip; 3005, Modulation chip; 3006, Detector chip; 3007, Amplifier chip; 3008, Processing chip; 3009, Optical switching chip; L1, First optical channel; L2, Second optical channel; L3, Third optical channel; M1, First electrical channel; M2, Second electrical channel; M3, Third electrical channel; 1002, First coupler; 1003, Second coupler; 10011, Transparent substrate layer; 100121, Upper cladding layer; 100122, Lower cladding layer; 1003a, Waveguide core layer; 10031, Input / output terminal; 10032, Beam expander region; 10033, Diffraction region; 10034, Microlens; 10035, Metal reflective layer. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0023] In this document, suffixes such as "module," "part," or "unit" used to denote elements are used only for the purpose of illustrative purposes and have no specific meaning in themselves. Therefore, "module," "part," or "unit" may be used interchangeably.

[0024] In this document, the terms "upper," "lower," "inner," "outer," "front," "rear," "one end," and "the other end," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the present invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0025] In this document, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0026] In this document, "and / or" includes any and all combinations of one or more of the listed related items.

[0027] In this article, "multiple" means two or more, that is, it includes two, three, four, five, etc.

[0028] As used in this specification, the term "about" typically means + / -5% of the value, more typically + / -4% of the value, more typically + / -3% of the value, more typically + / -2% of the value, even more typically + / -1% of the value, and even more typically + / -0.5% of the value.

[0029] In this specification, certain embodiments may be disclosed in a range-bound format. It should be understood that this "range-bound" description is merely for convenience and brevity and should not be construed as a rigid limitation on the disclosed range. Therefore, the description of a range should be considered as having specifically disclosed all possible subranges and the individual numerical values ​​within those ranges. For example, a description of the range 1-6 should be considered as having specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and the individual numbers within those ranges, such as 1, 2, 3, 4, 5, and 6. This rule applies regardless of the breadth of the range.

[0030] Optical chips (or photonic chips, which can be simply referred to as chips in this article): A photonic chip is an integrated circuit chip based on photonics principles. It achieves optoelectronic integration by integrating photonic devices onto the chip. Photonic chips realize various complex functions through the generation, transmission, processing, modulation, and detection of light waves. The "scale" of an optical chip refers to the size of the photonic computing array on a mask within a conventional wafer area (such as an 8-inch or 12-inch wafer), typically expressed in the form X1*X2, where X1 represents the number of rows in the photonic computing array, and X2 represents the number of columns. X1 and X2 are primarily limited by: 1) the size of the computing unit; and 2) the area of ​​a single mask exposure plate on an 8-inch or 12-inch wafer.

[0031] Coupler: A coupler in an optical chip is a key passive component used to achieve optical power redistribution and mode conversion. Its core function is to efficiently and controllably transmit optical signals between different optical waveguides on the chip through specific structures (such as waveguide proximity effect, grating, etc.). It can distribute input optical energy to one or more output ports according to a predetermined ratio and predetermined deflection angle.

[0032] Translucent substrate layer: refers to a substrate (substrate) made of a material with high light transmittance. Specifically, a translucent substrate layer / translucent substrate refers to the chip's supporting substrate material exhibiting excellent optical transmittance properties with low absorption and low scattering within the target operating wavelength range (such as visible light and near-infrared). In particular, the translucent substrate layer in this invention can be a glass substrate, and the corresponding chip can be referred to as a glass substrate chip (or simply a glass chip).

[0033] Transparent substrate waveguide chip: refers to an integrated photonic chip that uses a material with high light transmittance as a substrate, on which or inside an optical waveguide structure is built to guide and manipulate optical signals.

[0034] A blazed grating is a diffraction grating that uses a specially shaped groove (usually a sawtooth profile) to concentrate the energy of incident light onto a specific, predetermined order. Unlike ordinary gratings that disperse energy across multiple orders, it utilizes the "blaze effect." By controlling the tilt angle of the grooves, the specular reflection direction is aligned with the diffraction direction of the desired order, thereby maximizing the intensity of diffracted light at that order. This design significantly improves the diffraction efficiency of the grating in a specific wavelength band (i.e., the blaze wavelength).

[0035] Example 1 It is worth noting that in traditional optoelectronic computing, inter-chip data transfer between multiple chips often relies on electrical channels. However, in electrical channel applications, the greater the bandwidth, the greater the loss. Therefore, the applicant notes that in large-scale optoelectronic computing scenarios, long-distance electrical channels face significant challenges, including increased losses and the inability to improve bandwidth.

[0036] Especially during model training, the model needs to learn from massive amounts of data and continuously adjust (i.e., switch) its weight and bias values. This places extremely high demands on the computational scale and efficiency of the chip system.

[0037] To address this, the present invention employs an optoelectronic collaborative system, which combines the computational requirements of the entire model training process to design computational areas (i.e., optical computational areas) and processing areas that are dominated by light and electricity, respectively. At the same time, different types of chips are used for the core optical computational area to complete different computational and transmission tasks. By multi-dimensionally allocating signal types, chip types, and chip tasks, the stability of high-speed computation can be ensured as much as possible while greatly improving the scale and efficiency of computation.

[0038] From another perspective, unlike typical centralized architectures (such as direct signal input modulation and multiplication operations on the optical chip), this invention decouples the optical computing functions of the optical chip and uses different types of optical chips connected in series based on optical channels to achieve the complete optical computing task. This decoupling-based classification of chip functions and chip materials can significantly improve the computing performance of the assembled chip system.

[0039] See Figure 1 As shown, the present invention provides an inter-chip communication system, comprising: Light source 3002; A glass substrate chip 3001 includes a glass substrate layer 3001b and a waveguide layer 3001a; wherein, a computing area and a processing area are provided on the outer surface of the waveguide layer 3001a. The computing area includes: The driver chip 3004; the modulation chip 3005, wherein the modulation chip 3005 is connected to the light source through a first optical channel L1 via the waveguide layer 3001b, and the modulation chip is connected to the driver chip through a first electrical channel M1; and the computing chip 3003, wherein the computing chip 3003 is connected to the modulation chip 3005 through a second optical channel L2. The processing area includes: The detector chip 3006 is connected to the computing chip 3003 via a third optical channel L3; the amplifier chip 3007 is connected to the detector chip via a second electrical channel M2; and the processing chip 3008 is connected to the amplifier chip 3007 via a third electrical channel M3.

[0040] In other words, this embodiment actually provides a computing system that uses inter-chip transmission.

[0041] In some embodiments, the computing chip is an electrical matrix multiplier chip, an optoelectronic matrix multiplier chip, or an XPU electrical chip.

[0042] In this embodiment, it is equivalent to using a glass substrate chip as a carrier platform, and integrating multiple independent chips on its plane.

[0043] Preferably, the computing chip is an optical chip or optoelectronic chip disposed on a glass substrate chip and independent of the glass substrate chip.

[0044] Preferably, the computing chip is a silicon-based optical chip, such as a typical silicon-based optical chip substrate (or substrate) which is an SOI substrate, which refers to a substrate consisting of a top silicon device layer, a middle silicon dioxide insulating layer, and a bottom silicon support substrate.

[0045] For example, the optoelectronic matrix multiplier chip is a typical silicon-based optical chip.

[0046] It should be noted that optical computation often involves two major modulation stages: 1) Modulate the external optical signal (provided by a light source) to form the input signal; 2) Each computing unit in the optical chip has a different weight, so optical signals of different power levels are used as weight signals. The power level of the weight signal also needs to be set by modulation.

[0047] In other words, the two modulation stages modulate the multiplier and multiplicand of the multiplication formula, respectively.

[0048] The calculation formula for the matrix multiplication chip is as follows: Z = W * X; where Z is the output matrix (i.e., the result of the light operation), W is the weight matrix, and X is the input matrix.

[0049] In this embodiment, the modulation chip 3005 is used to modulate each input signal (or modulation signal) in the input matrix.

[0050] Furthermore, the computing unit within the computing chip may be equipped with a modulator, which is used to modulate each weight signal in the weight matrix separately.

[0051] Preferably, the modulator of the computing chip is a phase change material layer deposited on the computing unit.

[0052] It is worth noting that in this embodiment, a computation area dominated by optical channels and a processing area dominated by electrical signals are first set up according to the two major stages of problem solving and result processing. Among them, the computation area is designed with two modes, external modulation and internal modulation, for the two modulation stages respectively.

[0053] The input signal is generated using an external modulation chip, while the weight signal is generated using a built-in modulator within the computing chip. This computing scheme, which combines a silicon-based optical chip (as a computing chip), a modulation chip, and a glass chip based on decoupling of the modulation stage, enables large-scale stable computation.

[0054] First, the external decoupling of the modulation chip simplifies the architecture design and fabrication of silicon-based optical chips. Furthermore, the disassembly of the modulation region reduces the impact on the phase-change material layer within the silicon-based optical chip during modulation. Additionally, core computation and signal transmission are implemented using silicon-based optical chips and glass-based optical chips, respectively. Glass-based optical chips, with their lower transmission loss, are used as the transmission medium for input signals to achieve long-distance transmission between the light source, glass substrate chip, modulation chip, glass substrate chip, and silicon-based optical chip. Simultaneously, the modulation speed advantage of silicon-based optical chips is utilized as the computation chip to achieve more efficient computation.

[0055] Therefore, this differentiated chip combination scheme based on decoupled architecture can improve the overall computing performance of optical chip systems through higher performance utilization.

[0056] For example, during high-frequency training and solving, the modulation components of the input signal may generate significant heat. External configuration can reduce the impact of high-frequency modulation on the state of the phase change material layer. Furthermore, by configuring the weight modulation, which requires a relatively low switching frequency (or modulation speed), within the silicon chip itself, rapid modulation operations can be achieved on-chip. Therefore, this decoupled architecture, which balances computational efficiency and stability, can comprehensively coordinate issues in optical computation processes (especially model training).

[0057] From another perspective, this invention actually provides a chip system that achieves multi-level decoupling in the computing stage and computing functions.

[0058] Preferably, all optical channels are via the waveguide layer 3001a.

[0059] In some embodiments, at least one electrical channel is also via the waveguide layer 3001a.

[0060] Alternatively, in other embodiments, at least one electrical channel may be disposed on the outside of the waveguide layer (or, the glass substrate chip), such as by forming metal leads (i.e., electrical channels) to connect two or more chips through wire bonding.

[0061] In some embodiments, the modulation chip may be an electro-optic modulator chip, which has at least one modulation unit. Specifically, the modulation unit may be made of an optical waveguide. The electro-optic effect of the material can be utilized to change the physical properties (such as refractive index) of the optical waveguide by applying an electric field, thereby achieving modulation of the optical signal (i.e., light wave) passing through the optical waveguide. The electrical signal for applying the electric field is provided by a driver chip.

[0062] Optical channel refers to the transmission path / communication path of optical signals. In this embodiment, the optical channel is mainly used to realize the transmission of optical signals between chips, so it can also be called inter-chip transmission channel / inter-chip communication channel.

[0063] During the calculation process, the exemplary communication flow of the signal in the inter-chip communication system is as follows: (1) First, an input optical signal is provided by the light source 3002, and the optical signal enters the modulation chip 3005 through the first optical channel L1. The computing chip 3003 can have a computing array of size X1*X2, that is, it has X1*X2 computing units. Similarly, the modulation chip 3005 can also be provided with X1*X2 modulation units, and the modulation units are electrically connected to the driver chip 3004. Therefore, through the electrical signal provided by the driver chip 3004, the modulation units can modulate the input optical signal to form a modulated signal, which is then transmitted to the corresponding computing unit in the computing chip 3003 through the second optical channel L2. (2) The computing unit performs optical operations based on the input modulation signal (or input matrix) and weight signal, and sends the result of the optical operation (or output matrix) to the detector chip 3006 in the processing area through the second optical channel L2; (3) The detection chip 3006 receives the result of the optical operation and converts it into an electrical signal. Then the amplification chip 3007 amplifies the result in the form of the electrical signal and finally transmits it to the processing chip 3008. The processing chip 3008 can store or format the results for subsequent applications.

[0064] In some embodiments, when the computing chip is an XPU electronic chip, an optical switching chip 3009 is further disposed between the computing area and the processing area; correspondingly, the third optical channel L3 includes: At least one first sub-channel L31, the first sub-channel L31 being used to connect the computing chip and the optical switching chip; Multiple second sub-channels L32 are used to connect the optical switching chip and the detection chip; The optical switching chip is used to control the startup state of the second sub-channel.

[0065] In other words, in a preferred embodiment, the optical switching chip is an optical switch chip, and its first sub-channel and second sub-channel are the input and output channels of the optical switch chip, respectively.

[0066] In this embodiment, by selecting an optical switch chip, large-scale signal communication can be achieved with a limited number of sub-channels, thereby reducing the number of signal channels, reducing the difficulty of connection architecture design, and reducing implementation costs.

[0067] For example, optical switch chips can use wavelength division multiplexing and space division multiplexing functions to modulate multiple electrical signal channels onto light of different wavelengths, and then transmit and switch them through a single optical fiber, thereby physically reducing the number of signal channels required (i.e., the number of optical fibers and switch ports).

[0068] In some embodiments, the waveguide layer includes a waveguide core layer and a cladding layer, and the waveguide core layer is made of at least one or more materials: silicon nitride, silicon oxynitride, niobium oxide, and tantalum oxide.

[0069] In some embodiments, the glass substrate layer 3001b is a silicate glass substrate or a microcrystalline glass substrate.

[0070] For example, the glass substrate can be a silicon dioxide substrate, a silicon oxide substrate, etc.

[0071] In some embodiments, the modulation chip is an optical chip.

[0072] In some embodiments, the driver chip is an electrical chip.

[0073] In some embodiments, the detection chip is an optical chip.

[0074] In some embodiments, the amplification chip is an electrical chip.

[0075] In some embodiments, the modulation chip and the driver chip can be integrated into a single chip, meaning that modulation and driving functions are integrated on the same chip. Alternatively, the modulation chip and the driver chip can be implemented as two separate chips.

[0076] In some embodiments, the processing chip includes at least one of the following: a memory chip, a signal preprocessing chip, and a post-processing chip.

[0077] In some embodiments, the computing chip is an inference chip.

[0078] In some embodiments, the computing area may further include at least one of the following chips: a memory chip, a signal preprocessing chip, and a post-processing chip. It is understood that the configuration of different types of chips can be flexibly adjusted according to the actual computing task.

[0079] In some embodiments, XPU chip may refer to a novel heterogeneous computing chip.

[0080] In some embodiments, the XPU chip can refer to various dedicated computing chips or accelerators, such as various processors whose architectures are optimized for specific computing loads and workloads.

[0081] In some embodiments, an inter-chip coupling component is disposed at at least one end of at least one optical channel, the inter-chip coupling component comprising: The first coupler is disposed at the optical output end of one of the chips; A second coupler is disposed at the optical receiver end of another chip that is disposed opposite to it. Among them, the first coupler and the second coupler are grating couplers.

[0082] In some embodiments, the first coupler causes the incoming first incident light to deflect by a first angle and be converted into a second incident light, while the second coupler is used to receive the second incident light and cause the second incident light to deflect by a second angle and be converted into a third incident light, wherein the second angle is greater than or equal to the first angle, and the first angle is less than or equal to 90°.

[0083] In some embodiments, the first angle is greater than 70°.

[0084] In other embodiments, such as when the inter-chip communication system / computing system is applied to the model inference stage, its computing chip can also directly use a glass substrate chip. Taking inference chips as an example, they are typically used to solve stable computational models, that is, the weights of the computational model are relatively fixed, and the input signal needs to be modulated to obtain different solutions. For scenarios with lower requirements for weight switching, a glass substrate chip is preferred for computation.

[0085] For example, in some embodiments, the computing chip can also be directly integrated with the glass substrate chip as a single integrated chip. Therefore, this invention also provides an easily scalable inter-chip communication system for inference-type optoelectronic computing needs, facilitating the large-scale integration of multiple chips.

[0086] From another perspective, this invention provides a communication mechanism that uses a glass chip as an extension platform and employs low-power optical interconnects for the core computing stage. This decoupling scheme based on glass chips and optical interconnects has at least the following technical advantages: 1) The overall signal loss is relatively small, making it easier to achieve higher bandwidth; for the core optical computing part and the connection part between the computing area and the processing area, the transmission mode dominated by optical communication is configured to reduce signal loss to a large extent; conversely, the larger the bandwidth of the traditional electrical signal transmission scheme, the greater the loss, and the bandwidth is very limited. 2) For chips adjacent to the processing area, the solution still retains electrical communication to achieve fast signal post-processing through short-distance electrical communication, while controlling signal loss through short-distance application; 3) Modulation decoupling in the computing area can reduce the mutual influence in the modulation stage and, to a certain extent, maximize the performance utilization of various types of chips through independent decoupling.

[0087] In some embodiments, to improve overall computational efficiency while ensuring result reliability, different bandwidths can be configured for the computation area and the processing area, such as a higher bandwidth for the computation area than for the processing area. This partitioning design balances computational efficiency and result reliability.

[0088] Meanwhile, using a large-area glass substrate as a carrier platform can carry more signal transmission tasks and also control the temperature increase during the chip's operation, which is conducive to achieving better heat dissipation control.

[0089] In this regard, the decoupled chip system of the present invention has a strong advantage for large-scale computing needs with ultra-low loss requirements.

[0090] Furthermore, in order to reduce signal crosstalk, a certain distance needs to be reserved between different chips, which in turn increases the communication distance of the optical and electrical channels to a certain extent.

[0091] Example 2 It should be noted that, for the sake of elaboration, Figures 1-3 The optical channel shown is only an exemplary illustration of one transmission direction, and the specific structure or type of the optical channel will be described exemplarily in this embodiment.

[0092] Specifically, the present invention also provides a low-loss optical transmission scheme suitable for inter-chip communication, as described below.Figures 4-6 An illustrative example will be provided: An inter-chip coupling component is disposed at at least one end of at least one optical channel, the inter-chip coupling component comprising: First coupler 1002, the first coupler is disposed at the optical output end of one of the chips; The second coupler 1003 is disposed at the optical receiver end of another chip disposed opposite to it; that is, the first coupler and the second coupler will be used for light transmission and reception, respectively.

[0093] The preferred type of coupler is a grating coupler.

[0094] For example, taking a glass substrate chip and a modulation chip as examples, at least one first coupler can be disposed on the glass substrate chip, while a corresponding second coupler is disposed on the modulation chip to realize signal transmission.

[0095] For example, taking a glass chip and a computing chip as examples, a first coupler can be set on the glass chip and a second coupler can be set on the computing chip, so that the input signal (or modulated signal) generated by the modulation chip can be transmitted to the computing chip.

[0096] Specifically, the two stacked chips can be staggered on the couplers, so that there is a certain distance between the adjacent first and second couplers in the horizontal direction (i.e., the direction where the chip surface is located), thereby achieving a difference in the deflection angle of the first and second couplers. Thus, the oppositely positioned first and second couplers are equivalent to forming a coupler assembly. At the same time, the light-transmitting substrate layer can further reduce the loss that may occur during light transmission.

[0097] The deflection angle refers to the angle between the original direction of light propagation and the direction of light propagation after deflection.

[0098] See Figure 4 As shown, in this embodiment, the first coupler is used as the optical signal output end, that is, it is configured to carry the deflection function of light; the second coupler is used as the optical signal transmission end, that is, it is configured to have the functions of receiving, deflecting and transmitting (specifically, it needs to capture and collect the optical signal after it has been deflected by a chip, deflect the captured signal, and then continue to transmit the deflected signal to the waveguide in the next chip).

[0099] Preferably, in this embodiment, the first coupler, which serves as the optical signal output terminal, is designed with a small deflection angle of less than 90°, thereby greatly reducing the design difficulty of the first coupler's deflection. It should be noted that because the deflection angle is small, the first coupler faces relatively less pressure in its deflection function, making it easier to complete the deflection task with relatively low loss. In other words, the deflection difficulty of the first coupler is low, thus resulting in only a small amount of signal loss. Simultaneously, assigning the task of performing large-angle deflection to the second coupler allows for the transmission of light between different chips (i.e., inter-chip transmission) with relatively limited structural reinforcement.

[0100] In other words, this combination of large and small deflection angles reduces the design burden on the first and second couplers. Specifically, the first coupler uses a small deflection angle design to ensure that the light maintains high transmission efficiency during deflection (i.e., reducing potential losses during deflection); at the same time, a localized reinforcement structure (such as a diffraction direction reinforcement structure) is designed for the receiving function of the second coupler to enhance the light capture efficiency and redirection efficiency, further reducing light loss.

[0101] The local reinforcement design achieved by the first and second couplers through the synergy of deflection angle and reinforcement structure can perform local reinforcement of the coupler components at a lower cost (i.e., focus the function on the second coupler), thereby greatly reducing the overall configuration difficulty and cost of couplers in multi-chip systems.

[0102] Furthermore, the applicant noted that during inter-chip transmission, since the second coupler already integrates receiving, deflection, and transmission functions, only relatively simple structural reinforcement design is required on top of the above structure (see below). Figures 5-7 (The structural reinforcement design is illustrated by example) This can achieve more efficient capture and transmission of light, thus achieving twice the result with half the effort.

[0103] Specifically, taking the multi-chip system provided in this embodiment as an example, considering one X1*X2 optical chip, to achieve optical communication connections with the upper and lower optical chips, at least X1 first couplers and X1 second couplers are required. Therefore, for large-scale optical chips, such as 128*128 or even 1024*1024 chips, the design and fabrication difficulties of the couplers pose extremely high challenges to the implementation of multi-chip systems.

[0104] The coupler component based on local reinforcement design provided in this application can simplify half of the coupler (i.e., the first coupler) into a basic structure, while only local reinforcement is performed on the second coupler, thereby greatly reducing the difficulty of coupler design and configuration.

[0105] Furthermore, in some embodiments, the first angle is greater than 70°.

[0106] Furthermore, in some embodiments, the first angle is greater than 75°.

[0107] Furthermore, in some embodiments, the first angle is greater than 80°.

[0108] In some embodiments, the substrate layer selected as the carrier platform chip in this embodiment can be a light-transmitting substrate layer.

[0109] Preferably, the light-transmitting substrate layer in this embodiment is a glass substrate layer (correspondingly, the optical chip is a glass substrate chip). By combining the glass substrate layer with the optical waveguide, a computing matrix scale of ultra-large area can be achieved (such as a computing scale of 5000×5000 on a 12-inch wafer; or even beyond a 12-inch wafer, a larger matrix scale can be achieved).

[0110] In this embodiment, all optical chips can be glass substrate chips, thereby realizing a large-scale multi-chip overlapping system. However, such a large-scale multi-chip overlapping system will significantly increase the difficulty of inter-chip transmission.

[0111] This embodiment provides a scheme for differentiating the deflection angle at the output and input ports of optical signals. This differentiated design is beneficial to improving the transmission efficiency of optical signals between chips, and can also reduce the design difficulty of couplers to a certain extent.

[0112] Preferably, when two glass chips are stacked, a transition layer (not shown in the figure) is provided between two adjacent glass chips. That is, a transition layer can be provided between the waveguide layer of one optical chip and the light-transmitting substrate layer of another waveguide.

[0113] Preferably, the transition layer material can be silicon oxynitride (Si-ON), and the specific silicon-nitrogen-oxygen ratio is usually around 4:2:4. The specific ratio can be adjusted according to process requirements. The thickness of the transition layer can usually be less than 100 nm, such as preferably 50 nm.

[0114] In this embodiment, a transition layer is used as a connection between adjacent chips, which is beneficial to achieve stable connection between large-scale optical chips, such as reducing defects and faults that may exist between adjacent chips due to stress problems (such as reducing cracks).

[0115] Specifically, the coupler assembly implements a local reinforcement design based on the difference in deflection angle. For example, the first coupler preferably adopts a conventional coupler, while the second coupler is provided with a local reinforcement structure, such as a diffraction direction reinforcement structure.

[0116] In some embodiments, the second coupler is provided with a diffraction direction enhancement structure, the type of which includes: a blazed grating, a metallic reflective layer, and / or a microlens.

[0117] Preferably, in some embodiments, the second coupler includes: A substrate layer (which may be a light-transmitting substrate layer 10011) is provided with a lower cladding layer 100122. A waveguide core layer 1003a is sequentially provided on the lower cladding layer 100122. The waveguide core layer 1003a includes an input / output terminal 10031, a beam expanding region 10032, and a diffraction region 10033 (e.g., ...) sequentially arranged. Figure 6 As shown); an upper cladding layer 100121 is further provided on the waveguide core layer 1003a; wherein, the diffraction region and the beam expanding region are used to receive the second incident light, and to deflect the second incident light by a second angle to convert it into a third incident light, and to transmit the third incident light to the next stage waveguide through the input / output terminal 10031.

[0118] In some embodiments, the waveguide core layer 1003a may be made of silicon or silicon nitride, the lower cladding may be made of silicon dioxide, and the upper cladding may be made of silicon dioxide, polymer / polyimide, or silicon nitride.

[0119] Preferably, the diffraction region can employ a blazed grating structure. In some embodiments, the type of the diffraction region includes at least one of the following: linear, fan-shaped, or a combination of dot-line and dot-line shapes.

[0120] For example, in some embodiments, the type of the diffraction region includes at least one of the following: second-order step, third-order step. Figure 5 A side view of a two-stage stepped blazed grating structure is shown.

[0121] For example, in some embodiments, the second coupler further includes a metal reflective layer 10035 disposed on the outer surface of the upper cladding, such as... Figure 7 As shown.

[0122] For example, in some embodiments, the diffraction direction enhancement structure is a microlens 10034 disposed on the outer surface of the light-transmitting substrate, such as... Figure 7 As shown.

[0123] In some embodiments, the type of the first coupler includes: a single-stage diffraction grating coupler, a bidirectional grating coupler, and / or a symmetrical grating coupler.

[0124] In other words, in this embodiment, the first coupler preferably adopts a more conventional grating coupler to achieve local simplification of the coupler.

[0125] For example, a single-order diffraction grating coupler is a basic grating structure in optical chips. Its design goal is usually to concentrate light energy into a single diffraction order (such as the -1st order of vertical incident / outgoing light) to achieve efficient coupling between the chip and the optical fiber. Therefore, it can be called a standard grating coupler. If its structure allows light energy to radiate symmetrically in both directions of the substrate, it is called a bidirectional grating coupler.

[0126] For example, a symmetrical grating coupler is a special grating structure designed to produce symmetrical or approximately symmetrical diffraction of incident light energy in directions perpendicular to the grating plane (i.e., upward and downward).

[0127] In other embodiments, the first coupler may be a directional grating, meaning that within a 360° range, the grating can receive light signals from a specific direction and output them from that specific direction. Light from directions other than the two specific directions will be attenuated to a greater extent possible through designs such as asymmetric designs or reflectors (mirrors).

[0128] As mentioned earlier, this invention addresses the functional differences between the first and second couplers by designing small and large deflection angles. Furthermore, it adapts the first and second couplers to different deflection angles through structural and functional variations. This type of coupler assembly with differentiated deflection angles and structural functions not only improves the optical signal transmission efficiency between chips (i.e., reduces energy consumption), but also reduces the overall design and fabrication difficulty of the couplers through localized functional enhancements, making the large-scale chip system easier to implement.

[0129] Furthermore, based on this locally reinforced coupler assembly, the present invention can provide a multi-chip system that may include at least two optical chips stacked vertically.

[0130] In other words, based on this inter-chip communication system design, the present invention can not only achieve large-scale expansion in the horizontal direction, but also stack chips in the vertical direction.

[0131] For example, the computing chips can be multiple stacked in the vertical direction. This stacking scheme is preferably implemented with the computing chips as glass substrate chips, and the computing chips can be connected to each other using the aforementioned low-loss coupler components.

[0132] In some embodiments, at least two optical chips may use the same light-transmitting substrate layer.

[0133] Furthermore, the multi-chip system may also include at least three optical chips stacked vertically.

[0134] In this embodiment, the signal transmission between optical chips can use the coupler component described in any of the above embodiments, which will not be repeated here.

[0135] In some embodiments, the computing unit includes a phase change material layer.

[0136] In some embodiments, the thickness of the phase change material layer is greater than or equal to 100 nm.

[0137] In some embodiments, the width of the phase change material layer ranges from 2 μm to 30 μm.

[0138] In some embodiments, the spacing between adjacent computing units is typically greater than 50 μm, and preferably in the range of 100 to 200 μm.

[0139] In some embodiments, the phase change material layer is made of a superlattice material.

[0140] In some embodiments, the phase change material layer is formed of a chalcogenide compound containing antimony or selenium, or the phase change material layer contains the chalcogenide compound, wherein the chalcogenide compound includes Sb2Se3 or SbSe, Sb2S3 or SbS, Ge2Sb2Se4Te.

[0141] In some embodiments, the phase change material of the phase change material layer includes a compound or alloy containing an elemental combination of germanium, antimony, selenium, and vanadium oxide, or a mixture of said compounds; said compounds include: NbOx, GeTe, GeSb, GaSb, AgInSbTe, InSb, InSbTe, InSe, SbTe, TeGeSbS, AgSbSe, SbSe, GeSbMnSn, AgSbTe, AuSbTe, and AlSb.

[0142] In some embodiments, if multiple computing chips are stacked vertically, an external light source (such as a laser) can be used to modulate the phase change material layer in the multi-layered computing chips. Specifically, the system may include: a first laser and a second laser disposed outside the optical chip; when the first laser provides a first sub-light source and the second laser provides a second sub-light source, a focal point light source is formed at the intersection of the first and second sub-light sources; when the focal point light source is located in the computing unit, the focal point light source can modulate the state of the phase change material layer.

[0143] It should be noted that in this embodiment, two modes can be used for modulation of the light source input stage and the transmission stage: direct chip transmission and spatial light modulation, respectively. Specifically, a first external light source is used as the signal light input, and a modulation chip is connected to the glass substrate chip to achieve synchronous input of the optical signal. On the other hand, dual modulators are used in combination, and spatial light modulation (i.e., the beams of two lasers are confocalized in space) is used to perform weight modulation on individual computing units in the multilayer chip.

[0144] In this embodiment, the external configuration of the first modulator and the second modulator can actually place the main active devices outside the chip structure, thereby reducing the difficulty of integrating active devices on the glass substrate chip.

[0145] In other words, the signal modulation mode that combines chip transmission and spatial light modulation enables the integration of relatively pure passive devices in the multi-chip structure within the chip system, which also makes glass substrate chips easier to implement.

[0146] In some embodiments, the modulation threshold value of the computing unit is 100 pJ. When the power of the focal point light source is greater than the modulation threshold value, the phase change material layer will undergo a state change.

[0147] In this embodiment, on the one hand, the critical value of weight modulation of the computing unit is increased by designing the size of the phase change material of the computing unit. On the other hand, the spacing data is set to ensure that adjacent computing units maintain a large spacing. Thus, through the design of the space and the modulation critical value, it can be ensured that when the two lasers of the two lasers are confocal, only one material point is modulated, avoiding interference to other schemes in the spatial light modulation mode.

[0148] In other words, because the distance between the weighting units is on the order of 100 micrometers, this threshold ensures that when two laser beams are confocal, only one material point is modulated.

[0149] It should be noted that integrating active devices on light-transmitting substrates, especially glass substrates, is extremely difficult (the non-conductive nature of glass substrates significantly increases the difficulty of transmitting electrical signals).

[0150] To address this, this embodiment provides an optical signal modulation mode based on the coordinated use of chip transmission and spatial light modulation. This coordinated mode facilitates the unified external configuration of active devices, thereby avoiding or alleviating the difficulty of large-scale integration of active devices on a glass substrate. Furthermore, this application coordinates the design of the computing units in terms of modulation threshold and spacing to provide a high-power modulation mode for the computing units. This high-power modulation mode can reduce or avoid mismodulation of adjacent computing units due to local light diffusion under spatial light modulation.

[0151] In some embodiments, it also includes: An external light source, which provides an external light source; A splitter connected to the external light source is used to split the external light source into m beams of external light signals; the splitter is connected to the modulation chip.

[0152] In some embodiments, the type of the light-transmitting substrate includes at least one of the following: glass substrate, sapphire substrate, aluminum nitride substrate, polymer substrate, magnesium oxide substrate, yttrium-stabilized zirconium oxide, and flexible transparent substrate.

[0153] In some embodiments, the glass substrate is one of a silicate glass substrate or a microcrystalline glass substrate.

[0154] Furthermore, the present invention is not limited to horizontal expansion, but also provides a multi-chip stacking scheme in the vertical direction. Specifically, the present invention provides a chip system for vertically stacking multiple light-transmitting chips based on differentiated coupler components.

[0155] In particular, the present invention uses a glass substrate to fabricate large-scale light-transmitting chips. At the same time, the local reinforcement design achieved by the first and second couplers in terms of deflection angle and reinforcement structure can perform local reinforcement of the coupler components at a lower cost (i.e., focus the function on the second coupler). This can greatly reduce the overall configuration difficulty and cost of couplers in multi-chip systems.

[0156] By leveraging the crucial role of the coupler component in optical signal transmission efficiency, this invention enables signal transmission to multiple vertically stacked optical chips based on a shared light source, thereby reducing the difficulty of supplying light sources in multi-chip systems.

[0157] Furthermore, for this vertically stacked chip system, the present invention also provides a spatial light-based signal modulation mode. Specifically, by coordinating the modulation threshold and array arrangement (such as spacing) of the computing units, the present invention enables precise single modulation of the computing units within the chip system using a confocal modulation method. Moreover, this external spatial light signal modulation mode significantly alleviates the pressure on integrating active devices (such as modulators) on the glass substrate chip.

[0158] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0159] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a computer terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0160] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. An interchip communication system, characterized by, Comprise: a light source (3002); a glass substrate chip (3001), comprising: a glass substrate layer (3001b), a waveguide layer (3001a); wherein the outer surface of the waveguide layer (3001a) is provided with a calculation area and a processing area; the calculation area comprises: a driving chip (3004); a modulation chip (3005) connected with the light source through a first light channel (L1) via the waveguide layer (3001a), and connected with the driving chip through a first electrical channel (M1); a calculation chip (3003) connected with the modulation chip through a second light channel (L2); the processing area comprises: a detection chip (3006) connected with the calculation chip (3003) through a third light channel (L3); an amplification chip (3007) connected with the detection chip through a second electrical channel (M2); a processing chip (3008) connected with the amplification chip (3007) through a third electrical channel (M3).

2. The inter-slice communication system of claim 1, wherein, The type of the calculation chip is an electrical matrix multiplier chip, an optoelectronic combined matrix multiplier chip, or an XPU electrical chip.

3. The inter-slice communication system of claim 1, wherein, When the type of the calculation chip is an XPU electrical chip, an optical switching chip is further provided between the calculation area and the processing area; correspondingly, the third light channel (L3) comprises: at least one first sub-channel (L31) for connecting the calculation chip and the optical switching chip; a plurality of second sub-channels (L32) for connecting the optical switching chip and the detection chip; the optical switching chip is used to control the start state of the second sub-channels.

4. The inter-slice communication system of claim 1, wherein, The waveguide layer comprises a waveguide core layer and a cladding layer, and the material type of the waveguide core layer is at least one or more of the following: silicon nitride, silicon oxynitride, niobium oxide, and tantalum oxide.

5. The inter-slice communication system of claim 1, wherein, The glass substrate layer (3001b) is a silicate glass substrate or a microcrystalline glass substrate.

6. The inter-slice communication system of claim 1, wherein, The modulation chip is an optical chip; and / or, the driving chip is an electrical chip; and / or, the detection chip is an optical chip; and / or, the amplification chip is an electrical chip.

7. The inter-slice communication system of claim 1, wherein, The processing signal comprises at least one of the following: a storage chip, a signal preprocessing chip, and a post-processing chip; and / or, the calculation chip is an inference type chip.

8. The inter-slice communication system of claim 1, wherein, An inter-chip coupling assembly is configured at least at one end of at least one light channel, the inter-chip coupling assembly comprising: a first coupler provided at the light output end of one of the chips; a second coupler provided at the light receiving end of the other oppositely arranged chip; wherein the types of the first coupler and the second coupler are grating couplers.

9. The inter-slice communication system of claim 8, wherein, The first coupler deflects the first incident light by a first angle to convert into a second incident light, and the second coupler is configured to receive the second incident light and deflect the second incident light by a second angle to convert into a third incident light, wherein the second angle is greater than or equal to the first angle, and the first angle is less than or equal to 90°.

10. The inter-slice communication system of claim 9, wherein, The first angle is greater than 70°.

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