Display device

Abstract

The invention relates to a display device. According to one aspect of the present disclosure, a display device includes: a substrate in which a plurality of sub-pixels including first sub-pixels are defined; a power line disposed on the substrate; a driving transistor disposed in the first sub-pixel on the substrate; a first reflective electrode and a second reflective electrode disposed on the driving transistor in the first sub-pixel; a first light emitting diode disposed on one of the first reflective electrode and the second reflective electrode in the first sub-pixel; a conductive layer disposed on the other of the first reflective electrode and the second reflective electrode; a first connection electrode electrically connected to the power supply line; a second connection electrode electrically connected to the driving transistor; and a third connection electrode electrically connected to one of the first connection electrode and the second connection electrode through the conductive layer and electrically connected to the first light emitting diode. Accordingly, a portion where the light emitting diode is not provided can be repaired without a separate repair process.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, for example, but not limited to, a display device comprising sub-pixels in which a plurality of light-emitting diodes are disposed in series. Background Technology

[0002] As display devices used for computer monitors, televisions, or mobile phones, there are organic light-emitting display devices (OLEDs) that are self-emissive devices and liquid crystal display devices (LCDs) that require a separate light source, but these are not limited to.

[0003] The applications of display devices have diversified to personal digital assistants, computer monitors, and televisions, and research is underway on display devices with large display areas and reduced size and weight.

[0004] Furthermore, display devices, including those using light-emitting diodes (LEDs), are currently attracting attention as next-generation display devices. Because LEDs are formed from inorganic rather than organic materials, they offer superior reliability, resulting in a longer lifespan than liquid crystal displays or organic light-emitting displays. In addition, LEDs feature fast turn-on speed, excellent luminous efficiency, and strong shock resistance, thus exhibiting excellent stability and the ability to display high-brightness images.

[0005] The descriptions provided in the background section should not be considered prior art simply because they are mentioned or associated with in the background section. The background section may contain information describing one or more aspects of the subject matter art. Summary of the Invention

[0006] One objective of this disclosure is to provide a display device in which a plurality of light-emitting diodes are connected in series with each other in a sub-pixel.

[0007] Another objective of this disclosure is to provide a display device with improved power consumption.

[0008] Another objective of this disclosure is to provide a display device that automatically repairs itself during the manufacturing process when any light-emitting diode is missing in a sub-pixel.

[0009] The purpose of this disclosure is not limited to the above-described purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0010] According to one aspect of this disclosure, a display device includes: a substrate defining a plurality of sub-pixels, including a first sub-pixel; a power line disposed on the substrate; a driving transistor disposed on the substrate in the first sub-pixel; a first reflective electrode and a second reflective electrode disposed in the first sub-pixel on the driving transistor; a first light-emitting diode disposed in the first sub-pixel on one of the first and second reflective electrodes; a conductive layer disposed on the other of the first and second reflective electrodes; a first connecting electrode electrically connected to the power line; a second connecting electrode electrically connected to the driving transistor; and a third connecting electrode electrically connected via the conductive layer to one of the first and second connecting electrodes and electrically connected to the first light-emitting diode. Therefore, portions where the light-emitting diode is not disposed can be repaired without a separate repair process.

[0011] According to another aspect of this disclosure, a display device includes: a substrate comprising a plurality of sub-pixels; a plurality of driving transistors disposed on the substrate in each of the plurality of sub-pixels; a power line disposed on the substrate; a first light-emitting diode disposed in a first sub-pixel of the plurality of sub-pixels; a second light-emitting diode and a third light-emitting diode disposed in a second sub-pixel of the plurality of sub-pixels, emitting light of the same color and connected in series; and a conductive pattern comprising a conductive layer disposed on a reflective electrode, and electrically connecting the first light-emitting diode to the power line or a driving transistor disposed in the first sub-pixel of the plurality of driving transistors, wherein the second light-emitting diode is electrically connected to a driving transistor disposed in the second sub-pixel of the plurality of driving transistors, and the third light-emitting diode is electrically connected to the power line. Therefore, the plurality of light-emitting diodes are connected in series in a sub-pixel, thereby reducing power consumption. Furthermore, if any one light-emitting diode is not transferred in a sub-pixel, repair is achieved in the untransferred area.

[0012] Further details of exemplary implementations are included in the detailed description and accompanying drawings.

[0013] According to this disclosure, when any light-emitting diode is not transferred in a sub-pixel, the display device can be automatically repaired during the manufacturing process without a separate repair process.

[0014] According to this disclosure, multiple light-emitting diodes disposed in a sub-pixel are connected in series, thereby reducing the power consumption of the display device for driving at low power.

[0015] The effects of this disclosure are not limited to those illustrated above, and many more effects are included in this specification.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and constitute a part of this application, are included to provide a further understanding of this disclosure. The drawings illustrate embodiments of the disclosure and, together with the description, serve to illustrate the principles of the disclosure. The above and other aspects, features, and other advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0018] Figure 1 This is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0019] Figure 2A This is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0020] Figure 2B This is a perspective view of a splicing display device according to an exemplary embodiment of the present disclosure;

[0021] Figure 3 This is a circuit diagram of a first sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0022] Figure 4 This is a cross-sectional view of a first sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0023] Figure 5 This is a circuit diagram of the second sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0024] Figure 6 This is a cross-sectional view of a second sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0025] Figures 7A to 7G This is a process diagram illustrating a method for manufacturing a first sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0026] Figure 8 This is a cross-sectional view of a first sub-pixel of a display device according to another exemplary embodiment of the present disclosure;

[0027] Figure 9 This is a cross-sectional view of a second sub-pixel of a display device according to another exemplary embodiment of the present disclosure; and

[0028] Figures 10A to 10G This is a process diagram illustrating a method for manufacturing a first sub-pixel of a display device according to another exemplary embodiment of the present disclosure.

[0029] Throughout the accompanying drawings and detailed embodiments, unless otherwise stated, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustrative purposes, and convenience, the relative dimensions and depictions of these elements may be exaggerated. Detailed Implementation

[0030] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations relevant to this document will be omitted where such descriptions would be deemed to unnecessarily obscure the essential points of the inventive concept. The described progression of processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to the order described herein and can be modified as is known in the art, except for steps and / or operations that must occur in a specific order. The names of the various elements used in the following explanation are chosen solely for ease of specification and may therefore differ from those used in actual products.

[0031] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the following exemplary embodiments, taken in conjunction with the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. Exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the disclosure and scope of this disclosure.

[0032] The shapes (e.g., dimensions, lengths, widths, heights, thicknesses, positions, radii, diameters, and areas), ratios, angles, quantities, etc., shown in the accompanying drawings used to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural form.

[0033] The word "exemplary" is used to indicate that something is used as an example or illustration. An aspect is an example aspect. "Implementation method," "example," "aspect," etc., should not be construed as being preferred or advantageous over other implementations. Implementation method, example, example implementation method, aspect, etc., can refer to one or more implementation methods, one or more examples, one or more example implementation methods, or one or more aspects, unless otherwise stated. Furthermore, the term "may" includes all the meanings of the term "able to."

[0034] Even if not explicitly stated, components should be interpreted as including a normal error range.

[0035] When using terms such as “above,” “over,” “below,” and “next to” to describe the positional relationship between two parts, one or more parts may be located between the two parts unless these terms are used in conjunction with the terms “immediately adjacent” or “directly.”

[0036] Terms such as “below,” “lower,” “above,” and “upper” are used herein to describe the relationships between elements as shown in the figures. It will be understood that these terms are spatially relative and based on the orientation depicted in the figures.

[0037] When one element or layer is disposed "on" another element or layer, the element or layer may be directly above the other element or layer, or another element or layer may be inserted between them.

[0038] Although the terms "first," "second," "A," "B," "a," and "b," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component mentioned below can be a second component in the technical concept of this disclosure.

[0039] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, "at least one of the first element, the second element, and the third element" means combinations of all three listed elements, combinations of any two of the three elements, and each individual element, namely the first element, the second element, or the third element.

[0040] Throughout the specification, the same reference numerals generally denote the same elements.

[0041] The dimensions and thicknesses of each component shown in the accompanying drawings are for illustrative purposes only, and this disclosure is not limited to the dimensions and thicknesses of the components shown.

[0042] The features of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole, and may be technically interlocked and operated in various ways, and these embodiments may be implemented independently or in association with each other.

[0043] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments pertain. It will be further understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technical field and should not be interpreted in an idealized or overly formal manner unless explicitly defined herein. For example, the terms “component” or “unit” can be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit arrangement, or any structure configured to perform the described functions, as would be understood by one of ordinary skill in the art.

[0044] In the following, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0045] Figure 1 This is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure.

[0046] exist Figure 1 For ease of description, only the display panel PN, the gating driver GD, the data driver DD, and the timing controller TC are shown among the various components of the display device 100. Therefore, as an example, one or more additional components may be further included.

[0047] Reference Figure 1 The display device 100 includes: a display panel PN, which includes a plurality of sub-pixels SP; a gating driver GD and a data driver DD, which provide various signals to the display panel PN; and a timing controller TC, which controls the gating driver GD and the data driver DD.

[0048] The gating driver GD provides multiple scan signals to multiple scan lines SL based on multiple gating control signals provided by the timing controller TC. Although in Figure 1 The diagram illustrates a gate driver (GD) positioned spaced apart from one side of the display panel PN, but the number and placement of gate drivers (GDs) are not limited to this. As an example, two or more gate drivers may be present. As an example, two or more gate drivers may be positioned spaced apart from opposite sides of the display panel PN, but are not limited to this. As an example, the gate drivers may be positioned on the display panel PN in a gate-in-panel (GIP) configuration, or may be separately positioned on a separate panel and connected to one or more sides of the display panel PN, for example, in a tape-on-board (TAB) configuration, chip-on-glass (COG) configuration, chip-on-panel (COP) configuration, or chip-on-film (COF) configuration, but are not limited to this.

[0049] Based on multiple data control signals provided by the timing controller TC, the data driver DD converts the image data input from the timing controller TC into a data voltage using a reference gamma voltage. The data driver DD can then supply the converted data voltage to multiple data lines DL.

[0050] The timing controller TC aligns the image data input from an external source to provide the image data to the data driver DD. The timing controller TC can generate gating control signals and data control signals using synchronization signals input from an external source (e.g., dot clock signals, data enable signals, and horizontal / vertical synchronization signals). Furthermore, the timing controller TC provides the generated gating control signals and data control signals to the gating driver GD and the data driver DD, respectively, to control the gating driver GD and the data driver DD.

[0051] The display panel PN is a configuration for displaying images to the user and includes multiple subpixels SP. In the display panel PN, multiple scan lines SL and multiple data lines DL intersect each other, and the multiple subpixels SP are respectively connected to the scan lines SL and data lines DL. Furthermore, although not shown in the accompanying drawings, as an example, each of the multiple subpixels SP may also be connected to a high-potential power line VDD, a low-potential power line VSS, a reference line, etc., but is not limited thereto.

[0052] In the display panel PN, a valid area AA and an invalid area NA adjacent to the valid area AA can be defined. As an example, the invalid area NA can completely or partially surround the valid area AA, but is not limited to this.

[0053] The effective area AA is the area in the display device 100 where the image is displayed. Within the effective area AA, multiple sub-pixels SP constituting multiple pixels PX and circuitry for driving the multiple sub-pixels SP can be provided. The multiple sub-pixels SP are the smallest units constituting the effective area AA, and n sub-pixels SP can form one pixel PX, where n is an integer equal to or greater than 1. In each of the multiple sub-pixels SP, a light-emitting diode (LED) and a thin-film transistor for driving the LED can be provided. Depending on the type of the display panel PN, the multiple LEDs can be defined in different ways. For example, when the display panel PN is an inorganic light-emitting display panel PN, the LEDs can be light-emitting diodes (LEDs) or miniature light-emitting diodes (LEDs), but are not limited to these.

[0054] Within the effective area AA, multiple signal lines are provided to transmit various signals to multiple sub-pixels SP. For example, the multiple signal lines may include multiple data lines DL providing data voltage to each of the multiple sub-pixels SP and multiple scan lines providing gating voltage to each of the multiple sub-pixels SP. Multiple scan lines SL extend in one direction within the effective area AA to connect to the multiple sub-pixels SP, and multiple data lines DL extend in a different direction within the effective area AA to connect to the multiple sub-pixels SP. Furthermore, a low-potential power line VSS and a high-potential power line VDD may also be provided within the effective area AA, but are not limited to these.

[0055] The invalid region NA is the area where no image is displayed; therefore, the invalid region NA can be defined as the area extending from the valid region AA. Within the invalid region NA, links, pad electrodes, or driver ICs such as strobe driver ICs or data driver ICs can be configured to transmit signals to the sub-pixels SP of the valid region AA.

[0056] Meanwhile, the invalid region NA may be partially or completely located on the rear surface of the display panel PN (e.g., the surface where no sub-pixels SP are provided), or it may be omitted, for example, from the front side of the display panel PN, and is not limited to what is shown in the figures. As an example, the invalid region NA may be curved toward the rear surface of the display panel PN, such that part or all of the invalid region NA is not visible from the front side of the display panel PN, but is not limited thereto.

[0057] Meanwhile, drivers such as the gate driver GD, data driver DD, and timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD can be installed in the inactive area NA in a gate-in-panel (GIP) manner, or between multiple sub-pixels SP in the active area AA in a gate-in-active-area (GIA) manner, but is not limited thereto. For example, the data driver DD and timing controller TC can be formed in separate flexible films or printed circuit boards, and can be electrically connected to the display panel PN by combining the flexible film and the printed circuit board to the inactive area NA of the display panel PN (e.g., pad electrodes formed in the inactive area NA). If the gate driver GD is installed in a GIP manner, and the data driver DD and timing controller TC transmit signals to the display panel PN through the pad electrodes of the inactive area NA, it is necessary to ensure that the area of ​​the inactive area NA used for setting the gate driver GD and the pad electrodes is adequate. This may increase the bezel size.

[0058] In contrast, when the gate driver GD is mounted in the active area AA in a GIA configuration, and the side lines SRL connecting the signal lines on the front surface of the display panel PN to the pad electrodes on the rear surface of the display panel PN are formed to bond the flexible film and printed circuit board to the rear surface of the display panel PN, the inactive area NA on the front surface of the display panel PN can be reduced or minimized. As an example, when the gate driver GD, data driver DD, and timing controller TC are connected to the display panel PN as described above, a virtually bezel-less design can be achieved, which will refer to... Figure 2A and Figure 2B To describe in more detail.

[0059] Figure 2A This is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure, and Figure 2B This is a perspective view of a splicing display device according to an exemplary embodiment of the present disclosure.

[0060] First, refer to Figure 2A In the invalid area NA of the display panel PN, multiple pad electrodes are provided for transmitting various signals to multiple sub-pixels SP. For example, in the invalid area NA on the front surface of the display panel PN, a first pad electrode PAD1 is provided for transmitting signals to multiple sub-pixels SP. In the invalid area NA on the rear surface of the display panel PN, a second pad electrode PAD2 is provided that is electrically connected to driving components (e.g., flexible film and printed circuit board).

[0061] In this case, although not shown in the accompanying drawings, various signal lines (e.g., scan lines SL or data lines DL) connected to multiple sub-pixels SP extend from the active area AA to the inactive area NA to be electrically connected to the first pad electrode PAD1.

[0062] Furthermore, the side line SRL is disposed along the side surface of the display panel PN. The side line SRL can electrically connect the first pad electrode PAD1 on the front surface of the display panel PN to the second pad electrode PAD2 on the rear surface of the display panel PN. Therefore, signals from the driving components on the rear surface of the display panel PN can be transmitted to multiple sub-pixels SP through the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Thus, a signal transmission path is formed from the front surface to the side and rear surfaces of the display panel PN to reduce or minimize the area of ​​the inactive region NA of the display panel PN.

[0063] In addition, refer to Figure 2B A large-screen splicing display device TD can be achieved by connecting multiple display devices 100. In this case, such as... Figure 2AAs shown, when a splicing display device TD is implemented using a display device 100 with a reduced or minimized bezel, the seam area between the display devices 100 where no image is displayed is reduced or minimized, thereby improving the display quality.

[0064] For example, multiple sub-pixels SP form a pixel PX, and the distance D1 between the outermost pixel PX of one display device 100 and the outermost pixel PX of another display device 100 adjacent to the one display device 100 can be made equal to the distance D1 between pixels PX in the one display device 100. Therefore, the distance between pixels PX between display devices 100 is constantly configured to reduce or minimize the seam area.

[0065] However, Figure 2A and Figure 2B This is illustrative, and therefore the display device 100 according to the exemplary embodiments of this disclosure may be a general display device 100 with a bezel, but is not limited thereto.

[0066] Multiple subpixels SP that form a pixel PX can be composed of subpixels SP that emit light of different colors. For example, such as Figure 2B As shown, the multiple sub-pixels SP may include a red sub-pixel RSP, a green sub-pixel GSP, and a blue sub-pixel BSP. However, it is not limited to this, and the multiple sub-pixels SP may also include sub-pixels SP that emit light of different colors (e.g., white light). The implementation is not limited to this. As an example, at least some of the multiple sub-pixels SP forming a pixel PX may be configured to emit light of the same color, but are not limited to this. As an example, sub-pixels that emit light of other colors such as cyan, magenta, and yellow may be optionally or additionally included.

[0067] As an example, at least one, some, or each of the multiple sub-pixels SP of a pixel PX may include two light-emitting diodes (LEDs), but is not limited thereto. In this case, the two LEDs can emit light of the same color. For example, two LEDs emitting red light can be provided in the red sub-pixel RSP, two LEDs emitting green light can be provided in the green sub-pixel GSP, and two LEDs emitting blue light can be provided in the blue sub-pixel BSP. The implementation is not limited thereto. As an example, at least one or some of the multiple sub-pixels SP of a pixel PX may include three or more LEDs, but is not limited thereto. As an example, three or more LEDs can emit light of the same color, but is not limited thereto. As an example, the multiple sub-pixels SP of a pixel PX may include the same number of LEDs or different numbers of LEDs, but is not limited thereto.

[0068] Meanwhile, as an example, the plurality of sub-pixels SP may include light-emitting diodes (LEDs) or miniature light-emitting diodes (LEDs). As an example, a transfer method is primarily used to transfer LEDs onto the display device, and in this case, LEDs may not be transferred, or even if transferred, the LEDs may be missing during the manufacturing process, but this is not a limitation. In the display device 100 according to an exemplary embodiment of this disclosure, among the plurality of sub-pixels SP, a sub-pixel SP in which one LED is not transferred or is missing is defined as a first sub-pixel SP1. Furthermore, a sub-pixel SP in which two LEDs are normally transferred is defined as a second sub-pixel SP2. The first sub-pixel SP1 and the second sub-pixel SP2 will be described in more detail below.

[0069] Figure 3 This is a circuit diagram of a first sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Specifically, Figure 3 This is a circuit diagram of the pixel circuit of the first sub-pixel SP1 of a display device 100 according to an exemplary embodiment of the present disclosure.

[0070] Reference Figure 3 The first sub-pixel SP1 can be connected to a first scan line SL1, a second scan line SL2, a data line DL, a light-emitting line EL, a high-potential voltage line VL1, a low-potential voltage line VL2, and a reference voltage line VL3. The first sub-pixel SP1 can be equipped with a pixel circuit including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C1, a second capacitor C2, and a third capacitor C3, as well as a first light-emitting diode LED1 connected to the pixel circuit. In this case, the high-potential voltage line VL1 is referred to as the first power line, the low-potential voltage line VL2 is referred to as the second power line, and the reference voltage line VL3 can be referred to as the third power line. The implementation is not limited to this. As an example, the pixel circuit of the first sub-pixel SP1 of the display device 100 can be changed in various ways. As an example, at least one of the signal lines or components mentioned above can be omitted, or at least one additional signal line or component can be further included.

[0071] First, the pixel circuit of the first sub-pixel SP1 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include a gate, a source, and a drain.

[0072] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be either N-type transistors or P-type transistors. In an N-type transistor, the charge carriers are electrons, allowing electrons to flow from the source to the drain and current to flow from the drain to the source. In a P-type transistor, the charge carriers are holes, allowing holes to flow from the source to the drain and current to flow from the source to the drain. For example, one or more of the transistors can be N-type transistors, and another of the transistors can be a P-type transistor, but this is not a limitation. The following description assumes that the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are P-type transistors, but this disclosure is not limited thereto.

[0073] The first transistor T1 may include a first gate, a first source, and a first drain. The first gate is connected to a first scan line SL1, the first source may be connected to a data line DL, and the first drain may be connected to a first node N1. The first transistor T1 can transmit the data voltage Vdata from the data line DL to the first node N1 based on a first scan signal S1 of the first scan line SL1.

[0074] The third transistor T3 may include a third gate, a third source, and a third drain. The third gate is connected to the light-emitting line EL, the third source is connected to the reference voltage line VL3, and the third drain is connected to the first node N1. The third transistor T3 can transfer the reference voltage from the reference voltage line VL3 to the first node N1 according to the light-emitting signal EM, and allows the second node N2 and the third node N3 to maintain a constant voltage when the first light-emitting diode LED1 emits light. The third transistor T3 may be referred to as the first light-emitting transistor.

[0075] The fourth transistor T4 may include a fourth gate, a fourth source, and a fourth drain. The fourth gate may be connected to the first scan line SL1, the fourth source may be connected to the second node N2, and the fourth drain may be connected to the third node N3. The fourth transistor T4 shorts the sixth gate and sixth drain of the sixth transistor T6 and performs a diode connection to the sixth transistor T6. In the diode connection, the gate and drain are shorted, causing the transistor to operate as a diode.

[0076] As an example, the fourth transistor T4 can be implemented using a structure with two transistors connected in series, but is not limited to this. As an example, the fourth transistor T4 can be implemented using a structure including one transistor or a structure with three or more transistors connected in series. The fourth transistor T4 may include a fourth-first transistor T4-1 and a fourth-second transistor T4-2. The gates of the fourth-first transistor T4-1 and the fourth-second transistor T4-2 can be connected to the first scan line SL1, and the drain or source of the fourth-first transistor T4-1 can be connected to the source or drain of the fourth-second transistor T4-2. Because the fourth transistor T4 is implemented using two transistors connected in series, reliability is enhanced, and current leakage from the sixth gate of the sixth transistor T6 can be reduced or minimized.

[0077] The fifth transistor T5 may include a fifth gate, a fifth source, and a fifth drain. The fifth gate may be connected to the second scan line SL2, the fifth source may be connected to the reference voltage line VL3, and the fifth drain may be connected to the third node N3. The fifth transistor T5 can provide the reference voltage Vref to the third node N3 based on the second scan signal S2 of the second scan line SL2, and can reset the sixth drain of the sixth transistor T6, which is the third node N3, to the reference voltage.

[0078] As an example, the fifth transistor T5 can be implemented using a structure with two transistors connected in series, but is not limited to this. As an example, the fifth transistor T5 can be implemented using a structure including one transistor or a structure with three or more transistors connected in series. The fifth transistor T5 may include a 5-1 transistor T5-1 and a 5-2 transistor T5-2. The gates of the 5-1 transistor T5-1 and the 5-2 transistor T5-2 can be connected to the second scan line SL2, and the drain or source of the 5-1 transistor T5-1 can be connected to the source or drain of the 5-2 transistor T5-2. Because the fifth transistor T5 is implemented using two transistors connected in series, reliability is enhanced, and current leakage from the sixth gate of the sixth transistor T6 can be reduced or minimized.

[0079] The sixth transistor T6 may include a sixth gate, a sixth source, and a sixth drain. The sixth gate is connected to the second node N2, the sixth source is connected to the fourth node N4, and the sixth drain is connected to the third node N3. The sixth transistor T6 is turned on to control the drive current flowing in the first light-emitting diode LED1, and may be referred to as the drive transistor DT.

[0080] The second transistor T2 may include a second gate, a second source, and a second drain. The second gate is connected to the first scan line SL1, the second source is connected to the high-potential voltage line VL1, and the second drain is connected to the fourth node N4. The second transistor T2 can transmit the high-potential power supply voltage VDD to the fourth node N4 based on the first scan signal S1 of the first scan line SL1.

[0081] The seventh transistor T7 may include a seventh gate, a seventh source, and a seventh drain. The seventh gate is connected to the light-emitting line EL, the seventh source is connected to the third node N3, and the seventh drain may be connected to the low-potential voltage line VL2. The seventh transistor T7 can provide a low-potential supply voltage VSS to the third node N3 based on the light-emitting signal EM to allow drive current to flow. The seventh transistor T7 may be referred to as the second light-emitting transistor.

[0082] The first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5, which are controlled by the first scan signal S1 or the second scan signal S2, can be referred to as scan transistors.

[0083] The first capacitor C1 may include a capacitor electrode connected to the first node N1 and a capacitor electrode connected to the second node N2. While the first light-emitting diode LED1 emits light, the first capacitor C1 keeps the voltage applied to the sixth gate of the sixth transistor T6 constant to maintain a constant drive current.

[0084] The second capacitor C2 may include capacitor electrodes connected to the fourth node N4 and capacitor electrodes connected to the high-potential power line VDD. That is, the second capacitor C2 may include capacitor electrodes connected to the cathode and anode of the first light-emitting diode LED1. The second capacitor C2 enables the first light-emitting diode LED1 to emit light while maintaining the same brightness, and simultaneously maintains a constant voltage on the first light-emitting diode LED1 to allow the same drive current to flow.

[0085] The third capacitor C3 may include a capacitor electrode connected to the second node N2 and a capacitor electrode connected to the fourth node N4. In other words, the third capacitor C3 may be a capacitor formed between the sixth gate and the sixth source of the sixth transistor T6 and between the sixth gate and the cathode of the first light-emitting diode LED1. Therefore, the third capacitor C3 can maintain the gate-source voltage of the sixth transistor T6.

[0086] As described above, the first sub-pixel SP1 is the sub-pixel SP among multiple sub-pixels SP where the light-emitting diode has not been transferred or is missing. However, as Figure 3As shown, the locations where LEDs other than the first LED1 need to be set are not open circuits but connected, allowing the first LED1 to light up normally. In the following text, reference will be made to... Figure 4 Describe in detail the cross-sectional structure of the first sub-pixel SP1.

[0087] Figure 4 This is a cross-sectional view of a first sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Assuming in... Figure 4 In the first sub-pixel Sp1, the first light-emitting diode LED1 is normally transferred to the first reflective electrode RE1, but the light-emitting diode that needs to be set is not transferred to the second reflective electrode RE2 or is missing from the second reflective electrode RE2.

[0088] Reference Figure 4 The substrate 110 is a substrate that supports components disposed thereon. As an example, the substrate 110 may be an insulating substrate. For example, the substrate 110 may be formed of glass or resin. Alternatively, the substrate 110 may comprise a polymer or plastic. In some exemplary embodiments, the substrate 110 may be formed of a flexible plastic material. Multiple pixels are formed on the substrate 110 to display an image.

[0089] As an example, a light-shielding layer BSM can be provided on substrate 110. The light-shielding layer BSM blocks light incident on the active layer ACT of multiple transistors to reduce or minimize leakage current. For example, the light-shielding layer BSM is provided below the active layer ACT of the driving transistor DT to block light incident on the active layer ACT. If light shines on the active layer ACT, leakage current is generated, which reduces the reliability of the transistor. Therefore, a light-shielding layer BSM is provided on substrate 110 to improve the reliability of the driving transistor DT. The light-shielding layer BSM can be made of an opaque conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto. The implementation is not limited thereto. As an example, the light-shielding layer BSM can be provided on a different layer than substrate 110. As an example, the light-shielding layer BSM can be provided on any layer as long as it is provided below the active layer ACT. As an example, the light-shielding layer BSM can be omitted depending on the design.

[0090] A buffer layer 111 may be disposed on the substrate 110. As an example, the buffer layer 111 may be disposed on the light-shielding layer BSM. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 may be composed of a single layer, double layer, or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, depending on the type of substrate 110 or the type of transistor, the buffer layer 111 may be omitted, but is not limited thereto.

[0091] A drive transistor DT, comprising an active layer ACT, a gate GE, a source SE, and a drain DE, is disposed on the buffer layer 111.

[0092] However, although in Figure 4 Although not shown, an additional buffer layer may be provided between the substrate 110 and the light-shielding layer BSM. Like the buffer layer 111 described above, the additional buffer layer may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx) to reduce the penetration of moisture or impurities through the substrate 110, but is not limited thereto.

[0093] First, the active layer ACT of the driving transistor DT can be disposed on the buffer layer 111. The active layer ACT can be formed of a semiconductor material (e.g., oxide semiconductor, amorphous silicon, polycrystalline silicon, compound semiconductor, or organic semiconductor), but is not limited thereto. Furthermore, even if not shown in the figures, other transistors besides the driving transistor DT (e.g., switching transistors, sensing transistors, and light-emitting control transistors) can be further disposed. The active layers of the transistors can also be formed of a semiconductor material (e.g., oxide semiconductor, amorphous silicon, polycrystalline silicon, compound semiconductor, or organic semiconductor), but are not limited thereto. The active layers of the transistors included in the pixel circuit (e.g., driving transistor DT, switching transistor, sensing transistor, and light-emitting control transistor) can be formed of the same material or different materials.

[0094] A gate insulating layer 112 may be disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer that electrically insulates the active layer ACT from the gate GE, and may be composed of a single layer, double layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0095] The gate GE can be disposed on the gate insulating layer 112. The gate GE can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0096] Furthermore, as an example, an intermediate electrode CNT may be disposed on the gate insulating layer 112 or on a layer other than the gate insulating layer 112. As an example, the intermediate electrode CNT may be formed of the same material as the gate GE or may be formed of a different material than the gate GE. As an example, the intermediate electrode CNT may be electrically connected to the light-shielding layer BSM, but is not limited thereto.

[0097] As an example, a first interlayer insulating layer 113 may be provided on the gate GE, but is not limited thereto. Contact holes may be formed in the first interlayer insulating layer 113, through which the source SE and drain DE are connected to the active layer ACT. The first interlayer insulating layer 113 is an insulating layer protecting the components beneath it, and may be composed of a single layer, double layer, or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0098] As an example, a conductive layer TM may be provided on the first interlayer insulating layer 113. The conductive layer TM may be provided above the gate GE. As an example, the conductive layer TM may at least partially overlap with the gate GE, but is not limited thereto. As an example, the conductive layer TM may form a storage capacitor together with the gate GE. However, according to an exemplary embodiment, the conductive layer TM may be omitted.

[0099] As an example, a second interlayer insulating layer 114 may be provided on the conductive layer TM, but is not limited thereto. Contact holes may be formed in the second interlayer insulating layer 114, through which the source SE and drain DE are connected to the active layer ACT. The second interlayer insulating layer 114 is an insulating layer protecting the components beneath it, and may be composed of a single layer, double layer, or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0100] As an example, the source SE and drain DE, electrically connected to the active layer ACT, can be disposed on the second interlayer insulating layer 114. As an example, the drain DE can be electrically connected to the conductive layer CL via a second additional electrode AE2 and a second connecting electrode CE2, but is not limited thereto. The source SE and drain DE can be made of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but are not limited thereto.

[0101] As an example, the power line VL is disposed on the second interlayer insulation layer 114, or on a layer other than the second interlayer insulation layer 114, but is not limited thereto. Specifically, the power line VL may be disposed on the second interlayer insulation layer 114 in a manner similar to that of the source (SE) and drain (DE) to be spaced apart from the source (SE) and drain (DE), and may be formed of the same material as the source (SE) material and drain (DE) material, but is not limited thereto. The power line VL may be a low-potential power line, and in this case, a low-potential voltage may be supplied to the power line VL. However, this disclosure is not limited thereto, and the power line VL may be a high-potential power line. As an example, the power line VL may be disposed on a different layer from the source (SE) and drain (DE), or may be formed of a different material than the source (SE) material and drain (DE) material, but is not limited thereto.

[0102] As an example, the power line VL can be electrically connected to the first auxiliary electrode AE1 and the first connecting electrode CE1. Therefore, the high-potential voltage line VL1 can be connected to the second electrode 125 of the first light-emitting diode LED1 through the first auxiliary electrode AE1 and the first connecting electrode CE1. Thus, the power line VL can transmit a high-potential voltage to the first auxiliary electrode AE1, the first connecting electrode CE1, and the second electrode 125 of the first light-emitting diode LED1. The implementation is not limited to this. As an example, the power line VL can be electrically connected to the second electrode 125 of the first light-emitting diode LED1 without the first auxiliary electrode AE1 and / or the first connecting electrode CE1, but is not limited to this.

[0103] An outer coating 115 can be provided on the source electrode SE, drain electrode DE, and power line VL. The outer coating 115 can be configured to cover the source electrode SE, drain electrode DE, and power line VL. Thus, the outer coating 115 can planarize the top surface of the structure disposed thereunder (e.g., the source electrode SE, drain electrode DE, and power line VL). Furthermore, the outer coating 115 may include one or more contact holes. The outer coating 115 can be made of, for example, benzocyclobutene or acrylic-based organic materials, but is not limited thereto.

[0104] As an example, the first reflective electrode RE1 and the second reflective electrode RE2 may be disposed on the outer coating 115, but are not limited thereto. The first reflective electrode RE1 is disposed below the first light-emitting diode LED1 to reflect light emitted from the first light-emitting diode LED1 to the upper part of the substrate 110. As an example, the second reflective electrode RE2 may be electrically connected to the first light-emitting diode LED1 via a third connecting electrode CE3, but are not limited thereto. Furthermore, as an example, the second reflective electrode RE2 may be electrically connected to the driving transistor DT via a second connecting electrode CE2, but are not limited thereto. By combining considerations of light reflection efficiency and resistance, the first reflective electrode RE1 and the second reflective electrode RE2 may comprise various conductive layers. For example, the first reflective electrode RE1 and the second reflective electrode RE2 may use opaque conductive layers such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), or alloys thereof, as well as transparent conductive layers such as indium tin oxide, but are not limited thereto.

[0105] Meanwhile, as an example, the first additional electrode AE1 and the second additional electrode AE2 can be disposed on the outer coating 115. The first additional electrode AE1 and the second additional electrode AE2 can be disposed on the same layer as the first reflective electrode RE1 and the second reflective electrode RE2, but are not limited thereto. Furthermore, the first additional electrode AE1 and the second additional electrode AE2 can be formed of the same material as the first reflective electrode RE1 and the second reflective electrode RE2, but are not limited thereto. As an example, the first additional electrode AE1 and the second additional electrode AE2 can be disposed on different layers from the first reflective electrode RE1 and the second reflective electrode RE2, or the first additional electrode AE1 and the second additional electrode AE2 can be formed of different materials from the first reflective electrode RE1 and the second reflective electrode RE2, but are not limited thereto.

[0106] The first auxiliary electrode AE1 can be connected to the power line VL through the contact hole of the outer coating 115. Furthermore, the first auxiliary electrode AE1 can be electrically connected to the first light-emitting diode LED1 through the first connecting electrode CE1.

[0107] The second auxiliary electrode AE2 can be connected to the drain DE of the driving transistor DT through the contact hole of the outer coating 115. Furthermore, the second auxiliary electrode AE2 can be electrically connected to the second reflective electrode RE2 through the second connecting electrode CE2.

[0108] An adhesive layer AD can be disposed on the first reflective electrode RE1 and the second reflective electrode RE2. The adhesive layer AD can be disposed between one of the first reflective electrode RE1 and the second reflective electrode RE2 and the first light-emitting diode LED1. (Refer to...) Figure 4 In the first sub-pixel SP1, a first light-emitting diode (LED1) is transferred to a first reflective electrode RE1, allowing an adhesive layer AD to be disposed between the first reflective electrode RE1 and the first LED1. Therefore, the first LED1 can be fixed to the first reflective electrode RE1. Thus, as an example, the adhesive layer AD may include protrusions in the area overlapping with the first LED1, but is not limited to this. Therefore, the adhesive layer AD may include steps in the area overlapping with the first reflective electrode RE1. The implementation is not limited to this. As an example, the adhesive layer AD may not include protrusions in the area overlapping with the first LED1, or it may not include steps in the area overlapping with the first reflective electrode RE1. As an example, the adhesive layer AD may have a constant thickness in the area overlapping with the first reflective electrode RE1. For example, the adhesive layer AD may completely cover the first reflective electrode RE1. Specifically, the adhesive layer AD may cover all of the top and side surfaces of the first reflective electrode RE1, but is not limited to this.

[0109] The adhesive layer AD can completely cover the second reflective electrode RE2. Specifically, the adhesive layer AD can cover all of the top and side surfaces of the second reflective electrode RE2. In addition, the adhesive layer AD may also include openings that expose at least a portion of the first additional electrode AE1 and the second additional electrode AE2.

[0110] For example, the adhesive layer AD can be selected from any, but not limited to, adhesive polymers, epoxy resin resists, UV resins, polyimides, acrylates, polyurethanes, and polydimethylsiloxane (PDMS).

[0111] The first light-emitting diode LED1 is disposed on the first reflective electrode RE1. The first light-emitting diode LED1 may include a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and an encapsulation film 126.

[0112] A first semiconductor layer 121 is disposed on the adhesive layer AD, and a second semiconductor layer 123 may be disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may be layers formed by doping an n-type or p-type impurity into a specific material. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may be layers doped with an n-type or p-type impurity in a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). Furthermore, the p-type impurity may be magnesium (Mg), zinc (Zn), and beryllium (Be), and the n-type impurity may be silicon (Si), germanium, and tin (Sn), but are not limited thereto.

[0113] The light-emitting layer 122 may be disposed between the first semiconductor layer 121 and the second semiconductor layer 123. Holes and electrons are supplied from the first semiconductor layer 121 and the second semiconductor layer 123 to the light-emitting layer 122 to emit light. The light-emitting layer 122 may be formed of a single-layer or multiple quantum well (MQW) structure, and may be formed, for example, of indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0114] The first electrode 124 may be disposed on the first semiconductor layer 121. The first electrode 124 may be an electrode that electrically connects the driving transistor DT and the first semiconductor layer 121. As an example, the first electrode 124 may be disposed on the top surface of the first semiconductor layer 121 exposed from the light-emitting layer 122 and the second semiconductor layer 123, but is not limited thereto.

[0115] As an example, the first electrode 124 can be electrically connected to the second reflective electrode RE2 via the third connecting electrode CE3, but is not limited thereto.

[0116] The first electrode 124 may be made of a conductive material (e.g., a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof), but is not limited thereto.

[0117] The second electrode 125 may be disposed on the second semiconductor layer 123. As an example, the second electrode 125 may be disposed on the top surface of the second semiconductor layer 123, but is not limited thereto. The second electrode 125 may be an electrode that electrically connects the power line VL and the second semiconductor layer 123. The second electrode 125 may be electrically connected to the power line VL via the first connection electrode CE1.

[0118] The second electrode 125 may be made of a conductive material (e.g., a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof), but is not limited thereto.

[0119] Next, an encapsulation film 126 can be provided surrounding the first semiconductor layer 121, the light-emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The encapsulation film 126 is formed of an insulating material to protect the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123. Furthermore, contact holes are formed in the encapsulation film 126 to expose the first electrode 124 and the second electrode 125, electrically connecting the first electrode 124 to the third connecting electrode CE3 and electrically connecting the second electrode 125 to the first connecting electrode CE1. As an example, one contact hole can be formed to expose both the first electrode 124 and the second electrode 125, or two contact holes can be formed to expose the first electrode 124 and the second electrode 125 respectively, but this is not a limitation. As an example, the encapsulation film 126 can be omitted depending on the design.

[0120] Meanwhile, as an example, a portion of the side surface of the first semiconductor layer 121 may be exposed from the encapsulation film 126, but is not limited thereto. The first light-emitting diode (LED1) fabricated on the wafer is separated from the wafer to be transferred onto the display panel PN. However, during the process of separating the first LED1 from the wafer, a portion of the encapsulation film 126 may be torn. For example, during the process of separating the first LED1 from the wafer, a portion of the encapsulation film 126 adjacent to the lower edge of the first semiconductor layer 121 of the first LED1 may be torn. Therefore, the lower portion of the side surface of the first semiconductor layer 121 may be exposed to the outside. However, even if the lower portion of the first LED1 is exposed from the encapsulation film 126, the first connection electrode CE1 and the third connection electrode CE3 are formed after the formation of the first planarization layer PAC1 and the second planarization layer PAC2 covering the side surface of the first semiconductor layer 121. Therefore, short-circuit defects can be reduced.

[0121] In the first sub-pixel SP1, a first planarization layer PAC1 can be disposed on the first reflective electrode RE1 and the second reflective electrode RE2. As an example, the first planarization layer PAC1 can be disposed on the adhesive layer AD, but is not limited thereto. The first planarization layer PAC1 can be configured to surround the side surface of the first light-emitting diode LED1. Specifically, the first planarization layer PAC1 can contact at least a portion of the side surface of the first light-emitting diode LED1. As an example, the first planarization layer PAC1 can contact at least the portion of the side surface of the first light-emitting diode LED1 exposed from the encapsulation film 126, but is not limited thereto. Therefore, the first planarization layer PAC1 can fix and protect the first light-emitting diode LED1.

[0122] As an example, the maximum height of the first planarization layer PAC1 may be less than the maximum height of the first light-emitting diode LED1, but is not limited thereto. As an example, the maximum height of the first planarization layer PAC1 may be lower than the top surface of the second electrode 125 of the first light-emitting diode LED1. As an example, the closer to the first light-emitting diode LED1, the greater the height of the first planarization layer PAC1, but is not limited thereto. As an example, the first planarization layer PAC1 may have a constant height. As an example, the maximum height of the first planarization layer PAC1 may be equal to or greater than the maximum height of the first light-emitting diode LED1. In this case, as an example, contact holes may be formed in the first planarization layer PAC1 to expose the first electrode 124 or the second electrode 125.

[0123] The first planarization layer PAC1 may not overlap with the top surface of the first light-emitting diode LED1. For example, the first planarization layer PAC1 may not overlap with the top surfaces of the first electrode 124 and the second electrode 125 of the first light-emitting diode LED1.

[0124] As an example, the first planarization layer PAC1 may include a recess in the region overlapping with the second reflective electrode RE2, but is not limited thereto. Therefore, the first planarization layer PAC1 may form a step in the region overlapping with the second reflective electrode RE2. The implementation is not limited thereto. As an example, the first planarization layer PAC1 may not include a recess in the region overlapping with the second reflective electrode RE2. As an example, the first planarization layer PAC1 may have a constant thickness in the region overlapping with the second reflective electrode RE2.

[0125] The first planarization layer PAC1 may include openings that expose the first additional electrode AE1 and the second additional electrode AE2. In this case, the openings of the first planarization layer PAC1 are formed to overlap with and be continuous with the openings of the adhesive layer AD. Therefore, a portion of the top surfaces of the first additional electrode AE1 and the second additional electrode AE2 can be exposed through the openings of the first planarization layer PAC1 and the adhesive layer AD.

[0126] For example, the first planarization layer PAC1 may be composed of benzocyclobutene or an acrylic-based organic material, but is not limited thereto.

[0127] A second planarization layer PAC2 can be disposed on the first planarization layer PAC1. The second planarization layer PAC2 can be spaced apart from the first light-emitting diode LED1 on the first planarization layer PAC1. As an example, the second planarization layer PAC2 can expose the portion of the top surface of the first planarization layer PAC1 adjacent to the first light-emitting diode LED1.

[0128] As an example, the second planarization layer PAC2 may also be disposed on a portion of the top surface of the first light-emitting diode LED1, but is not limited thereto. For example, the second planarization layer PAC2 may be disposed on the first light-emitting diode LED1 between the first electrode 124 and the second electrode 125. However, the second planarization layer PAC2 may not overlap with the first electrode 124 and the second electrode 125 of the first light-emitting diode LED1.

[0129] The second planarization layer PAC2 may cover the side surface of the first planarization layer PAC1. For example, the second planarization layer PAC2 may fill the openings in the first planarization layer PAC1 and the adhesive layer AD that expose the first additional electrode AE1 and the second additional electrode AE2. Furthermore, the second planarization layer PAC2 may include contact holes to connect the first connecting electrode CE1 and the second connecting electrode CE2 to the first additional electrode AE1 and the second additional electrode AE2.

[0130] Furthermore, as an example, the second planarization layer PAC2 may include an opening in the region overlapping with the second reflective electrode RE2, but is not limited thereto. As an example, the opening of the second planarization layer PAC2 may overlap with a recess in the first planarization layer PAC1. Therefore, as an example, at least a portion or all of the recess in the first planarization layer PAC1 may be exposed through the opening in the second planarization layer PAC2. As an example, the second planarization layer PAC2 may cover the step of the recess in the first planarization layer PAC1, but is not limited thereto.

[0131] As an example, a conductive layer CL is disposed on the first planarization layer PAC1. For example, the conductive layer CL may be disposed in a recess of the first planarization layer PAC1 exposed by an opening in the second planarization layer PAC2. As an example, the conductive layer CL may overlap with the second reflective electrode RE2. Furthermore, the conductive layer CL may be disposed in an opening in the second planarization layer PAC2. The implementation is not limited to this. As an example, the conductive layer CL may not overlap with the second reflective electrode RE2. As an example, the conductive layer CL may be disposed in a recess of the first planarization layer PAC1 exposed by an opening in the second planarization layer PAC2 and may extend to the peripheral region of the recess in the first planarization layer PAC1. As an example, at least a portion of the conductive layer CL may be disposed between the second planarization layer PAC2 and the first planarization layer PAC1, but this is not a limitation.

[0132] As an example, the width of the conductive layer CL can be smaller than the width of the recess in the first planarization layer PAC1, but is not limited thereto. Furthermore, as an example, the width of the conductive layer CL can be smaller than the width of the second reflective electrode RE2, but is not limited thereto. As an example, the conductive layer CL can be spaced apart from the step of the recess in the first planarization layer PAC1. Furthermore, as an example, the conductive layer CL can be spaced apart from the second planarization layer PAC2. As an example, the entire conductive layer CL can be disposed within the opening of the second planarization layer PAC2, but is not limited thereto. As an example, the entire conductive layer CL can overlap with the second reflective electrode RE2, but is not limited thereto.

[0133] The conductive layer CL can be made of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited to these.

[0134] As an example, an insulating pattern IDP can be set on the conductive layer CL.

[0135] As an example, the insulating pattern IDP can be spaced apart from the second planarization layer PAC2. As an example, the width of the insulating pattern IDP decreases upwards, but is not limited to this. The width of the bottom surface of the insulating pattern IDP can be smaller than the width of the conductive layer CL. As an example, the insulating pattern IDP may not completely cover the conductive layer CL. Therefore, a portion of the top surface of the conductive layer CL can be exposed by the insulating pattern IDP. As an example, a portion of the top surface of the conductive layer CL can be exposed on both sides of the insulating pattern IDP, but is not limited to this.

[0136] As an example, the insulating pattern IDP can be formed in the same process step as the second planarization layer PAC2. As an example, the insulating pattern IDP can include the same material as the second planarization layer PAC2, but is not limited thereto. The implementation is not limited thereto. As an example, the insulating pattern IDP can be formed in different process steps as the second planarization layer PAC2, and / or, the insulating pattern IDP can include different materials as the second planarization layer PAC2, but is not limited thereto. As an example, the insulating pattern IDP can be omitted depending on the design. (Refer to...) Figures 7A to 7G Describe in detail the manufacturing process of the insulating pattern IDP.

[0137] As an example, the height of the top surface of the insulating pattern IDP can be lower than the height of the top surface of the second planarization layer PAC2. For example, the first planarization layer PAC1 can be disposed below the second planarization layer PAC2, allowing the top surface of the second planarization layer PAC2 to be higher. Conversely, the insulating pattern IDP is disposed on a recess of the first planarization layer PAC1, which can be disposed on the second reflective electrode RE2. Therefore, when the insulating pattern IDP and the second planarization layer PAC2 are formed using the same process, the heights of the top surfaces of the insulating pattern IDP and the second planarization layer PAC2 can differ from each other depending on the height of the first planarization layer PAC1, which can be disposed below it. The implementation is not limited to this. As an example, the height of the top surface of the insulating pattern IDP can be equal to or higher than the height of the top surface of the second planarization layer PAC2. As an example, the height of the top surface of the conductive layer CL can be less than, equal to, or greater than the thickness of the recess of the first planarization layer PAC1, but is not limited to this.

[0138] The first connecting electrode CE1, the second connecting electrode CE2, and the third connecting electrode CE3 are disposed on the second planarization layer PAC2 and the insulating pattern IPD.

[0139] The first connecting electrode CE1 electrically connects the power line VL to the first light-emitting diode LED1. Specifically, the first connecting electrode CE1 can be connected to a first auxiliary electrode AE1, which is connected to the power line VL through a contact hole in the second planarization layer PAC2. Furthermore, the first connecting electrode CE1 can be connected to the second electrode 125 of the first light-emitting diode LED1.

[0140] The third connecting electrode CE3 electrically connects the first light-emitting diode LED1 to the conductive layer CL. Specifically, the third connecting electrode CE3 can electrically connect the first electrode 124 of the first light-emitting diode LED1 to the conductive layer CL.

[0141] The third connecting electrode CE3 may contact the conductive layer CL exposed near the insulating pattern IDP (e.g., on one side of the insulating pattern IDP). For example, the third connecting electrode CE3 extends along the side surface of the second planarization layer PAC2 adjacent to the insulating pattern IDP and the recess of the first planarization layer PAC1 to contact the exposed conductive layer CL. Furthermore, as an example, the third connecting electrode CE3 may extend along the side surface of the insulating pattern IDP to the top surface of the insulating pattern IDP, but is not limited thereto. As an example, the third connecting electrode CE3 may extend only to the conductive layer CL exposed near the insulating pattern IDP, or only to the side surface of the insulating pattern IDP without extending to the top surface of the insulating pattern IDP.

[0142] The first connecting electrode CE1 and the third connecting electrode CE3 can be spaced apart from each other on the second planarization layer PAC2 that overlaps with the first light-emitting diode LED1.

[0143] The second connection electrode CE2 electrically connects the conductive layer CL to the driving transistor DT. Although in Figure 4 The diagram illustrates a second connection electrode CE2 electrically connecting the conductive layer CL to the drain DE of the driving transistor DT, but is not limited thereto. For example, the second connection electrode CE2 can electrically connect the conductive layer CL to the source SE of the driving transistor DT.

[0144] The second connection electrode CE2 can contact the top surface of the second additional electrode AE2 connected to the driving transistor DT through the contact hole of the second planarization layer PAC2. The implementation is not limited to this. As an example, the second connection electrode CE2 can be directly connected to the driving transistor DT without the second additional electrode AE2.

[0145] The second connecting electrode CE2 extends along the side surface of the second planarization layer PAC2 adjacent to the insulating pattern IDP and the recess of the first planarization layer PAC1 to contact the exposed conductive layer CL. Furthermore, as an example, the second connecting electrode CE2 may extend along the side surface of the insulating pattern IDP to the top surface of the insulating pattern IDP, or only to the conductive layer CL exposed near the insulating pattern IDP, or only to the side surface of the insulating pattern IDP without extending to the top surface of the insulating pattern IDP.

[0146] As an example, the second connecting electrode CE2 and the third connecting electrode CE3 may be spaced apart from each other on the insulating pattern IDP, but are not limited thereto.

[0147] As mentioned above, in Figure 4 For ease of description, an example has been described in which the first light-emitting diode LED1 is disposed on the first reflective electrode RE1. However, this disclosure is not limited thereto, and the first light-emitting diode LED1 is disposed on the second reflective electrode RE2, while the light-emitting diode that needs to be disposed on the first reflective electrode may not be moved or may be missing.

[0148] When the first light-emitting diode (LED1) is disposed on the second reflective electrode RE2 and the LED that needs to be disposed on the first reflective electrode is not moved or is missing, the conductive layer CL can be disposed on the first reflective electrode RE1. In this case, except for the change in the position of the conductive layer CL and the first light-emitting diode (LED1), the other components are the same as described above.

[0149] For example, the first connection electrode CE1, connected to the power line VL, can be electrically connected to the conductive layer CL. The second connection electrode CE2, connected to the driving transistor DT, can be electrically connected to the first electrode 124 of the first light-emitting diode LED1. Then, the third connection electrode CE3 can electrically connect the second electrode 125 of the first light-emitting diode LED1 to the conductive layer CL.

[0150] As an example, optionally, a black matrix BM may be provided on the first connecting electrode CE1, the second connecting electrode CE2, and the third connecting electrode CE3, but is not limited thereto. As an example, the black matrix BM may be omitted from one or more of the first connecting electrode CE1, the second connecting electrode CE2, and the third connecting electrode CE3, but is not limited thereto.

[0151] The black matrix BM can be positioned at a predetermined interval from the first light-emitting diode LED1 and the insulating pattern IDP. The black matrix BM can be disposed along the contact holes of the second planarization layer PAC2. The black matrix BM can be formed of an opaque material to reduce color mixing between multiple sub-pixels SP, and can be formed, for example, of black resin, but is not limited thereto.

[0152] The third flattening layer, PAC3, can be set on the black matrix BM.

[0153] The third planarization layer PAC3 covers the lower structure including the first light-emitting diode LED1 to protect these structures. The third planarization layer PAC3 may consist of a single layer, a double layer, or multiple layers, and may be formed, for example, from a photoresist or an acrylic-based organic material, but is not limited thereto.

[0154] Next, we will refer to Figure 5 and Figure 6 This describes the second sub-pixel in which the light-emitting diode transitions normally.

[0155] Figure 5 This is a circuit diagram of a second sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 6 This is a cross-sectional view of a second sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0156] First, refer to Figure 5 The second sub-pixel SP2 includes a second light-emitting diode (LED2) and a third light-emitting diode (LED3). The second LED2 and the third LED3 can be connected in series. For example, the anode of the second LED2 can be connected to a high-potential voltage line VL1, and the cathode can be connected to the anode of the third LED3. Furthermore, the cathode of the third LED3 can be connected to the sixth transistor T6 via a fourth node N4.

[0157] Figure 5 The pixel circuit of the second sub-pixel SP2 and Figure 3 The only difference in the pixel circuit of the first sub-pixel SP1 is the number of light-emitting diodes, so redundant descriptions will be omitted or given briefly.

[0158] Next, refer to Figure 6 In addition to Figure 6 In the second sub-pixel SP2, the second light-emitting diode LED2 is disposed on the third reflective electrode RE3 and the third light-emitting diode LED3 is disposed on the fourth reflective electrode RE4, in addition to the components being... Figure 4 The components of the first sub-pixel SP1 are essentially the same. Therefore, redundant descriptions will be omitted or given only briefly. As an example, unless the specific description is set for the components in the second sub-pixel SP2, the same content as described for the first sub-pixel SP1 can be applied.

[0159] Specifically, in the second sub-pixel SP2, the second light-emitting diode LED2 and the third light-emitting diode LED3 can be positioned above the third reflective electrode RE3 and the fourth reflective electrode RE4.

[0160] Similar to the first light-emitting diode LED1, the second light-emitting diode LED2 and the third light-emitting diode LED3 can be fixed to the third reflective electrode RE3 and the fourth reflective electrode RE4 by the adhesive layer AD.

[0161] The second LED (LED2) and the third LED (LED3) can emit light of the same color. For example, if the second LED (LED2) is a red LED emitting red light, then the third LED (LED3) can also be a red LED. In this case, the second sub-pixel SP2 can be a red sub-pixel RSP. If the second LED (LED2) is a green LED emitting green light, then the third LED (LED3) can also be a green LED. In this case, the second sub-pixel SP2 can be a green sub-pixel GSP. If the second LED (LED2) is a blue LED emitting blue light, then the third LED (LED3) can also be a blue LED. In this case, the second sub-pixel SP2 can be a blue sub-pixel BSP.

[0162] Meanwhile, as an example, either the second LED2 or the third LED3 can be a primary (main) LED, and the other can be a redundant LED, but is not limited to this. The redundant LED can be an additional LED transferred in preparation for a defect in the primary LED. If the primary LED is defective, the redundant LED can be used instead. Therefore, transferring both the primary and redundant LEDs together to a single sub-pixel reduces or minimizes the degradation in display quality caused by defects in either the primary or redundant LED.

[0163] In the second sub-pixel, the second light-emitting diode (LED2) and the third light-emitting diode (LED3) can be fixed to the third reflective electrode (RE3) and the fourth reflective electrode (RE4) via an adhesive layer (AD). The adhesive layer AD may include protrusions in the region overlapping with the second light-emitting diode (LED2). Furthermore, the adhesive layer AD may include protrusions in the region overlapping with the third light-emitting diode (LED3). Therefore, in the second sub-pixel SP2, the adhesive layer AD may include multiple protrusions. Additionally, the adhesive layer AD may include steps in the region overlapping with the third reflective electrode (RE3). Furthermore, the adhesive layer AD may include steps in the region overlapping with the fourth reflective electrode (RE4).

[0164] In the second sub-pixel SP2, the first planarization layer PAC1 can be configured to surround the side surfaces of the second light-emitting diode LED2 and the third light-emitting diode LED3. Therefore, the first planarization layer PAC1 can contact at least a portion of the side surfaces of the second light-emitting diode LED2 and the third light-emitting diode LED3. As an example, the first planarization layer PAC1 can fill the space between the second light-emitting diode LED2 and the third light-emitting diode LED3, but is not limited thereto.

[0165] The first planarization layer PAC1 may not overlap with the top surfaces of the second LED2 and the third LED3. As an example, the maximum height of the first planarization layer PAC1 may be lower than the maximum height of the second LED2 and the third LED3, but is not limited thereto. For example, the maximum height of the first planarization layer PAC1 may be lower than the first electrode 124 and the second electrode 125 of each of the second LED2 and the third LED3. As an example, the height of the top surface of the first planarization layer PAC1 may decrease as it moves away from each of the second LED2 and the third LED3, but is not limited thereto.

[0166] In the second sub-pixel SP2, the second planarization layer PAC2 can be disposed on the first planarization layer PAC1. The second planarization layer PAC2 can be configured to be spaced apart from the second light-emitting diode LED2 and the third light-emitting diode LED3.

[0167] The second planarization layer PAC2 may overlap with a portion of the top surface of the second light-emitting diode LED2 and the third light-emitting diode LED3. In this case, the second planarization layer PAC2 may not overlap with the first electrode 124 and the second electrode 125 of each of the second light-emitting diodes LED2 and LED3.

[0168] The second planarization layer PAC2 may cover the side surface of the first planarization layer PAC1. The second planarization layer PAC2 may fill the openings formed in the adhesive layer AD and the first planarization layer PAC1 to expose a portion of the top surfaces of the first additional electrode AE1 and the second additional electrode AE2. However, the second planarization layer PAC2 may include multiple contact holes to allow the fourth connecting electrode CE4 and the fifth connecting electrode CE5 to connect to the first additional electrode AE1 and the second additional electrode AE2.

[0169] A fourth connecting electrode CE4, a fifth connecting electrode CE5, and a sixth connecting electrode CE6 are disposed on the second planarization layer PAC2.

[0170] The fourth connecting electrode CE4 is electrically connected to the power line VL. The fourth connecting electrode CE4 can electrically connect the power line VL to the second light-emitting diode LED2. For example, the fourth connecting electrode CE4 can electrically connect the power line VL and the second electrode 125 of the second light-emitting diode LED2. The fourth connecting electrode CE4 extends along a portion of a plurality of contact holes in the second planarization layer PAC2 to contact the first additional electrode AE1 connected to the power line VL.

[0171] The fifth connection electrode CE5 can electrically connect the driving transistor DT to the third light-emitting diode LED3. For example, the fifth connection electrode CE5 can electrically connect the drain DE of the driving transistor DT to the first electrode 124 of the third light-emitting diode LED3. The fifth connection electrode CE5 extends along another portion of the plurality of contact holes in the second planarization layer PAC2 to contact the second additional electrode AE2 connected to the driving transistor DT.

[0172] The sixth connecting electrode CE6 can electrically connect the second light-emitting diode LED2 and the third light-emitting diode LED3. For example, the sixth connecting electrode CE6 can electrically connect the first electrode 124 of the second light-emitting diode LED2 and the second electrode 125 of the third light-emitting diode LED3.

[0173] The fourth connecting electrode CE4 and the sixth connecting electrode CE6 can be spaced apart from each other on the second planarization layer PAC2 that overlaps with the second light-emitting diode LED2. Furthermore, the fifth connecting electrode CE5 and the sixth connecting electrode CE6 can be spaced apart from each other above the second planarization layer PAC2 that overlaps with the third light-emitting diode LED3.

[0174] In the following text, reference will be made to Figures 7A to 7G A method for manufacturing a first sub-pixel of a display device according to an exemplary embodiment of the present disclosure is described in detail.

[0175] Figures 7A to 7G This is a process diagram illustrating a method for manufacturing a first sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0176] First, refer to Figure 7A The first auxiliary electrode AE1, the second auxiliary electrode AE2, the first reflective electrode RE1, and the second reflective electrode RE2 can be disposed on the substrate 110. Furthermore, a material for forming the adhesive layer AD is coated on the first auxiliary electrode AE1, the second auxiliary electrode AE2, the first reflective electrode RE1, and the second reflective electrode RE2 to form the adhesive layer AD.

[0177] The first light-emitting diode (LED1) can be transferred to the region overlapping the first reflective electrode RE1 on the coated adhesive layer AD. At this time, in the region overlapping the second reflective electrode RE2, the LED may not be transferred or may be missing. After transferring the first LED1, a process for initial etching of the adhesive layer AD can be performed. This etches the region of the adhesive layer AD excluding the region overlapping the first LED1. Therefore, a protrusion can be formed in the adhesive layer AD in the region overlapping the first LED1.

[0178] Next, the material used to form the first planarization layer PAC1 is coated onto the adhesive layer AD to form the first planarization layer PAC1. At this time, the material used to form the first planarization layer PAC1 can cover the upper part of the first light-emitting diode LED1. Then, an initial etching process of the first planarization layer PAC1 can be performed to expose the adhesive layer AD in the area overlapping with the first additional electrode AE1 and the second additional electrode AE2.

[0179] Next, a pattern mask PM is provided in the region that overlaps with at least a portion of the first auxiliary electrode AE1, the second auxiliary electrode AE2, the first light-emitting diode LED1, and the second reflective electrode RE2, and a negative etching process can be performed.

[0180] Therefore, as Figure 7B As shown, the top surface of the first light-emitting diode LED1 is exposed, and a recess in the first planarization layer PAC1 can be formed in the region overlapping with the second reflective electrode RE2. Furthermore, the adhesive layer AD overlapping with the first additional electrode AE1 and the second additional electrode AE2 can be etched. Therefore, the first additional electrode AE1 and the second additional electrode AE2 can be exposed.

[0181] Meanwhile, although the etching process for the first planarization layer PAC1 has been described in this specification as negative etching, this disclosure is not limited thereto. For example, the first planarization layer PAC1 can also be etched using a positive etching process. In this case, the pattern mask can be set in an area other than the area to be etched.

[0182] Next, refer to Figure 7C The process of placing the conductive layer CL on the first planarization layer PAC1 can be performed. Furthermore, the pattern mask PM' is disposed in the area overlapping with the second reflective electrode RE2, and a forward etching process can be performed there.

[0183] Therefore, as Figure 7D As shown, the conductive layer CL is only retained on the second reflective electrode RE2, and the conductive layer CL can be removed from all other areas.

[0184] Next, refer to Figure 7E A process for placing a second planarization layer PAC2 on the first planarization layer PAC1 can be performed. Furthermore, after placing the second planarization layer PAC2, an etching process for exposing the first electrode 124 and the second electrode 125 of the first light-emitting diode LED1 can be performed. During this etching process, in order to suppress the electrical connection between the first electrode 124 and the second electrode 125 of the first light-emitting diode LED1, the second planarization layer PAC2 is patterned so that a portion of the second planarization layer PAC2 remains on the first light-emitting diode LED1 between the first electrode 124 and the second electrode 125. At this time, under normal circumstances, the light-emitting diode is also disposed on the second reflective electrode RE2, so the etching process of the second planarization layer PAC2 can be performed by assuming that the light-emitting diode is normally disposed on the second reflective electrode RE2. When the light-emitting diode is normally transferred to the second reflective electrode RE2, similar to the first light-emitting diode LED1, the second planarization layer PAC2 is patterned so that it is also partially retained between the first and second electrodes on the transferred light-emitting diode. However, in the first sub-pixel SP1 according to an exemplary embodiment of this disclosure, the light-emitting diode is not transferred to the second reflective electrode RE2 or is missing. Therefore, a second planarization layer PAC2 needs to be retained on the light-emitting diode between the first and second electrodes. Figure 7D An insulating pattern IDP is formed on the conductive layer CL disposed in the region overlapping with the second reflective electrode RE2. Therefore, the insulating pattern IDP can be spaced apart from the second planarization layer PAC2. As an example, the insulating pattern IDP can expose the conductive layer CL on both sides of the insulating pattern IDP, but is not limited to this. As an example, the insulating pattern IDP can be disposed at the central portion of the conductive layer CL, or disposed offset from the central portion of the conductive layer CL. As an example, the insulating pattern IDP can be offset from the central portion of the conductive layer CL in the same direction as the direction in which the reserved portion of the second planarization layer PAC2 between the first electrode 124 and the second electrode 125 on the first light-emitting diode LED1 is offset from the central portion of the first light-emitting diode LED1, but is not limited to this. As an example, the size of the insulating pattern IDP can be similar to or different from the size of the reserved portion of the second planarization layer PAC2 between the first electrode 124 and the second electrode 125 on the first light-emitting diode LED1, but is not limited to this. Furthermore, contact holes for partially exposing the first additional electrode AE1 and the second additional electrode AE2 can be formed together on the second planarization layer PAC2 using the same process.

[0185] Next, a process can be performed to place the first connecting electrode CE1, the second connecting electrode CE2, and the third connecting electrode CE3 on the second planarization layer PAC2. At this time, the first connecting electrode CE1 can be configured to connect to the second electrode 125 of the first light-emitting diode (LED1). Furthermore, the third connecting electrode CE3 can be configured to connect to the first electrode 124. However, the first electrode 124 and the second electrode 125 of the first LED1 should not be electrically connected to each other. Therefore, the first connecting electrode CE1 and the third connecting electrode CE3 can be configured to be spaced apart from each other on the second planarization layer PAC2 formed on the first LED1. Meanwhile, as described above, under normal circumstances, the LED should be normally disposed on the second reflective electrode RE2, so the process can be performed by assuming that the LED is normally transferred to the second reflective electrode RE2. If it is assumed that the LED is normally transferred to the second reflective electrode RE2, then the third connecting electrode CE3 is connected to the second electrode of the LED, and the second connecting electrode CE2 is connected to the first electrode of the LED. Therefore, the third connecting electrode CE3 and the second connecting electrode CE2 can be configured to be spaced apart from each other. However, in the first sub-pixel SP1 according to an exemplary embodiment of this disclosure, the light-emitting diode is not transferred or is missing on the second reflective electrode RE2, so an insulating pattern IDP can be formed on the second reflective electrode RE2 instead of a light-emitting diode. Therefore, the third connecting electrode CE3 and the second connecting electrode CE2 can be configured to be spaced apart from each other on the insulating pattern IDP. Furthermore, each of the third connecting electrode CE3 and the second connecting electrode CE2 can be configured to contact the conductive layer CL exposed near the insulating pattern IDP (e.g., respectively on both sides of the insulating pattern IDP, but not limited thereto). During this process, the third connecting electrode CE3 and the second connecting electrode CE2 can be electrically connected through the conductive layer CL. Therefore, even if the light-emitting diode is not transferred or is missing on the second reflective electrode RE2, the first electrode 124 of the first light-emitting diode LED1 and the driving transistor DT can be electrically connected. As an example, the third connecting electrode CE3 and the second connecting electrode CE2 can be configured to be connected to each other and / or overlap each other on the insulating pattern IDP, but are not limited thereto. As an example, the recessed portions of the insulating pattern IDP, the conductive layer CL, and / or the first planarization layer PAC1 can be omitted, but are not limited thereto. As an example, the third connecting electrode CE3 and the second connecting electrode CE2 can be directly connected to each other on the conductive layer CL, or directly connected to each other without the conductive layer CL, but are not limited thereto. As an example, the third connecting electrode CE3 and the second connecting electrode CE2 can overlap each other on the conductive layer CL or the first planarization layer PAC1, but are not limited thereto.

[0186] Next, refer to Figure 7FThe process of placing the black matrix BM on the first connecting electrode CE1, the second connecting electrode CE2, and the third connecting electrode CE3 can be performed. In this case, the black matrix BM can be configured to be spaced apart from the first light-emitting diode LED1 and the insulating pattern IDP, so as not to overlap with them.

[0187] Finally, refer to Figure 7G The manufacturing process of the first sub-pixel SP1 of the display device 100 can be completed by coating a material on the black matrix BM to form the third planarization layer PAC3.

[0188] Meanwhile, a display device using micro-LEDs as light-emitting diodes can be manufactured by forming multiple micro-LEDs on a wafer and transferring the micro-LEDs onto a substrate of the display device. However, various defects may occur during the process of transferring multiple micro-LEDs with tiny dimensions from the wafer to the substrate. For example, in some sub-pixels, defects such as untransferred or missing micro-LEDs may occur. Therefore, taking into account the defects during the transfer process of multiple micro-LEDs, multiple micro-LEDs emitting the same color of light can be transferred in a single sub-pixel.

[0189] As described above, when multiple micro-LEDs are transferred within a sub-pixel, these micro-LEDs are connected in parallel, ensuring that even if one micro-LED fails to transfer or is missing, the other micro-LEDs can still be driven normally. However, when multiple micro-LEDs are connected in parallel, there is a problem of increased power consumption for driving the display device.

[0190] As mentioned above, to suppress increased power consumption, multiple micro-LEDs can be connected in series within a sub-pixel. However, if multiple micro-LEDs are connected in series, when a defect occurs where any micro-LED fails to transfer or is missing, another micro-LED will not be electrically connected, causing the corresponding sub-pixel to become a dark spot, thereby reducing the reliability of the display device. Therefore, to repair a sub-pixel that has become a dark spot so that it can operate as a normal pixel, the problem lies in the additional need for a separate repair process to connect the wiring at the location of the defect.

[0191] Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, when a defect occurs in a sub-pixel SP1 where a light-emitting diode is not transferred or is missing, a conductive layer CL is disposed on the second reflective electrode RE2 where no light-emitting diode is disposed. Furthermore, the conductive layer CL, the normally transferred first light-emitting diode LED1, the driving transistor DT, or the power line VL can be electrically connected respectively. Therefore, the area where the light-emitting diode was not transferred can be automatically repaired during the manufacturing process without a separate repair process.

[0192] As described above, in the display device 100 according to an exemplary embodiment of the present disclosure, automatic electrical connection of another light-emitting diode is achieved in a sub-pixel SP1 including a region where one light-emitting diode has not been transferred. Therefore, the first sub-pixel SP1, which is a dark spot, can operate as a normal sub-pixel without a separate repair process. Therefore, the display device 100 according to the exemplary embodiment of the present disclosure does not require a separate repair process, thereby shortening the process time and improving the process efficiency.

[0193] Furthermore, in the display device 100 according to an exemplary embodiment of the present disclosure, a plurality of light-emitting diodes LED2 and LED3 disposed in a sub-pixel SP2 can be connected in series. Therefore, the power consumption consumed in driving the display device 100 can be reduced.

[0194] Figure 8 This is a cross-sectional view of a first sub-pixel of a display device according to another exemplary embodiment of the present disclosure. In addition to including an additional black matrix BM' between the first planarization layer PAC1 and the second planarization layer PAC2, Figure 8 The components of the first sub-pixel SP1 and Figure 4 The components of the first sub-pixel SP1 are basically the same. Therefore, redundant descriptions will be omitted or given only briefly.

[0195] Reference Figure 8 An additional black matrix BM' can be set on the first planarization layer PAC1. An additional black matrix BM' can be set between the first planarization layer PAC1 and the second planarization layer PAC2. The additional black matrix BM' can cover the top and side surfaces of the first planarization layer PAC1.

[0196] The additional black matrix BM' can be configured to surround the side surface of the first light-emitting diode LED1. Specifically, the additional black matrix BM' can contact at least a portion of the side surface of the first light-emitting diode LED1. The maximum height of the additional black matrix BM' can be less than the maximum height of the first light-emitting diode LED1. For example, the maximum height of the additional black matrix BM' can be lower than the top surface of the second electrode 125 of the first light-emitting diode LED1. The closer to the first light-emitting diode LED1, the greater the height of the additional black matrix BM'.

[0197] The additional black matrix BM' may not overlap with the top surface of the first light-emitting diode LED1. For example, the additional black matrix BM' may not overlap with the top surfaces of the first electrode 124 and the second electrode 125 of the first light-emitting diode LED1.

[0198] The additional black matrix BM' may include multiple openings. The first connecting electrode CE1 and the first additional electrode AE1 can be connected through multiple openings. In addition, the second connecting electrode CE2 and the second additional electrode AE2 can be connected through multiple openings.

[0199] As an example, the additional black matrix BM' can be formed from black resin, but is not limited to this.

[0200] As an example, the conductive layer CL can be disposed on the additional black matrix BM'. Specifically, the conductive layer CL can be configured to contact the top surface of the additional black matrix BM' in the region overlapping with the second reflective electrode RE2.

[0201] Furthermore, a second planarization layer PAC2 can be disposed on the additional black matrix BM'. Therefore, the second planarization layer PAC2 and the conductive layer CL can be disposed on the same layer. The second planarization layer PAC2 can be configured to be spaced apart from the first light-emitting diode LED1. Therefore, the second planarization layer PAC2 can expose the portion of the top surface of the additional black matrix BM' adjacent to the first light-emitting diode LED1.

[0202] The second planarization layer PAC2 may include contact holes through openings in the additional black matrix BM'. Therefore, the first connecting electrode CE1 can contact the first additional electrode AE1 through the contact holes in the second planarization layer PAC2. Furthermore, the second connecting electrode CE2 can contact the second additional electrode AE2.

[0203] Figure 9 This is a cross-sectional view of a second sub-pixel of a display device according to another exemplary embodiment of the present disclosure. In addition to including an additional black matrix BM' between the first planarization layer PAC1 and the second planarization layer PAC2, Figure 9 The components of the second sub-pixel SP2 and Figure 5 The components of the second sub-pixel SP2 are basically the same. Furthermore, except that the second light-emitting diode LED2 is disposed on the third reflective electrode RE3 and the third light-emitting diode LED3 is disposed on the fourth reflective electrode RE4, Figure 9 The components of the second sub-pixel SP2 and Figure 8 The components of the first sub-pixel SP1 are basically the same. Therefore, redundant descriptions will be omitted or given only briefly.

[0204] Reference Figure 9The first planarization layer PAC1 can be filled between the second light-emitting diode LED2 and the third light-emitting diode LED3. Therefore, the first planarization layer PAC1 can contact the side surfaces of the second light-emitting diode LED2 and the third light-emitting diode LED3. Furthermore, the first planarization layer PAC1 can have a recessed shape in the middle between the second light-emitting diode LED2 and the third light-emitting diode LED3, but is not limited to this. The closer to the second light-emitting diode LED2, the greater the height of the top surface of the first planarization layer PAC1. Furthermore, the closer to the third light-emitting diode LED3, the greater the height of the top surface of the first planarization layer PAC1. The first planarization layer PAC1 may not overlap with the first electrode 124 and the second electrode 125 of the second light-emitting diode LED2 and the third light-emitting diode LED3.

[0205] An additional black matrix BM' can be formed on the first planarization layer PAC1. The additional black matrix BM' can fill the space between the second light-emitting diode LED2 and the third light-emitting diode LED3. Therefore, one end of the additional black matrix BM' contacts the side surface of the second light-emitting diode LED2, while the other end can contact the side surface of the third light-emitting diode LED3. The top surface of the additional black matrix BM' can have a recessed shape in the middle between the second light-emitting diode LED2 and the third light-emitting diode LED3, but is not limited to this. For example, the closer to the second light-emitting diode LED2, the greater the height of the top surface of the additional black matrix BM'. Furthermore, the closer to the third light-emitting diode LED3, the greater the height of the top surface of the additional black matrix BM'. The additional black matrix BM' may not overlap with the first electrode 124 and the second electrode 125 of each of the second light-emitting diode LED2 and the third light-emitting diode LED3.

[0206] The second planarization layer PAC2 can be disposed on the additional black matrix BM'. The second planarization layer PAC2 can be spaced apart from the second light-emitting diode LED2 and the third light-emitting diode LED3. Therefore, the additional black matrix BM' can be exposed in the peripheral portion adjacent to the second light-emitting diode LED2 and the third light-emitting diode LED3. The second planarization layer PAC2 can be partially disposed on each of the second light-emitting diode LED2 and the third light-emitting diode LED3. However, the second planarization layer PAC2 located on the second light-emitting diode LED2 and the third light-emitting diode LED3 may not overlap with the first electrode 124 and the second electrode 125 of each of the second light-emitting diode LED2 and the third light-emitting diode LED3.

[0207] In the following text, reference will be made to Figures 10A to 10G A method for manufacturing a first sub-pixel of a display device according to another exemplary embodiment of the present disclosure is described in detail.

[0208] Figures 10A to 10G This is a process diagram illustrating a method for manufacturing a first sub-pixel of a display device according to another exemplary embodiment of the present disclosure.

[0209] First, refer to Figure 10A The first auxiliary electrode AE1, the second auxiliary electrode AE2, the first reflective electrode RE1, and the second reflective electrode RE2 can be disposed on the substrate 110. Furthermore, a material for forming the adhesive layer AD is coated on the first auxiliary electrode AE1, the second auxiliary electrode AE2, the first reflective electrode RE1, and the second reflective electrode RE2 to form the adhesive layer AD.

[0210] The first light-emitting diode (LED1) can be transferred to the region overlapping the first reflective electrode RE1 on the coated adhesive layer AD. At this time, in the region overlapping the second reflective electrode RE2, the LED may not be transferred or may be missing. After transferring the first LED1, a process for initial etching of the adhesive layer AD can be performed. This etches the region of the adhesive layer AD except for the region overlapping the first LED1. Therefore, a protrusion can be formed in the adhesive layer AD in the region overlapping the first LED1.

[0211] Next, the material used to form the first planarization layer PAC1 is coated onto the adhesive layer AD to form the first planarization layer PAC1. Furthermore, an etching process can be performed. During this process, the adhesive layer AD on the first additional electrode AE1 and the second additional electrode AE2 is etched to expose the first additional electrode AE1 and the second additional electrode AE2.

[0212] Meanwhile, although the etching process for the first planarization layer PAC1 has been described in this specification as negative etching, this disclosure is not limited thereto. For example, the first planarization layer PAC1 can also be etched using a positive etching process. In this case, the pattern mask is set in an area other than the area to be etched.

[0213] Next, a pattern mask PM is formed in the region overlapping at least a portion of the first light-emitting diode LED1 and the second reflective electrode RE2, and a negative etching process can be performed. Thus, as... Figure 10B As shown, the top surface of the first light-emitting diode LED1 is exposed, and a recess can be formed in the region overlapping with the second reflective electrode RE2.

[0214] Next, refer to Figure 10CThe additional black matrix BM' can be formed by coating the first planarization layer PAC1 with a material for forming the additional black matrix BM'. At this time, the additional black matrix BM' can cover the upper part of the first light-emitting diode LED1. Next, a primary etching process can be performed to etch the area overlapping the first light-emitting diode LED1, the first additional electrode AE1, and the second additional electrode AE2. Therefore, the first light-emitting diode LED1, the first additional electrode AE1, and the second additional electrode AE2 can be exposed.

[0215] Next, a process can be performed to place the conductive layer CL on the additional black matrix BM'. Furthermore, a pattern mask PM' is disposed in the region overlapping with the second reflective electrode RE2, and a positive etching process can be performed.

[0216] Therefore, as Figure 10D As shown, the conductive layer CL is only retained on the second reflective electrode RE2, and the conductive layer CL can be removed from all other areas.

[0217] Next, refer to Figure 10E A process for placing the second planarization layer PAC2 can be performed. Furthermore, after placing the second planarization layer PAC2, an etching process for exposing the first electrode 124 and the second electrode 125 of the first light-emitting diode LED1 can be performed. During this etching process, in order to suppress the electrical connection between the first electrode 124 and the second electrode 125 of the first light-emitting diode LED1, the second planarization layer PAC2 can be patterned so that a portion of the second planarization layer PAC2 remains on the first light-emitting diode LED1 between the first electrode 124 and the second electrode 125. At this time, in the normal state, the light-emitting diode is also disposed on the second reflective electrode RE2, so the etching process of the second planarization layer PAC2 can be performed by assuming that the light-emitting diode is normally disposed on the second reflective electrode RE2. When the light-emitting diode is normally transferred to the second reflective electrode RE2, similar to the first light-emitting diode LED1, the second planarization layer PAC2 can be patterned so that it is also partially retained between the first and second electrodes on the transferred light-emitting diode. However, in the first sub-pixel SP1 according to an exemplary embodiment of this disclosure, the light-emitting diode is not transferred to the second reflective electrode RE2 or is missing. Therefore, a second planarization layer PAC2 needs to be retained on the light-emitting diode between the first and second electrodes. Figure 10D An insulating pattern IDP is formed on the conductive layer CL in the region overlapping with the second reflective electrode RE2. Therefore, the insulating pattern IDP can be spaced apart from the second planarization layer PAC2. Furthermore, contact holes for exposing portions of the first additional electrode AE1 and the second additional electrode AE2 can be formed together in the second planarization layer PAC2 using the same process.

[0218] Next, a process can be performed to place the first connecting electrode CE1, the second connecting electrode CE2, and the third connecting electrode CE3 on the second planarization layer PAC2. At this time, the first connecting electrode CE1 can be configured to connect to the second electrode 125 of the first light-emitting diode (LED1). Furthermore, the third connecting electrode CE3 can be configured to connect to the first electrode 124. However, the first electrode 124 and the second electrode 125 of the first LED1 should not be electrically connected to each other. Therefore, the first connecting electrode CE1 and the third connecting electrode CE3 can be configured to be spaced apart from each other on the second planarization layer PAC2 formed on the first LED1. Meanwhile, as described above, under normal circumstances, the LED should be normally disposed on the second reflective electrode RE2, so the process can be performed by assuming that the LED is normally transferred to the second reflective electrode RE2. If it is assumed that the LED is normally transferred to the second reflective electrode RE2, then the third connecting electrode CE3 is connected to the second electrode of the LED, and the second connecting electrode CE2 can be connected to the first electrode of the LED. Therefore, the third connecting electrode and the second connecting electrode CE2 can be configured to be spaced apart from each other. However, in the first sub-pixel SP1 according to an exemplary embodiment of this disclosure, the light-emitting diode is not transferred or is missing from the second reflective electrode RE2, so an insulating pattern IDP can be formed on the second reflective electrode RE2 instead of a light-emitting diode. Therefore, the third connecting electrode CE3 and the second connecting electrode CE2 can be configured to be spaced apart from each other on the insulating pattern IDP. Furthermore, each of the third connecting electrode CE3 and the second connecting electrode CE2 can be configured to contact the conductive layer CL exposed near the insulating pattern IDP. During this process, the third connecting electrode CE3 and the second connecting electrode CE2 can be electrically connected through the conductive layer CL. Therefore, even if the light-emitting diode is not transferred or is missing from the second reflective electrode RE2, the first electrode 124 of the first light-emitting diode LED1 and the driving transistor DT can still be electrically connected.

[0219] Next, refer to Figure 10F The process of placing the black matrix BM on the first connecting electrode CE1, the second connecting electrode CE2, and the third connecting electrode CE3 can be performed. In this case, the black matrix BM can be configured to be spaced apart from the first light-emitting diode LED1 and the insulating pattern IDP, thus avoiding overlap.

[0220] Finally, refer to Figure 10G The manufacturing process of the first sub-pixel SP1 of another display device 200 disclosed herein can be accomplished by coating a material for forming the third planarization layer PAC3 onto the black matrix BM.

[0221] Therefore, in a display device 200 according to another exemplary embodiment of the present disclosure, when a defect occurs in a sub-pixel SP1 where a light-emitting diode is not transferred or is missing, a conductive layer CL is disposed in the area overlapping with the second reflective electrode RE2 where no light-emitting diode is disposed. Furthermore, the normally transferred first light-emitting diode LED1, driving transistor DT, or power line VL can be electrically connected through the conductive layer CL. Therefore, the area where the light-emitting diode was not transferred can be automatically repaired during the manufacturing process without a separate repair process.

[0222] As described above, in another exemplary embodiment of the display device 200 according to the present disclosure, the first sub-pixel SP1, which is a dark spot, can operate as a normal sub-pixel without a separate repair process. Therefore, the display device 200 according to the exemplary embodiment of the present disclosure does not require a separate repair process, thereby further shortening the process time and further improving the process efficiency.

[0223] Furthermore, in another exemplary embodiment of the display device 200 according to this disclosure, a plurality of light-emitting diodes LED2 and LED3 disposed in a sub-pixel SP2 can be connected in series. Therefore, the power consumption consumed in driving the display device 200 can also be reduced.

[0224] Exemplary embodiments of this disclosure can also be described as follows:

[0225] According to one aspect of this disclosure, a display device includes: a substrate defining a plurality of sub-pixels, including a first sub-pixel; a power line disposed on the substrate; a driving transistor disposed on the substrate in the first sub-pixel; a first reflective electrode and a second reflective electrode disposed in the first sub-pixel on the driving transistor; a first light-emitting diode disposed in the first sub-pixel on one of the first and second reflective electrodes; a conductive layer disposed on the other of the first and second reflective electrodes; a first connecting electrode electrically connected to the power line; a second connecting electrode electrically connected to the driving transistor; and a third connecting electrode electrically connected via the conductive layer to one of the first and second connecting electrodes and electrically connected to the first light-emitting diode.

[0226] The display device may further include: an adhesive layer disposed in a first sub-pixel on a first reflective electrode and a second reflective electrode; a first planarization layer disposed on the adhesive layer; a second planarization layer disposed on the first planarization layer; and an insulating pattern disposed on a conductive layer overlapping the conductive layer.

[0227] One of the first and second connecting electrodes may be spaced apart from the third connecting electrode on an insulating pattern.

[0228] One of the first and second connecting electrodes and the third connecting electrode may be in contact with at least a portion of the conductive layer.

[0229] The first planarization layer may include at least one recess, and a conductive layer is disposed in the recess.

[0230] The second planarization layer may include an opening that overlaps with another of the first and second reflective electrodes.

[0231] The conductive layer can be disposed in the opening, and the conductive layer and the second planarization layer can be spaced apart from each other in the opening.

[0232] The insulating pattern may include the same material as the second planarization layer.

[0233] The first planarization layer may contact at least a portion of the side surface of the first light-emitting diode.

[0234] The maximum height of the first planarization layer can be lower than the maximum height of the first light-emitting diode.

[0235] The display device may further include a black matrix disposed on the second planarization layer, the first connecting electrode, the second connecting electrode, and the third connecting electrode.

[0236] The display device may further include a black matrix disposed between a first planarization layer and a second planarization layer, wherein the first connecting electrode, the second connecting electrode and the third connecting electrode may be disposed on the second planarization layer.

[0237] The black matrix can be placed below the conductive layer.

[0238] The black matrix can cover the top and side surfaces of the first planarization layer.

[0239] The plurality of sub-pixels may further include a second sub-pixel, and the second sub-pixel may include: a third reflective electrode and a fourth reflective electrode disposed on the driving transistor; a second light-emitting diode disposed on the third reflective electrode; a third light-emitting diode disposed on the fourth reflective electrode; a fourth connecting electrode electrically connected to a power line; a fifth connecting electrode electrically connected to the driving transistor; and a sixth connecting electrode electrically connected to the second light-emitting diode and the third light-emitting diode.

[0240] The display device may further include: an adhesive layer disposed on the third and fourth reflective electrodes in the second sub-pixel; a first planarization layer disposed on the adhesive layer; and a second planarization layer disposed on the first planarization layer.

[0241] The first planarization layer may contact at least a portion of the side surfaces of the second and third light-emitting diodes, and the maximum height of the first planarization layer may be lower than the maximum height of the top surface of the second or third light-emitting diode.

[0242] The second planarization layer can be spaced apart from the second or third light-emitting diode. The fourth, fifth, and sixth connecting electrodes can be disposed on the second planarization layer, and the black matrix can be disposed on the fourth, fifth, and sixth connecting electrodes.

[0243] The display device may further include a black matrix disposed between the first planarization layer and the second planarization layer, and covering the top surface and side surface of the first planarization layer, wherein the fourth connecting electrode, the fifth connecting electrode and the sixth connecting electrode may be disposed on the second planarization layer.

[0244] According to another aspect of this disclosure, a display device includes: a substrate including a plurality of sub-pixels; a plurality of driving transistors disposed on the substrate in each of the plurality of sub-pixels; a power line disposed on the substrate; a first light-emitting diode disposed in a first sub-pixel of the plurality of sub-pixels; a second light-emitting diode and a third light-emitting diode disposed in a second sub-pixel of the plurality of sub-pixels, emitting light of the same color and connected in series; and a conductive pattern including a conductive layer disposed on a reflective electrode and electrically connecting the first light-emitting diode and the power line or the driving transistors disposed in the first sub-pixel of the plurality of driving transistors, wherein the second light-emitting diode is electrically connected to the driving transistors disposed in the second sub-pixel of the plurality of driving transistors, and the third light-emitting diode is electrically connected to the power line.

[0245] The display device may further include: a first planarization layer disposed on the power lines and a plurality of driving transistors, and surrounding the side surfaces of the first light-emitting diode, the second light-emitting diode and the third light-emitting diode; and a second planarization layer disposed on the first planarization layer.

[0246] The conductive pattern may include: a first connecting electrode connected to a power line or a driving transistor disposed in a first sub-pixel among a plurality of driving transistors; and a third connecting electrode connected to a first light-emitting diode, wherein the first connecting electrode and the third connecting electrode may be in contact with the conductive layer.

[0247] The display device may further include: an insulating layer disposed on the conductive layer to overlap the conductive layer, wherein the first connecting electrode and the third connecting electrode may be spaced apart from each other on the insulating layer.

[0248] The display device may also include a black matrix disposed on a second planarization layer.

[0249] The display device may further include a black matrix disposed between the first planarization layer and the second planarization layer.

[0250] The black matrix can contact the side surfaces of the first, second, and third LEDs, and the maximum height of the top surface of the black matrix can be lower than the maximum height of the top surface of each of the first, second, and third LEDs.

[0251] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

[0252] Cross-references to related applications

[0253] This application claims priority and benefit to Korean Patent Application No. 10-2024-0117028, filed on August 29, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety as if fully set forth herein.

Claims

1. A display device comprising: a substrate in which a plurality of subpixels including a first subpixel are defined; a power supply line provided over the substrate; a first driver transistor provided over the substrate in the first subpixel; a first light-emitting diode provided over the first driver transistor in the first subpixel; a first connection electrode electrically connected to the power supply line; a second connection electrode electrically connected to the first driver transistor; and a third connection electrode electrically connected to one of the first connection electrode and the second connection electrode and electrically connected to the first light-emitting diode.

2. The display device according to claim 1, further comprising: a conductive layer provided over the first driver transistor to horizontally space apart from the first light-emitting diode, wherein the third connection electrode is electrically connected to the one of the first connection electrode and the second connection electrode through the conductive layer.

3. The display device according to claim 2, further comprising: a first reflective electrode and a second reflective electrode provided over the first driver transistor in the first subpixel, wherein the first light-emitting diode is provided over the first reflective electrode, and the conductive layer is provided over the second reflective electrode.

4. The display device according to claim 3, further comprising: an adhesive layer provided over the first reflective electrode and the second reflective electrode in the first subpixel; a first planarization layer provided over the adhesive layer; a second planarization layer provided over the first planarization layer; and an insulating pattern provided to overlap the conductive layer over the conductive layer. the one of the first connection electrode and the second connection electrode is spaced apart from the third connection electrode over the insulating pattern provided to overlap the conductive layer over the conductive layer. the one of the first connection electrode and the second connection electrode and the third connection electrode are in contact with at least a part of the conductive layer.

5. The display device according to claim 2, wherein 7. The display device according to claim 2, further comprising:

6. The display device of claim 5, wherein, an insulating pattern provided to overlap the conductive layer over the conductive layer so that the conductive layer is exposed by the insulating pattern on both sides of the insulating pattern. the one of the first connection electrode and the second connection electrode and the third connection electrode are in contact with the parts of the conductive layer exposed by the insulating pattern on both sides of the insulating pattern, respectively.

9. The display device according to claim 2, further comprising:

8. The display device of claim 7, wherein, a first planarization layer provided over the first driver transistor; and a second planarization layer provided over the first planarization layer. ​ ​ a second planarization layer disposed on the first planarization layer, wherein the conductive layer is disposed on the first planarization layer.

10. The display device of claim 9, wherein, the first planarization layer includes at least one recess, and the conductive layer is disposed in the recess.

11. The display device of claim 9, wherein, the second planarization layer includes an opening overlapping the conductive layer.

12. The display device according to claim 11, further comprising: an insulating pattern disposed to overlap the conductive layer on the conductive layer so that the conductive layer is exposed by the insulating pattern on both sides of the insulating pattern, wherein the insulating pattern is horizontally spaced apart from the second planarization layer.

13. The display device of claim 11, wherein, the conductive layer is disposed in the opening, and the conductive layer and the second planarization layer are horizontally spaced apart from each other in the opening.

14. The display device of claim 12, wherein, the insulating pattern includes the same material as the second planarization layer.

15. The display device of claim 9, wherein, the first planarization layer is in contact with at least a portion of a side surface of the first light emitting diode.

16. The display device of claim 15, wherein, a maximum height of the first planarization layer is lower than a maximum height of the first light emitting diode.

17. The display device according to claim 9, further comprising: a black matrix disposed on the second planarization layer, the first connection electrode, the second connection electrode, and the third connection electrode.

18. The display device according to claim 9, further comprising: a black matrix disposed between the first planarization layer and the second planarization layer, wherein the first connection electrode, the second connection electrode, and the third connection electrode are disposed on the second planarization layer.

19. The display device of claim 18, wherein, the black matrix is disposed under the conductive layer.

20. The display device of claim 19, wherein, the black matrix covers a top surface and a side surface of the first planarization layer.

21. The display device of claim 1, wherein, the other one of the first connection electrode and the second connection electrode is electrically connected to a first electrode of the first light emitting diode, and the third connection electrode is electrically connected to a second electrode of the first light emitting diode.

22. The display device of claim 1, wherein, the plurality of sub-pixels further includes a second sub-pixel, and the second sub-pixel includes: a second drive transistor disposed on the substrate; a second light emitting diode disposed over the second drive transistor; a third light emitting diode disposed over the second drive transistor to be horizontally spaced apart from the second light emitting diode; a fourth connection electrode electrically connected to the power supply line; a fifth connection electrode electrically connected to the second drive transistor; and a sixth connection electrode electrically connected to the second light emitting diode and the third light emitting diode.

23. The display device according to claim 22, further comprising: a third reflective electrode and a fourth reflective electrode disposed on the second drive transistor, wherein the second light emitting diode is disposed over the third reflective electrode, and the third light emitting diode is disposed over the fourth reflective electrode.

24. The display device according to claim 23, further comprising: an adhesive layer provided over the third reflective electrode and the fourth reflective electrode in the second sub-pixel; a first planarization layer provided over the adhesive layer; and a second planarization layer provided over the first planarization layer. the first planarization layer is in contact with at least part of a side surface of the second light-emitting diode and at least part of a side surface of the third light-emitting diode, and a maximum height of the first planarization layer is lower than a maximum height of a top surface of the second light-emitting diode or the third light-emitting diode.

25. The display device of claim 24, wherein, the second planarization layer is horizontally spaced apart from the second light-emitting diode or the third light-emitting diode, the fourth connection electrode, the fifth connection electrode, and the sixth connection electrode are provided over the second planarization layer, and a black matrix is provided over the fourth connection electrode, the fifth connection electrode, and the sixth connection electrode.

26. The display device of claim 25, wherein, 27. The display device according to claim 25, further comprising: a black matrix provided between the first planarization layer and the second planarization layer and covering a top surface and a side surface of the first planarization layer, wherein the fourth connection electrode, the fifth connection electrode, and the sixth connection electrode are provided over the second planarization layer. the fourth connection electrode electrically connects the power supply line and a second electrode of the second light-emitting diode, the fifth connection electrode electrically connects a drain of the second drive transistor and a first electrode of the third light-emitting diode, and the sixth connection electrode electrically connects a first electrode of the second light-emitting diode and a second electrode of the third light-emitting diode.

28. The display device of claim 22, wherein, 29. A display device comprising: a substrate including a plurality of sub-pixels; a drive transistor provided over the substrate in each of the plurality of sub-pixels; a power supply line provided over the substrate; a first light-emitting diode provided in a first sub-pixel of the plurality of sub-pixels; a second light-emitting diode and a third light-emitting diode provided in a second sub-pixel of the plurality of sub-pixels, emitting light of the same color and connected in series; and a conductive pattern including a conductive layer provided over the drive transistor provided in the first sub-pixel and electrically connecting the first light-emitting diode with the power supply line or the drive transistor provided in the first sub-pixel, wherein the second light-emitting diode is electrically connected to the drive transistor provided in the second sub-pixel, and the third light-emitting diode is electrically connected to the power supply line.

30. The display device according to claim 29, further comprising: ​ ​ a first planarization layer disposed over the power supply line and the driving transistor, and surrounding side surfaces of the first light emitting diode, side surfaces of the second light emitting diode, and side surfaces of the third light emitting diode; and a second planarization layer disposed on the first planarization layer.

31. The display device of claim 29, wherein, The conductive pattern further includes: a first connection electrode connected to the driving transistor disposed in the first sub-pixel or the power supply line; and a third connection electrode connected to the first light emitting diode, wherein the first connection electrode and the third connection electrode are in contact with the conductive layer.

32. The display device according to claim 31, further comprising: an insulating layer disposed on the conductive layer to overlap the conductive layer, wherein the first connection electrode and the third connection electrode are spaced apart from each other on the insulating layer.

33. The display device according to claim 30, further comprising: a black matrix disposed on the second planarization layer.

34. The display device according to claim 30, further comprising: a black matrix disposed between the first planarization layer and the second planarization layer.

35. A display device according to claim 34, wherein, The black matrix is in contact with the side surfaces of the first light emitting diode, the side surfaces of the second light emitting diode, and the side surfaces of the third light emitting diode, and a maximum height of a top surface of the black matrix is lower than a maximum height of a top surface of each of the first light emitting diode, the second light emitting diode, and the third light emitting diode.

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